| stats.txt (9838:43d22d746e7a) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 681070 # Simulator instruction rate (inst/s) 8host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 269712940 # Simulator tick rate (ticks/s) 10host_mem_usage 243700 # Number of bytes of host memory used 11host_seconds 0.97 # Real time elapsed on the host | 7host_inst_rate 200508 # Simulator instruction rate (inst/s) 8host_op_rate 200507 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 79406810 # Simulator tick rate (ticks/s) 10host_mem_usage 291148 # Number of bytes of host memory used 11host_seconds 3.31 # Real time elapsed on the host |
| 12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory --- 144 unchanged lines hidden (view full) --- 164system.l2c.overall_misses::cpu1.data 23 # number of overall misses 165system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 166system.l2c.overall_misses::cpu2.data 16 # number of overall misses 167system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 168system.l2c.overall_misses::cpu3.data 16 # number of overall misses 169system.l2c.overall_misses::total 592 # number of overall misses 170system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 171system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles | 12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory --- 144 unchanged lines hidden (view full) --- 164system.l2c.overall_misses::cpu1.data 23 # number of overall misses 165system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 166system.l2c.overall_misses::cpu2.data 16 # number of overall misses 167system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 168system.l2c.overall_misses::cpu3.data 16 # number of overall misses 169system.l2c.overall_misses::total 592 # number of overall misses 170system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 171system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles |
| 172system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles 173system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles 174system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles 175system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles | 172system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles 173system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 174system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 175system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles |
| 176system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 177system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles | 176system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 177system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles |
| 178system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles | 178system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles |
| 179system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles | 179system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles |
| 180system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles 181system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles | 180system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 181system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles |
| 182system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles | 182system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles |
| 183system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles | 183system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles |
| 184system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 185system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles | 184system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 185system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles |
| 186system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles 187system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles 188system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles 189system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles | 186system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles 187system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 188system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 189system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles |
| 190system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 191system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles | 190system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 191system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles |
| 192system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles | 192system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles |
| 193system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 194system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles | 193system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 194system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles |
| 195system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles 196system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles 197system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles 198system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles | 195system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles 196system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 197system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 198system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles |
| 199system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 200system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles | 199system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 200system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles |
| 201system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles | 201system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles |
| 202system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 203system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 204system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 205system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 206system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 207system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 208system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 209system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) --- 62 unchanged lines hidden (view full) --- 272system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 273system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 274system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 275system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 276system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 277system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 278system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 279system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency | 202system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 203system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 204system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 205system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 206system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 207system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 208system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 209system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) --- 62 unchanged lines hidden (view full) --- 272system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 273system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 274system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 275system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 276system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 277system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 278system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 279system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency |
| 280system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency 281system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency 282system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency 283system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency | 280system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency 281system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 282system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 283system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency |
| 284system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 285system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency | 284system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 285system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency |
| 286system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency | 286system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency |
| 287system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency | 287system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency |
| 288system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency 289system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency | 288system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 289system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency |
| 290system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency | 290system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency |
| 291system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency | 291system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency |
| 292system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 293system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency | 292system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 293system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency |
| 294system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency 295system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency 296system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency 297system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency | 294system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 295system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 296system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 297system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency |
| 298system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 299system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency | 298system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 299system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency |
| 300system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency | 300system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency |
| 301system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency | 301system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency |
| 303system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency 304system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency 305system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency 306system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency | 303system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 304system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 305system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 306system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency |
| 307system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency | 307system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency |
| 309system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency | 309system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency |
| 310system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 313system.l2c.blocked::no_targets 0 # number of cycles access was blocked 314system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.l2c.fast_writes 0 # number of fast writes performed 317system.l2c.cache_copies 0 # number of cache copies performed --- 62 unchanged lines hidden (view full) --- 380system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 381system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 382system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 383system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 384system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 385system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 386system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles 387system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles | 310system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 313system.l2c.blocked::no_targets 0 # number of cycles access was blocked 314system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.l2c.fast_writes 0 # number of fast writes performed 317system.l2c.cache_copies 0 # number of cache copies performed --- 62 unchanged lines hidden (view full) --- 380system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 381system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 382system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 383system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 384system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 385system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 386system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles 387system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles |
| 388system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles 389system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles | 388system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles 389system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles |
| 390system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles | 390system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles |
| 391system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles | 391system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles |
| 392system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles 393system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles 394system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles | 392system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles 393system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles 394system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles |
| 395system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles | 395system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles |
| 396system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles | 396system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles |
| 397system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles | 397system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles |
| 398system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles 399system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles | 398system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles 399system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles |
| 400system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles | 400system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles |
| 401system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles 402system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles 403system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles | 401system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles 402system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles 403system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles |
| 404system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles | 404system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles |
| 405system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles | 405system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles |
| 406system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles | 406system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles |
| 407system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles | 407system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles |
| 409system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles | 409system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles |
| 410system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 411system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 412system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 413system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses --- 36 unchanged lines hidden (view full) --- 454system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 455system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 457system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 458system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 459system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 460system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency | 410system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 411system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 412system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 413system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses --- 36 unchanged lines hidden (view full) --- 454system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 455system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 457system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 458system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 459system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 460system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency |
| 462system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency 463system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency | 462system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency 463system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency |
| 464system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency | 464system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency |
| 465system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency | 465system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency |
| 466system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency | 466system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency |
| 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency | 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency |
| 470system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency | 470system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency |
| 471system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency | 471system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency |
| 472system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 472system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 474system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency | 474system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency |
| 475system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency | 475system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency |
| 478system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency | 478system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency |
| 479system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency | 479system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency |
| 480system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency | 480system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency |
| 481system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 481system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 483system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency | 483system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency |
| 484system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 485system.toL2Bus.throughput 646588875 # Throughput (bytes/s) 486system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 487system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 488system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 489system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 490system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 491system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution --- 270 unchanged lines hidden (view full) --- 762system.cpu1.num_fp_insts 0 # number of float instructions 763system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 764system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 765system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 766system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 767system.cpu1.num_mem_refs 58020 # number of memory refs 768system.cpu1.num_load_insts 41540 # Number of load instructions 769system.cpu1.num_store_insts 16480 # Number of store instructions | 484system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 485system.toL2Bus.throughput 646588875 # Throughput (bytes/s) 486system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 487system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 488system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 489system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 490system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 491system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution --- 270 unchanged lines hidden (view full) --- 762system.cpu1.num_fp_insts 0 # number of float instructions 763system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 764system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 765system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 766system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 767system.cpu1.num_mem_refs 58020 # number of memory refs 768system.cpu1.num_load_insts 41540 # Number of load instructions 769system.cpu1.num_store_insts 16480 # Number of store instructions |
| 770system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles 771system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles 772system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles 773system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles | 770system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles 771system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles 772system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles 773system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles |
| 774system.cpu1.icache.tags.replacements 280 # number of replacements | 774system.cpu1.icache.tags.replacements 280 # number of replacements |
| 775system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use | 775system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use |
| 776system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 777system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 778system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 779system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 776system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 777system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 778system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 779system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 780system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor | 780system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor |
| 781system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 782system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 783system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits 784system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits 785system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits 786system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits 787system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 788system.cpu1.icache.overall_hits::total 163138 # number of overall hits 789system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 790system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 791system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 792system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 793system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 794system.cpu1.icache.overall_misses::total 366 # number of overall misses | 781system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 782system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 783system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits 784system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits 785system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits 786system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits 787system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 788system.cpu1.icache.overall_hits::total 163138 # number of overall hits 789system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 790system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 791system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 792system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 793system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 794system.cpu1.icache.overall_misses::total 366 # number of overall misses |
| 795system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles 796system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles 797system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles 798system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles 799system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles 800system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles | 795system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles 796system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles 797system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles 798system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles 799system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles 800system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles |
| 801system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 802system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 803system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 804system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 805system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 806system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 807system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 808system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 810system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 811system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 812system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses | 801system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 802system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 803system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 804system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 805system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 806system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 807system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 808system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 810system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 811system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 812system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses |
| 813system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency 814system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency 815system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency 816system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency 817system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency 818system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency | 813system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency 814system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency 815system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 816system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency 817system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 818system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency |
| 819system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 820system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 821system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 822system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 823system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 824system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 825system.cpu1.icache.fast_writes 0 # number of fast writes performed 826system.cpu1.icache.cache_copies 0 # number of cache copies performed 827system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 828system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 829system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 830system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 831system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 832system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 819system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 820system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 821system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 822system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 823system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 824system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 825system.cpu1.icache.fast_writes 0 # number of fast writes performed 826system.cpu1.icache.cache_copies 0 # number of cache copies performed 827system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 828system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 829system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 830system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 831system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 832system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 833system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles 834system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles 835system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles 836system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles 837system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles 838system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles | 833system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles 834system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles 835system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles 836system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles 837system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles 838system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles |
| 839system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 840system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 842system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 843system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 844system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses | 839system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 840system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 842system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 843system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 844system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses |
| 845system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency 846system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency 847system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency 848system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency 849system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency 850system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency | 845system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency 846system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency 847system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 848system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 849system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 850system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency |
| 851system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 852system.cpu1.dcache.tags.replacements 0 # number of replacements 853system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use 854system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 855system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 856system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 857system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 858system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 873system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses 874system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses 875system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses 876system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses 877system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses 878system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses 879system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses 880system.cpu1.dcache.overall_misses::total 263 # number of overall misses | 851system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 852system.cpu1.dcache.tags.replacements 0 # number of replacements 853system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use 854system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 855system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 856system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 857system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 858system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 873system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses 874system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses 875system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses 876system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses 877system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses 878system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses 879system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses 880system.cpu1.dcache.overall_misses::total 263 # number of overall misses |
| 881system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles 882system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles 883system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles 884system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles | 881system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles 882system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles 883system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles 884system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles |
| 885system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles 886system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles | 885system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles 886system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles |
| 887system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles 888system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles 889system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles 890system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles | 887system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles 888system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles 889system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles 890system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles |
| 891system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) 892system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) 893system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) 894system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) 895system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) 896system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 897system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses 898system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 903system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses 904system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses 905system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses 906system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses 907system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses 908system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses 909system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses 910system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses | 891system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) 892system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) 893system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) 894system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) 895system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) 896system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 897system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses 898system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 903system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses 904system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses 905system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses 906system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses 907system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses 908system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses 909system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses 910system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses |
| 911system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency 912system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency 913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency 914system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency | 911system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency 912system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency 913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency 914system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency |
| 915system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency 916system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency | 915system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency 916system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency |
| 917system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency 918system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency 919system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency 920system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency | 917system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 918system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency 919system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 920system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency |
| 921system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 922system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 923system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 924system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 925system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 926system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 927system.cpu1.dcache.fast_writes 0 # number of fast writes performed 928system.cpu1.dcache.cache_copies 0 # number of cache copies performed 929system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses 930system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 931system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses 932system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 933system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses 934system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 935system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 936system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 937system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 938system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses | 921system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 922system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 923system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 924system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 925system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 926system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 927system.cpu1.dcache.fast_writes 0 # number of fast writes performed 928system.cpu1.dcache.cache_copies 0 # number of cache copies performed 929system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses 930system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 931system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses 932system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 933system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses 934system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 935system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 936system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 937system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 938system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses |
| 939system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles 940system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles 941system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles 942system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles | 939system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles 940system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles 941system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles 942system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles |
| 943system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles 944system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles | 943system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles 944system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles |
| 945system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles 946system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles 947system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles 948system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles | 945system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles 946system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles 947system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles 948system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles |
| 949system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses 950system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses 951system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses 952system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses 953system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses 954system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses 955system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses 956system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses 957system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses 958system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses | 949system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses 950system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses 951system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses 952system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses 953system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses 954system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses 955system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses 956system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses 957system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses 958system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses |
| 959system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency 960system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency 961system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency 962system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency | 959system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency 960system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency 961system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency 962system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency |
| 963system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 964system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency | 963system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 964system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency |
| 965system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency 966system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency 967system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency 968system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency | 965system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 966system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 967system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 968system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency |
| 969system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 970system.cpu2.numCycles 525588 # number of cpu cycles simulated 971system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 972system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 973system.cpu2.committedInsts 164866 # Number of instructions committed 974system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 975system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 976system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 977system.cpu2.num_func_calls 637 # number of times a function call or return occured 978system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 979system.cpu2.num_int_insts 112988 # number of integer instructions 980system.cpu2.num_fp_insts 0 # number of float instructions 981system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 982system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 983system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 984system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 985system.cpu2.num_mem_refs 59208 # number of memory refs 986system.cpu2.num_load_insts 42171 # Number of load instructions 987system.cpu2.num_store_insts 17037 # Number of store instructions | 969system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 970system.cpu2.numCycles 525588 # number of cpu cycles simulated 971system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 972system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 973system.cpu2.committedInsts 164866 # Number of instructions committed 974system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 975system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 976system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 977system.cpu2.num_func_calls 637 # number of times a function call or return occured 978system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 979system.cpu2.num_int_insts 112988 # number of integer instructions 980system.cpu2.num_fp_insts 0 # number of float instructions 981system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 982system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 983system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 984system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 985system.cpu2.num_mem_refs 59208 # number of memory refs 986system.cpu2.num_load_insts 42171 # Number of load instructions 987system.cpu2.num_store_insts 17037 # Number of store instructions |
| 988system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles 989system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles 990system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles 991system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles | 988system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles 989system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles 990system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles 991system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles |
| 992system.cpu2.icache.tags.replacements 280 # number of replacements | 992system.cpu2.icache.tags.replacements 280 # number of replacements |
| 993system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use | 993system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use |
| 994system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 995system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 996system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 997system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 994system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 995system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 996system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 997system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 998system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor | 998system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor |
| 999system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1000system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1001system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits 1002system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits 1003system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits 1004system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits 1005system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1006system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1007system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1008system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1009system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1010system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1011system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1012system.cpu2.icache.overall_misses::total 366 # number of overall misses | 999system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1000system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1001system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits 1002system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits 1003system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits 1004system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits 1005system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1006system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1007system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1008system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1009system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1010system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1011system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1012system.cpu2.icache.overall_misses::total 366 # number of overall misses |
| 1013system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles 1014system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles 1015system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles 1016system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles 1017system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles 1018system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles | 1013system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles 1014system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles 1015system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles 1016system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles 1017system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles 1018system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles |
| 1019system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1020system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1021system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1022system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1023system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1024system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1025system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1026system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1027system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1028system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1029system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1030system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses | 1019system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1020system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1021system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1022system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1023system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1024system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1025system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1026system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1027system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1028system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1029system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1030system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses |
| 1031system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency 1032system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency 1033system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency 1034system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency 1035system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency 1036system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency | 1031system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency 1032system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency 1033system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1034system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency 1035system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1036system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency |
| 1037system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1043system.cpu2.icache.fast_writes 0 # number of fast writes performed 1044system.cpu2.icache.cache_copies 0 # number of cache copies performed 1045system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1046system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1047system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1048system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1049system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1050system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 1037system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1043system.cpu2.icache.fast_writes 0 # number of fast writes performed 1044system.cpu2.icache.cache_copies 0 # number of cache copies performed 1045system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1046system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1047system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1048system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1049system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1050system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 1051system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles 1052system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles 1053system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles 1054system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles 1055system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles 1056system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles | 1051system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles 1052system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles 1053system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles 1054system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles 1055system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles 1056system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles |
| 1057system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1058system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1059system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1060system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1061system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1062system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses | 1057system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1058system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1059system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1060system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1061system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1062system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses |
| 1063system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency 1064system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency 1065system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency 1066system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency 1067system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency 1068system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency | 1063system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency 1064system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency 1065system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1066system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1067system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1068system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency |
| 1069system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1070system.cpu2.dcache.tags.replacements 0 # number of replacements | 1069system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1070system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 1071system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use | 1071system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use |
| 1072system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1073system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1074system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1075system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1072system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1073system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1074system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1075system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1076system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor | 1076system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor |
| 1077system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1078system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1079system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits 1080system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits 1081system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits 1082system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits 1083system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 1084system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 1091system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses 1092system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses 1093system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses 1094system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses 1095system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses 1096system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses 1097system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses 1098system.cpu2.dcache.overall_misses::total 262 # number of overall misses | 1077system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1078system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1079system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits 1080system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits 1081system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits 1082system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits 1083system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 1084system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 1091system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses 1092system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses 1093system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses 1094system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses 1095system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses 1096system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses 1097system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses 1098system.cpu2.dcache.overall_misses::total 262 # number of overall misses |
| 1099system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles 1100system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles 1101system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles 1102system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles | 1099system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles 1100system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles 1101system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles 1102system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles |
| 1103system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles 1104system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles | 1103system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles 1104system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles |
| 1105system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles 1106system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles 1107system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles 1108system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles | 1105system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles 1106system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles 1107system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles 1108system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles |
| 1109system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) 1110system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) 1111system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) 1112system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) 1113system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) 1114system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) 1115system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses 1116system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 1121system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses 1122system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses 1123system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 1124system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 1125system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses 1126system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses 1127system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses 1128system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses | 1109system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) 1110system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) 1111system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) 1112system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) 1113system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) 1114system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) 1115system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses 1116system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 1121system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses 1122system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses 1123system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 1124system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 1125system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses 1126system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses 1127system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses 1128system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses |
| 1129system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency 1130system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency 1131system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency 1132system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency | 1129system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency 1130system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency 1131system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency 1132system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency |
| 1133system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency 1134system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency | 1133system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency 1134system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency |
| 1135system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency 1136system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency 1137system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency 1138system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency | 1135system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1136system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency 1137system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1138system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency |
| 1139system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1140system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1141system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1142system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1143system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1144system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1145system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1146system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1147system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses 1148system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1149system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses 1150system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses 1151system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses 1152system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 1153system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1154system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1155system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1156system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses | 1139system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1140system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1141system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1142system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1143system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1144system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1145system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1146system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1147system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses 1148system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1149system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses 1150system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses 1151system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses 1152system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 1153system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1154system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1155system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1156system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses |
| 1157system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles 1158system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles 1159system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles 1160system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles | 1157system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles 1158system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles 1159system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles 1160system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles |
| 1161system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles 1162system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles | 1161system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles 1162system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles |
| 1163system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles 1164system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles 1165system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles 1166system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles | 1163system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles 1164system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles 1165system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles 1166system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles |
| 1167system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses 1168system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses 1169system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses 1170system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses 1171system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 1172system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 1173system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses 1174system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses 1175system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses 1176system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses | 1167system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses 1168system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses 1169system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses 1170system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses 1171system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 1172system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 1173system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses 1174system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses 1175system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses 1176system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses |
| 1177system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency 1178system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency 1179system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency 1180system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency | 1177system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency 1178system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency 1179system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency 1180system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency |
| 1181system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1182system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency | 1181system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1182system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency |
| 1183system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency 1184system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency 1185system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency 1186system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency | 1183system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1184system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1185system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1186system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency |
| 1187system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1188system.cpu3.numCycles 525588 # number of cpu cycles simulated 1189system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1190system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1191system.cpu3.committedInsts 176656 # Number of instructions committed 1192system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1193system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1194system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 213 unchanged lines hidden --- | 1187system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1188system.cpu3.numCycles 525588 # number of cpu cycles simulated 1189system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1190system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1191system.cpu3.committedInsts 176656 # Number of instructions committed 1192system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1193system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1194system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 213 unchanged lines hidden --- |