| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated |
| 4sim_ticks 262970500 # Number of ticks simulated 5final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 262793500 # Number of ticks simulated 5final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 110323 # Simulator instruction rate (inst/s) 8host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43749084 # Simulator tick rate (ticks/s) 10host_mem_usage 287188 # Number of bytes of host memory used 11host_seconds 6.01 # Real time elapsed on the host 12sim_insts 663135 # Number of instructions simulated 13sim_ops 663135 # Number of ops (including micro ops) simulated | 7host_inst_rate 1490059 # Simulator instruction rate (inst/s) 8host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 590046557 # Simulator tick rate (ticks/s) 10host_mem_usage 244196 # Number of bytes of host memory used 11host_seconds 0.45 # Real time elapsed on the host 12sim_insts 663601 # Number of instructions simulated 13sim_ops 663601 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory | 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory |
| 24system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory | 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory |
| 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory | 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory |
| 26system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory | 26system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory |
| 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory | 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory | 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory |
| 37system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) 60system.membus.throughput 139303293 # Throughput (bytes/s) 61system.membus.trans_dist::ReadReq 430 # Transaction distribution 62system.membus.trans_dist::ReadResp 430 # Transaction distribution 63system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 64system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 65system.membus.trans_dist::ReadExReq 208 # Transaction distribution 66system.membus.trans_dist::ReadExResp 142 # Transaction distribution 67system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes) 68system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes) 69system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes) 70system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) 71system.membus.data_through_bus 36608 # Total data (bytes) 72system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 73system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) 74system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 75system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) 76system.membus.respLayer0.utilization 2.1 # Layer utilization (%) 77system.toL2Bus.throughput 646591335 # Throughput (bytes/s) 78system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 79system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 80system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 81system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 82system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 83system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 84system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 85system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) 86system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) 87system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) 88system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) 89system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) 90system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) 91system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) 92system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) 93system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) 94system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) 95system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) 96system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) 97system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) 98system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) 99system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) 100system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) 101system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) 102system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) 103system.toL2Bus.data_through_bus 116032 # Total data (bytes) 104system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) 105system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) 106system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 107system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) 108system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 109system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) 110system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 111system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) 112system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) 113system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) 114system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) 115system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) 116system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) 117system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) 118system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 119system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) 120system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) 121system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) 122system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) |
| 60system.cpu0.workload.num_syscalls 89 # Number of system calls | 123system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 61system.cpu0.numCycles 525941 # number of cpu cycles simulated | 124system.cpu0.numCycles 525587 # number of cpu cycles simulated |
| 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 125system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 126system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 64system.cpu0.committedInsts 158580 # Number of instructions committed 65system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses | 127system.cpu0.committedInsts 158574 # Number of instructions committed 128system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed 129system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses |
| 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 68system.cpu0.num_func_calls 390 # number of times a function call or return occured | 130system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 131system.cpu0.num_func_calls 390 # number of times a function call or return occured |
| 69system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls 70system.cpu0.num_int_insts 109212 # number of integer instructions | 132system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls 133system.cpu0.num_int_insts 109208 # number of integer instructions |
| 71system.cpu0.num_fp_insts 0 # number of float instructions | 134system.cpu0.num_fp_insts 0 # number of float instructions |
| 72system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read 73system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written | 135system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read 136system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written |
| 74system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 75system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written | 137system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 138system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written |
| 76system.cpu0.num_mem_refs 74024 # number of memory refs 77system.cpu0.num_load_insts 49009 # Number of load instructions 78system.cpu0.num_store_insts 25015 # Number of store instructions | 139system.cpu0.num_mem_refs 74021 # number of memory refs 140system.cpu0.num_load_insts 49007 # Number of load instructions 141system.cpu0.num_store_insts 25014 # Number of store instructions |
| 79system.cpu0.num_idle_cycles 0 # Number of idle cycles | 142system.cpu0.num_idle_cycles 0 # Number of idle cycles |
| 80system.cpu0.num_busy_cycles 525941 # Number of busy cycles | 143system.cpu0.num_busy_cycles 525587 # Number of busy cycles |
| 81system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 82system.cpu0.idle_fraction 0 # Percentage of idle cycles 83system.cpu0.icache.replacements 215 # number of replacements | 144system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 145system.cpu0.idle_fraction 0 # Percentage of idle cycles 146system.cpu0.icache.replacements 215 # number of replacements |
| 84system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use 85system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. | 147system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use 148system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. |
| 86system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. | 149system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. |
| 87system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. | 150system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. |
| 88system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 151system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 89system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor 90system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy 91system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy 92system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits 93system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits 94system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits 95system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits 96system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits 97system.cpu0.icache.overall_hits::total 158176 # number of overall hits | 152system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor 153system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy 154system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy 155system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits 156system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits 157system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits 158system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits 159system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits 160system.cpu0.icache.overall_hits::total 158170 # number of overall hits |
| 98system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 99system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 100system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 101system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 102system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 103system.cpu0.icache.overall_misses::total 467 # number of overall misses | 161system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 162system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 163system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 164system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 165system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 166system.cpu0.icache.overall_misses::total 467 # number of overall misses |
| 104system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles 105system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles 106system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles 107system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles 108system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles 109system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles 110system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses) 111system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses) 112system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses 113system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses 114system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses 115system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses | 167system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles 168system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles 169system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles 170system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles 171system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles 172system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles 173system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) 174system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) 175system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses 176system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses 177system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses 178system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses |
| 116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses 117system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses 118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses 119system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses 120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses 121system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses | 179system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses 180system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses 181system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses 182system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses 183system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses 184system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses |
| 122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency 123system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency 124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency 125system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency 126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency 127system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency | 185system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency 186system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency 187system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency 188system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency 189system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency 190system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency |
| 128system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 134system.cpu0.icache.fast_writes 0 # number of fast writes performed 135system.cpu0.icache.cache_copies 0 # number of cache copies performed 136system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 137system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 138system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 139system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 140system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 141system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses | 191system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 192system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 193system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 195system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 196system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 197system.cpu0.icache.fast_writes 0 # number of fast writes performed 198system.cpu0.icache.cache_copies 0 # number of cache copies performed 199system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 200system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 201system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 202system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 203system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 204system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses |
| 142system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles 143system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles 144system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles 145system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles 146system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17209000 # number of overall MSHR miss cycles 147system.cpu0.icache.overall_mshr_miss_latency::total 17209000 # number of overall MSHR miss cycles | 205system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles 206system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles 207system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles 208system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles 209system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles 210system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles |
| 148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses 149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses 150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses 151system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses 152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses 153system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses | 211system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses 212system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses 213system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses 214system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses 215system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses 216system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses |
| 154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average ReadReq mshr miss latency 155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36850.107066 # average ReadReq mshr miss latency 156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency 157system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency 158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency 159system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency | 217system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency 218system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency 219system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency 220system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency 221system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency 222system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency |
| 160system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu0.dcache.replacements 2 # number of replacements | 223system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 224system.cpu0.dcache.replacements 2 # number of replacements |
| 162system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use 163system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. | 225system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use 226system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. |
| 164system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. | 227system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. |
| 165system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. | 228system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. |
| 166system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 229system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 167system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor 168system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy 169system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy 170system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits 171system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits | 230system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor 231system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy 232system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy 233system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits 234system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits |
| 172system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits 173system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits 174system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 175system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits | 235system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits 236system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits 237system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 238system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits |
| 176system.cpu0.dcache.demand_hits::cpu0.data 73608 # number of demand (read+write) hits 177system.cpu0.dcache.demand_hits::total 73608 # number of demand (read+write) hits 178system.cpu0.dcache.overall_hits::cpu0.data 73608 # number of overall hits 179system.cpu0.dcache.overall_hits::total 73608 # number of overall hits 180system.cpu0.dcache.ReadReq_misses::cpu0.data 171 # number of ReadReq misses 181system.cpu0.dcache.ReadReq_misses::total 171 # number of ReadReq misses 182system.cpu0.dcache.WriteReq_misses::cpu0.data 184 # number of WriteReq misses 183system.cpu0.dcache.WriteReq_misses::total 184 # number of WriteReq misses | 239system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits 240system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits 241system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits 242system.cpu0.dcache.overall_hits::total 73607 # number of overall hits 243system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 244system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 245system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 246system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses |
| 184system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 185system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses | 247system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 248system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses |
| 186system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses 187system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses 188system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses 189system.cpu0.dcache.overall_misses::total 355 # number of overall misses 190system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4683500 # number of ReadReq miss cycles 191system.cpu0.dcache.ReadReq_miss_latency::total 4683500 # number of ReadReq miss cycles 192system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7047500 # number of WriteReq miss cycles 193system.cpu0.dcache.WriteReq_miss_latency::total 7047500 # number of WriteReq miss cycles 194system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 364500 # number of SwapReq miss cycles 195system.cpu0.dcache.SwapReq_miss_latency::total 364500 # number of SwapReq miss cycles 196system.cpu0.dcache.demand_miss_latency::cpu0.data 11731000 # number of demand (read+write) miss cycles 197system.cpu0.dcache.demand_miss_latency::total 11731000 # number of demand (read+write) miss cycles 198system.cpu0.dcache.overall_miss_latency::cpu0.data 11731000 # number of overall miss cycles 199system.cpu0.dcache.overall_miss_latency::total 11731000 # number of overall miss cycles 200system.cpu0.dcache.ReadReq_accesses::cpu0.data 48999 # number of ReadReq accesses(hits+misses) 201system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) 202system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) 203system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) | 249system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 250system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 251system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 252system.cpu0.dcache.overall_misses::total 353 # number of overall misses 253system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles 254system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles 255system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles 256system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles 257system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles 258system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles 259system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles 260system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles 261system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles 262system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles 263system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) 264system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) 265system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) 266system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) |
| 204system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 205system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 267system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 268system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 206system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses 207system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses 208system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses 209system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses 210system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses 211system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses 212system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses 213system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses | 269system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses 270system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses 271system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses 272system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses 273system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses 274system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses 275system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses 276system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses |
| 214system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 215system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses | 277system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 278system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses |
| 216system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses 217system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses 218system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses 219system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses 220system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency 221system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency 222system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency 223system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency 224system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency 225system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency 226system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency 227system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency 228system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency 229system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency | 279system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses 280system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses 281system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses 282system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses 283system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency 284system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency 285system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency 286system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency 287system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency 288system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency 289system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency 290system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency 291system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency 292system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency |
| 230system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 231system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 232system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 233system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 234system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 235system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 236system.cpu0.dcache.fast_writes 0 # number of fast writes performed 237system.cpu0.dcache.cache_copies 0 # number of cache copies performed 238system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 239system.cpu0.dcache.writebacks::total 1 # number of writebacks | 293system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 294system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 295system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 296system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 297system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 298system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 299system.cpu0.dcache.fast_writes 0 # number of fast writes performed 300system.cpu0.dcache.cache_copies 0 # number of cache copies performed 301system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 302system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 240system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses 241system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses 242system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses 243system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses | 303system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 304system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 305system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 306system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses |
| 244system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 245system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses | 307system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 308system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses |
| 246system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses 247system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses 248system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses 249system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses 250system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles 251system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles 252system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles 253system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles 254system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles 255system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles 256system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles 257system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles 258system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles 259system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles 260system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses 261system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses 262system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses 263system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses | 309system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 310system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 311system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 312system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 313system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles 314system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles 315system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles 316system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles 317system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles 318system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles 319system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles 320system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles 321system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles 322system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles 323system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses 324system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses 325system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses 326system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses |
| 264system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 265system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses | 327system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 328system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses |
| 266system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses 267system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses 268system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses 269system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses 270system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency 271system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency 272system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency 273system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency 274system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency 275system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency 276system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency 277system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency 278system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency 279system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency | 329system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses 330system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses 331system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses 332system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses 333system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency 334system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency 335system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency 336system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency 337system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency 338system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency 339system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency 340system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency 341system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency 342system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency |
| 280system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 343system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 281system.cpu1.numCycles 525940 # number of cpu cycles simulated | 344system.cpu1.numCycles 525587 # number of cpu cycles simulated |
| 282system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 345system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 284system.cpu1.committedInsts 166746 # Number of instructions committed 285system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed 286system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses | 347system.cpu1.committedInsts 173389 # Number of instructions committed 348system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed 349system.cpu1.num_int_alu_accesses 107707 # Number of integer alu accesses |
| 287system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 288system.cpu1.num_func_calls 637 # number of times a function call or return occured | 350system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 351system.cpu1.num_func_calls 637 # number of times a function call or return occured |
| 289system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls 290system.cpu1.num_int_insts 110403 # number of integer instructions | 352system.cpu1.num_conditional_control_insts 36848 # number of instructions that are conditional controls 353system.cpu1.num_int_insts 107707 # number of integer instructions |
| 291system.cpu1.num_fp_insts 0 # number of float instructions | 354system.cpu1.num_fp_insts 0 # number of float instructions |
| 292system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read 293system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written | 355system.cpu1.num_int_register_reads 245634 # number of times the integer registers were read 356system.cpu1.num_int_register_writes 91167 # number of times the integer registers were written |
| 294system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 295system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written | 357system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 358system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written |
| 296system.cpu1.num_mem_refs 54388 # number of memory refs 297system.cpu1.num_load_insts 40871 # Number of load instructions 298system.cpu1.num_store_insts 13517 # Number of store instructions 299system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles 300system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles 301system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles 302system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles | 359system.cpu1.num_mem_refs 47028 # number of memory refs 360system.cpu1.num_load_insts 39502 # Number of load instructions 361system.cpu1.num_store_insts 7526 # Number of store instructions 362system.cpu1.num_idle_cycles 69346.001736 # Number of idle cycles 363system.cpu1.num_busy_cycles 456240.998264 # Number of busy cycles 364system.cpu1.not_idle_fraction 0.868060 # Percentage of non-idle cycles 365system.cpu1.idle_fraction 0.131940 # Percentage of idle cycles |
| 303system.cpu1.icache.replacements 280 # number of replacements | 366system.cpu1.icache.replacements 280 # number of replacements |
| 304system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use 305system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. | 367system.cpu1.icache.tagsinuse 70.017443 # Cycle average of tags in use 368system.cpu1.icache.total_refs 173056 # Total number of references to valid blocks. |
| 306system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. | 369system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. |
| 307system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. | 370system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks. |
| 308system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 371system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 309system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor 310system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy 311system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy 312system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits 313system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits 314system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits 315system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits 316system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits 317system.cpu1.icache.overall_hits::total 166413 # number of overall hits | 372system.cpu1.icache.occ_blocks::cpu1.inst 70.017443 # Average occupied blocks per requestor 373system.cpu1.icache.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 374system.cpu1.icache.occ_percent::total 0.136753 # Average percentage of cache occupancy 375system.cpu1.icache.ReadReq_hits::cpu1.inst 173056 # number of ReadReq hits 376system.cpu1.icache.ReadReq_hits::total 173056 # number of ReadReq hits 377system.cpu1.icache.demand_hits::cpu1.inst 173056 # number of demand (read+write) hits 378system.cpu1.icache.demand_hits::total 173056 # number of demand (read+write) hits 379system.cpu1.icache.overall_hits::cpu1.inst 173056 # number of overall hits 380system.cpu1.icache.overall_hits::total 173056 # number of overall hits |
| 318system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 319system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 320system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 321system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 322system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 323system.cpu1.icache.overall_misses::total 366 # number of overall misses | 381system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 382system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 383system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 384system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 385system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 386system.cpu1.icache.overall_misses::total 366 # number of overall misses |
| 324system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles 325system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles 326system.cpu1.icache.demand_miss_latency::cpu1.inst 7565000 # number of demand (read+write) miss cycles 327system.cpu1.icache.demand_miss_latency::total 7565000 # number of demand (read+write) miss cycles 328system.cpu1.icache.overall_miss_latency::cpu1.inst 7565000 # number of overall miss cycles 329system.cpu1.icache.overall_miss_latency::total 7565000 # number of overall miss cycles 330system.cpu1.icache.ReadReq_accesses::cpu1.inst 166779 # number of ReadReq accesses(hits+misses) 331system.cpu1.icache.ReadReq_accesses::total 166779 # number of ReadReq accesses(hits+misses) 332system.cpu1.icache.demand_accesses::cpu1.inst 166779 # number of demand (read+write) accesses 333system.cpu1.icache.demand_accesses::total 166779 # number of demand (read+write) accesses 334system.cpu1.icache.overall_accesses::cpu1.inst 166779 # number of overall (read+write) accesses 335system.cpu1.icache.overall_accesses::total 166779 # number of overall (read+write) accesses 336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002195 # miss rate for ReadReq accesses 337system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses 338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses 339system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses 340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses 341system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses 342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency 343system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency 344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency 345system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency 346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency 347system.cpu1.icache.overall_avg_miss_latency::total 20669.398907 # average overall miss latency | 387system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7542000 # number of ReadReq miss cycles 388system.cpu1.icache.ReadReq_miss_latency::total 7542000 # number of ReadReq miss cycles 389system.cpu1.icache.demand_miss_latency::cpu1.inst 7542000 # number of demand (read+write) miss cycles 390system.cpu1.icache.demand_miss_latency::total 7542000 # number of demand (read+write) miss cycles 391system.cpu1.icache.overall_miss_latency::cpu1.inst 7542000 # number of overall miss cycles 392system.cpu1.icache.overall_miss_latency::total 7542000 # number of overall miss cycles 393system.cpu1.icache.ReadReq_accesses::cpu1.inst 173422 # number of ReadReq accesses(hits+misses) 394system.cpu1.icache.ReadReq_accesses::total 173422 # number of ReadReq accesses(hits+misses) 395system.cpu1.icache.demand_accesses::cpu1.inst 173422 # number of demand (read+write) accesses 396system.cpu1.icache.demand_accesses::total 173422 # number of demand (read+write) accesses 397system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses 398system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses 399system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses 400system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses 401system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses 402system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses 403system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses 404system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses 405system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency 406system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency 407system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency 408system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency 409system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency 410system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency |
| 348system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu1.icache.fast_writes 0 # number of fast writes performed 355system.cpu1.icache.cache_copies 0 # number of cache copies performed 356system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 357system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 358system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 359system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 360system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 361system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 411system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu1.icache.fast_writes 0 # number of fast writes performed 418system.cpu1.icache.cache_copies 0 # number of cache copies performed 419system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 420system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 421system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 422system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 423system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 424system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 362system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6833000 # number of ReadReq MSHR miss cycles 363system.cpu1.icache.ReadReq_mshr_miss_latency::total 6833000 # number of ReadReq MSHR miss cycles 364system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6833000 # number of demand (read+write) MSHR miss cycles 365system.cpu1.icache.demand_mshr_miss_latency::total 6833000 # number of demand (read+write) MSHR miss cycles 366system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6833000 # number of overall MSHR miss cycles 367system.cpu1.icache.overall_mshr_miss_latency::total 6833000 # number of overall MSHR miss cycles 368system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for ReadReq accesses 369system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002195 # mshr miss rate for ReadReq accesses 370system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for demand accesses 371system.cpu1.icache.demand_mshr_miss_rate::total 0.002195 # mshr miss rate for demand accesses 372system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for overall accesses 373system.cpu1.icache.overall_mshr_miss_rate::total 0.002195 # mshr miss rate for overall accesses 374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency 375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18669.398907 # average ReadReq mshr miss latency 376system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency 377system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency 378system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency 379system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency | 425system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806511 # number of ReadReq MSHR miss cycles 426system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806511 # number of ReadReq MSHR miss cycles 427system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806511 # number of demand (read+write) MSHR miss cycles 428system.cpu1.icache.demand_mshr_miss_latency::total 6806511 # number of demand (read+write) MSHR miss cycles 429system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806511 # number of overall MSHR miss cycles 430system.cpu1.icache.overall_mshr_miss_latency::total 6806511 # number of overall MSHR miss cycles 431system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for ReadReq accesses 432system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses 433system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for demand accesses 434system.cpu1.icache.demand_mshr_miss_rate::total 0.002110 # mshr miss rate for demand accesses 435system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for overall accesses 436system.cpu1.icache.overall_mshr_miss_rate::total 0.002110 # mshr miss rate for overall accesses 437system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency 438system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590 # average ReadReq mshr miss latency 439system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency 440system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency 441system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency 442system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency |
| 380system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu1.dcache.replacements 0 # number of replacements | 443system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 444system.cpu1.dcache.replacements 0 # number of replacements |
| 382system.cpu1.dcache.tagsinuse 27.686467 # Cycle average of tags in use 383system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks. | 445system.cpu1.dcache.tagsinuse 27.692937 # Cycle average of tags in use 446system.cpu1.dcache.total_refs 17380 # Total number of references to valid blocks. |
| 384system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. | 447system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. |
| 385system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks. | 448system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. |
| 386system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 449system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 387system.cpu1.dcache.occ_blocks::cpu1.data 27.686467 # Average occupied blocks per requestor 388system.cpu1.dcache.occ_percent::cpu1.data 0.054075 # Average percentage of cache occupancy 389system.cpu1.dcache.occ_percent::total 0.054075 # Average percentage of cache occupancy 390system.cpu1.dcache.ReadReq_hits::cpu1.data 40710 # number of ReadReq hits 391system.cpu1.dcache.ReadReq_hits::total 40710 # number of ReadReq hits 392system.cpu1.dcache.WriteReq_hits::cpu1.data 13344 # number of WriteReq hits 393system.cpu1.dcache.WriteReq_hits::total 13344 # number of WriteReq hits 394system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits 395system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits 396system.cpu1.dcache.demand_hits::cpu1.data 54054 # number of demand (read+write) hits 397system.cpu1.dcache.demand_hits::total 54054 # number of demand (read+write) hits 398system.cpu1.dcache.overall_hits::cpu1.data 54054 # number of overall hits 399system.cpu1.dcache.overall_hits::total 54054 # number of overall hits 400system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses 401system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses | 450system.cpu1.dcache.occ_blocks::cpu1.data 27.692937 # Average occupied blocks per requestor 451system.cpu1.dcache.occ_percent::cpu1.data 0.054088 # Average percentage of cache occupancy 452system.cpu1.dcache.occ_percent::total 0.054088 # Average percentage of cache occupancy 453system.cpu1.dcache.ReadReq_hits::cpu1.data 39322 # number of ReadReq hits 454system.cpu1.dcache.ReadReq_hits::total 39322 # number of ReadReq hits 455system.cpu1.dcache.WriteReq_hits::cpu1.data 7334 # number of WriteReq hits 456system.cpu1.dcache.WriteReq_hits::total 7334 # number of WriteReq hits 457system.cpu1.dcache.SwapReq_hits::cpu1.data 19 # number of SwapReq hits 458system.cpu1.dcache.SwapReq_hits::total 19 # number of SwapReq hits 459system.cpu1.dcache.demand_hits::cpu1.data 46656 # number of demand (read+write) hits 460system.cpu1.dcache.demand_hits::total 46656 # number of demand (read+write) hits 461system.cpu1.dcache.overall_hits::cpu1.data 46656 # number of overall hits 462system.cpu1.dcache.overall_hits::total 46656 # number of overall hits 463system.cpu1.dcache.ReadReq_misses::cpu1.data 172 # number of ReadReq misses 464system.cpu1.dcache.ReadReq_misses::total 172 # number of ReadReq misses |
| 402system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 403system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses | 465system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 466system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses |
| 404system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses 405system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses 406system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses 407system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses 408system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses 409system.cpu1.dcache.overall_misses::total 259 # number of overall misses 410system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2954500 # number of ReadReq miss cycles 411system.cpu1.dcache.ReadReq_miss_latency::total 2954500 # number of ReadReq miss cycles 412system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1962000 # number of WriteReq miss cycles 413system.cpu1.dcache.WriteReq_miss_latency::total 1962000 # number of WriteReq miss cycles 414system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 274000 # number of SwapReq miss cycles 415system.cpu1.dcache.SwapReq_miss_latency::total 274000 # number of SwapReq miss cycles 416system.cpu1.dcache.demand_miss_latency::cpu1.data 4916500 # number of demand (read+write) miss cycles 417system.cpu1.dcache.demand_miss_latency::total 4916500 # number of demand (read+write) miss cycles 418system.cpu1.dcache.overall_miss_latency::cpu1.data 4916500 # number of overall miss cycles 419system.cpu1.dcache.overall_miss_latency::total 4916500 # number of overall miss cycles 420system.cpu1.dcache.ReadReq_accesses::cpu1.data 40863 # number of ReadReq accesses(hits+misses) 421system.cpu1.dcache.ReadReq_accesses::total 40863 # number of ReadReq accesses(hits+misses) 422system.cpu1.dcache.WriteReq_accesses::cpu1.data 13450 # number of WriteReq accesses(hits+misses) 423system.cpu1.dcache.WriteReq_accesses::total 13450 # number of WriteReq accesses(hits+misses) 424system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) 425system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 426system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses 427system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses 428system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses 429system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses 430system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses 431system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses 432system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses 433system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses 434system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses 435system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses 436system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses 437system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses 438system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses 439system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses 440system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency 441system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency 442system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency 443system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency 444system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency 445system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency 446system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency 447system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency 448system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency 449system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency | 467system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses 468system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses 469system.cpu1.dcache.demand_misses::cpu1.data 278 # number of demand (read+write) misses 470system.cpu1.dcache.demand_misses::total 278 # number of demand (read+write) misses 471system.cpu1.dcache.overall_misses::cpu1.data 278 # number of overall misses 472system.cpu1.dcache.overall_misses::total 278 # number of overall misses 473system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3331000 # number of ReadReq miss cycles 474system.cpu1.dcache.ReadReq_miss_latency::total 3331000 # number of ReadReq miss cycles 475system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2174000 # number of WriteReq miss cycles 476system.cpu1.dcache.WriteReq_miss_latency::total 2174000 # number of WriteReq miss cycles 477system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 282000 # number of SwapReq miss cycles 478system.cpu1.dcache.SwapReq_miss_latency::total 282000 # number of SwapReq miss cycles 479system.cpu1.dcache.demand_miss_latency::cpu1.data 5505000 # number of demand (read+write) miss cycles 480system.cpu1.dcache.demand_miss_latency::total 5505000 # number of demand (read+write) miss cycles 481system.cpu1.dcache.overall_miss_latency::cpu1.data 5505000 # number of overall miss cycles 482system.cpu1.dcache.overall_miss_latency::total 5505000 # number of overall miss cycles 483system.cpu1.dcache.ReadReq_accesses::cpu1.data 39494 # number of ReadReq accesses(hits+misses) 484system.cpu1.dcache.ReadReq_accesses::total 39494 # number of ReadReq accesses(hits+misses) 485system.cpu1.dcache.WriteReq_accesses::cpu1.data 7440 # number of WriteReq accesses(hits+misses) 486system.cpu1.dcache.WriteReq_accesses::total 7440 # number of WriteReq accesses(hits+misses) 487system.cpu1.dcache.SwapReq_accesses::cpu1.data 84 # number of SwapReq accesses(hits+misses) 488system.cpu1.dcache.SwapReq_accesses::total 84 # number of SwapReq accesses(hits+misses) 489system.cpu1.dcache.demand_accesses::cpu1.data 46934 # number of demand (read+write) accesses 490system.cpu1.dcache.demand_accesses::total 46934 # number of demand (read+write) accesses 491system.cpu1.dcache.overall_accesses::cpu1.data 46934 # number of overall (read+write) accesses 492system.cpu1.dcache.overall_accesses::total 46934 # number of overall (read+write) accesses 493system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004355 # miss rate for ReadReq accesses 494system.cpu1.dcache.ReadReq_miss_rate::total 0.004355 # miss rate for ReadReq accesses 495system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014247 # miss rate for WriteReq accesses 496system.cpu1.dcache.WriteReq_miss_rate::total 0.014247 # miss rate for WriteReq accesses 497system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.773810 # miss rate for SwapReq accesses 498system.cpu1.dcache.SwapReq_miss_rate::total 0.773810 # miss rate for SwapReq accesses 499system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005923 # miss rate for demand accesses 500system.cpu1.dcache.demand_miss_rate::total 0.005923 # miss rate for demand accesses 501system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005923 # miss rate for overall accesses 502system.cpu1.dcache.overall_miss_rate::total 0.005923 # miss rate for overall accesses 503system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070 # average ReadReq miss latency 504system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070 # average ReadReq miss latency 505system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962 # average WriteReq miss latency 506system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962 # average WriteReq miss latency 507system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4338.461538 # average SwapReq miss latency 508system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency 509system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency 510system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency 511system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency 512system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency |
| 450system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 451system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 452system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 453system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 454system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 455system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 456system.cpu1.dcache.fast_writes 0 # number of fast writes performed 457system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 513system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu1.dcache.fast_writes 0 # number of fast writes performed 520system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 458system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses 459system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses | 521system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses 522system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses |
| 460system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 461system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses | 523system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 524system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses |
| 462system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses 463system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 464system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses 465system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 466system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses 467system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 468system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles 469system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles 470system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles 471system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles 472system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles 473system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles 474system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles 475system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles 476system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles 477system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles 478system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses 479system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses 480system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses 481system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses 482system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses 483system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses 484system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses 485system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses 486system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses 487system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses 488system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency 489system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency 490system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency 491system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency 492system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency 493system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency 494system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency 495system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency 496system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency 497system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency | 525system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses 526system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses 527system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses 528system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 529system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses 530system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses 531system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles 532system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles 533system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles 534system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles 535system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles 536system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 537system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles 538system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles 539system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles 540system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles 541system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses 542system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses 543system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses 544system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses 545system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses 546system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses 547system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses 548system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses 549system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses 550system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses 551system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency 552system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency 553system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency 554system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency 555system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency 556system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency 557system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency 558system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency 559system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency 560system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency |
| 498system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 561system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 499system.cpu2.numCycles 525941 # number of cpu cycles simulated | 562system.cpu2.numCycles 525587 # number of cpu cycles simulated |
| 500system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 563system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 564system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 502system.cpu2.committedInsts 169995 # Number of instructions committed 503system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed 504system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses | 565system.cpu2.committedInsts 164870 # Number of instructions committed 566system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed 567system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses |
| 505system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 506system.cpu2.num_func_calls 637 # number of times a function call or return occured | 568system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 569system.cpu2.num_func_calls 637 # number of times a function call or return occured |
| 507system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls 508system.cpu2.num_int_insts 110917 # number of integer instructions | 570system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls 571system.cpu2.num_int_insts 112982 # number of integer instructions |
| 509system.cpu2.num_fp_insts 0 # number of float instructions | 572system.cpu2.num_fp_insts 0 # number of float instructions |
| 510system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read 511system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written | 573system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read 574system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written |
| 512system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 513system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written | 575system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 576system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written |
| 514system.cpu2.num_mem_refs 53535 # number of memory refs 515system.cpu2.num_load_insts 41127 # Number of load instructions 516system.cpu2.num_store_insts 12408 # Number of store instructions 517system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles 518system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles 519system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles 520system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles | 577system.cpu2.num_mem_refs 59198 # number of memory refs 578system.cpu2.num_load_insts 42166 # Number of load instructions 579system.cpu2.num_store_insts 17032 # Number of store instructions 580system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles 581system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles 582system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles 583system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles |
| 521system.cpu2.icache.replacements 280 # number of replacements | 584system.cpu2.icache.replacements 280 # number of replacements |
| 522system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use 523system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. | 585system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use 586system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. |
| 524system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. | 587system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. |
| 525system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. | 588system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. |
| 526system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 589system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 527system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor 528system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy 529system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy 530system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits 531system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits 532system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits 533system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits 534system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits 535system.cpu2.icache.overall_hits::total 169662 # number of overall hits | 590system.cpu2.icache.occ_blocks::cpu2.inst 67.624903 # Average occupied blocks per requestor 591system.cpu2.icache.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 592system.cpu2.icache.occ_percent::total 0.132080 # Average percentage of cache occupancy 593system.cpu2.icache.ReadReq_hits::cpu2.inst 164537 # number of ReadReq hits 594system.cpu2.icache.ReadReq_hits::total 164537 # number of ReadReq hits 595system.cpu2.icache.demand_hits::cpu2.inst 164537 # number of demand (read+write) hits 596system.cpu2.icache.demand_hits::total 164537 # number of demand (read+write) hits 597system.cpu2.icache.overall_hits::cpu2.inst 164537 # number of overall hits 598system.cpu2.icache.overall_hits::total 164537 # number of overall hits |
| 536system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 537system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 538system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 539system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 540system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 541system.cpu2.icache.overall_misses::total 366 # number of overall misses | 599system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 600system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 601system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 602system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 603system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 604system.cpu2.icache.overall_misses::total 366 # number of overall misses |
| 542system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5281000 # number of ReadReq miss cycles 543system.cpu2.icache.ReadReq_miss_latency::total 5281000 # number of ReadReq miss cycles 544system.cpu2.icache.demand_miss_latency::cpu2.inst 5281000 # number of demand (read+write) miss cycles 545system.cpu2.icache.demand_miss_latency::total 5281000 # number of demand (read+write) miss cycles 546system.cpu2.icache.overall_miss_latency::cpu2.inst 5281000 # number of overall miss cycles 547system.cpu2.icache.overall_miss_latency::total 5281000 # number of overall miss cycles 548system.cpu2.icache.ReadReq_accesses::cpu2.inst 170028 # number of ReadReq accesses(hits+misses) 549system.cpu2.icache.ReadReq_accesses::total 170028 # number of ReadReq accesses(hits+misses) 550system.cpu2.icache.demand_accesses::cpu2.inst 170028 # number of demand (read+write) accesses 551system.cpu2.icache.demand_accesses::total 170028 # number of demand (read+write) accesses 552system.cpu2.icache.overall_accesses::cpu2.inst 170028 # number of overall (read+write) accesses 553system.cpu2.icache.overall_accesses::total 170028 # number of overall (read+write) accesses 554system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002153 # miss rate for ReadReq accesses 555system.cpu2.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 556system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002153 # miss rate for demand accesses 557system.cpu2.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 558system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002153 # miss rate for overall accesses 559system.cpu2.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 560system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14428.961749 # average ReadReq miss latency 561system.cpu2.icache.ReadReq_avg_miss_latency::total 14428.961749 # average ReadReq miss latency 562system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency 563system.cpu2.icache.demand_avg_miss_latency::total 14428.961749 # average overall miss latency 564system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency 565system.cpu2.icache.overall_avg_miss_latency::total 14428.961749 # average overall miss latency | 605system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251500 # number of ReadReq miss cycles 606system.cpu2.icache.ReadReq_miss_latency::total 5251500 # number of ReadReq miss cycles 607system.cpu2.icache.demand_miss_latency::cpu2.inst 5251500 # number of demand (read+write) miss cycles 608system.cpu2.icache.demand_miss_latency::total 5251500 # number of demand (read+write) miss cycles 609system.cpu2.icache.overall_miss_latency::cpu2.inst 5251500 # number of overall miss cycles 610system.cpu2.icache.overall_miss_latency::total 5251500 # number of overall miss cycles 611system.cpu2.icache.ReadReq_accesses::cpu2.inst 164903 # number of ReadReq accesses(hits+misses) 612system.cpu2.icache.ReadReq_accesses::total 164903 # number of ReadReq accesses(hits+misses) 613system.cpu2.icache.demand_accesses::cpu2.inst 164903 # number of demand (read+write) accesses 614system.cpu2.icache.demand_accesses::total 164903 # number of demand (read+write) accesses 615system.cpu2.icache.overall_accesses::cpu2.inst 164903 # number of overall (read+write) accesses 616system.cpu2.icache.overall_accesses::total 164903 # number of overall (read+write) accesses 617system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002219 # miss rate for ReadReq accesses 618system.cpu2.icache.ReadReq_miss_rate::total 0.002219 # miss rate for ReadReq accesses 619system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002219 # miss rate for demand accesses 620system.cpu2.icache.demand_miss_rate::total 0.002219 # miss rate for demand accesses 621system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002219 # miss rate for overall accesses 622system.cpu2.icache.overall_miss_rate::total 0.002219 # miss rate for overall accesses 623system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14348.360656 # average ReadReq miss latency 624system.cpu2.icache.ReadReq_avg_miss_latency::total 14348.360656 # average ReadReq miss latency 625system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency 626system.cpu2.icache.demand_avg_miss_latency::total 14348.360656 # average overall miss latency 627system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency 628system.cpu2.icache.overall_avg_miss_latency::total 14348.360656 # average overall miss latency |
| 566system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu2.icache.fast_writes 0 # number of fast writes performed 573system.cpu2.icache.cache_copies 0 # number of cache copies performed 574system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 575system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 576system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 577system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 578system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 579system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 629system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 630system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 631system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 632system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 633system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 634system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 635system.cpu2.icache.fast_writes 0 # number of fast writes performed 636system.cpu2.icache.cache_copies 0 # number of cache copies performed 637system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 638system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 639system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 640system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 641system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 642system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 580system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4549000 # number of ReadReq MSHR miss cycles 581system.cpu2.icache.ReadReq_mshr_miss_latency::total 4549000 # number of ReadReq MSHR miss cycles 582system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4549000 # number of demand (read+write) MSHR miss cycles 583system.cpu2.icache.demand_mshr_miss_latency::total 4549000 # number of demand (read+write) MSHR miss cycles 584system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4549000 # number of overall MSHR miss cycles 585system.cpu2.icache.overall_mshr_miss_latency::total 4549000 # number of overall MSHR miss cycles 586system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for ReadReq accesses 587system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 588system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for demand accesses 589system.cpu2.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 590system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for overall accesses 591system.cpu2.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 592system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average ReadReq mshr miss latency 593system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12428.961749 # average ReadReq mshr miss latency 594system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency 595system.cpu2.icache.demand_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency 596system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency 597system.cpu2.icache.overall_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency | 643system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4514513 # number of ReadReq MSHR miss cycles 644system.cpu2.icache.ReadReq_mshr_miss_latency::total 4514513 # number of ReadReq MSHR miss cycles 645system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4514513 # number of demand (read+write) MSHR miss cycles 646system.cpu2.icache.demand_mshr_miss_latency::total 4514513 # number of demand (read+write) MSHR miss cycles 647system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4514513 # number of overall MSHR miss cycles 648system.cpu2.icache.overall_mshr_miss_latency::total 4514513 # number of overall MSHR miss cycles 649system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for ReadReq accesses 650system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002219 # mshr miss rate for ReadReq accesses 651system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for demand accesses 652system.cpu2.icache.demand_mshr_miss_rate::total 0.002219 # mshr miss rate for demand accesses 653system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for overall accesses 654system.cpu2.icache.overall_mshr_miss_rate::total 0.002219 # mshr miss rate for overall accesses 655system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average ReadReq mshr miss latency 656system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12334.734973 # average ReadReq mshr miss latency 657system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency 658system.cpu2.icache.demand_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency 659system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency 660system.cpu2.icache.overall_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency |
| 598system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu2.dcache.replacements 0 # number of replacements | 661system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 662system.cpu2.dcache.replacements 0 # number of replacements |
| 600system.cpu2.dcache.tagsinuse 25.908378 # Cycle average of tags in use 601system.cpu2.dcache.total_refs 27066 # Total number of references to valid blocks. | 663system.cpu2.dcache.tagsinuse 26.764140 # Cycle average of tags in use 664system.cpu2.dcache.total_refs 36333 # Total number of references to valid blocks. |
| 602system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. | 665system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. |
| 603system.cpu2.dcache.avg_refs 933.310345 # Average number of references to valid blocks. | 666system.cpu2.dcache.avg_refs 1252.862069 # Average number of references to valid blocks. |
| 604system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 667system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 605system.cpu2.dcache.occ_blocks::cpu2.data 25.908378 # Average occupied blocks per requestor 606system.cpu2.dcache.occ_percent::cpu2.data 0.050602 # Average percentage of cache occupancy 607system.cpu2.dcache.occ_percent::total 0.050602 # Average percentage of cache occupancy 608system.cpu2.dcache.ReadReq_hits::cpu2.data 40963 # number of ReadReq hits 609system.cpu2.dcache.ReadReq_hits::total 40963 # number of ReadReq hits 610system.cpu2.dcache.WriteReq_hits::cpu2.data 12235 # number of WriteReq hits 611system.cpu2.dcache.WriteReq_hits::total 12235 # number of WriteReq hits 612system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits 613system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 614system.cpu2.dcache.demand_hits::cpu2.data 53198 # number of demand (read+write) hits 615system.cpu2.dcache.demand_hits::total 53198 # number of demand (read+write) hits 616system.cpu2.dcache.overall_hits::cpu2.data 53198 # number of overall hits 617system.cpu2.dcache.overall_hits::total 53198 # number of overall hits 618system.cpu2.dcache.ReadReq_misses::cpu2.data 157 # number of ReadReq misses 619system.cpu2.dcache.ReadReq_misses::total 157 # number of ReadReq misses 620system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 621system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 622system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses 623system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses 624system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses 625system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses 626system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses 627system.cpu2.dcache.overall_misses::total 262 # number of overall misses 628system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2754500 # number of ReadReq miss cycles 629system.cpu2.dcache.ReadReq_miss_latency::total 2754500 # number of ReadReq miss cycles 630system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1914500 # number of WriteReq miss cycles 631system.cpu2.dcache.WriteReq_miss_latency::total 1914500 # number of WriteReq miss cycles 632system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 286000 # number of SwapReq miss cycles 633system.cpu2.dcache.SwapReq_miss_latency::total 286000 # number of SwapReq miss cycles 634system.cpu2.dcache.demand_miss_latency::cpu2.data 4669000 # number of demand (read+write) miss cycles 635system.cpu2.dcache.demand_miss_latency::total 4669000 # number of demand (read+write) miss cycles 636system.cpu2.dcache.overall_miss_latency::cpu2.data 4669000 # number of overall miss cycles 637system.cpu2.dcache.overall_miss_latency::total 4669000 # number of overall miss cycles 638system.cpu2.dcache.ReadReq_accesses::cpu2.data 41120 # number of ReadReq accesses(hits+misses) 639system.cpu2.dcache.ReadReq_accesses::total 41120 # number of ReadReq accesses(hits+misses) 640system.cpu2.dcache.WriteReq_accesses::cpu2.data 12340 # number of WriteReq accesses(hits+misses) 641system.cpu2.dcache.WriteReq_accesses::total 12340 # number of WriteReq accesses(hits+misses) 642system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 643system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 644system.cpu2.dcache.demand_accesses::cpu2.data 53460 # number of demand (read+write) accesses 645system.cpu2.dcache.demand_accesses::total 53460 # number of demand (read+write) accesses 646system.cpu2.dcache.overall_accesses::cpu2.data 53460 # number of overall (read+write) accesses 647system.cpu2.dcache.overall_accesses::total 53460 # number of overall (read+write) accesses 648system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003818 # miss rate for ReadReq accesses 649system.cpu2.dcache.ReadReq_miss_rate::total 0.003818 # miss rate for ReadReq accesses 650system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008509 # miss rate for WriteReq accesses 651system.cpu2.dcache.WriteReq_miss_rate::total 0.008509 # miss rate for WriteReq accesses 652system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.772727 # miss rate for SwapReq accesses 653system.cpu2.dcache.SwapReq_miss_rate::total 0.772727 # miss rate for SwapReq accesses 654system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004901 # miss rate for demand accesses 655system.cpu2.dcache.demand_miss_rate::total 0.004901 # miss rate for demand accesses 656system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004901 # miss rate for overall accesses 657system.cpu2.dcache.overall_miss_rate::total 0.004901 # miss rate for overall accesses 658system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17544.585987 # average ReadReq miss latency 659system.cpu2.dcache.ReadReq_avg_miss_latency::total 17544.585987 # average ReadReq miss latency 660system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18233.333333 # average WriteReq miss latency 661system.cpu2.dcache.WriteReq_avg_miss_latency::total 18233.333333 # average WriteReq miss latency 662system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5607.843137 # average SwapReq miss latency 663system.cpu2.dcache.SwapReq_avg_miss_latency::total 5607.843137 # average SwapReq miss latency 664system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency 665system.cpu2.dcache.demand_avg_miss_latency::total 17820.610687 # average overall miss latency 666system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency 667system.cpu2.dcache.overall_avg_miss_latency::total 17820.610687 # average overall miss latency | 668system.cpu2.dcache.occ_blocks::cpu2.data 26.764140 # Average occupied blocks per requestor 669system.cpu2.dcache.occ_percent::cpu2.data 0.052274 # Average percentage of cache occupancy 670system.cpu2.dcache.occ_percent::total 0.052274 # Average percentage of cache occupancy 671system.cpu2.dcache.ReadReq_hits::cpu2.data 42000 # number of ReadReq hits 672system.cpu2.dcache.ReadReq_hits::total 42000 # number of ReadReq hits 673system.cpu2.dcache.WriteReq_hits::cpu2.data 16859 # number of WriteReq hits 674system.cpu2.dcache.WriteReq_hits::total 16859 # number of WriteReq hits 675system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 676system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits 677system.cpu2.dcache.demand_hits::cpu2.data 58859 # number of demand (read+write) hits 678system.cpu2.dcache.demand_hits::total 58859 # number of demand (read+write) hits 679system.cpu2.dcache.overall_hits::cpu2.data 58859 # number of overall hits 680system.cpu2.dcache.overall_hits::total 58859 # number of overall hits 681system.cpu2.dcache.ReadReq_misses::cpu2.data 158 # number of ReadReq misses 682system.cpu2.dcache.ReadReq_misses::total 158 # number of ReadReq misses 683system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 684system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 685system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses 686system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses 687system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses 688system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses 689system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses 690system.cpu2.dcache.overall_misses::total 267 # number of overall misses 691system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2136000 # number of ReadReq miss cycles 692system.cpu2.dcache.ReadReq_miss_latency::total 2136000 # number of ReadReq miss cycles 693system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1926500 # number of WriteReq miss cycles 694system.cpu2.dcache.WriteReq_miss_latency::total 1926500 # number of WriteReq miss cycles 695system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 214000 # number of SwapReq miss cycles 696system.cpu2.dcache.SwapReq_miss_latency::total 214000 # number of SwapReq miss cycles 697system.cpu2.dcache.demand_miss_latency::cpu2.data 4062500 # number of demand (read+write) miss cycles 698system.cpu2.dcache.demand_miss_latency::total 4062500 # number of demand (read+write) miss cycles 699system.cpu2.dcache.overall_miss_latency::cpu2.data 4062500 # number of overall miss cycles 700system.cpu2.dcache.overall_miss_latency::total 4062500 # number of overall miss cycles 701system.cpu2.dcache.ReadReq_accesses::cpu2.data 42158 # number of ReadReq accesses(hits+misses) 702system.cpu2.dcache.ReadReq_accesses::total 42158 # number of ReadReq accesses(hits+misses) 703system.cpu2.dcache.WriteReq_accesses::cpu2.data 16968 # number of WriteReq accesses(hits+misses) 704system.cpu2.dcache.WriteReq_accesses::total 16968 # number of WriteReq accesses(hits+misses) 705system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 706system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 707system.cpu2.dcache.demand_accesses::cpu2.data 59126 # number of demand (read+write) accesses 708system.cpu2.dcache.demand_accesses::total 59126 # number of demand (read+write) accesses 709system.cpu2.dcache.overall_accesses::cpu2.data 59126 # number of overall (read+write) accesses 710system.cpu2.dcache.overall_accesses::total 59126 # number of overall (read+write) accesses 711system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003748 # miss rate for ReadReq accesses 712system.cpu2.dcache.ReadReq_miss_rate::total 0.003748 # miss rate for ReadReq accesses 713system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006424 # miss rate for WriteReq accesses 714system.cpu2.dcache.WriteReq_miss_rate::total 0.006424 # miss rate for WriteReq accesses 715system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.838710 # miss rate for SwapReq accesses 716system.cpu2.dcache.SwapReq_miss_rate::total 0.838710 # miss rate for SwapReq accesses 717system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004516 # miss rate for demand accesses 718system.cpu2.dcache.demand_miss_rate::total 0.004516 # miss rate for demand accesses 719system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004516 # miss rate for overall accesses 720system.cpu2.dcache.overall_miss_rate::total 0.004516 # miss rate for overall accesses 721system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13518.987342 # average ReadReq miss latency 722system.cpu2.dcache.ReadReq_avg_miss_latency::total 13518.987342 # average ReadReq miss latency 723system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17674.311927 # average WriteReq miss latency 724system.cpu2.dcache.WriteReq_avg_miss_latency::total 17674.311927 # average WriteReq miss latency 725system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4115.384615 # average SwapReq miss latency 726system.cpu2.dcache.SwapReq_avg_miss_latency::total 4115.384615 # average SwapReq miss latency 727system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency 728system.cpu2.dcache.demand_avg_miss_latency::total 15215.355805 # average overall miss latency 729system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency 730system.cpu2.dcache.overall_avg_miss_latency::total 15215.355805 # average overall miss latency |
| 668system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu2.dcache.fast_writes 0 # number of fast writes performed 675system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 731system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 732system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 734system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 736system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu2.dcache.fast_writes 0 # number of fast writes performed 738system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 676system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses 677system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 678system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 679system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 680system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses 681system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 682system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 683system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 684system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 685system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses 686system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2440500 # number of ReadReq MSHR miss cycles 687system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2440500 # number of ReadReq MSHR miss cycles 688system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704500 # number of WriteReq MSHR miss cycles 689system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704500 # number of WriteReq MSHR miss cycles 690system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 184000 # number of SwapReq MSHR miss cycles 691system.cpu2.dcache.SwapReq_mshr_miss_latency::total 184000 # number of SwapReq MSHR miss cycles 692system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4145000 # number of demand (read+write) MSHR miss cycles 693system.cpu2.dcache.demand_mshr_miss_latency::total 4145000 # number of demand (read+write) MSHR miss cycles 694system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4145000 # number of overall MSHR miss cycles 695system.cpu2.dcache.overall_mshr_miss_latency::total 4145000 # number of overall MSHR miss cycles 696system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003818 # mshr miss rate for ReadReq accesses 697system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses 698system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008509 # mshr miss rate for WriteReq accesses 699system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008509 # mshr miss rate for WriteReq accesses 700system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.772727 # mshr miss rate for SwapReq accesses 701system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses 702system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for demand accesses 703system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses 704system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses 705system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses 706system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency 707system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency 708system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency 709system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency 710system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency 711system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency 712system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency 713system.cpu2.dcache.demand_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency 714system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency 715system.cpu2.dcache.overall_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency | 739system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 158 # number of ReadReq MSHR misses 740system.cpu2.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 741system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 742system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 743system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses 744system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 745system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 746system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 747system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 748system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 749system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814014 # number of ReadReq MSHR miss cycles 750system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1814014 # number of ReadReq MSHR miss cycles 751system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1708500 # number of WriteReq MSHR miss cycles 752system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1708500 # number of WriteReq MSHR miss cycles 753system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 110000 # number of SwapReq MSHR miss cycles 754system.cpu2.dcache.SwapReq_mshr_miss_latency::total 110000 # number of SwapReq MSHR miss cycles 755system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3522514 # number of demand (read+write) MSHR miss cycles 756system.cpu2.dcache.demand_mshr_miss_latency::total 3522514 # number of demand (read+write) MSHR miss cycles 757system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3522514 # number of overall MSHR miss cycles 758system.cpu2.dcache.overall_mshr_miss_latency::total 3522514 # number of overall MSHR miss cycles 759system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003748 # mshr miss rate for ReadReq accesses 760system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003748 # mshr miss rate for ReadReq accesses 761system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006424 # mshr miss rate for WriteReq accesses 762system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 763system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.838710 # mshr miss rate for SwapReq accesses 764system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.838710 # mshr miss rate for SwapReq accesses 765system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for demand accesses 766system.cpu2.dcache.demand_mshr_miss_rate::total 0.004516 # mshr miss rate for demand accesses 767system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for overall accesses 768system.cpu2.dcache.overall_mshr_miss_rate::total 0.004516 # mshr miss rate for overall accesses 769system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266 # average ReadReq mshr miss latency 770system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266 # average ReadReq mshr miss latency 771system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927 # average WriteReq mshr miss latency 772system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927 # average WriteReq mshr miss latency 773system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2115.384615 # average SwapReq mshr miss latency 774system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2115.384615 # average SwapReq mshr miss latency 775system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency 776system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency 777system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency 778system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency |
| 716system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 779system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 717system.cpu3.numCycles 525940 # number of cpu cycles simulated | 780system.cpu3.numCycles 525586 # number of cpu cycles simulated |
| 718system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 781system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 782system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 720system.cpu3.committedInsts 167814 # Number of instructions committed 721system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed 722system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses | 783system.cpu3.committedInsts 166768 # Number of instructions committed 784system.cpu3.committedOps 166768 # Number of ops (including micro ops) committed 785system.cpu3.num_int_alu_accesses 112266 # Number of integer alu accesses |
| 723system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 724system.cpu3.num_func_calls 637 # number of times a function call or return occured | 786system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 787system.cpu3.num_func_calls 637 # number of times a function call or return occured |
| 725system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls 726system.cpu3.num_int_insts 111369 # number of integer instructions | 788system.cpu3.num_conditional_control_insts 31259 # number of instructions that are conditional controls 789system.cpu3.num_int_insts 112266 # number of integer instructions |
| 727system.cpu3.num_fp_insts 0 # number of float instructions | 790system.cpu3.num_fp_insts 0 # number of float instructions |
| 728system.cpu3.num_int_register_reads 278793 # number of times the integer registers were read 729system.cpu3.num_int_register_writes 105918 # number of times the integer registers were written | 791system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read 792system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written |
| 730system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 731system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written | 793system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 794system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written |
| 732system.cpu3.num_mem_refs 55316 # number of memory refs 733system.cpu3.num_load_insts 41342 # Number of load instructions 734system.cpu3.num_store_insts 13974 # Number of store instructions 735system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles 736system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles 737system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles 738system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles | 795system.cpu3.num_mem_refs 57176 # number of memory refs 796system.cpu3.num_load_insts 41805 # Number of load instructions 797system.cpu3.num_store_insts 15371 # Number of store instructions 798system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles 799system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles 800system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles 801system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles |
| 739system.cpu3.icache.replacements 281 # number of replacements | 802system.cpu3.icache.replacements 281 # number of replacements |
| 740system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use 741system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. | 803system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use 804system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. |
| 742system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. | 805system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. |
| 743system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. | 806system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. |
| 744system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 745system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor 746system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy 747system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy 748system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits 749system.cpu3.icache.ReadReq_hits::total 167480 # number of ReadReq hits 750system.cpu3.icache.demand_hits::cpu3.inst 167480 # number of demand (read+write) hits 751system.cpu3.icache.demand_hits::total 167480 # number of demand (read+write) hits 752system.cpu3.icache.overall_hits::cpu3.inst 167480 # number of overall hits 753system.cpu3.icache.overall_hits::total 167480 # number of overall hits | 808system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor 809system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy 810system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy 811system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # number of ReadReq hits 812system.cpu3.icache.ReadReq_hits::total 166434 # number of ReadReq hits 813system.cpu3.icache.demand_hits::cpu3.inst 166434 # number of demand (read+write) hits 814system.cpu3.icache.demand_hits::total 166434 # number of demand (read+write) hits 815system.cpu3.icache.overall_hits::cpu3.inst 166434 # number of overall hits 816system.cpu3.icache.overall_hits::total 166434 # number of overall hits |
| 754system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 755system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 756system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 757system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 758system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 759system.cpu3.icache.overall_misses::total 367 # number of overall misses | 817system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 818system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 819system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 820system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 821system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 822system.cpu3.icache.overall_misses::total 367 # number of overall misses |
| 760system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5162000 # number of ReadReq miss cycles 761system.cpu3.icache.ReadReq_miss_latency::total 5162000 # number of ReadReq miss cycles 762system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles 763system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles 764system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles 765system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles 766system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) 767system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) 768system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses 769system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses 770system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses 771system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses 772system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses 773system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses 774system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses 775system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses 776system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses 777system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses 778system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency 779system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency 780system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency 781system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency 782system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency 783system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency | 823system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5149000 # number of ReadReq miss cycles 824system.cpu3.icache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles 825system.cpu3.icache.demand_miss_latency::cpu3.inst 5149000 # number of demand (read+write) miss cycles 826system.cpu3.icache.demand_miss_latency::total 5149000 # number of demand (read+write) miss cycles 827system.cpu3.icache.overall_miss_latency::cpu3.inst 5149000 # number of overall miss cycles 828system.cpu3.icache.overall_miss_latency::total 5149000 # number of overall miss cycles 829system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) 830system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) 831system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses 832system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses 833system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses 834system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses 835system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses 836system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses 837system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses 838system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses 839system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # miss rate for overall accesses 840system.cpu3.icache.overall_miss_rate::total 0.002200 # miss rate for overall accesses 841system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752 # average ReadReq miss latency 842system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752 # average ReadReq miss latency 843system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency 844system.cpu3.icache.demand_avg_miss_latency::total 14029.972752 # average overall miss latency 845system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency 846system.cpu3.icache.overall_avg_miss_latency::total 14029.972752 # average overall miss latency |
| 784system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu3.icache.fast_writes 0 # number of fast writes performed 791system.cpu3.icache.cache_copies 0 # number of cache copies performed 792system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 793system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 794system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 795system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 796system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 797system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses | 847system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 848system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 849system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 850system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 851system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 852system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 853system.cpu3.icache.fast_writes 0 # number of fast writes performed 854system.cpu3.icache.cache_copies 0 # number of cache copies performed 855system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 856system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 857system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 858system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 859system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 860system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses |
| 798system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4428000 # number of ReadReq MSHR miss cycles 799system.cpu3.icache.ReadReq_mshr_miss_latency::total 4428000 # number of ReadReq MSHR miss cycles 800system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4428000 # number of demand (read+write) MSHR miss cycles 801system.cpu3.icache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles 802system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4428000 # number of overall MSHR miss cycles 803system.cpu3.icache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles 804system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for ReadReq accesses 805system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002187 # mshr miss rate for ReadReq accesses 806system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for demand accesses 807system.cpu3.icache.demand_mshr_miss_rate::total 0.002187 # mshr miss rate for demand accesses 808system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for overall accesses 809system.cpu3.icache.overall_mshr_miss_rate::total 0.002187 # mshr miss rate for overall accesses 810system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency 811system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12065.395095 # average ReadReq mshr miss latency 812system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency 813system.cpu3.icache.demand_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency 814system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency 815system.cpu3.icache.overall_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency | 861system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4414501 # number of ReadReq MSHR miss cycles 862system.cpu3.icache.ReadReq_mshr_miss_latency::total 4414501 # number of ReadReq MSHR miss cycles 863system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4414501 # number of demand (read+write) MSHR miss cycles 864system.cpu3.icache.demand_mshr_miss_latency::total 4414501 # number of demand (read+write) MSHR miss cycles 865system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4414501 # number of overall MSHR miss cycles 866system.cpu3.icache.overall_mshr_miss_latency::total 4414501 # number of overall MSHR miss cycles 867system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for ReadReq accesses 868system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002200 # mshr miss rate for ReadReq accesses 869system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for demand accesses 870system.cpu3.icache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses 871system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for overall accesses 872system.cpu3.icache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses 873system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average ReadReq mshr miss latency 874system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079 # average ReadReq mshr miss latency 875system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency 876system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency 877system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency 878system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency |
| 816system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 817system.cpu3.dcache.replacements 0 # number of replacements | 879system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 880system.cpu3.dcache.replacements 0 # number of replacements |
| 818system.cpu3.dcache.tagsinuse 26.814972 # Cycle average of tags in use 819system.cpu3.dcache.total_refs 30179 # Total number of references to valid blocks. | 881system.cpu3.dcache.tagsinuse 25.941840 # Cycle average of tags in use 882system.cpu3.dcache.total_refs 33003 # Total number of references to valid blocks. |
| 820system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. | 883system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. |
| 821system.cpu3.dcache.avg_refs 1040.655172 # Average number of references to valid blocks. | 884system.cpu3.dcache.avg_refs 1138.034483 # Average number of references to valid blocks. |
| 822system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 885system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 823system.cpu3.dcache.occ_blocks::cpu3.data 26.814972 # Average occupied blocks per requestor 824system.cpu3.dcache.occ_percent::cpu3.data 0.052373 # Average percentage of cache occupancy 825system.cpu3.dcache.occ_percent::total 0.052373 # Average percentage of cache occupancy 826system.cpu3.dcache.ReadReq_hits::cpu3.data 41164 # number of ReadReq hits 827system.cpu3.dcache.ReadReq_hits::total 41164 # number of ReadReq hits 828system.cpu3.dcache.WriteReq_hits::cpu3.data 13787 # number of WriteReq hits 829system.cpu3.dcache.WriteReq_hits::total 13787 # number of WriteReq hits 830system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits 831system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits 832system.cpu3.dcache.demand_hits::cpu3.data 54951 # number of demand (read+write) hits 833system.cpu3.dcache.demand_hits::total 54951 # number of demand (read+write) hits 834system.cpu3.dcache.overall_hits::cpu3.data 54951 # number of overall hits 835system.cpu3.dcache.overall_hits::total 54951 # number of overall hits 836system.cpu3.dcache.ReadReq_misses::cpu3.data 171 # number of ReadReq misses 837system.cpu3.dcache.ReadReq_misses::total 171 # number of ReadReq misses 838system.cpu3.dcache.WriteReq_misses::cpu3.data 106 # number of WriteReq misses 839system.cpu3.dcache.WriteReq_misses::total 106 # number of WriteReq misses 840system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses 841system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses 842system.cpu3.dcache.demand_misses::cpu3.data 277 # number of demand (read+write) misses 843system.cpu3.dcache.demand_misses::total 277 # number of demand (read+write) misses 844system.cpu3.dcache.overall_misses::cpu3.data 277 # number of overall misses 845system.cpu3.dcache.overall_misses::total 277 # number of overall misses 846system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2803500 # number of ReadReq miss cycles 847system.cpu3.dcache.ReadReq_miss_latency::total 2803500 # number of ReadReq miss cycles 848system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2201500 # number of WriteReq miss cycles 849system.cpu3.dcache.WriteReq_miss_latency::total 2201500 # number of WriteReq miss cycles 850system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 368000 # number of SwapReq miss cycles 851system.cpu3.dcache.SwapReq_miss_latency::total 368000 # number of SwapReq miss cycles 852system.cpu3.dcache.demand_miss_latency::cpu3.data 5005000 # number of demand (read+write) miss cycles 853system.cpu3.dcache.demand_miss_latency::total 5005000 # number of demand (read+write) miss cycles 854system.cpu3.dcache.overall_miss_latency::cpu3.data 5005000 # number of overall miss cycles 855system.cpu3.dcache.overall_miss_latency::total 5005000 # number of overall miss cycles 856system.cpu3.dcache.ReadReq_accesses::cpu3.data 41335 # number of ReadReq accesses(hits+misses) 857system.cpu3.dcache.ReadReq_accesses::total 41335 # number of ReadReq accesses(hits+misses) 858system.cpu3.dcache.WriteReq_accesses::cpu3.data 13893 # number of WriteReq accesses(hits+misses) 859system.cpu3.dcache.WriteReq_accesses::total 13893 # number of WriteReq accesses(hits+misses) 860system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) 861system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) 862system.cpu3.dcache.demand_accesses::cpu3.data 55228 # number of demand (read+write) accesses 863system.cpu3.dcache.demand_accesses::total 55228 # number of demand (read+write) accesses 864system.cpu3.dcache.overall_accesses::cpu3.data 55228 # number of overall (read+write) accesses 865system.cpu3.dcache.overall_accesses::total 55228 # number of overall (read+write) accesses 866system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004137 # miss rate for ReadReq accesses 867system.cpu3.dcache.ReadReq_miss_rate::total 0.004137 # miss rate for ReadReq accesses 868system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007630 # miss rate for WriteReq accesses 869system.cpu3.dcache.WriteReq_miss_rate::total 0.007630 # miss rate for WriteReq accesses 870system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.873418 # miss rate for SwapReq accesses 871system.cpu3.dcache.SwapReq_miss_rate::total 0.873418 # miss rate for SwapReq accesses 872system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005016 # miss rate for demand accesses 873system.cpu3.dcache.demand_miss_rate::total 0.005016 # miss rate for demand accesses 874system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005016 # miss rate for overall accesses 875system.cpu3.dcache.overall_miss_rate::total 0.005016 # miss rate for overall accesses 876system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16394.736842 # average ReadReq miss latency 877system.cpu3.dcache.ReadReq_avg_miss_latency::total 16394.736842 # average ReadReq miss latency 878system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20768.867925 # average WriteReq miss latency 879system.cpu3.dcache.WriteReq_avg_miss_latency::total 20768.867925 # average WriteReq miss latency 880system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5333.333333 # average SwapReq miss latency 881system.cpu3.dcache.SwapReq_avg_miss_latency::total 5333.333333 # average SwapReq miss latency 882system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency 883system.cpu3.dcache.demand_avg_miss_latency::total 18068.592058 # average overall miss latency 884system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency 885system.cpu3.dcache.overall_avg_miss_latency::total 18068.592058 # average overall miss latency | 886system.cpu3.dcache.occ_blocks::cpu3.data 25.941840 # Average occupied blocks per requestor 887system.cpu3.dcache.occ_percent::cpu3.data 0.050668 # Average percentage of cache occupancy 888system.cpu3.dcache.occ_percent::total 0.050668 # Average percentage of cache occupancy 889system.cpu3.dcache.ReadReq_hits::cpu3.data 41638 # number of ReadReq hits 890system.cpu3.dcache.ReadReq_hits::total 41638 # number of ReadReq hits 891system.cpu3.dcache.WriteReq_hits::cpu3.data 15196 # number of WriteReq hits 892system.cpu3.dcache.WriteReq_hits::total 15196 # number of WriteReq hits 893system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 894system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 895system.cpu3.dcache.demand_hits::cpu3.data 56834 # number of demand (read+write) hits 896system.cpu3.dcache.demand_hits::total 56834 # number of demand (read+write) hits 897system.cpu3.dcache.overall_hits::cpu3.data 56834 # number of overall hits 898system.cpu3.dcache.overall_hits::total 56834 # number of overall hits 899system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses 900system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses 901system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 902system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 903system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses 904system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses 905system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 906system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 907system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 908system.cpu3.dcache.overall_misses::total 268 # number of overall misses 909system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2247500 # number of ReadReq miss cycles 910system.cpu3.dcache.ReadReq_miss_latency::total 2247500 # number of ReadReq miss cycles 911system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1908500 # number of WriteReq miss cycles 912system.cpu3.dcache.WriteReq_miss_latency::total 1908500 # number of WriteReq miss cycles 913system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 217500 # number of SwapReq miss cycles 914system.cpu3.dcache.SwapReq_miss_latency::total 217500 # number of SwapReq miss cycles 915system.cpu3.dcache.demand_miss_latency::cpu3.data 4156000 # number of demand (read+write) miss cycles 916system.cpu3.dcache.demand_miss_latency::total 4156000 # number of demand (read+write) miss cycles 917system.cpu3.dcache.overall_miss_latency::cpu3.data 4156000 # number of overall miss cycles 918system.cpu3.dcache.overall_miss_latency::total 4156000 # number of overall miss cycles 919system.cpu3.dcache.ReadReq_accesses::cpu3.data 41797 # number of ReadReq accesses(hits+misses) 920system.cpu3.dcache.ReadReq_accesses::total 41797 # number of ReadReq accesses(hits+misses) 921system.cpu3.dcache.WriteReq_accesses::cpu3.data 15305 # number of WriteReq accesses(hits+misses) 922system.cpu3.dcache.WriteReq_accesses::total 15305 # number of WriteReq accesses(hits+misses) 923system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 924system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 925system.cpu3.dcache.demand_accesses::cpu3.data 57102 # number of demand (read+write) accesses 926system.cpu3.dcache.demand_accesses::total 57102 # number of demand (read+write) accesses 927system.cpu3.dcache.overall_accesses::cpu3.data 57102 # number of overall (read+write) accesses 928system.cpu3.dcache.overall_accesses::total 57102 # number of overall (read+write) accesses 929system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003804 # miss rate for ReadReq accesses 930system.cpu3.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses 931system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007122 # miss rate for WriteReq accesses 932system.cpu3.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses 933system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828125 # miss rate for SwapReq accesses 934system.cpu3.dcache.SwapReq_miss_rate::total 0.828125 # miss rate for SwapReq accesses 935system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004693 # miss rate for demand accesses 936system.cpu3.dcache.demand_miss_rate::total 0.004693 # miss rate for demand accesses 937system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004693 # miss rate for overall accesses 938system.cpu3.dcache.overall_miss_rate::total 0.004693 # miss rate for overall accesses 939system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 14135.220126 # average ReadReq miss latency 940system.cpu3.dcache.ReadReq_avg_miss_latency::total 14135.220126 # average ReadReq miss latency 941system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17509.174312 # average WriteReq miss latency 942system.cpu3.dcache.WriteReq_avg_miss_latency::total 17509.174312 # average WriteReq miss latency 943system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4103.773585 # average SwapReq miss latency 944system.cpu3.dcache.SwapReq_avg_miss_latency::total 4103.773585 # average SwapReq miss latency 945system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency 946system.cpu3.dcache.demand_avg_miss_latency::total 15507.462687 # average overall miss latency 947system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency 948system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency |
| 886system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu3.dcache.fast_writes 0 # number of fast writes performed 893system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 949system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 950system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 951system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 952system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 953system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 954system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 955system.cpu3.dcache.fast_writes 0 # number of fast writes performed 956system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 894system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 171 # number of ReadReq MSHR misses 895system.cpu3.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses 896system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 897system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 898system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses 899system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses 900system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses 901system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses 902system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses 903system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses 904system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2461500 # number of ReadReq MSHR miss cycles 905system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2461500 # number of ReadReq MSHR miss cycles 906system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1989500 # number of WriteReq MSHR miss cycles 907system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1989500 # number of WriteReq MSHR miss cycles 908system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 230000 # number of SwapReq MSHR miss cycles 909system.cpu3.dcache.SwapReq_mshr_miss_latency::total 230000 # number of SwapReq MSHR miss cycles 910system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4451000 # number of demand (read+write) MSHR miss cycles 911system.cpu3.dcache.demand_mshr_miss_latency::total 4451000 # number of demand (read+write) MSHR miss cycles 912system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4451000 # number of overall MSHR miss cycles 913system.cpu3.dcache.overall_mshr_miss_latency::total 4451000 # number of overall MSHR miss cycles 914system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004137 # mshr miss rate for ReadReq accesses 915system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004137 # mshr miss rate for ReadReq accesses 916system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007630 # mshr miss rate for WriteReq accesses 917system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007630 # mshr miss rate for WriteReq accesses 918system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.873418 # mshr miss rate for SwapReq accesses 919system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.873418 # mshr miss rate for SwapReq accesses 920system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for demand accesses 921system.cpu3.dcache.demand_mshr_miss_rate::total 0.005016 # mshr miss rate for demand accesses 922system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for overall accesses 923system.cpu3.dcache.overall_mshr_miss_rate::total 0.005016 # mshr miss rate for overall accesses 924system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14394.736842 # average ReadReq mshr miss latency 925system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14394.736842 # average ReadReq mshr miss latency 926system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18768.867925 # average WriteReq mshr miss latency 927system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18768.867925 # average WriteReq mshr miss latency 928system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3333.333333 # average SwapReq mshr miss latency 929system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3333.333333 # average SwapReq mshr miss latency 930system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16068.592058 # average overall mshr miss latency 931system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16068.592058 # average overall mshr miss latency 932system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16068.592058 # average overall mshr miss latency 933system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16068.592058 # average overall mshr miss latency | 957system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 159 # number of ReadReq MSHR misses 958system.cpu3.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses 959system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses 960system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 961system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses 962system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 963system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 964system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 965system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 966system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 967system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1924510 # number of ReadReq MSHR miss cycles 968system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1924510 # number of ReadReq MSHR miss cycles 969system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1690500 # number of WriteReq MSHR miss cycles 970system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1690500 # number of WriteReq MSHR miss cycles 971system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 111500 # number of SwapReq MSHR miss cycles 972system.cpu3.dcache.SwapReq_mshr_miss_latency::total 111500 # number of SwapReq MSHR miss cycles 973system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3615010 # number of demand (read+write) MSHR miss cycles 974system.cpu3.dcache.demand_mshr_miss_latency::total 3615010 # number of demand (read+write) MSHR miss cycles 975system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3615010 # number of overall MSHR miss cycles 976system.cpu3.dcache.overall_mshr_miss_latency::total 3615010 # number of overall MSHR miss cycles 977system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003804 # mshr miss rate for ReadReq accesses 978system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003804 # mshr miss rate for ReadReq accesses 979system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007122 # mshr miss rate for WriteReq accesses 980system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007122 # mshr miss rate for WriteReq accesses 981system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828125 # mshr miss rate for SwapReq accesses 982system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828125 # mshr miss rate for SwapReq accesses 983system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for demand accesses 984system.cpu3.dcache.demand_mshr_miss_rate::total 0.004693 # mshr miss rate for demand accesses 985system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for overall accesses 986system.cpu3.dcache.overall_mshr_miss_rate::total 0.004693 # mshr miss rate for overall accesses 987system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12103.836478 # average ReadReq mshr miss latency 988system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12103.836478 # average ReadReq mshr miss latency 989system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15509.174312 # average WriteReq mshr miss latency 990system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15509.174312 # average WriteReq mshr miss latency 991system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2103.773585 # average SwapReq mshr miss latency 992system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2103.773585 # average SwapReq mshr miss latency 993system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency 994system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency 995system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency 996system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency |
| 934system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.l2c.replacements 0 # number of replacements | 997system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 998system.l2c.replacements 0 # number of replacements |
| 936system.l2c.tagsinuse 349.061652 # Cycle average of tags in use | 999system.l2c.tagsinuse 349.045938 # Cycle average of tags in use |
| 937system.l2c.total_refs 1220 # Total number of references to valid blocks. 938system.l2c.sampled_refs 429 # Sample count of references to valid blocks. 939system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. 940system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1000system.l2c.total_refs 1220 # Total number of references to valid blocks. 1001system.l2c.sampled_refs 429 # Sample count of references to valid blocks. 1002system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. 1003system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 941system.l2c.occ_blocks::writebacks 0.889079 # Average occupied blocks per requestor 942system.l2c.occ_blocks::cpu0.inst 231.800504 # Average occupied blocks per requestor 943system.l2c.occ_blocks::cpu0.data 54.209816 # Average occupied blocks per requestor 944system.l2c.occ_blocks::cpu1.inst 51.703511 # Average occupied blocks per requestor 945system.l2c.occ_blocks::cpu1.data 6.143370 # Average occupied blocks per requestor 946system.l2c.occ_blocks::cpu2.inst 1.773026 # Average occupied blocks per requestor 947system.l2c.occ_blocks::cpu2.data 0.811968 # Average occupied blocks per requestor 948system.l2c.occ_blocks::cpu3.inst 0.886563 # Average occupied blocks per requestor 949system.l2c.occ_blocks::cpu3.data 0.843815 # Average occupied blocks per requestor | 1004system.l2c.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor 1005system.l2c.occ_blocks::cpu0.inst 231.790377 # Average occupied blocks per requestor 1006system.l2c.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor 1007system.l2c.occ_blocks::cpu1.inst 51.556644 # Average occupied blocks per requestor 1008system.l2c.occ_blocks::cpu1.data 6.123911 # Average occupied blocks per requestor 1009system.l2c.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 1010system.l2c.occ_blocks::cpu2.data 0.843759 # Average occupied blocks per requestor 1011system.l2c.occ_blocks::cpu3.inst 1.030265 # Average occupied blocks per requestor 1012system.l2c.occ_blocks::cpu3.data 0.831019 # Average occupied blocks per requestor |
| 950system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 951system.l2c.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 952system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy | 1013system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 1014system.l2c.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 1015system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy |
| 953system.l2c.occ_percent::cpu1.inst 0.000789 # Average percentage of cache occupancy 954system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy | 1016system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 1017system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy |
| 955system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy | 1018system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy |
| 956system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy 957system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy | 1019system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 1020system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy |
| 958system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 959system.l2c.occ_percent::total 0.005326 # Average percentage of cache occupancy 960system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 961system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 962system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 963system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 964system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 965system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits --- 27 unchanged lines hidden (view full) --- 993system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 994system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 995system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 996system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 997system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 998system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 999system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 1000system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses | 1021system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 1022system.l2c.occ_percent::total 0.005326 # Average percentage of cache occupancy 1023system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 1024system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 1025system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 1026system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 1027system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 1028system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits --- 27 unchanged lines hidden (view full) --- 1056system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 1057system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 1058system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 1059system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 1060system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 1061system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 1062system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 1063system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses |
| 1001system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 1002system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 1003system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses 1004system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses | 1064system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 1065system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 1066system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses 1067system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses |
| 1005system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1006system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 1007system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 1008system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1009system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1010system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1011system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1012system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses --- 7 unchanged lines hidden (view full) --- 1020system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1021system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 1022system.l2c.overall_misses::cpu1.data 23 # number of overall misses 1023system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 1024system.l2c.overall_misses::cpu2.data 16 # number of overall misses 1025system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 1026system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1027system.l2c.overall_misses::total 592 # number of overall misses | 1068system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1069system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 1070system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 1071system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1072system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1073system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1074system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1075system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses --- 7 unchanged lines hidden (view full) --- 1083system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1084system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 1085system.l2c.overall_misses::cpu1.data 23 # number of overall misses 1086system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 1087system.l2c.overall_misses::cpu2.data 16 # number of overall misses 1088system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 1089system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1090system.l2c.overall_misses::total 592 # number of overall misses |
| 1028system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles | 1091system.l2c.ReadReq_miss_latency::cpu0.inst 14926500 # number of ReadReq miss cycles |
| 1029system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles | 1092system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles |
| 1030system.l2c.ReadReq_miss_latency::cpu1.inst 3455000 # number of ReadReq miss cycles 1031system.l2c.ReadReq_miss_latency::cpu1.data 419000 # number of ReadReq miss cycles 1032system.l2c.ReadReq_miss_latency::cpu2.inst 568500 # number of ReadReq miss cycles 1033system.l2c.ReadReq_miss_latency::cpu2.data 100000 # number of ReadReq miss cycles 1034system.l2c.ReadReq_miss_latency::cpu3.inst 385500 # number of ReadReq miss cycles 1035system.l2c.ReadReq_miss_latency::cpu3.data 95500 # number of ReadReq miss cycles 1036system.l2c.ReadReq_miss_latency::total 23392500 # number of ReadReq miss cycles | 1093system.l2c.ReadReq_miss_latency::cpu1.inst 3437500 # number of ReadReq miss cycles 1094system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 1095system.l2c.ReadReq_miss_latency::cpu2.inst 598000 # number of ReadReq miss cycles 1096system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles 1097system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 1098system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles 1099system.l2c.ReadReq_miss_latency::total 23505000 # number of ReadReq miss cycles |
| 1037system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles | 1100system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles |
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| 1060system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 1061system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 1062system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 1063system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 1064system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 1065system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 1066system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 1067system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 1068system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 1069system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1070system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1071system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) | 1123system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 1124system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 1125system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 1126system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 1127system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 1128system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 1129system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 1130system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 1131system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 1132system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1133system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1134system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) |
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| 1112system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses | 1175system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses |
| 1113system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1114system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1115system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1116system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1117system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1118system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1119system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1120system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses --- 7 unchanged lines hidden (view full) --- 1128system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1129system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 1130system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 1131system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 1132system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 1133system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 1134system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 1135system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses | 1176system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1177system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1178system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1179system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1180system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1181system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1182system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1183system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses --- 7 unchanged lines hidden (view full) --- 1191system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1192system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 1193system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 1194system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 1195system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 1196system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 1197system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 1198system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses |
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| 1137system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency | 1200system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency |
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| 1146system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52300 # average ReadExReq miss latency 1147system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52928.571429 # average ReadExReq miss latency 1148system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency 1149system.l2c.ReadExReq_avg_miss_latency::total 52390.845070 # average ReadExReq miss latency 1150system.l2c.demand_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency | 1209system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency 1210system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency 1211system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.785714 # average ReadExReq miss latency 1212system.l2c.ReadExReq_avg_miss_latency::total 52478.866197 # average ReadExReq miss latency 1213system.l2c.demand_avg_miss_latency::cpu0.inst 52373.684211 # average overall miss latency |
| 1151system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency | 1214system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency |
| 1152system.l2c.demand_avg_miss_latency::cpu1.inst 52348.484848 # average overall miss latency 1153system.l2c.demand_avg_miss_latency::cpu1.data 52326.086957 # average overall miss latency 1154system.l2c.demand_avg_miss_latency::cpu2.inst 47375 # average overall miss latency 1155system.l2c.demand_avg_miss_latency::cpu2.data 52562.500000 # average overall miss latency 1156system.l2c.demand_avg_miss_latency::cpu3.inst 42833.333333 # average overall miss latency 1157system.l2c.demand_avg_miss_latency::cpu3.data 52218.750000 # average overall miss latency 1158system.l2c.demand_avg_miss_latency::total 52081.081081 # average overall miss latency 1159system.l2c.overall_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency | 1215system.l2c.demand_avg_miss_latency::cpu1.inst 52083.333333 # average overall miss latency 1216system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency 1217system.l2c.demand_avg_miss_latency::cpu2.inst 49833.333333 # average overall miss latency 1218system.l2c.demand_avg_miss_latency::cpu2.data 53187.500000 # average overall miss latency 1219system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 1220system.l2c.demand_avg_miss_latency::cpu3.data 52156.187500 # average overall miss latency 1221system.l2c.demand_avg_miss_latency::total 52292.228041 # average overall miss latency 1222system.l2c.overall_avg_miss_latency::cpu0.inst 52373.684211 # average overall miss latency |
| 1160system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency | 1223system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency |
| 1161system.l2c.overall_avg_miss_latency::cpu1.inst 52348.484848 # average overall miss latency 1162system.l2c.overall_avg_miss_latency::cpu1.data 52326.086957 # average overall miss latency 1163system.l2c.overall_avg_miss_latency::cpu2.inst 47375 # average overall miss latency 1164system.l2c.overall_avg_miss_latency::cpu2.data 52562.500000 # average overall miss latency 1165system.l2c.overall_avg_miss_latency::cpu3.inst 42833.333333 # average overall miss latency 1166system.l2c.overall_avg_miss_latency::cpu3.data 52218.750000 # average overall miss latency 1167system.l2c.overall_avg_miss_latency::total 52081.081081 # average overall miss latency | 1224system.l2c.overall_avg_miss_latency::cpu1.inst 52083.333333 # average overall miss latency 1225system.l2c.overall_avg_miss_latency::cpu1.data 53000 # average overall miss latency 1226system.l2c.overall_avg_miss_latency::cpu2.inst 49833.333333 # average overall miss latency 1227system.l2c.overall_avg_miss_latency::cpu2.data 53187.500000 # average overall miss latency 1228system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 1229system.l2c.overall_avg_miss_latency::cpu3.data 52156.187500 # average overall miss latency 1230system.l2c.overall_avg_miss_latency::total 52292.228041 # average overall miss latency |
| 1168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1174system.l2c.fast_writes 0 # number of fast writes performed 1175system.l2c.cache_copies 0 # number of cache copies performed | 1231system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1232system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1233system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1234system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1235system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1236system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1237system.l2c.fast_writes 0 # number of fast writes performed 1238system.l2c.cache_copies 0 # number of cache copies performed |
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|
| 1176system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits 1177system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits | 1241system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits 1242system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits |
| 1178system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits 1179system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits | 1243system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits |
| 1180system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits | 1244system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits |
| 1245system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 1246system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits |
|
| 1181system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits 1182system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits | 1247system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits 1248system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits |
| 1183system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits 1184system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits | 1249system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits |
| 1185system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits | 1250system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits |
| 1251system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 1252system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits |
|
| 1186system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 1187system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits | 1253system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 1254system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits |
| 1188system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits 1189system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits | 1255system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits |
| 1190system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1191system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses 1192system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses | 1256system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1257system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses 1258system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses |
| 1193system.l2c.ReadReq_mshr_misses::cpu1.inst 66 # number of ReadReq MSHR misses 1194system.l2c.ReadReq_mshr_misses::cpu1.data 8 # number of ReadReq MSHR misses | 1259system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses 1260system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses |
| 1195system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses 1196system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses | 1261system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses 1262system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses |
| 1197system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses 1198system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses | 1263system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses 1264system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses |
| 1199system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1200system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses | 1265system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1266system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses |
| 1201system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses 1202system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 1203system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses 1204system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses | 1267system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses 1268system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses 1269system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses 1270system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses |
| 1205system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1206system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses 1207system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses 1208system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1209system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1210system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 1211system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses | 1271system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1272system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses 1273system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses 1274system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1275system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1276system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 1277system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses |
| 1212system.l2c.demand_mshr_misses::cpu1.inst 66 # number of demand (read+write) MSHR misses 1213system.l2c.demand_mshr_misses::cpu1.data 23 # number of demand (read+write) MSHR misses | 1278system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses 1279system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses |
| 1214system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses 1215system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses | 1280system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses 1281system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses |
| 1216system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses 1217system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses | 1282system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses 1283system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses |
| 1218system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 1219system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 1220system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses | 1284system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 1285system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 1286system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses |
| 1221system.l2c.overall_mshr_misses::cpu1.inst 66 # number of overall MSHR misses 1222system.l2c.overall_mshr_misses::cpu1.data 23 # number of overall MSHR misses | 1287system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses 1288system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses |
| 1223system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses 1224system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses | 1289system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses 1290system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses |
| 1225system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1226system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses | 1291system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses 1292system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses |
| 1227system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses | 1293system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses |
| 1228system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11405500 # number of ReadReq MSHR miss cycles | 1294system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles |
| 1229system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles | 1295system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles |
| 1230system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2640000 # number of ReadReq MSHR miss cycles 1231system.l2c.ReadReq_mshr_miss_latency::cpu1.data 320000 # number of ReadReq MSHR miss cycles 1232system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 82500 # number of ReadReq MSHR miss cycles | 1296system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles 1297system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles 1298system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles |
| 1233system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles | 1299system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles |
| 1234system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles 1235system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles 1236system.l2c.ReadReq_mshr_miss_latency::total 17208000 # number of ReadReq MSHR miss cycles 1237system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1124491 # number of UpgradeReq MSHR miss cycles 1238system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 601497 # number of UpgradeReq MSHR miss cycles 1239system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 642995 # number of UpgradeReq MSHR miss cycles 1240system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 840000 # number of UpgradeReq MSHR miss cycles 1241system.l2c.UpgradeReq_mshr_miss_latency::total 3208983 # number of UpgradeReq MSHR miss cycles | 1300system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles 1301system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 1302system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 1303system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 1304system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 764491 # number of UpgradeReq MSHR miss cycles 1305system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 1306system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles 1307system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles |
| 1242system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles | 1308system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles |
| 1243system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles 1244system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 571500 # number of ReadExReq MSHR miss cycles 1245system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 569500 # number of ReadExReq MSHR miss cycles 1246system.l2c.ReadExReq_mshr_miss_latency::total 5705000 # number of ReadExReq MSHR miss cycles 1247system.l2c.demand_mshr_miss_latency::cpu0.inst 11405500 # number of demand (read+write) MSHR miss cycles | 1309system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles 1310system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles 1311system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560499 # number of ReadExReq MSHR miss cycles 1312system.l2c.ReadExReq_mshr_miss_latency::total 5719499 # number of ReadExReq MSHR miss cycles 1313system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles |
| 1248system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles | 1314system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles |
| 1249system.l2c.demand_mshr_miss_latency::cpu1.inst 2640000 # number of demand (read+write) MSHR miss cycles 1250system.l2c.demand_mshr_miss_latency::cpu1.data 920000 # number of demand (read+write) MSHR miss cycles 1251system.l2c.demand_mshr_miss_latency::cpu2.inst 82500 # number of demand (read+write) MSHR miss cycles 1252system.l2c.demand_mshr_miss_latency::cpu2.data 611500 # number of demand (read+write) MSHR miss cycles 1253system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles 1254system.l2c.demand_mshr_miss_latency::cpu3.data 609500 # number of demand (read+write) MSHR miss cycles 1255system.l2c.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles 1256system.l2c.overall_mshr_miss_latency::cpu0.inst 11405500 # number of overall MSHR miss cycles | 1315system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles 1316system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles 1317system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles 1318system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles 1319system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles 1320system.l2c.demand_mshr_miss_latency::cpu3.data 640499 # number of demand (read+write) MSHR miss cycles 1321system.l2c.demand_mshr_miss_latency::total 22942499 # number of demand (read+write) MSHR miss cycles 1322system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles |
| 1257system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles | 1323system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles |
| 1258system.l2c.overall_mshr_miss_latency::cpu1.inst 2640000 # number of overall MSHR miss cycles 1259system.l2c.overall_mshr_miss_latency::cpu1.data 920000 # number of overall MSHR miss cycles 1260system.l2c.overall_mshr_miss_latency::cpu2.inst 82500 # number of overall MSHR miss cycles 1261system.l2c.overall_mshr_miss_latency::cpu2.data 611500 # number of overall MSHR miss cycles 1262system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles 1263system.l2c.overall_mshr_miss_latency::cpu3.data 609500 # number of overall MSHR miss cycles 1264system.l2c.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles | 1324system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles 1325system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles 1326system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles 1327system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles 1328system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles 1329system.l2c.overall_mshr_miss_latency::cpu3.data 640499 # number of overall MSHR miss cycles 1330system.l2c.overall_mshr_miss_latency::total 22942499 # number of overall MSHR miss cycles |
| 1265system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1266system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses | 1331system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1332system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses |
| 1267system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for ReadReq accesses 1268system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.727273 # mshr miss rate for ReadReq accesses | 1333system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1334system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses |
| 1269system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 1270system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses | 1335system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 1336system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses |
| 1271system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1272system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses | 1337system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 1338system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses |
| 1273system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 1274system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1275system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1276system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1277system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 1339system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 1340system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1341system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1342system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1343system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 1278system.l2c.UpgradeReq_mshr_miss_rate::total 0.975610 # mshr miss rate for UpgradeReq accesses | 1344system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses |
| 1279system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1280system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1281system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1282system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1283system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1284system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1285system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses | 1345system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1346system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1347system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1348system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1349system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1350system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1351system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses |
| 1286system.l2c.demand_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for demand accesses 1287system.l2c.demand_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for demand accesses | 1352system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1353system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses |
| 1288system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses 1289system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses | 1354system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses 1355system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses |
| 1290system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1291system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses | 1356system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses 1357system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses |
| 1292system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1293system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1294system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses | 1358system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1359system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1360system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses |
| 1295system.l2c.overall_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for overall accesses 1296system.l2c.overall_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for overall accesses | 1361system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1362system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses |
| 1297system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses 1298system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses | 1363system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses 1364system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses |
| 1299system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1300system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses | 1365system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses 1366system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses |
| 1301system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses | 1367system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses |
| 1302system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average ReadReq mshr miss latency | 1368system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency |
| 1303system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency | 1369system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency |
| 1304system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency | 1370system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency |
| 1305system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency | 1371system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency |
| 1306system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency | 1372system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency |
| 1307system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1308system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1309system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency | 1373system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1374system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1375system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency |
| 1310system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency 1311system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency 1312system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency 1313system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency | 1376system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 1377system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1378system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40236.368421 # average UpgradeReq mshr miss latency 1379system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency |
| 1314system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency | 1380system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency |
| 1315system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency | 1381system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency |
| 1316system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency | 1382system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency |
| 1317system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency 1318system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency 1319system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency 1320system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency 1321system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency | 1383system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency 1384system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency 1385system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857 # average ReadExReq mshr miss latency 1386system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency 1387system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency |
| 1322system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency | 1388system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency |
| 1323system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1324system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency 1325system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency 1326system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency | 1389system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 1390system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency 1391system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 1392system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency |
| 1327system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency | 1393system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency |
| 1328system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency 1329system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency 1330system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency | 1394system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency 1395system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency 1396system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency |
| 1331system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency | 1397system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency |
| 1332system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1333system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency 1334system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency 1335system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency | 1398system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 1399system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency 1400system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 1401system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency |
| 1336system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency | 1402system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency |
| 1337system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency 1338system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency | 1403system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency 1404system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency |
| 1339system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1340 1341---------- End Simulation Statistics ---------- | 1405system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1406 1407---------- End Simulation Statistics ---------- |