| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262299000 # Number of ticks simulated 5final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000269 # Number of seconds simulated 4sim_ticks 268912000 # Number of ticks simulated 5final_tick 268912000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1271827 # Simulator instruction rate (inst/s) 8host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 503510999 # Simulator tick rate (ticks/s) 10host_mem_usage 230932 # Number of bytes of host memory used 11host_seconds 0.52 # Real time elapsed on the host 12sim_insts 662502 # Number of instructions simulated 13sim_ops 662502 # Number of ops (including micro ops) simulated | 7host_inst_rate 548575 # Simulator instruction rate (inst/s) 8host_op_rate 548567 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 220132321 # Simulator tick rate (ticks/s) 10host_mem_usage 230896 # Number of bytes of host memory used 11host_seconds 1.22 # Real time elapsed on the host 12sim_insts 670117 # Number of instructions simulated 13sim_ops 670117 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory | 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory |
| 25system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory | 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory |
| 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory | 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory | 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory |
| 37system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu0.inst 67828881 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 39269352 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14041768 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5235914 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 475992 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3569941 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1903969 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3807937 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 136133754 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 67828881 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14041768 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 475992 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1903969 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 84250610 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 67828881 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 39269352 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14041768 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5235914 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 475992 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3569941 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1903969 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3807937 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 136133754 # Total bandwidth to/from this memory (bytes/s) |
| 60system.cpu0.workload.num_syscalls 89 # Number of system calls | 60system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 61system.cpu0.numCycles 524598 # number of cpu cycles simulated | 61system.cpu0.numCycles 537824 # number of cpu cycles simulated |
| 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 64system.cpu0.committedInsts 158353 # Number of instructions committed 65system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses | 64system.cpu0.committedInsts 160927 # Number of instructions committed 65system.cpu0.committedOps 160927 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 110780 # Number of integer alu accesses |
| 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 68system.cpu0.num_func_calls 390 # number of times a function call or return occured | 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 68system.cpu0.num_func_calls 390 # number of times a function call or return occured |
| 69system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls 70system.cpu0.num_int_insts 109064 # number of integer instructions | 69system.cpu0.num_conditional_control_insts 26423 # number of instructions that are conditional controls 70system.cpu0.num_int_insts 110780 # number of integer instructions |
| 71system.cpu0.num_fp_insts 0 # number of float instructions | 71system.cpu0.num_fp_insts 0 # number of float instructions |
| 72system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read 73system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written | 72system.cpu0.num_int_register_reads 320484 # number of times the integer registers were read 73system.cpu0.num_int_register_writes 112387 # number of times the integer registers were written |
| 74system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 75system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written | 74system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 75system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written |
| 76system.cpu0.num_mem_refs 73905 # number of memory refs 77system.cpu0.num_load_insts 48930 # Number of load instructions 78system.cpu0.num_store_insts 24975 # Number of store instructions | 76system.cpu0.num_mem_refs 75192 # number of memory refs 77system.cpu0.num_load_insts 49788 # Number of load instructions 78system.cpu0.num_store_insts 25404 # Number of store instructions |
| 79system.cpu0.num_idle_cycles 0 # Number of idle cycles | 79system.cpu0.num_idle_cycles 0 # Number of idle cycles |
| 80system.cpu0.num_busy_cycles 524598 # Number of busy cycles | 80system.cpu0.num_busy_cycles 537824 # Number of busy cycles |
| 81system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 82system.cpu0.idle_fraction 0 # Percentage of idle cycles 83system.cpu0.icache.replacements 215 # number of replacements | 81system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 82system.cpu0.idle_fraction 0 # Percentage of idle cycles 83system.cpu0.icache.replacements 215 # number of replacements |
| 84system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use 85system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. | 84system.cpu0.icache.tagsinuse 212.253377 # Cycle average of tags in use 85system.cpu0.icache.total_refs 160523 # Total number of references to valid blocks. |
| 86system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. | 86system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. |
| 87system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. | 87system.cpu0.icache.avg_refs 343.732334 # Average number of references to valid blocks. |
| 88system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 88system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 89system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor 90system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy 91system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy 92system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits 93system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits 94system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits 95system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits 96system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits 97system.cpu0.icache.overall_hits::total 157949 # number of overall hits | 89system.cpu0.icache.occ_blocks::cpu0.inst 212.253377 # Average occupied blocks per requestor 90system.cpu0.icache.occ_percent::cpu0.inst 0.414557 # Average percentage of cache occupancy 91system.cpu0.icache.occ_percent::total 0.414557 # Average percentage of cache occupancy 92system.cpu0.icache.ReadReq_hits::cpu0.inst 160523 # number of ReadReq hits 93system.cpu0.icache.ReadReq_hits::total 160523 # number of ReadReq hits 94system.cpu0.icache.demand_hits::cpu0.inst 160523 # number of demand (read+write) hits 95system.cpu0.icache.demand_hits::total 160523 # number of demand (read+write) hits 96system.cpu0.icache.overall_hits::cpu0.inst 160523 # number of overall hits 97system.cpu0.icache.overall_hits::total 160523 # number of overall hits |
| 98system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 99system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 100system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 101system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 102system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 103system.cpu0.icache.overall_misses::total 467 # number of overall misses | 98system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 99system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 100system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 101system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 102system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 103system.cpu0.icache.overall_misses::total 467 # number of overall misses |
| 104system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles 105system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles 106system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles 107system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles 108system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles 109system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles 110system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) 111system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) 112system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses 113system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses 114system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses 115system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses 116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses 117system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses 118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses 119system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses 120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses 121system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses 122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency 123system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency 124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 125system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency 126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 127system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency | 104system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles 105system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles 106system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles 107system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles 108system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles 109system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles 110system.cpu0.icache.ReadReq_accesses::cpu0.inst 160990 # number of ReadReq accesses(hits+misses) 111system.cpu0.icache.ReadReq_accesses::total 160990 # number of ReadReq accesses(hits+misses) 112system.cpu0.icache.demand_accesses::cpu0.inst 160990 # number of demand (read+write) accesses 113system.cpu0.icache.demand_accesses::total 160990 # number of demand (read+write) accesses 114system.cpu0.icache.overall_accesses::cpu0.inst 160990 # number of overall (read+write) accesses 115system.cpu0.icache.overall_accesses::total 160990 # number of overall (read+write) accesses 116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses 117system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses 118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses 119system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses 120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses 121system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses 122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency 123system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency 124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency 125system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency 126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency 127system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency |
| 128system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 134system.cpu0.icache.fast_writes 0 # number of fast writes performed 135system.cpu0.icache.cache_copies 0 # number of cache copies performed 136system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 137system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 138system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 139system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 140system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 141system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses | 128system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 134system.cpu0.icache.fast_writes 0 # number of fast writes performed 135system.cpu0.icache.cache_copies 0 # number of cache copies performed 136system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 137system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 138system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 139system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 140system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 141system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses |
| 142system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles 143system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 144system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles 145system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles 146system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles 147system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles 148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses 149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses 150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses 151system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses 152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses 153system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses 154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency 155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency 156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 157system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency 158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 159system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency | 142system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles 143system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles 144system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles 145system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles 146system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles 147system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles 148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses 149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses 150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses 151system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses 152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses 153system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses 154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency 155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency 156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency 157system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency 158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency 159system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency |
| 160system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu0.dcache.replacements 2 # number of replacements | 160system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu0.dcache.replacements 2 # number of replacements |
| 162system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use 163system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. | 162system.cpu0.dcache.tagsinuse 145.513886 # Cycle average of tags in use 163system.cpu0.dcache.total_refs 74668 # Total number of references to valid blocks. |
| 164system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. | 164system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. |
| 165system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. | 165system.cpu0.dcache.avg_refs 447.113772 # Average number of references to valid blocks. |
| 166system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 166system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 167system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor 168system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy 169system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy 170system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits 171system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits 172system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits 173system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits | 167system.cpu0.dcache.occ_blocks::cpu0.data 145.513886 # Average occupied blocks per requestor 168system.cpu0.dcache.occ_percent::cpu0.data 0.284207 # Average percentage of cache occupancy 169system.cpu0.dcache.occ_percent::total 0.284207 # Average percentage of cache occupancy 170system.cpu0.dcache.ReadReq_hits::cpu0.data 49616 # number of ReadReq hits 171system.cpu0.dcache.ReadReq_hits::total 49616 # number of ReadReq hits 172system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits 173system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits |
| 174system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 175system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits | 174system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 175system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits |
| 176system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits 177system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits 178system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits 179system.cpu0.dcache.overall_hits::total 73499 # number of overall hits | 176system.cpu0.dcache.demand_hits::cpu0.data 74786 # number of demand (read+write) hits 177system.cpu0.dcache.demand_hits::total 74786 # number of demand (read+write) hits 178system.cpu0.dcache.overall_hits::cpu0.data 74786 # number of overall hits 179system.cpu0.dcache.overall_hits::total 74786 # number of overall hits |
| 180system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses 181system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 182system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 183system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 184system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 185system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 186system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses 187system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses 188system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses 189system.cpu0.dcache.overall_misses::total 345 # number of overall misses | 180system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses 181system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 182system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 183system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 184system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 185system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 186system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses 187system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses 188system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses 189system.cpu0.dcache.overall_misses::total 345 # number of overall misses |
| 190system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles 191system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles 192system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles 193system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles 194system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles 195system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles 196system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles 197system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles 198system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles 199system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles 200system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) 201system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) 202system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) 203system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) | 190system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles 191system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles 192system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles 193system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles 194system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles 195system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles 196system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles 197system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles 198system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles 199system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles 200system.cpu0.dcache.ReadReq_accesses::cpu0.data 49778 # number of ReadReq accesses(hits+misses) 201system.cpu0.dcache.ReadReq_accesses::total 49778 # number of ReadReq accesses(hits+misses) 202system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) 203system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) |
| 204system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 205system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 204system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 205system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 206system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses 207system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses 208system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses 209system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses 210system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses 211system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses 212system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses 213system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses | 206system.cpu0.dcache.demand_accesses::cpu0.data 75131 # number of demand (read+write) accesses 207system.cpu0.dcache.demand_accesses::total 75131 # number of demand (read+write) accesses 208system.cpu0.dcache.overall_accesses::cpu0.data 75131 # number of overall (read+write) accesses 209system.cpu0.dcache.overall_accesses::total 75131 # number of overall (read+write) accesses 210system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003254 # miss rate for ReadReq accesses 211system.cpu0.dcache.ReadReq_miss_rate::total 0.003254 # miss rate for ReadReq accesses 212system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses 213system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses |
| 214system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 215system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses | 214system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 215system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses |
| 216system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses 217system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses 218system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses 219system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses 220system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency 221system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency 222system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency 223system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency 224system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency 225system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency 226system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency 227system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency 228system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency 229system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency | 216system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses 217system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses 218system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses 219system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses 220system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency 221system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency 222system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency 223system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency 224system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency 225system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency 226system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency 227system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency 228system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency 229system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency |
| 230system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 231system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 232system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 233system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 234system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 235system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 236system.cpu0.dcache.fast_writes 0 # number of fast writes performed 237system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 242system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 243system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 244system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 245system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 246system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses 247system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses 248system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses 249system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses | 230system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 231system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 232system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 233system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 234system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 235system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 236system.cpu0.dcache.fast_writes 0 # number of fast writes performed 237system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 242system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 243system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 244system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 245system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 246system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses 247system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses 248system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses 249system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses |
| 250system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles 251system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles 252system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles 253system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles 254system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles 255system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles 256system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles 257system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles 258system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles 259system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles 260system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses 261system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses 262system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses 263system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses | 250system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles 251system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles 252system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles 253system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles 254system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles 255system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles 256system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles 257system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles 258system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles 259system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles 260system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003254 # mshr miss rate for ReadReq accesses 261system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003254 # mshr miss rate for ReadReq accesses 262system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses 263system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses |
| 264system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 265system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses | 264system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 265system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses |
| 266system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses 267system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses 268system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses 269system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses 270system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency 271system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency 272system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency 273system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency 274system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency 275system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency 276system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency 277system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency 278system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency 279system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency | 266system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses 267system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses 268system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses 269system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses 270system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency 271system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency 272system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency 273system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency 274system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency 275system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency 276system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency 277system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency 278system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency 279system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency |
| 280system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 280system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 281system.cpu1.numCycles 524598 # number of cpu cycles simulated | 281system.cpu1.numCycles 537824 # number of cpu cycles simulated |
| 282system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 282system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 284system.cpu1.committedInsts 172389 # Number of instructions committed 285system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed 286system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses | 284system.cpu1.committedInsts 159902 # Number of instructions committed 285system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed 286system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses |
| 287system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 288system.cpu1.num_func_calls 637 # number of times a function call or return occured | 287system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 288system.cpu1.num_func_calls 637 # number of times a function call or return occured |
| 289system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls 290system.cpu1.num_int_insts 107964 # number of integer instructions | 289system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls 290system.cpu1.num_int_insts 114536 # number of integer instructions |
| 291system.cpu1.num_fp_insts 0 # number of float instructions | 291system.cpu1.num_fp_insts 0 # number of float instructions |
| 292system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read 293system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written | 292system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read 293system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written |
| 294system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 295system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written | 294system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 295system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written |
| 296system.cpu1.num_mem_refs 47914 # number of memory refs 297system.cpu1.num_load_insts 39632 # Number of load instructions 298system.cpu1.num_store_insts 8282 # Number of store instructions 299system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles 300system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles 301system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles 302system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles | 296system.cpu1.num_mem_refs 64016 # number of memory refs 297system.cpu1.num_load_insts 42937 # Number of load instructions 298system.cpu1.num_store_insts 21079 # Number of store instructions 299system.cpu1.num_idle_cycles 71606.001734 # Number of idle cycles 300system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles 301system.cpu1.not_idle_fraction 0.866860 # Percentage of non-idle cycles 302system.cpu1.idle_fraction 0.133140 # Percentage of idle cycles |
| 303system.cpu1.icache.replacements 280 # number of replacements | 303system.cpu1.icache.replacements 280 # number of replacements |
| 304system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use 305system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. | 304system.cpu1.icache.tagsinuse 69.902178 # Cycle average of tags in use 305system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. |
| 306system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. | 306system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. |
| 307system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. | 307system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. |
| 308system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 308system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 309system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor 310system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy 311system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy 312system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits 313system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits 314system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits 315system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits 316system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits 317system.cpu1.icache.overall_hits::total 172056 # number of overall hits | 309system.cpu1.icache.occ_blocks::cpu1.inst 69.902178 # Average occupied blocks per requestor 310system.cpu1.icache.occ_percent::cpu1.inst 0.136528 # Average percentage of cache occupancy 311system.cpu1.icache.occ_percent::total 0.136528 # Average percentage of cache occupancy 312system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits 313system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits 314system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits 315system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits 316system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits 317system.cpu1.icache.overall_hits::total 159569 # number of overall hits |
| 318system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 319system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 320system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 321system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 322system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 323system.cpu1.icache.overall_misses::total 366 # number of overall misses | 318system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 319system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 320system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 321system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 322system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 323system.cpu1.icache.overall_misses::total 366 # number of overall misses |
| 324system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles 325system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles 326system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles 327system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles 328system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles 329system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles 330system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) 331system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) 332system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses 333system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses 334system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses 335system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses 336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses 337system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses 338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses 339system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses 340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses 341system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses 342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency 343system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency 344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency 345system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency 346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency 347system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency | 324system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles 325system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles 326system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles 327system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles 328system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles 329system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles 330system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) 331system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) 332system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses 333system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses 334system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses 335system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses 336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses 337system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses 338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses 339system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses 340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses 341system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses 342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency 343system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency 344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency 345system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency 346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency 347system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency |
| 348system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu1.icache.fast_writes 0 # number of fast writes performed 355system.cpu1.icache.cache_copies 0 # number of cache copies performed 356system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 357system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 358system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 359system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 360system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 361system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 348system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu1.icache.fast_writes 0 # number of fast writes performed 355system.cpu1.icache.cache_copies 0 # number of cache copies performed 356system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 357system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 358system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 359system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 360system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 361system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 362system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles 363system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles 364system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles 365system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles 366system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles 367system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles 368system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses 369system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses 370system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses 371system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses 372system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses 373system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses 374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency 375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency 376system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency 377system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency 378system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency 379system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency | 362system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6886000 # number of ReadReq MSHR miss cycles 363system.cpu1.icache.ReadReq_mshr_miss_latency::total 6886000 # number of ReadReq MSHR miss cycles 364system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6886000 # number of demand (read+write) MSHR miss cycles 365system.cpu1.icache.demand_mshr_miss_latency::total 6886000 # number of demand (read+write) MSHR miss cycles 366system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6886000 # number of overall MSHR miss cycles 367system.cpu1.icache.overall_mshr_miss_latency::total 6886000 # number of overall MSHR miss cycles 368system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for ReadReq accesses 369system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002288 # mshr miss rate for ReadReq accesses 370system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for demand accesses 371system.cpu1.icache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses 372system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for overall accesses 373system.cpu1.icache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses 374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average ReadReq mshr miss latency 375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650 # average ReadReq mshr miss latency 376system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency 377system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency 378system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency 379system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency |
| 380system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu1.dcache.replacements 0 # number of replacements | 380system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu1.dcache.replacements 0 # number of replacements |
| 382system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use 383system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. | 382system.cpu1.dcache.tagsinuse 27.730072 # Cycle average of tags in use 383system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks. |
| 384system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. | 384system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. |
| 385system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. | 385system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks. |
| 386system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 386system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 387system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor 388system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy 389system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy 390system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits 391system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits 392system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits 393system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits 394system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits 395system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits 396system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits 397system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits 398system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits 399system.cpu1.dcache.overall_hits::total 47544 # number of overall hits 400system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses 401system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses 402system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses 403system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses 404system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses 405system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses 406system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses 407system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses 408system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses 409system.cpu1.dcache.overall_misses::total 277 # number of overall misses 410system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles 411system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles 412system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles 413system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles 414system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles 415system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles 416system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles 417system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles 418system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles 419system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles 420system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses) 421system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses) 422system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) 423system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) 424system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) 425system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) 426system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses 427system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses 428system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses 429system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses 430system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses 431system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses 432system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses 433system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses 434system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses 435system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses 436system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses 437system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses 438system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses 439system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses 440system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency 441system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency 442system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency 443system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency 444system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency 445system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency 446system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency 447system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency 448system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency 449system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency | 387system.cpu1.dcache.occ_blocks::cpu1.data 27.730072 # Average occupied blocks per requestor 388system.cpu1.dcache.occ_percent::cpu1.data 0.054160 # Average percentage of cache occupancy 389system.cpu1.dcache.occ_percent::total 0.054160 # Average percentage of cache occupancy 390system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits 391system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits 392system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits 393system.cpu1.dcache.WriteReq_hits::total 20903 # number of WriteReq hits 394system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits 395system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits 396system.cpu1.dcache.demand_hits::cpu1.data 63679 # number of demand (read+write) hits 397system.cpu1.dcache.demand_hits::total 63679 # number of demand (read+write) hits 398system.cpu1.dcache.overall_hits::cpu1.data 63679 # number of overall hits 399system.cpu1.dcache.overall_hits::total 63679 # number of overall hits 400system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses 401system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses 402system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 403system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 404system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses 405system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses 406system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses 407system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses 408system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses 409system.cpu1.dcache.overall_misses::total 259 # number of overall misses 410system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3030000 # number of ReadReq miss cycles 411system.cpu1.dcache.ReadReq_miss_latency::total 3030000 # number of ReadReq miss cycles 412system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2410000 # number of WriteReq miss cycles 413system.cpu1.dcache.WriteReq_miss_latency::total 2410000 # number of WriteReq miss cycles 414system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 772000 # number of SwapReq miss cycles 415system.cpu1.dcache.SwapReq_miss_latency::total 772000 # number of SwapReq miss cycles 416system.cpu1.dcache.demand_miss_latency::cpu1.data 5440000 # number of demand (read+write) miss cycles 417system.cpu1.dcache.demand_miss_latency::total 5440000 # number of demand (read+write) miss cycles 418system.cpu1.dcache.overall_miss_latency::cpu1.data 5440000 # number of overall miss cycles 419system.cpu1.dcache.overall_miss_latency::total 5440000 # number of overall miss cycles 420system.cpu1.dcache.ReadReq_accesses::cpu1.data 42929 # number of ReadReq accesses(hits+misses) 421system.cpu1.dcache.ReadReq_accesses::total 42929 # number of ReadReq accesses(hits+misses) 422system.cpu1.dcache.WriteReq_accesses::cpu1.data 21009 # number of WriteReq accesses(hits+misses) 423system.cpu1.dcache.WriteReq_accesses::total 21009 # number of WriteReq accesses(hits+misses) 424system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) 425system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 426system.cpu1.dcache.demand_accesses::cpu1.data 63938 # number of demand (read+write) accesses 427system.cpu1.dcache.demand_accesses::total 63938 # number of demand (read+write) accesses 428system.cpu1.dcache.overall_accesses::cpu1.data 63938 # number of overall (read+write) accesses 429system.cpu1.dcache.overall_accesses::total 63938 # number of overall (read+write) accesses 430system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003564 # miss rate for ReadReq accesses 431system.cpu1.dcache.ReadReq_miss_rate::total 0.003564 # miss rate for ReadReq accesses 432system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005045 # miss rate for WriteReq accesses 433system.cpu1.dcache.WriteReq_miss_rate::total 0.005045 # miss rate for WriteReq accesses 434system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.852941 # miss rate for SwapReq accesses 435system.cpu1.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses 436system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004051 # miss rate for demand accesses 437system.cpu1.dcache.demand_miss_rate::total 0.004051 # miss rate for demand accesses 438system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004051 # miss rate for overall accesses 439system.cpu1.dcache.overall_miss_rate::total 0.004051 # miss rate for overall accesses 440system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569 # average ReadReq miss latency 441system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569 # average ReadReq miss latency 442system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057 # average WriteReq miss latency 443system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057 # average WriteReq miss latency 444system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828 # average SwapReq miss latency 445system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828 # average SwapReq miss latency 446system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency 447system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004 # average overall miss latency 448system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency 449system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004 # average overall miss latency |
| 450system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 451system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 452system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 453system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 454system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 455system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 456system.cpu1.dcache.fast_writes 0 # number of fast writes performed 457system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 450system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 451system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 452system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 453system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 454system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 455system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 456system.cpu1.dcache.fast_writes 0 # number of fast writes performed 457system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 458system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses 459system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 460system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses 461system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses 462system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses 463system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses 464system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses 465system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses 466system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses 467system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses 468system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles 469system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles 470system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles 471system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles 472system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles 473system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles 474system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles 475system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles 476system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles 477system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles 478system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses 479system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses 480system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses 481system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses 482system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses 483system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses 484system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses 485system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses 486system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses 487system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses 488system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency 489system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency 490system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency 491system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency 492system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency 493system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency 494system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency 495system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency 496system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency 497system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency | 458system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses 459system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses 460system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 461system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 462system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses 463system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 464system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses 465system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 466system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses 467system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 468system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2570001 # number of ReadReq MSHR miss cycles 469system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles 470system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092000 # number of WriteReq MSHR miss cycles 471system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2092000 # number of WriteReq MSHR miss cycles 472system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 598000 # number of SwapReq MSHR miss cycles 473system.cpu1.dcache.SwapReq_mshr_miss_latency::total 598000 # number of SwapReq MSHR miss cycles 474system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4662001 # number of demand (read+write) MSHR miss cycles 475system.cpu1.dcache.demand_mshr_miss_latency::total 4662001 # number of demand (read+write) MSHR miss cycles 476system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4662001 # number of overall MSHR miss cycles 477system.cpu1.dcache.overall_mshr_miss_latency::total 4662001 # number of overall MSHR miss cycles 478system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003564 # mshr miss rate for ReadReq accesses 479system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003564 # mshr miss rate for ReadReq accesses 480system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.005045 # mshr miss rate for WriteReq accesses 481system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.005045 # mshr miss rate for WriteReq accesses 482system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.852941 # mshr miss rate for SwapReq accesses 483system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses 484system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for demand accesses 485system.cpu1.dcache.demand_mshr_miss_rate::total 0.004051 # mshr miss rate for demand accesses 486system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for overall accesses 487system.cpu1.dcache.overall_mshr_miss_rate::total 0.004051 # mshr miss rate for overall accesses 488system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157 # average ReadReq mshr miss latency 489system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157 # average ReadReq mshr miss latency 490system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057 # average WriteReq mshr miss latency 491system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057 # average WriteReq mshr miss latency 492system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828 # average SwapReq mshr miss latency 493system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828 # average SwapReq mshr miss latency 494system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency 495system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency 496system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency 497system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency |
| 498system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 498system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 499system.cpu2.numCycles 524598 # number of cpu cycles simulated | 499system.cpu2.numCycles 537824 # number of cpu cycles simulated |
| 500system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 500system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 502system.cpu2.committedInsts 165564 # Number of instructions committed 503system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed 504system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses | 502system.cpu2.committedInsts 177221 # Number of instructions committed 503system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed 504system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses |
| 505system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 506system.cpu2.num_func_calls 637 # number of times a function call or return occured | 505system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 506system.cpu2.num_func_calls 637 # number of times a function call or return occured |
| 507system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls 508system.cpu2.num_int_insts 112387 # number of integer instructions | 507system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls 508system.cpu2.num_int_insts 109567 # number of integer instructions |
| 509system.cpu2.num_fp_insts 0 # number of float instructions | 509system.cpu2.num_fp_insts 0 # number of float instructions |
| 510system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read 511system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written | 510system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read 511system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written |
| 512system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 513system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written | 512system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 513system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written |
| 514system.cpu2.num_mem_refs 57957 # number of memory refs 515system.cpu2.num_load_insts 41868 # Number of load instructions 516system.cpu2.num_store_insts 16089 # Number of store instructions 517system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles 518system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles 519system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles 520system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles 521system.cpu2.icache.replacements 280 # number of replacements 522system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use 523system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. 524system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. 525system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. | 514system.cpu2.num_mem_refs 47896 # number of memory refs 515system.cpu2.num_load_insts 40447 # Number of load instructions 516system.cpu2.num_store_insts 7449 # Number of store instructions 517system.cpu2.num_idle_cycles 71882.001733 # Number of idle cycles 518system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles 519system.cpu2.not_idle_fraction 0.866347 # Percentage of non-idle cycles 520system.cpu2.idle_fraction 0.133653 # Percentage of idle cycles 521system.cpu2.icache.replacements 281 # number of replacements 522system.cpu2.icache.tagsinuse 67.531468 # Cycle average of tags in use 523system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. 524system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. 525system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. |
| 526system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 526system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 527system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor 528system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy 529system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy 530system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits 531system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits 532system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits 533system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits 534system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits 535system.cpu2.icache.overall_hits::total 165231 # number of overall hits 536system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 537system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 538system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 539system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 540system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 541system.cpu2.icache.overall_misses::total 366 # number of overall misses 542system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles 543system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles 544system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles 545system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles 546system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles 547system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles 548system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) 549system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) 550system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses 551system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses 552system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses 553system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses 554system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses 555system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses 556system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses 557system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses 558system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses 559system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses 560system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency 561system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency 562system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 563system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency 564system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 565system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency | 527system.cpu2.icache.occ_blocks::cpu2.inst 67.531468 # Average occupied blocks per requestor 528system.cpu2.icache.occ_percent::cpu2.inst 0.131897 # Average percentage of cache occupancy 529system.cpu2.icache.occ_percent::total 0.131897 # Average percentage of cache occupancy 530system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits 531system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits 532system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits 533system.cpu2.icache.demand_hits::total 176887 # number of demand (read+write) hits 534system.cpu2.icache.overall_hits::cpu2.inst 176887 # number of overall hits 535system.cpu2.icache.overall_hits::total 176887 # number of overall hits 536system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses 537system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses 538system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses 539system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses 540system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses 541system.cpu2.icache.overall_misses::total 367 # number of overall misses 542system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5709500 # number of ReadReq miss cycles 543system.cpu2.icache.ReadReq_miss_latency::total 5709500 # number of ReadReq miss cycles 544system.cpu2.icache.demand_miss_latency::cpu2.inst 5709500 # number of demand (read+write) miss cycles 545system.cpu2.icache.demand_miss_latency::total 5709500 # number of demand (read+write) miss cycles 546system.cpu2.icache.overall_miss_latency::cpu2.inst 5709500 # number of overall miss cycles 547system.cpu2.icache.overall_miss_latency::total 5709500 # number of overall miss cycles 548system.cpu2.icache.ReadReq_accesses::cpu2.inst 177254 # number of ReadReq accesses(hits+misses) 549system.cpu2.icache.ReadReq_accesses::total 177254 # number of ReadReq accesses(hits+misses) 550system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses 551system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses 552system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses 553system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses 554system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses 555system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses 556system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses 557system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses 558system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses 559system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses 560system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency 561system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency 562system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency 563system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency 564system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency 565system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency |
| 566system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu2.icache.fast_writes 0 # number of fast writes performed 573system.cpu2.icache.cache_copies 0 # number of cache copies performed | 566system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu2.icache.fast_writes 0 # number of fast writes performed 573system.cpu2.icache.cache_copies 0 # number of cache copies performed |
| 574system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 575system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 576system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 577system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 578system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 579system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 580system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles 581system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles 582system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles 583system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles 584system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles 585system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles 586system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses 587system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses 588system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses 589system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses 590system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses 591system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses 592system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency 593system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency 594system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 595system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency 596system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 597system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency | 574system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses 575system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 576system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses 577system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 578system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses 579system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 580system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles 581system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles 582system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles 583system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles 584system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles 585system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles 586system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses 587system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses 588system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses 589system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses 590system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses 591system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses 592system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency 593system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency 594system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency 595system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency 596system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency 597system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency |
| 598system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu2.dcache.replacements 0 # number of replacements | 598system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu2.dcache.replacements 0 # number of replacements |
| 600system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use 601system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. | 600system.cpu2.dcache.tagsinuse 26.637011 # Cycle average of tags in use 601system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. |
| 602system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. | 602system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. |
| 603system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. | 603system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. |
| 604system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 604system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 605system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor 606system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy 607system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy 608system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits 609system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits 610system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits 611system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits 612system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 613system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 614system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits 615system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits 616system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits 617system.cpu2.dcache.overall_hits::total 57622 # number of overall hits 618system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses 619system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses 620system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 621system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses | 605system.cpu2.dcache.occ_blocks::cpu2.data 26.637011 # Average occupied blocks per requestor 606system.cpu2.dcache.occ_percent::cpu2.data 0.052025 # Average percentage of cache occupancy 607system.cpu2.dcache.occ_percent::total 0.052025 # Average percentage of cache occupancy 608system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits 609system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits 610system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits 611system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits 612system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits 613system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits 614system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits 615system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits 616system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits 617system.cpu2.dcache.overall_hits::total 47539 # number of overall hits 618system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses 619system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses 620system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 621system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses |
| 622system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses 623system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses | 622system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses 623system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses |
| 624system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses 625system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses 626system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses 627system.cpu2.dcache.overall_misses::total 263 # number of overall misses 628system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles 629system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles 630system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles 631system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles 632system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles 633system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles 634system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles 635system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles 636system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles 637system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles 638system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) 639system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) 640system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) 641system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) 642system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 643system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 644system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses 645system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses 646system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses 647system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses 648system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses 649system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses 650system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses 651system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses 652system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses 653system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses 654system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses 655system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses 656system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses 657system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses 658system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency 659system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency 660system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency 661system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency 662system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency 663system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency 664system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency 665system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency 666system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency 667system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency | 624system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses 625system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses 626system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses 627system.cpu2.dcache.overall_misses::total 278 # number of overall misses 628system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles 629system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles 630system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles 631system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles 632system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles 633system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles 634system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles 635system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles 636system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles 637system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles 638system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) 639system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) 640system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) 641system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) 642system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 643system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 644system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses 645system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses 646system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses 647system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses 648system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses 649system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses 650system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses 651system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses 652system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses 653system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses 654system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses 655system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses 656system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses 657system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses 658system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency 659system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency 660system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency 661system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency 662system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency 663system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency 664system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency 665system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency 666system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency 667system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency |
| 668system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu2.dcache.fast_writes 0 # number of fast writes performed 675system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 668system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu2.dcache.fast_writes 0 # number of fast writes performed 675system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 676system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses 677system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 678system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 679system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses | 676system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses 677system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 678system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 679system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses |
| 680system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses 681system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses | 680system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses 681system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses |
| 682system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses 683system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 684system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses 685system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 686system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles 687system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles 688system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles 689system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles 690system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles 691system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 692system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles 693system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles 694system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles 695system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles 696system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses 697system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses 698system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses 699system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses 700system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses 701system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses 702system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses 703system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses 704system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses 705system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses 706system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency 707system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency 708system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency 709system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency 710system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency 711system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency 712system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency 713system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency 714system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency 715system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency | 682system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses 683system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 684system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses 685system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses 686system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles 687system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles 688system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles 689system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles 690system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles 691system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles 692system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles 693system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles 694system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles 695system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles 696system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses 697system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses 698system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses 699system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses 700system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses 701system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses 702system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses 703system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses 704system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses 705system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses 706system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency 707system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency 708system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency 709system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency 710system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency 711system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency 712system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency 713system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency 714system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency 715system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency |
| 716system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 716system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 717system.cpu3.numCycles 524598 # number of cpu cycles simulated | 717system.cpu3.numCycles 537824 # number of cpu cycles simulated |
| 718system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 718system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 720system.cpu3.committedInsts 166196 # Number of instructions committed 721system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed 722system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses | 720system.cpu3.committedInsts 172067 # Number of instructions committed 721system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed 722system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses |
| 723system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 724system.cpu3.num_func_calls 637 # number of times a function call or return occured | 723system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 724system.cpu3.num_func_calls 637 # number of times a function call or return occured |
| 725system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls 726system.cpu3.num_int_insts 112131 # number of integer instructions | 725system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls 726system.cpu3.num_int_insts 111206 # number of integer instructions |
| 727system.cpu3.num_fp_insts 0 # number of float instructions | 727system.cpu3.num_fp_insts 0 # number of float instructions |
| 728system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read 729system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written | 728system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read 729system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written |
| 730system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 731system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written | 730system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 731system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written |
| 732system.cpu3.num_mem_refs 57260 # number of memory refs 733system.cpu3.num_load_insts 41737 # Number of load instructions 734system.cpu3.num_store_insts 15523 # Number of store instructions 735system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles 736system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles 737system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles 738system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles 739system.cpu3.icache.replacements 281 # number of replacements 740system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use 741system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. 742system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. 743system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. | 732system.cpu3.num_mem_refs 52937 # number of memory refs 733system.cpu3.num_load_insts 41268 # Number of load instructions 734system.cpu3.num_store_insts 11669 # Number of store instructions 735system.cpu3.num_idle_cycles 72158.001732 # Number of idle cycles 736system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles 737system.cpu3.not_idle_fraction 0.865833 # Percentage of non-idle cycles 738system.cpu3.idle_fraction 0.134167 # Percentage of idle cycles 739system.cpu3.icache.replacements 280 # number of replacements 740system.cpu3.icache.tagsinuse 65.342080 # Cycle average of tags in use 741system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. 742system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. 743system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. |
| 744system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 744system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 745system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor 746system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy 747system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy 748system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits 749system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits 750system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits 751system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits 752system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits 753system.cpu3.icache.overall_hits::total 165862 # number of overall hits 754system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 755system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 756system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 757system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 758system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 759system.cpu3.icache.overall_misses::total 367 # number of overall misses 760system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles 761system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles 762system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles 763system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles 764system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles 765system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles 766system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) 767system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) 768system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses 769system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses 770system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses 771system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses 772system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses 773system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses 774system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses 775system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses 776system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses 777system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses 778system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency 779system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency 780system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency 781system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency 782system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency 783system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency | 745system.cpu3.icache.occ_blocks::cpu3.inst 65.342080 # Average occupied blocks per requestor 746system.cpu3.icache.occ_percent::cpu3.inst 0.127621 # Average percentage of cache occupancy 747system.cpu3.icache.occ_percent::total 0.127621 # Average percentage of cache occupancy 748system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits 749system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits 750system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits 751system.cpu3.icache.demand_hits::total 171734 # number of demand (read+write) hits 752system.cpu3.icache.overall_hits::cpu3.inst 171734 # number of overall hits 753system.cpu3.icache.overall_hits::total 171734 # number of overall hits 754system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses 755system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses 756system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses 757system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses 758system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses 759system.cpu3.icache.overall_misses::total 366 # number of overall misses 760system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5645500 # number of ReadReq miss cycles 761system.cpu3.icache.ReadReq_miss_latency::total 5645500 # number of ReadReq miss cycles 762system.cpu3.icache.demand_miss_latency::cpu3.inst 5645500 # number of demand (read+write) miss cycles 763system.cpu3.icache.demand_miss_latency::total 5645500 # number of demand (read+write) miss cycles 764system.cpu3.icache.overall_miss_latency::cpu3.inst 5645500 # number of overall miss cycles 765system.cpu3.icache.overall_miss_latency::total 5645500 # number of overall miss cycles 766system.cpu3.icache.ReadReq_accesses::cpu3.inst 172100 # number of ReadReq accesses(hits+misses) 767system.cpu3.icache.ReadReq_accesses::total 172100 # number of ReadReq accesses(hits+misses) 768system.cpu3.icache.demand_accesses::cpu3.inst 172100 # number of demand (read+write) accesses 769system.cpu3.icache.demand_accesses::total 172100 # number of demand (read+write) accesses 770system.cpu3.icache.overall_accesses::cpu3.inst 172100 # number of overall (read+write) accesses 771system.cpu3.icache.overall_accesses::total 172100 # number of overall (read+write) accesses 772system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002127 # miss rate for ReadReq accesses 773system.cpu3.icache.ReadReq_miss_rate::total 0.002127 # miss rate for ReadReq accesses 774system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002127 # miss rate for demand accesses 775system.cpu3.icache.demand_miss_rate::total 0.002127 # miss rate for demand accesses 776system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002127 # miss rate for overall accesses 777system.cpu3.icache.overall_miss_rate::total 0.002127 # miss rate for overall accesses 778system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388 # average ReadReq miss latency 779system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388 # average ReadReq miss latency 780system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency 781system.cpu3.icache.demand_avg_miss_latency::total 15424.863388 # average overall miss latency 782system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency 783system.cpu3.icache.overall_avg_miss_latency::total 15424.863388 # average overall miss latency |
| 784system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu3.icache.fast_writes 0 # number of fast writes performed 791system.cpu3.icache.cache_copies 0 # number of cache copies performed | 784system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu3.icache.fast_writes 0 # number of fast writes performed 791system.cpu3.icache.cache_copies 0 # number of cache copies performed |
| 792system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 793system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 794system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 795system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 796system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 797system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 798system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles 799system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles 800system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles 801system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles 802system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles 803system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles 804system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses 805system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses 806system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses 807system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses 808system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses 809system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses 810system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency 811system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency 812system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency 813system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency 814system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency 815system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency | 792system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses 793system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 794system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses 795system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 796system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses 797system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 798system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4547000 # number of ReadReq MSHR miss cycles 799system.cpu3.icache.ReadReq_mshr_miss_latency::total 4547000 # number of ReadReq MSHR miss cycles 800system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4547000 # number of demand (read+write) MSHR miss cycles 801system.cpu3.icache.demand_mshr_miss_latency::total 4547000 # number of demand (read+write) MSHR miss cycles 802system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4547000 # number of overall MSHR miss cycles 803system.cpu3.icache.overall_mshr_miss_latency::total 4547000 # number of overall MSHR miss cycles 804system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for ReadReq accesses 805system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002127 # mshr miss rate for ReadReq accesses 806system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for demand accesses 807system.cpu3.icache.demand_mshr_miss_rate::total 0.002127 # mshr miss rate for demand accesses 808system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for overall accesses 809system.cpu3.icache.overall_mshr_miss_rate::total 0.002127 # mshr miss rate for overall accesses 810system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average ReadReq mshr miss latency 811system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268 # average ReadReq mshr miss latency 812system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency 813system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency 814system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency 815system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency |
| 816system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 817system.cpu3.dcache.replacements 0 # number of replacements | 816system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 817system.cpu3.dcache.replacements 0 # number of replacements |
| 818system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use 819system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. | 818system.cpu3.dcache.tagsinuse 25.848817 # Cycle average of tags in use 819system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks. |
| 820system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. | 820system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. |
| 821system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. | 821system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks. |
| 822system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 822system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 823system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor 824system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy 825system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy 826system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits 827system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits 828system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits 829system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits 830system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 831system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 832system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits 833system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits 834system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits 835system.cpu3.dcache.overall_hits::total 56922 # number of overall hits 836system.cpu3.dcache.ReadReq_misses::cpu3.data 155 # number of ReadReq misses 837system.cpu3.dcache.ReadReq_misses::total 155 # number of ReadReq misses 838system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses 839system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses 840system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 841system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 842system.cpu3.dcache.demand_misses::cpu3.data 263 # number of demand (read+write) misses 843system.cpu3.dcache.demand_misses::total 263 # number of demand (read+write) misses 844system.cpu3.dcache.overall_misses::cpu3.data 263 # number of overall misses 845system.cpu3.dcache.overall_misses::total 263 # number of overall misses 846system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2537000 # number of ReadReq miss cycles 847system.cpu3.dcache.ReadReq_miss_latency::total 2537000 # number of ReadReq miss cycles 848system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2026000 # number of WriteReq miss cycles 849system.cpu3.dcache.WriteReq_miss_latency::total 2026000 # number of WriteReq miss cycles 850system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles 851system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles 852system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles 853system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles 854system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles 855system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles 856system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses) 857system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses) 858system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) 859system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) 860system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) 861system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 862system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses 863system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses 864system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses 865system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses 866system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses 867system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses 868system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses 869system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses 870system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses 871system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses 872system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses 873system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses 874system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses 875system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses 876system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency 877system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency 878system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency 879system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency 880system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency 881system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency 882system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency 883system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency 884system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency 885system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency | 823system.cpu3.dcache.occ_blocks::cpu3.data 25.848817 # Average occupied blocks per requestor 824system.cpu3.dcache.occ_percent::cpu3.data 0.050486 # Average percentage of cache occupancy 825system.cpu3.dcache.occ_percent::total 0.050486 # Average percentage of cache occupancy 826system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits 827system.cpu3.dcache.ReadReq_hits::total 41084 # number of ReadReq hits 828system.cpu3.dcache.WriteReq_hits::cpu3.data 11491 # number of WriteReq hits 829system.cpu3.dcache.WriteReq_hits::total 11491 # number of WriteReq hits 830system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 831system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 832system.cpu3.dcache.demand_hits::cpu3.data 52575 # number of demand (read+write) hits 833system.cpu3.dcache.demand_hits::total 52575 # number of demand (read+write) hits 834system.cpu3.dcache.overall_hits::cpu3.data 52575 # number of overall hits 835system.cpu3.dcache.overall_hits::total 52575 # number of overall hits 836system.cpu3.dcache.ReadReq_misses::cpu3.data 176 # number of ReadReq misses 837system.cpu3.dcache.ReadReq_misses::total 176 # number of ReadReq misses 838system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 839system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 840system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses 841system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses 842system.cpu3.dcache.demand_misses::cpu3.data 281 # number of demand (read+write) misses 843system.cpu3.dcache.demand_misses::total 281 # number of demand (read+write) misses 844system.cpu3.dcache.overall_misses::cpu3.data 281 # number of overall misses 845system.cpu3.dcache.overall_misses::total 281 # number of overall misses 846system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4401000 # number of ReadReq miss cycles 847system.cpu3.dcache.ReadReq_miss_latency::total 4401000 # number of ReadReq miss cycles 848system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1861000 # number of WriteReq miss cycles 849system.cpu3.dcache.WriteReq_miss_latency::total 1861000 # number of WriteReq miss cycles 850system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 928000 # number of SwapReq miss cycles 851system.cpu3.dcache.SwapReq_miss_latency::total 928000 # number of SwapReq miss cycles 852system.cpu3.dcache.demand_miss_latency::cpu3.data 6262000 # number of demand (read+write) miss cycles 853system.cpu3.dcache.demand_miss_latency::total 6262000 # number of demand (read+write) miss cycles 854system.cpu3.dcache.overall_miss_latency::cpu3.data 6262000 # number of overall miss cycles 855system.cpu3.dcache.overall_miss_latency::total 6262000 # number of overall miss cycles 856system.cpu3.dcache.ReadReq_accesses::cpu3.data 41260 # number of ReadReq accesses(hits+misses) 857system.cpu3.dcache.ReadReq_accesses::total 41260 # number of ReadReq accesses(hits+misses) 858system.cpu3.dcache.WriteReq_accesses::cpu3.data 11596 # number of WriteReq accesses(hits+misses) 859system.cpu3.dcache.WriteReq_accesses::total 11596 # number of WriteReq accesses(hits+misses) 860system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 861system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 862system.cpu3.dcache.demand_accesses::cpu3.data 52856 # number of demand (read+write) accesses 863system.cpu3.dcache.demand_accesses::total 52856 # number of demand (read+write) accesses 864system.cpu3.dcache.overall_accesses::cpu3.data 52856 # number of overall (read+write) accesses 865system.cpu3.dcache.overall_accesses::total 52856 # number of overall (read+write) accesses 866system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004266 # miss rate for ReadReq accesses 867system.cpu3.dcache.ReadReq_miss_rate::total 0.004266 # miss rate for ReadReq accesses 868system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009055 # miss rate for WriteReq accesses 869system.cpu3.dcache.WriteReq_miss_rate::total 0.009055 # miss rate for WriteReq accesses 870system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830986 # miss rate for SwapReq accesses 871system.cpu3.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses 872system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005316 # miss rate for demand accesses 873system.cpu3.dcache.demand_miss_rate::total 0.005316 # miss rate for demand accesses 874system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005316 # miss rate for overall accesses 875system.cpu3.dcache.overall_miss_rate::total 0.005316 # miss rate for overall accesses 876system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818 # average ReadReq miss latency 877system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818 # average ReadReq miss latency 878system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524 # average WriteReq miss latency 879system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524 # average WriteReq miss latency 880system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559 # average SwapReq miss latency 881system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559 # average SwapReq miss latency 882system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency 883system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509 # average overall miss latency 884system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency 885system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509 # average overall miss latency |
| 886system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu3.dcache.fast_writes 0 # number of fast writes performed 893system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 886system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu3.dcache.fast_writes 0 # number of fast writes performed 893system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 894system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses 895system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses 896system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses 897system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 898system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 899system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 900system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses 901system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 902system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses 903system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 904system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles 905system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles 906system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # number of WriteReq MSHR miss cycles 907system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1702000 # number of WriteReq MSHR miss cycles 908system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles 909system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles 910system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles 911system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles 912system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles 913system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles 914system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # mshr miss rate for ReadReq accesses 915system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003714 # mshr miss rate for ReadReq accesses 916system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses 917system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses 918system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses 919system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses 920system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for demand accesses 921system.cpu3.dcache.demand_mshr_miss_rate::total 0.004599 # mshr miss rate for demand accesses 922system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for overall accesses 923system.cpu3.dcache.overall_mshr_miss_rate::total 0.004599 # mshr miss rate for overall accesses 924system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935 # average ReadReq mshr miss latency 925system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935 # average ReadReq mshr miss latency 926system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259 # average WriteReq mshr miss latency 927system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259 # average WriteReq mshr miss latency 928system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency 929system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency 930system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency 931system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency 932system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency 933system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency | 894system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 176 # number of ReadReq MSHR misses 895system.cpu3.dcache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 896system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 897system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 898system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses 899system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 900system.cpu3.dcache.demand_mshr_misses::cpu3.data 281 # number of demand (read+write) MSHR misses 901system.cpu3.dcache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 902system.cpu3.dcache.overall_mshr_misses::cpu3.data 281 # number of overall MSHR misses 903system.cpu3.dcache.overall_mshr_misses::total 281 # number of overall MSHR misses 904system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3873000 # number of ReadReq MSHR miss cycles 905system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3873000 # number of ReadReq MSHR miss cycles 906system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1546000 # number of WriteReq MSHR miss cycles 907system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1546000 # number of WriteReq MSHR miss cycles 908system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles 909system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles 910system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles 911system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles 912system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles 913system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles 914system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses 915system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses 916system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses 917system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses 918system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses 919system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses 920system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses 921system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses 922system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses 923system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses 924system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency 925system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency 926system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency 927system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # average WriteReq mshr miss latency 928system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559 # average SwapReq mshr miss latency 929system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559 # average SwapReq mshr miss latency 930system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency 931system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency 932system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency 933system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency |
| 934system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.l2c.replacements 0 # number of replacements | 934system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.l2c.replacements 0 # number of replacements |
| 936system.l2c.tagsinuse 349.180649 # Cycle average of tags in use 937system.l2c.total_refs 1220 # Total number of references to valid blocks. | 936system.l2c.tagsinuse 348.808930 # Cycle average of tags in use 937system.l2c.total_refs 1221 # Total number of references to valid blocks. |
| 938system.l2c.sampled_refs 429 # Sample count of references to valid blocks. | 938system.l2c.sampled_refs 429 # Sample count of references to valid blocks. |
| 939system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. | 939system.l2c.avg_refs 2.846154 # Average number of references to valid blocks. |
| 940system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 940system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 941system.l2c.occ_blocks::writebacks 0.889759 # Average occupied blocks per requestor 942system.l2c.occ_blocks::cpu0.inst 231.859241 # Average occupied blocks per requestor 943system.l2c.occ_blocks::cpu0.data 54.220371 # Average occupied blocks per requestor 944system.l2c.occ_blocks::cpu1.inst 51.601321 # Average occupied blocks per requestor 945system.l2c.occ_blocks::cpu1.data 6.129070 # Average occupied blocks per requestor 946system.l2c.occ_blocks::cpu2.inst 1.917102 # Average occupied blocks per requestor 947system.l2c.occ_blocks::cpu2.data 0.831909 # Average occupied blocks per requestor 948system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor 949system.l2c.occ_blocks::cpu3.data 0.844647 # Average occupied blocks per requestor | 941system.l2c.occ_blocks::writebacks 0.888060 # Average occupied blocks per requestor 942system.l2c.occ_blocks::cpu0.inst 231.678051 # Average occupied blocks per requestor 943system.l2c.occ_blocks::cpu0.data 54.187452 # Average occupied blocks per requestor 944system.l2c.occ_blocks::cpu1.inst 51.469392 # Average occupied blocks per requestor 945system.l2c.occ_blocks::cpu1.data 6.113383 # Average occupied blocks per requestor 946system.l2c.occ_blocks::cpu2.inst 1.770981 # Average occupied blocks per requestor 947system.l2c.occ_blocks::cpu2.data 0.842116 # Average occupied blocks per requestor 948system.l2c.occ_blocks::cpu3.inst 1.030371 # Average occupied blocks per requestor 949system.l2c.occ_blocks::cpu3.data 0.829126 # Average occupied blocks per requestor |
| 950system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy | 950system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy |
| 951system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy | 951system.l2c.occ_percent::cpu0.inst 0.003535 # Average percentage of cache occupancy |
| 952system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy | 952system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy |
| 953system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 954system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy 955system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy | 953system.l2c.occ_percent::cpu1.inst 0.000785 # Average percentage of cache occupancy 954system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 955system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy |
| 956system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy | 956system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy |
| 957system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy | 957system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy |
| 958system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy | 958system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy |
| 959system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy | 959system.l2c.occ_percent::total 0.005322 # Average percentage of cache occupancy |
| 960system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 961system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 962system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 963system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits | 960system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 961system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 962system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 963system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits |
| 964system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits | 964system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits |
| 965system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 966system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 967system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits | 965system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 966system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 967system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits |
| 968system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits | 968system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits |
| 969system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 970system.l2c.Writeback_hits::total 1 # number of Writeback hits 971system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 972system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 973system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 974system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 975system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 976system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits | 969system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 970system.l2c.Writeback_hits::total 1 # number of Writeback hits 971system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 972system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 973system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 974system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 975system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 976system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits |
| 977system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits | 977system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits |
| 978system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 979system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 980system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits | 978system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 979system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 980system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits |
| 981system.l2c.demand_hits::total 1220 # number of demand (read+write) hits | 981system.l2c.demand_hits::total 1221 # number of demand (read+write) hits |
| 982system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 983system.l2c.overall_hits::cpu0.data 5 # number of overall hits 984system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 985system.l2c.overall_hits::cpu1.data 3 # number of overall hits | 982system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 983system.l2c.overall_hits::cpu0.data 5 # number of overall hits 984system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 985system.l2c.overall_hits::cpu1.data 3 # number of overall hits |
| 986system.l2c.overall_hits::cpu2.inst 354 # number of overall hits | 986system.l2c.overall_hits::cpu2.inst 355 # number of overall hits |
| 987system.l2c.overall_hits::cpu2.data 9 # number of overall hits 988system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 989system.l2c.overall_hits::cpu3.data 9 # number of overall hits | 987system.l2c.overall_hits::cpu2.data 9 # number of overall hits 988system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 989system.l2c.overall_hits::cpu3.data 9 # number of overall hits |
| 990system.l2c.overall_hits::total 1220 # number of overall hits | 990system.l2c.overall_hits::total 1221 # number of overall hits |
| 991system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 992system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 993system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 994system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 995system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 996system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses | 991system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 992system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 993system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 994system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 995system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 996system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses |
| 997system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses | 997system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses |
| 998system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses | 998system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses |
| 999system.l2c.ReadReq_misses::total 450 # number of ReadReq misses | 999system.l2c.ReadReq_misses::total 449 # number of ReadReq misses |
| 1000system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses | 1000system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses |
| 1001system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses 1002system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 1003system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses 1004system.l2c.UpgradeReq_misses::total 69 # number of UpgradeReq misses | 1001system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 1002system.l2c.UpgradeReq_misses::cpu2.data 27 # number of UpgradeReq misses 1003system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses 1004system.l2c.UpgradeReq_misses::total 86 # number of UpgradeReq misses |
| 1005system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1006system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 1007system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 1008system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1009system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1010system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1011system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1012system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 1013system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 1014system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 1015system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses | 1005system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1006system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 1007system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 1008system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1009system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1010system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1011system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1012system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 1013system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 1014system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 1015system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses |
| 1016system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses | 1016system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses |
| 1017system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses | 1017system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses |
| 1018system.l2c.demand_misses::total 592 # number of demand (read+write) misses | 1018system.l2c.demand_misses::total 591 # number of demand (read+write) misses |
| 1019system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1020system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1021system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 1022system.l2c.overall_misses::cpu1.data 23 # number of overall misses 1023system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 1024system.l2c.overall_misses::cpu2.data 16 # number of overall misses | 1019system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1020system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1021system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 1022system.l2c.overall_misses::cpu1.data 23 # number of overall misses 1023system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 1024system.l2c.overall_misses::cpu2.data 16 # number of overall misses |
| 1025system.l2c.overall_misses::cpu3.inst 9 # number of overall misses | 1025system.l2c.overall_misses::cpu3.inst 8 # number of overall misses |
| 1026system.l2c.overall_misses::cpu3.data 16 # number of overall misses | 1026system.l2c.overall_misses::cpu3.data 16 # number of overall misses |
| 1027system.l2c.overall_misses::total 592 # number of overall misses 1028system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles | 1027system.l2c.overall_misses::total 591 # number of overall misses 1028system.l2c.ReadReq_miss_latency::cpu0.inst 14828000 # number of ReadReq miss cycles |
| 1029system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles | 1029system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles |
| 1030system.l2c.ReadReq_miss_latency::cpu1.inst 3402000 # number of ReadReq miss cycles 1031system.l2c.ReadReq_miss_latency::cpu1.data 411000 # number of ReadReq miss cycles 1032system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles 1033system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles 1034system.l2c.ReadReq_miss_latency::cpu3.inst 446000 # number of ReadReq miss cycles 1035system.l2c.ReadReq_miss_latency::cpu3.data 101000 # number of ReadReq miss cycles 1036system.l2c.ReadReq_miss_latency::total 23333000 # number of ReadReq miss cycles | 1030system.l2c.ReadReq_miss_latency::cpu1.inst 3308000 # number of ReadReq miss cycles 1031system.l2c.ReadReq_miss_latency::cpu1.data 398000 # number of ReadReq miss cycles 1032system.l2c.ReadReq_miss_latency::cpu2.inst 529000 # number of ReadReq miss cycles 1033system.l2c.ReadReq_miss_latency::cpu2.data 95000 # number of ReadReq miss cycles 1034system.l2c.ReadReq_miss_latency::cpu3.inst 418000 # number of ReadReq miss cycles 1035system.l2c.ReadReq_miss_latency::cpu3.data 104000 # number of ReadReq miss cycles 1036system.l2c.ReadReq_miss_latency::total 23112000 # number of ReadReq miss cycles |
| 1037system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles 1038system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles 1039system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles 1040system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles 1041system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles | 1037system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles 1038system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles 1039system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles 1040system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles 1041system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles |
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| 1052system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles | 1052system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles |
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| 1064system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) | 1064system.l2c.ReadReq_accesses::cpu2.inst 367 # number of ReadReq accesses(hits+misses) |
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| 1066system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) | 1066system.l2c.ReadReq_accesses::cpu3.inst 366 # number of ReadReq accesses(hits+misses) |
| 1067system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 1068system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 1069system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1070system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1071system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) | 1067system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 1068system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 1069system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1070system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1071system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) |
| 1072system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) 1073system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 1074system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) 1075system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) | 1072system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 1073system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) 1074system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) 1075system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) |
| 1076system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1077system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 1078system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 1079system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1080system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1081system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 1082system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 1083system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 1084system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses | 1076system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1077system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 1078system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 1079system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1080system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1081system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 1082system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 1083system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 1084system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses |
| 1085system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses | 1085system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses |
| 1086system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses | 1086system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses |
| 1087system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses | 1087system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses |
| 1088system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 1089system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 1090system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 1091system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 1092system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 1093system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses | 1088system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 1089system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 1090system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 1091system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 1092system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 1093system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses |
| 1094system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses | 1094system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses |
| 1095system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses | 1095system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses |
| 1096system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses | 1096system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses |
| 1097system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1098system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1099system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 1100system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 1101system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 1102system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses | 1097system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1098system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1099system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 1100system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 1101system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 1102system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses |
| 1103system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses | 1103system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses |
| 1104system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses | 1104system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses |
| 1105system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses | 1105system.l2c.ReadReq_miss_rate::cpu3.inst 0.021858 # miss rate for ReadReq accesses |
| 1106system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses | 1106system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses |
| 1107system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses | 1107system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses |
| 1108system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1109system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1110system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1111system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 1108system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1109system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1110system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1111system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 1112system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses | 1112system.l2c.UpgradeReq_miss_rate::total 0.977273 # miss rate for UpgradeReq accesses |
| 1113system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1114system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1115system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1116system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1117system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1118system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1119system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1120system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 1121system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses | 1113system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1114system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1115system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1116system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1117system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1118system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1119system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1120system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 1121system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses |
| 1122system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses | 1122system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses |
| 1123system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses | 1123system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses |
| 1124system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses | 1124system.l2c.demand_miss_rate::cpu3.inst 0.021858 # miss rate for demand accesses |
| 1125system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses | 1125system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses |
| 1126system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses | 1126system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses |
| 1127system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 1128system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1129system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 1130system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses | 1127system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 1128system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1129system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 1130system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses |
| 1131system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses | 1131system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses |
| 1132system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses | 1132system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses |
| 1133system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses | 1133system.l2c.overall_miss_rate::cpu3.inst 0.021858 # miss rate for overall accesses |
| 1134system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses | 1134system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses |
| 1135system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 1136system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency | 1135system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses 1136system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175 # average ReadReq miss latency |
| 1137system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency | 1137system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency |
| 1138system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq miss latency 1139system.l2c.ReadReq_avg_miss_latency::cpu1.data 51375 # average ReadReq miss latency 1140system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency 1141system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency 1142system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556 # average ReadReq miss latency 1143system.l2c.ReadReq_avg_miss_latency::cpu3.data 50500 # average ReadReq miss latency 1144system.l2c.ReadReq_avg_miss_latency::total 51851.111111 # average ReadReq miss latency | 1138system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50121.212121 # average ReadReq miss latency 1139system.l2c.ReadReq_avg_miss_latency::cpu1.data 49750 # average ReadReq miss latency 1140system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44083.333333 # average ReadReq miss latency 1141system.l2c.ReadReq_avg_miss_latency::cpu2.data 47500 # average ReadReq miss latency 1142system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52250 # average ReadReq miss latency 1143system.l2c.ReadReq_avg_miss_latency::cpu3.data 52000 # average ReadReq miss latency 1144system.l2c.ReadReq_avg_miss_latency::total 51474.387528 # average ReadReq miss latency |
| 1145system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 1146system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency 1147system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 1148system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency 1149system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency | 1145system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 1146system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency 1147system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 1148system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency 1149system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency |
| 1150system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency | 1150system.l2c.demand_avg_miss_latency::cpu0.inst 52028.070175 # average overall miss latency |
| 1151system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency | 1151system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency |
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| 1161system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency 1162system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency 1163system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1164system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1165system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency 1166system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency 1167system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency | 1161system.l2c.overall_avg_miss_latency::cpu1.inst 50121.212121 # average overall miss latency 1162system.l2c.overall_avg_miss_latency::cpu1.data 51217.391304 # average overall miss latency 1163system.l2c.overall_avg_miss_latency::cpu2.inst 44083.333333 # average overall miss latency 1164system.l2c.overall_avg_miss_latency::cpu2.data 51437.500000 # average overall miss latency 1165system.l2c.overall_avg_miss_latency::cpu3.inst 52250 # average overall miss latency 1166system.l2c.overall_avg_miss_latency::cpu3.data 52000 # average overall miss latency 1167system.l2c.overall_avg_miss_latency::total 51600.676819 # average overall miss latency |
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| 1202system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1203system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses | 1199system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1200system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses |
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| 1263system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles 1264system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles 1265system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles 1266system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles 1267system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles | 1260system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles 1261system.l2c.overall_mshr_miss_latency::cpu2.data 600000 # number of overall MSHR miss cycles 1262system.l2c.overall_mshr_miss_latency::cpu3.inst 322000 # number of overall MSHR miss cycles 1263system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles 1264system.l2c.overall_mshr_miss_latency::total 22890000 # number of overall MSHR miss cycles |
| 1268system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1269system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1270system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1271system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses | 1265system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1266system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1267system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1268system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses |
| 1272system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses 1273system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses 1274system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1275system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses | 1269system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for ReadReq accesses 1270system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 1271system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for ReadReq accesses 1272system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses |
| 1276system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 1277system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1278system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1279system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1280system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 1273system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 1274system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1275system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1276system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1277system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 1281system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses | 1278system.l2c.UpgradeReq_mshr_miss_rate::total 0.977273 # mshr miss rate for UpgradeReq accesses |
| 1282system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1283system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1284system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1285system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1286system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1287system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1288system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1289system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1290system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses | 1279system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1280system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1281system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1282system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1283system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1284system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1285system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1286system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1287system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses |
| 1291system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses 1292system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses 1293system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1294system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses | 1288system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for demand accesses 1289system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses 1290system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for demand accesses 1291system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses |
| 1295system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1296system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1297system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1298system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1299system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses | 1292system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1293system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1294system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1295system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1296system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses |
| 1300system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses 1301system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses 1302system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1303system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses | 1297system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for overall accesses 1298system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses 1299system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for overall accesses 1300system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses |
| 1304system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses | 1301system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses |
| 1305system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency | 1302system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average ReadReq mshr miss latency |
| 1306system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1307system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1308system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency | 1303system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1304system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1305system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency |
| 1309system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency | 1306system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency |
| 1310system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency | 1307system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency |
| 1311system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency | 1308system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40250 # average ReadReq mshr miss latency |
| 1312system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency | 1309system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency |
| 1313system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency | 1310system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814 # average ReadReq mshr miss latency |
| 1314system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1315system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1316system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1317system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency 1318system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency 1319system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1320system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency 1321system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1322system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 1323system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency | 1311system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1312system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1313system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1314system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency 1315system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency 1316system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1317system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency 1318system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1319system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 1320system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency |
| 1324system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency | 1321system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency |
| 1325system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1326system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1327system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency | 1322system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1323system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1324system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency |
| 1328system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency | 1325system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency |
| 1329system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency | 1326system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency |
| 1330system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency | 1327system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency |
| 1331system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 1328system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 1332system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency 1333system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency | 1329system.l2c.demand_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency 1330system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency |
| 1334system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1335system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1336system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency | 1331system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1332system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1333system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency |
| 1337system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency | 1334system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency |
| 1338system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency | 1335system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency |
| 1339system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency | 1336system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency |
| 1340system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 1337system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 1341system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency | 1338system.l2c.overall_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency |
| 1342system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1343 1344---------- End Simulation Statistics ---------- | 1339system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1340 1341---------- End Simulation Statistics ---------- |