| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 323904 # Simulator instruction rate (inst/s) 8host_op_rate 323899 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 128274037 # Simulator tick rate (ticks/s) 10host_mem_usage 231956 # Number of bytes of host memory used 11host_seconds 2.05 # Real time elapsed on the host | 7host_inst_rate 1070900 # Simulator instruction rate (inst/s) 8host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 424091073 # Simulator tick rate (ticks/s) 10host_mem_usage 232420 # Number of bytes of host memory used 11host_seconds 0.62 # Real time elapsed on the host |
| 12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated | 12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 36608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 572 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu0.workload.num_syscalls 89 # Number of system calls 24system.cpu0.numCycles 524596 # number of cpu cycles simulated 25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu0.committedInsts 158353 # Number of instructions committed 28system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed 29system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses 30system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 72system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles 73system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) 74system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) 75system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses 76system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses 77system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses 78system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses 79system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses | 60system.cpu0.workload.num_syscalls 89 # Number of system calls 61system.cpu0.numCycles 524596 # number of cpu cycles simulated 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu0.committedInsts 158353 # Number of instructions committed 65system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 109system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles 110system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) 111system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) 112system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses 113system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses 114system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses 115system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses 116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses |
| 117system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses |
|
| 80system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses | 118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses |
| 119system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses |
|
| 81system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses | 120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses |
| 121system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses |
|
| 82system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency | 122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency |
| 123system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency |
|
| 83system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency | 124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency |
| 125system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency |
|
| 84system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency | 126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency |
| 127system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency |
|
| 85system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 89system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91system.cpu0.icache.fast_writes 0 # number of fast writes performed 92system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 98system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 99system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles 100system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 101system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles 102system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles 103system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles 104system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles 105system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses | 128system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 134system.cpu0.icache.fast_writes 0 # number of fast writes performed 135system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 141system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 142system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles 143system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 144system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles 145system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles 146system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles 147system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles 148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses |
| 149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses |
|
| 106system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses | 150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses |
| 151system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses |
|
| 107system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses | 152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses |
| 153system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses |
|
| 108system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency | 154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency |
| 155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency |
|
| 109system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency | 156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency |
| 157system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency |
|
| 110system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency | 158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency |
| 159system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency |
|
| 111system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu0.dcache.replacements 9 # number of replacements 113system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use 114system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. 115system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 116system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. 117system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 118system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 154system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) 155system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 156system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 157system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses 158system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses 159system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses 160system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses 161system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses | 160system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu0.dcache.replacements 9 # number of replacements 162system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use 163system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. 164system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 165system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. 166system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 167system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 203system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) 204system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 205system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 206system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses 207system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses 208system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses 209system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses 210system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses |
| 211system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses |
|
| 162system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses | 212system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses |
| 213system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses |
|
| 163system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses | 214system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses |
| 215system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses |
|
| 164system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses | 216system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses |
| 217system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses |
|
| 165system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses | 218system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses |
| 219system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses |
|
| 166system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency | 220system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency |
| 221system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency |
|
| 167system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency | 222system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency |
| 223system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency |
|
| 168system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency | 224system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency |
| 225system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency |
|
| 169system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency | 226system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency |
| 227system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency |
|
| 170system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency | 228system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency |
| 229system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency |
|
| 171system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 178system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 194system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles 195system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles 196system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles 197system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles 198system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles 199system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles 200system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles 201system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses | 230system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 231system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 232system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 233system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 234system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 235system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 236system.cpu0.dcache.fast_writes 0 # number of fast writes performed 237system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 253system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles 254system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles 255system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles 256system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles 257system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles 258system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles 259system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles 260system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses |
| 261system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses |
|
| 202system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses | 262system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses |
| 263system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses |
|
| 203system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses | 264system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses |
| 265system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses |
|
| 204system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses | 266system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses |
| 267system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses |
|
| 205system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses | 268system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses |
| 269system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses |
|
| 206system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency | 270system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency |
| 271system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency |
|
| 207system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency | 272system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency |
| 273system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency |
|
| 208system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency | 274system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency |
| 275system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency |
|
| 209system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency | 276system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency |
| 277system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency |
|
| 210system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency | 278system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency |
| 279system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency |
|
| 211system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 212system.cpu1.numCycles 524596 # number of cpu cycles simulated 213system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 214system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 215system.cpu1.committedInsts 172325 # Number of instructions committed 216system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed 217system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses 218system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 260system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles 261system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) 262system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) 263system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses 264system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses 265system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses 266system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses 267system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses | 280system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 281system.cpu1.numCycles 524596 # number of cpu cycles simulated 282system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 284system.cpu1.committedInsts 172325 # Number of instructions committed 285system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed 286system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses 287system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 329system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles 330system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) 331system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) 332system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses 333system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses 334system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses 335system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses 336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses |
| 337system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses |
|
| 268system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses | 338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses |
| 339system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses |
|
| 269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses | 340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses |
| 341system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses |
|
| 270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency | 342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency |
| 343system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency |
|
| 271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency | 344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency |
| 345system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency |
|
| 272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency | 346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency |
| 347system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency |
|
| 273system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu1.icache.fast_writes 0 # number of fast writes performed 280system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 286system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 287system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles 288system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles 289system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles 290system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles 291system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles 292system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles 293system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses | 348system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu1.icache.fast_writes 0 # number of fast writes performed 355system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 361system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 362system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles 363system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles 364system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles 365system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles 366system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles 367system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles 368system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses |
| 369system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses |
|
| 294system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses | 370system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses |
| 371system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses |
|
| 295system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses | 372system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses |
| 373system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses |
|
| 296system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency | 374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency |
| 375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency |
|
| 297system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency | 376system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency |
| 377system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency |
|
| 298system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency | 378system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency |
| 379system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency |
|
| 299system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 300system.cpu1.dcache.replacements 2 # number of replacements 301system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use 302system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. 303system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. 304system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. 305system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 306system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 342system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) 343system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) 344system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) 345system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses 346system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses 347system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses 348system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses 349system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses | 380system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu1.dcache.replacements 2 # number of replacements 382system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use 383system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. 384system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. 385system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. 386system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 387system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 423system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) 424system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) 425system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) 426system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses 427system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses 428system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses 429system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses 430system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses |
| 431system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses |
|
| 350system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses | 432system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses |
| 433system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses |
|
| 351system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses | 434system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses |
| 435system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses |
|
| 352system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses | 436system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses |
| 437system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses |
|
| 353system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses | 438system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses |
| 439system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses |
|
| 354system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency | 440system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency |
| 441system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency |
|
| 355system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency | 442system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency |
| 443system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency |
|
| 356system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency | 444system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency |
| 445system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency |
|
| 357system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency | 446system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency |
| 447system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency |
|
| 358system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency | 448system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency |
| 449system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency |
|
| 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 363system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.cpu1.dcache.fast_writes 0 # number of fast writes performed 366system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 382system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles 383system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles 384system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles 385system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles 386system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles 387system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles 388system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles 389system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses | 450system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 451system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 452system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 453system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 454system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 455system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 456system.cpu1.dcache.fast_writes 0 # number of fast writes performed 457system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 473system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles 474system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles 475system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles 476system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles 477system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles 478system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles 479system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles 480system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses |
| 481system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses |
|
| 390system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses | 482system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses |
| 483system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses |
|
| 391system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses | 484system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses |
| 485system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses |
|
| 392system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses | 486system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses |
| 487system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses |
|
| 393system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses | 488system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses |
| 489system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses |
|
| 394system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency | 490system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency |
| 491system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency |
|
| 395system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency | 492system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency |
| 493system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency |
|
| 396system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency | 494system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency |
| 495system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency |
|
| 397system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency | 496system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency |
| 497system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency |
|
| 398system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency | 498system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency |
| 499system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency |
|
| 399system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu2.numCycles 524596 # number of cpu cycles simulated 401system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu2.committedInsts 165499 # Number of instructions committed 404system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed 405system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses 406system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 448system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles 449system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) 450system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) 451system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses 452system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses 453system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses 454system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses 455system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses | 500system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 501system.cpu2.numCycles 524596 # number of cpu cycles simulated 502system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 503system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 504system.cpu2.committedInsts 165499 # Number of instructions committed 505system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed 506system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses 507system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 549system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles 550system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) 551system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) 552system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses 553system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses 554system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses 555system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses 556system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses |
| 557system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses |
|
| 456system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses | 558system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses |
| 559system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses |
|
| 457system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses | 560system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses |
| 561system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses |
|
| 458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency | 562system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency |
| 563system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency |
|
| 459system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency | 564system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency |
| 565system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency |
|
| 460system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency | 566system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency |
| 567system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency |
|
| 461system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 465system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.cpu2.icache.fast_writes 0 # number of fast writes performed 468system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 474system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 475system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles 476system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles 477system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles 478system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles 479system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles 480system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles 481system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses | 568system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu2.icache.fast_writes 0 # number of fast writes performed 575system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 581system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 582system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles 583system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles 584system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles 585system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles 586system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles 587system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles 588system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses |
| 589system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses |
|
| 482system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses | 590system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses |
| 591system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses |
|
| 483system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses | 592system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses |
| 593system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses |
|
| 484system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency | 594system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency |
| 595system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency |
|
| 485system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency | 596system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency |
| 597system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency |
|
| 486system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency | 598system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency |
| 599system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency |
|
| 487system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu2.dcache.replacements 2 # number of replacements 489system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use 490system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. 491system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. 492system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. 493system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 530system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) 531system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 532system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 533system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses 534system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses 535system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses 536system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses 537system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses | 600system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 601system.cpu2.dcache.replacements 2 # number of replacements 602system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use 603system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. 604system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. 605system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. 606system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 643system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) 644system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 645system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 646system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses 647system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses 648system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses 649system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses 650system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses |
| 651system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses |
|
| 538system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses | 652system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses |
| 653system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses |
|
| 539system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses | 654system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses |
| 655system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses |
|
| 540system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses | 656system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses |
| 657system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses |
|
| 541system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses | 658system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses |
| 659system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses |
|
| 542system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency | 660system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency |
| 661system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency |
|
| 543system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency | 662system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency |
| 663system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency |
|
| 544system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency | 664system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency |
| 665system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency |
|
| 545system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency | 666system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency |
| 667system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency |
|
| 546system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency | 668system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency |
| 669system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency |
|
| 547system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu2.dcache.fast_writes 0 # number of fast writes performed 554system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 570system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles 571system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles 572system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 573system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles 574system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles 575system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles 576system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles 577system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses | 670system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu2.dcache.fast_writes 0 # number of fast writes performed 677system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 693system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles 694system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles 695system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 696system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles 697system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles 698system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles 699system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles 700system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses |
| 701system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses |
|
| 578system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses | 702system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses |
| 703system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses |
|
| 579system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses | 704system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses |
| 705system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses |
|
| 580system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses | 706system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses |
| 707system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses |
|
| 581system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses | 708system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses |
| 709system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses |
|
| 582system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency | 710system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency |
| 711system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency |
|
| 583system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency | 712system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency |
| 713system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency |
|
| 584system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency | 714system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency |
| 715system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency |
|
| 585system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency | 716system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency |
| 717system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency |
|
| 586system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency | 718system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency |
| 719system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency |
|
| 587system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu3.numCycles 524596 # number of cpu cycles simulated 589system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 590system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 591system.cpu3.committedInsts 166130 # Number of instructions committed 592system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed 593system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses 594system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 636system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles 637system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) 638system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) 639system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses 640system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses 641system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses 642system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses 643system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses | 720system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 721system.cpu3.numCycles 524596 # number of cpu cycles simulated 722system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 723system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 724system.cpu3.committedInsts 166130 # Number of instructions committed 725system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed 726system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses 727system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 769system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles 770system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) 771system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) 772system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses 773system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses 774system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses 775system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses 776system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses |
| 777system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses |
|
| 644system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses | 778system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses |
| 779system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses |
|
| 645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses | 780system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses |
| 781system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses |
|
| 646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency | 782system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency |
| 783system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency |
|
| 647system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency | 784system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency |
| 785system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency |
|
| 648system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency | 786system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency |
| 787system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency |
|
| 649system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 653system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu3.icache.fast_writes 0 # number of fast writes performed 656system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 662system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 663system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles 664system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles 665system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles 666system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles 667system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles 668system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles 669system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses | 788system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 789system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 791system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 793system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 794system.cpu3.icache.fast_writes 0 # number of fast writes performed 795system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 801system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 802system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles 803system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles 804system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles 805system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles 806system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles 807system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles 808system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses |
| 809system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses |
|
| 670system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses | 810system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses |
| 811system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses |
|
| 671system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses | 812system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses |
| 813system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses |
|
| 672system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency | 814system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency |
| 815system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency |
|
| 673system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency | 816system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency |
| 817system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency |
|
| 674system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency | 818system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency |
| 819system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency |
|
| 675system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu3.dcache.replacements 2 # number of replacements 677system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use 678system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. 679system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. 680system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. 681system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 682system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 718system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) 719system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) 720system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 721system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses 722system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses 723system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses 724system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses 725system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses | 820system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 821system.cpu3.dcache.replacements 2 # number of replacements 822system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use 823system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. 824system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. 825system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. 826system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 827system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor --- 35 unchanged lines hidden (view full) --- 863system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) 864system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) 865system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 866system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses 867system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses 868system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses 869system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses 870system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses |
| 871system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses |
|
| 726system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses | 872system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses |
| 873system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses |
|
| 727system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses | 874system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses |
| 875system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses |
|
| 728system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses | 876system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses |
| 877system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses |
|
| 729system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses | 878system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses |
| 879system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses |
|
| 730system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency | 880system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency |
| 881system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency |
|
| 731system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency | 882system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency |
| 883system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency |
|
| 732system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency | 884system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency |
| 885system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency |
|
| 733system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency | 886system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency |
| 887system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency |
|
| 734system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency | 888system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency |
| 889system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency |
|
| 735system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.cpu3.dcache.fast_writes 0 # number of fast writes performed 742system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 758system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles 759system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles 760system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles 761system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles 762system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles 763system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles 764system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles 765system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses | 890system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 896system.cpu3.dcache.fast_writes 0 # number of fast writes performed 897system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 913system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles 914system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles 915system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles 916system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles 917system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles 918system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles 919system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles 920system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses |
| 921system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses |
|
| 766system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses | 922system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses |
| 923system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses |
|
| 767system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses | 924system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses |
| 925system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses |
|
| 768system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses | 926system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses |
| 927system.cpu3.dcache.demand_mshr_miss_rate::total 0.004635 # mshr miss rate for demand accesses |
|
| 769system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses | 928system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses |
| 929system.cpu3.dcache.overall_mshr_miss_rate::total 0.004635 # mshr miss rate for overall accesses |
|
| 770system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency | 930system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency |
| 931system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13363.057325 # average ReadReq mshr miss latency |
|
| 771system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency | 932system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency |
| 933system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16259.259259 # average WriteReq mshr miss latency |
|
| 772system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency | 934system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency |
| 935system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency |
|
| 773system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency | 936system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency |
| 937system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency |
|
| 774system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency | 938system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency |
| 939system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency |
|
| 775system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.l2c.replacements 0 # number of replacements 777system.l2c.tagsinuse 353.886259 # Cycle average of tags in use 778system.l2c.total_refs 1223 # Total number of references to valid blocks. 779system.l2c.sampled_refs 434 # Sample count of references to valid blocks. 780system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. 781system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 782system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor --- 161 unchanged lines hidden (view full) --- 944system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 945system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 946system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 947system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses 948system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 949system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses 950system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 951system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses | 940system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 941system.l2c.replacements 0 # number of replacements 942system.l2c.tagsinuse 353.886259 # Cycle average of tags in use 943system.l2c.total_refs 1223 # Total number of references to valid blocks. 944system.l2c.sampled_refs 434 # Sample count of references to valid blocks. 945system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. 946system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 947system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor --- 161 unchanged lines hidden (view full) --- 1109system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 1110system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 1111system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 1112system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses 1113system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 1114system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses 1115system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 1116system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses |
| 1117system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses |
|
| 952system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 953system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 954system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 955system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 1118system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1119system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1120system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1121system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 1122system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses |
|
| 956system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 957system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 958system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 959system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses | 1123system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1124system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1125system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1126system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses |
| 1127system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
|
| 960system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 961system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 962system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 963system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses 964system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 965system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses 966system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 967system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses | 1128system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1129system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1130system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 1131system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses 1132system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 1133system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses 1134system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 1135system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses |
| 1136system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses |
|
| 968system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 969system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 970system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 971system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses 972system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 973system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses 974system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 975system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses | 1137system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 1138system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1139system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 1140system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses 1141system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 1142system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses 1143system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 1144system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses |
| 1145system.l2c.overall_miss_rate::total 0.325633 # miss rate for overall accesses |
|
| 976system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency 977system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency 978system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency 979system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency 980system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency 981system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency 982system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency 983system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency | 1146system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency 1147system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency 1148system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency 1149system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency 1150system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency 1151system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency 1152system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency 1153system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency |
| 1154system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency |
|
| 984system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency 985system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency 986system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency | 1155system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency 1156system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency 1157system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency |
| 1158system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency |
|
| 987system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 988system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency 989system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 990system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency | 1159system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 1160system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency 1161system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 1162system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency |
| 1163system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # average ReadExReq miss latency |
|
| 991system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 992system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency 993system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 994system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 995system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 996system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency 997system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 998system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency | 1164system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 1165system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency 1166system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 1167system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 1168system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1169system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1170system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1171system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency |
| 1172system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency |
|
| 999system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 1000system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency 1001system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 1002system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 1003system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1004system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1005system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1006system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency | 1173system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 1174system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency 1175system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 1176system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 1177system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1178system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1179system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1180system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency |
| 1181system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency |
|
| 1007system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1011system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1012system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1013system.l2c.fast_writes 0 # number of fast writes performed 1014system.l2c.cache_copies 0 # number of cache copies performed --- 92 unchanged lines hidden (view full) --- 1107system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1108system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1109system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1110system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses 1111system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses 1112system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses 1113system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1114system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses | 1182system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1183system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1184system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1185system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1186system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1187system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1188system.l2c.fast_writes 0 # number of fast writes performed 1189system.l2c.cache_copies 0 # number of cache copies performed --- 92 unchanged lines hidden (view full) --- 1282system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1283system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1284system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1285system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses 1286system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses 1287system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses 1288system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1289system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses |
| 1290system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses |
|
| 1115system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1116system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1117system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1118system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 1291system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1292system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1293system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1294system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 1295system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses |
|
| 1119system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1120system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1121system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1122system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses | 1296system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1297system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1298system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1299system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses |
| 1300system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
|
| 1123system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1124system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1125system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1126system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses 1127system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses 1128system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses 1129system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1130system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses | 1301system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1302system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1303system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1304system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses 1305system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses 1306system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses 1307system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1308system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses |
| 1309system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses |
|
| 1131system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1132system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1133system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1134system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses 1135system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses 1136system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses 1137system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1138system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses | 1310system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1311system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1312system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1313system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses 1314system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses 1315system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses 1316system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1317system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses |
| 1318system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses |
|
| 1139system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency 1140system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1141system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1142system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 1143system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency 1144system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1145system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1146system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency | 1319system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency 1320system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1321system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1322system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 1323system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency 1324system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1325system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1326system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency |
| 1327system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency |
|
| 1147system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1148system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1149system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1150system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency | 1328system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1329system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1330system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1331system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency |
| 1332system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency |
|
| 1151system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1152system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency 1153system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1154system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency | 1333system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1334system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency 1335system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1336system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency |
| 1337system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency |
|
| 1155system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1156system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1157system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1158system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1159system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1160system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1161system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1162system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 1338system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1339system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1340system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1341system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1342system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1343system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1344system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1345system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 1346system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency |
|
| 1163system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1164system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1165system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1166system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1167system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1168system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1169system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1170system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 1347system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1348system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1349system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1350system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1351system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1352system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1353system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1354system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 1355system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency |
|
| 1171system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1172 1173---------- End Simulation Statistics ---------- | 1356system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1357 1358---------- End Simulation Statistics ---------- |