| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1330969 # Simulator instruction rate (inst/s) 8host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 527074583 # Simulator tick rate (ticks/s) 10host_mem_usage 221728 # Number of bytes of host memory used 11host_seconds 0.50 # Real time elapsed on the host | 7host_inst_rate 323904 # Simulator instruction rate (inst/s) 8host_op_rate 323899 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 128274037 # Simulator tick rate (ticks/s) 10host_mem_usage 231956 # Number of bytes of host memory used 11host_seconds 2.05 # Real time elapsed on the host |
| 12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 36608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 572 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 61 unchanged lines hidden (view full) --- 81system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses 82system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency 83system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 84system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 85system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 36608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 572 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 61 unchanged lines hidden (view full) --- 81system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses 82system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency 83system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 84system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 85system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 89system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 90system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 89system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 91system.cpu0.icache.fast_writes 0 # number of fast writes performed 92system.cpu0.icache.cache_copies 0 # number of cache copies performed 93system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 94system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 95system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 96system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 97system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 98system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 167system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency 168system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency 169system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 170system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 171system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 91system.cpu0.icache.fast_writes 0 # number of fast writes performed 92system.cpu0.icache.cache_copies 0 # number of cache copies performed 93system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 94system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 95system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 96system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 97system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 98system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 167system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency 168system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency 169system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 170system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 171system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 175system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 176system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 175system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 179system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 180system.cpu0.dcache.writebacks::total 6 # number of writebacks 181system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses 182system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 183system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 184system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses 270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency 271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 273system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 179system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 180system.cpu0.dcache.writebacks::total 6 # number of writebacks 181system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses 182system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 183system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 184system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses 270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency 271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 273system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 277system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 278system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 277system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 279system.cpu1.icache.fast_writes 0 # number of fast writes performed 280system.cpu1.icache.cache_copies 0 # number of cache copies performed 281system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 282system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 283system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 284system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 285system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 286system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 355system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency 356system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency 357system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 358system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 279system.cpu1.icache.fast_writes 0 # number of fast writes performed 280system.cpu1.icache.cache_copies 0 # number of cache copies performed 281system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 282system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 283system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 284system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 285system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 286system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 355system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency 356system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency 357system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 358system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 363system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 364system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 363system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 365system.cpu1.dcache.fast_writes 0 # number of fast writes performed 366system.cpu1.dcache.cache_copies 0 # number of cache copies performed 367system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 368system.cpu1.dcache.writebacks::total 1 # number of writebacks 369system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses 370system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses 371system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses 372system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 457system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses 458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency 459system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 460system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 461system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked | 365system.cpu1.dcache.fast_writes 0 # number of fast writes performed 366system.cpu1.dcache.cache_copies 0 # number of cache copies performed 367system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 368system.cpu1.dcache.writebacks::total 1 # number of writebacks 369system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses 370system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses 371system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses 372system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 457system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses 458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency 459system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 460system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 461system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 465system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 466system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 465system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 467system.cpu2.icache.fast_writes 0 # number of fast writes performed 468system.cpu2.icache.cache_copies 0 # number of cache copies performed 469system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 470system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 471system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 472system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 473system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 474system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 543system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency 544system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency 545system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency 546system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency 547system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked | 467system.cpu2.icache.fast_writes 0 # number of fast writes performed 468system.cpu2.icache.cache_copies 0 # number of cache copies performed 469system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 470system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 471system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 472system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 473system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 474system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 543system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency 544system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency 545system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency 546system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency 547system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 551system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 552system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 551system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 553system.cpu2.dcache.fast_writes 0 # number of fast writes performed 554system.cpu2.dcache.cache_copies 0 # number of cache copies performed 555system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 556system.cpu2.dcache.writebacks::total 1 # number of writebacks 557system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses 558system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses 559system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 560system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses 646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency 647system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 648system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 649system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked | 553system.cpu2.dcache.fast_writes 0 # number of fast writes performed 554system.cpu2.dcache.cache_copies 0 # number of cache copies performed 555system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 556system.cpu2.dcache.writebacks::total 1 # number of writebacks 557system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses 558system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses 559system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 560system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses --- 84 unchanged lines hidden (view full) --- 645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses 646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency 647system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 648system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 649system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 653system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 654system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 653system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 655system.cpu3.icache.fast_writes 0 # number of fast writes performed 656system.cpu3.icache.cache_copies 0 # number of cache copies performed 657system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 658system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 659system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 660system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 661system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 662system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 731system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency 732system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency 733system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 734system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 735system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked | 655system.cpu3.icache.fast_writes 0 # number of fast writes performed 656system.cpu3.icache.cache_copies 0 # number of cache copies performed 657system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 658system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 659system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 660system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 661system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 662system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses --- 68 unchanged lines hidden (view full) --- 731system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency 732system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency 733system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 734system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 735system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 739system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 740system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 739system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 741system.cpu3.dcache.fast_writes 0 # number of fast writes performed 742system.cpu3.dcache.cache_copies 0 # number of cache copies performed 743system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 744system.cpu3.dcache.writebacks::total 1 # number of writebacks 745system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses 746system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 747system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses 748system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses --- 254 unchanged lines hidden (view full) --- 1003system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1004system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1005system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1006system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency 1007system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 741system.cpu3.dcache.fast_writes 0 # number of fast writes performed 742system.cpu3.dcache.cache_copies 0 # number of cache copies performed 743system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 744system.cpu3.dcache.writebacks::total 1 # number of writebacks 745system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses 746system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 747system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses 748system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses --- 254 unchanged lines hidden (view full) --- 1003system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1004system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1005system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1006system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency 1007system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 1011system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1012system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1011system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1012system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1013system.l2c.fast_writes 0 # number of fast writes performed 1014system.l2c.cache_copies 0 # number of cache copies performed 1015system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1016system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 1017system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits 1018system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits 1019system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits 1020system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits --- 153 unchanged lines hidden --- | 1013system.l2c.fast_writes 0 # number of fast writes performed 1014system.l2c.cache_copies 0 # number of cache copies performed 1015system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1016system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 1017system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits 1018system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits 1019system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits 1020system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits --- 153 unchanged lines hidden --- |