| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000264 # Number of seconds simulated 4sim_ticks 264174500 # Number of ticks simulated 5final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000264 # Number of seconds simulated 4sim_ticks 264174500 # Number of ticks simulated 5final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 587931 # Simulator instruction rate (inst/s) 8host_op_rate 587915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 234112560 # Simulator tick rate (ticks/s) 10host_mem_usage 258432 # Number of bytes of host memory used 11host_seconds 1.13 # Real time elapsed on the host | 7host_inst_rate 1178179 # Simulator instruction rate (inst/s) 8host_op_rate 1178160 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 469155398 # Simulator tick rate (ticks/s) 10host_mem_usage 303372 # Number of bytes of host memory used 11host_seconds 0.56 # Real time elapsed on the host |
| 12sim_insts 663394 # Number of instructions simulated 13sim_ops 663394 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 663394 # Number of instructions simulated 13sim_ops 663394 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory --- 30 unchanged lines hidden (view full) --- 54system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory --- 30 unchanged lines hidden (view full) --- 55system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) |
| 63system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls | 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 66system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states |
|
| 64system.cpu0.numCycles 528349 # number of cpu cycles simulated 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu0.committedInsts 158268 # Number of instructions committed 68system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction 118system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 121system.cpu0.op_class::total 158330 # Class of executed instruction | 67system.cpu0.numCycles 528349 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 158268 # Number of instructions committed 71system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 117system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 119system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 120system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction 121system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction 122system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 123system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 124system.cpu0.op_class::total 158330 # Class of executed instruction |
| 125system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 122system.cpu0.dcache.tags.replacements 2 # number of replacements 123system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 126system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 135system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses | 126system.cpu0.dcache.tags.replacements 2 # number of replacements 127system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use 128system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. 129system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 130system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. 131system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 132system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor 133system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy 134system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy 135system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 136system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 137system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 138system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 139system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses 140system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses |
| 141system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 137system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits 141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 143system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 237system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency 238system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency 239system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 240system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 241system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 242system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 243system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 244system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency | 142system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits 143system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits 144system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits 145system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits 146system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 147system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 148system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits 149system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits --- 92 unchanged lines hidden (view full) --- 242system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency 243system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency 244system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 245system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 246system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 247system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency 248system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency 249system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency |
| 250system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 245system.cpu0.icache.tags.replacements 215 # number of replacements 246system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use 247system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. 248system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 249system.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. 250system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor 252system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy 253system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy 254system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 255system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 256system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 257system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 258system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses 259system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses | 251system.cpu0.icache.tags.replacements 215 # number of replacements 252system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use 253system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. 254system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 255system.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. 256system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 257system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor 258system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy 259system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy 260system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 261system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 262system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 263system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 264system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses 265system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses |
| 266system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 260system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits 261system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits 262system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits 263system.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits 264system.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits 265system.cpu0.icache.overall_hits::total 157864 # number of overall hits 266system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 267system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 320system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 321system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 322system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency 323system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency 324system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 325system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 326system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 327system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency | 267system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits 268system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits 269system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits 270system.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits 271system.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits 272system.cpu0.icache.overall_hits::total 157864 # number of overall hits 273system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 274system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 327system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 328system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 329system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency 330system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency 331system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 332system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency 333system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency 334system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency |
| 335system.cpu1.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states |
|
| 328system.cpu1.numCycles 528348 # number of cpu cycles simulated 329system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 330system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 331system.cpu1.committedInsts 170000 # Number of instructions committed 332system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed 333system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses 334system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 335system.cpu1.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 378system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 379system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 380system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 381system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction 382system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction 383system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 384system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 385system.cpu1.op_class::total 170032 # Class of executed instruction | 336system.cpu1.numCycles 528348 # number of cpu cycles simulated 337system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 339system.cpu1.committedInsts 170000 # Number of instructions committed 340system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed 341system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses 342system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 343system.cpu1.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 386system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 387system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 388system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 389system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction 390system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction 391system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 392system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 393system.cpu1.op_class::total 170032 # Class of executed instruction |
| 394system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 386system.cpu1.dcache.tags.replacements 0 # number of replacements 387system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use 388system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. 389system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 390system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. 391system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 392system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor 393system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy 394system.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy 395system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 396system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 397system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 398system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 399system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses 400system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses | 395system.cpu1.dcache.tags.replacements 0 # number of replacements 396system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use 397system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. 398system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 399system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. 400system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 401system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor 402system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy 403system.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy 404system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 405system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 406system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 407system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 408system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses 409system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses |
| 410system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 401system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits 402system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits 403system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits 404system.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits 405system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 406system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 407system.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits 408system.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 499system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency 500system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency 501system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency 502system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 503system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 504system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 505system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 506system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency | 411system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits 412system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits 413system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits 414system.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits 415system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 416system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 417system.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits 418system.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 509system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency 510system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency 511system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency 512system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 513system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 514system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency 515system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency 516system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency |
| 517system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 507system.cpu1.icache.tags.replacements 280 # number of replacements 508system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use 509system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. 510system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 511system.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. 512system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor 514system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy 515system.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy 516system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 517system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 518system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 519system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 520system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 521system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses 522system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses | 518system.cpu1.icache.tags.replacements 280 # number of replacements 519system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use 520system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. 521system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 522system.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. 523system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 524system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor 525system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy 526system.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy 527system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 528system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 529system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 530system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 531system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 532system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses 533system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses |
| 534system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 523system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits 524system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits 525system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits 526system.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits 527system.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits 528system.cpu1.icache.overall_hits::total 169667 # number of overall hits 529system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 530system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 583system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses 584system.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 585system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency 586system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency 587system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 588system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 589system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 590system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency | 535system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits 536system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits 537system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits 538system.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits 539system.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits 540system.cpu1.icache.overall_hits::total 169667 # number of overall hits 541system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 542system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 595system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses 596system.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency 598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency 599system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 600system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency 601system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency 602system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency |
| 603system.cpu2.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states |
|
| 591system.cpu2.numCycles 528349 # number of cpu cycles simulated 592system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 593system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 594system.cpu2.committedInsts 165687 # Number of instructions committed 595system.cpu2.committedOps 165687 # Number of ops (including micro ops) committed 596system.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses 597system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 598system.cpu2.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 641system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction 642system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction 643system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction 644system.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction 645system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction 646system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 647system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 648system.cpu2.op_class::total 165719 # Class of executed instruction | 604system.cpu2.numCycles 528349 # number of cpu cycles simulated 605system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 607system.cpu2.committedInsts 165687 # Number of instructions committed 608system.cpu2.committedOps 165687 # Number of ops (including micro ops) committed 609system.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses 610system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 611system.cpu2.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 654system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction 655system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction 656system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction 657system.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction 658system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction 659system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 660system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 661system.cpu2.op_class::total 165719 # Class of executed instruction |
| 662system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 649system.cpu2.dcache.tags.replacements 0 # number of replacements 650system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use 651system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. 652system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 653system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. 654system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 655system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor 656system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy 657system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy 658system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 659system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 660system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 661system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 662system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses 663system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses | 663system.cpu2.dcache.tags.replacements 0 # number of replacements 664system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use 665system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. 666system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 667system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. 668system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 669system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor 670system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy 671system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy 672system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 673system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 674system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 675system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 676system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses 677system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses |
| 678system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 664system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits 665system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits 666system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits 667system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits 668system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 669system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 670system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits 671system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 762system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency 763system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency 764system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency 765system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency 766system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 767system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 768system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 769system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency | 679system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits 680system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits 681system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits 682system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits 683system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 684system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 685system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits 686system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 777system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency 778system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency 779system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency 780system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency 781system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 782system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency 783system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency 784system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency |
| 785system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 770system.cpu2.icache.tags.replacements 280 # number of replacements 771system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use 772system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. 773system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 774system.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. 775system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 776system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor 777system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy 778system.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy 779system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 780system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 781system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 782system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 783system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 784system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses 785system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses | 786system.cpu2.icache.tags.replacements 280 # number of replacements 787system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use 788system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. 789system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 790system.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. 791system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor 793system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy 794system.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy 795system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 796system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 797system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 798system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 799system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 800system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses 801system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses |
| 802system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 786system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits 787system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits 788system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits 789system.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits 790system.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits 791system.cpu2.icache.overall_hits::total 165354 # number of overall hits 792system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 793system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 846system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses 847system.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses 848system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency 849system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency 850system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 851system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 852system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 853system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency | 803system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits 804system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits 805system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits 806system.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits 807system.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits 808system.cpu2.icache.overall_hits::total 165354 # number of overall hits 809system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 810system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 863system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses 864system.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses 865system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency 866system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency 867system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 868system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency 869system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency 870system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency |
| 871system.cpu3.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states |
|
| 854system.cpu3.numCycles 528348 # number of cpu cycles simulated 855system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 856system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 857system.cpu3.committedInsts 169439 # Number of instructions committed 858system.cpu3.committedOps 169439 # Number of ops (including micro ops) committed 859system.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses 860system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 861system.cpu3.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 904system.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 905system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 906system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 907system.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction 908system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction 909system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 910system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 911system.cpu3.op_class::total 169471 # Class of executed instruction | 872system.cpu3.numCycles 528348 # number of cpu cycles simulated 873system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 874system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 875system.cpu3.committedInsts 169439 # Number of instructions committed 876system.cpu3.committedOps 169439 # Number of ops (including micro ops) committed 877system.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses 878system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 879system.cpu3.num_func_calls 637 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 922system.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 923system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 924system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 925system.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction 926system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction 927system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 928system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 929system.cpu3.op_class::total 169471 # Class of executed instruction |
| 930system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 912system.cpu3.dcache.tags.replacements 0 # number of replacements 913system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use 914system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. 915system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 916system.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. 917system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 918system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor 919system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy 920system.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy 921system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 922system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 923system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 924system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 925system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses 926system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses | 931system.cpu3.dcache.tags.replacements 0 # number of replacements 932system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use 933system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. 934system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 935system.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. 936system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 937system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor 938system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy 939system.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy 940system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 941system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 942system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 943system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 944system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses 945system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses |
| 946system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 927system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits 928system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits 929system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits 930system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits 931system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 932system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 933system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits 934system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 1025system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency 1026system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency 1027system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency 1028system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency 1029system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1030system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 1031system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1032system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency | 947system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits 948system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits 949system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits 950system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits 951system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 952system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 953system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits 954system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits --- 90 unchanged lines hidden (view full) --- 1045system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency 1046system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency 1047system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency 1048system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency 1049system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1050system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency 1051system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency 1052system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency |
| 1053system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1033system.cpu3.icache.tags.replacements 281 # number of replacements 1034system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use 1035system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. 1036system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1037system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. 1038system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1039system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor 1040system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy 1041system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy 1042system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1043system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1044system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1045system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1046system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1047system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses 1048system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses | 1054system.cpu3.icache.tags.replacements 281 # number of replacements 1055system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use 1056system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. 1057system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1058system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. 1059system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1060system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor 1061system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy 1062system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy 1063system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1064system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1065system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1066system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1067system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1068system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses 1069system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses |
| 1070system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1049system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits 1050system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits 1051system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits 1052system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits 1053system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits 1054system.cpu3.icache.overall_hits::total 169105 # number of overall hits 1055system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1056system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 1109system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses 1110system.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses 1111system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency 1112system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency 1113system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1114system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 1115system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1116system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency | 1071system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits 1072system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits 1073system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits 1074system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits 1075system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits 1076system.cpu3.icache.overall_hits::total 169105 # number of overall hits 1077system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1078system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 1131system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses 1132system.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses 1133system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency 1134system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency 1135system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1136system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency 1137system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency 1138system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency |
| 1139system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1117system.l2c.tags.replacements 0 # number of replacements 1118system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use 1119system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1120system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1121system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1122system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1123system.l2c.tags.occ_blocks::writebacks 0.880236 # Average occupied blocks per requestor 1124system.l2c.tags.occ_blocks::cpu0.inst 230.548613 # Average occupied blocks per requestor --- 15 unchanged lines hidden (view full) --- 1140system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1141system.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy 1142system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1143system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1144system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1145system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 1146system.l2c.tags.tag_accesses 19677 # Number of tag accesses 1147system.l2c.tags.data_accesses 19677 # Number of data accesses | 1140system.l2c.tags.replacements 0 # number of replacements 1141system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use 1142system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1143system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1144system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1145system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1146system.l2c.tags.occ_blocks::writebacks 0.880236 # Average occupied blocks per requestor 1147system.l2c.tags.occ_blocks::cpu0.inst 230.548613 # Average occupied blocks per requestor --- 15 unchanged lines hidden (view full) --- 1163system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1164system.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy 1165system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1166system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1167system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1168system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 1169system.l2c.tags.tag_accesses 19677 # Number of tag accesses 1170system.l2c.tags.data_accesses 19677 # Number of data accesses |
| 1171system.l2c.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1148system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1149system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1150system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1151system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1152system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1153system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1154system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1155system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits --- 385 unchanged lines hidden (view full) --- 1541system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 1542system.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 1543system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. 1544system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1545system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1546system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1547system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1548system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1172system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1173system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1174system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1175system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1176system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1177system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1178system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1179system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits --- 385 unchanged lines hidden (view full) --- 1565system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency 1566system.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency 1567system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. 1568system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1569system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1570system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1571system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1572system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1573system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1549system.membus.trans_dist::ReadResp 430 # Transaction distribution 1550system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 1551system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1552system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1553system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1554system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) 1555system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) 1556system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1571system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 1572system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1573system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. 1574system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1575system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1576system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1577system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1578system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1574system.membus.trans_dist::ReadResp 430 # Transaction distribution 1575system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 1576system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1577system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1578system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1579system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) 1580system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) 1581system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1596system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 1597system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1598system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. 1599system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1600system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1601system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1602system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1603system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1604system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states |
|
| 1579system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 1580system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1581system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 1582system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1583system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1584system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 1585system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 1586system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution --- 58 unchanged lines hidden --- | 1605system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 1606system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1607system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 1608system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1609system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1610system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 1611system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 1612system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution --- 58 unchanged lines hidden --- |