| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000264 # Number of seconds simulated 4sim_ticks 263565500 # Number of ticks simulated 5final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000264 # Number of seconds simulated 4sim_ticks 263565500 # Number of ticks simulated 5final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 798172 # Simulator instruction rate (inst/s) 8host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 317271660 # Simulator tick rate (ticks/s) 10host_mem_usage 306776 # Number of bytes of host memory used 11host_seconds 0.83 # Real time elapsed on the host | 7host_inst_rate 821706 # Simulator instruction rate (inst/s) 8host_op_rate 821692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 326627282 # Simulator tick rate (ticks/s) 10host_mem_usage 262816 # Number of bytes of host memory used 11host_seconds 0.81 # Real time elapsed on the host |
| 12sim_insts 663039 # Number of instructions simulated 13sim_ops 663039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory --- 175 unchanged lines hidden (view full) --- 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 663039 # Number of instructions simulated 13sim_ops 663039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory --- 175 unchanged lines hidden (view full) --- 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 203system.cpu0.dcache.fast_writes 0 # number of fast writes performed 204system.cpu0.dcache.cache_copies 0 # number of cache copies performed | |
| 205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 206system.cpu0.dcache.writebacks::total 1 # number of writebacks 207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses 208system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses 209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency 240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency 241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency 242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency 243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency 244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency 245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency 246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency | 203system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 204system.cpu0.dcache.writebacks::total 1 # number of writebacks 205system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses 206system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses 207system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 208system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 209system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 210system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses --- 26 unchanged lines hidden (view full) --- 237system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency 238system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency 239system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency 240system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency 241system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency 242system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency 243system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency 244system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency |
| 247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 248system.cpu0.icache.tags.replacements 215 # number of replacements 249system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use 250system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. 251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 252system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. 253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 254system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor 255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency 298system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency 299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 245system.cpu0.icache.tags.replacements 215 # number of replacements 246system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use 247system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. 248system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 249system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. 250system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor 252system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 294system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency 295system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency 296system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 297system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 298system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 299system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 300system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 301system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 305system.cpu0.icache.fast_writes 0 # number of fast writes performed 306system.cpu0.icache.cache_copies 0 # number of cache copies performed | |
| 307system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 308system.cpu0.icache.writebacks::total 215 # number of writebacks 309system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 310system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 311system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 312system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 313system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 314system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 325system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses 326system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses 327system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency 328system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency 329system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency 330system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency 331system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency 332system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency | 302system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 303system.cpu0.icache.writebacks::total 215 # number of writebacks 304system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 305system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 306system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 307system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 308system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 309system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 320system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses 321system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses 322system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency 323system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency 324system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency 325system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency 326system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency 327system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency |
| 333system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 334system.cpu1.numCycles 527130 # number of cpu cycles simulated 335system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 336system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 337system.cpu1.committedInsts 170790 # Number of instructions committed 338system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed 339system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses 340system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 341system.cpu1.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 465system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency 466system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency 467system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 328system.cpu1.numCycles 527130 # number of cpu cycles simulated 329system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 330system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 331system.cpu1.committedInsts 170790 # Number of instructions committed 332system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed 333system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses 334system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 335system.cpu1.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 459system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency 460system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency 461system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 465system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 473system.cpu1.dcache.fast_writes 0 # number of fast writes performed 474system.cpu1.dcache.cache_copies 0 # number of cache copies performed | |
| 475system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses 476system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses 477system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 478system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 479system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 480system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 481system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses 482system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 507system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency 508system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency 509system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency 510system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency 511system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency 512system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency 513system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency 514system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency | 467system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses 468system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses 469system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 470system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 471system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 472system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 473system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses 474system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 499system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency 500system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency 501system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency 502system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency 503system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency 504system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency 505system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency 506system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency |
| 515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 516system.cpu1.icache.tags.replacements 280 # number of replacements 517system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use 518system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. 519system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 520system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. 521system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 522system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor 523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency 567system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency 568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 507system.cpu1.icache.tags.replacements 280 # number of replacements 508system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use 509system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. 510system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 511system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. 512system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor 514system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 557system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency 558system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency 559system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 563system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 574system.cpu1.icache.fast_writes 0 # number of fast writes performed 575system.cpu1.icache.cache_copies 0 # number of cache copies performed | |
| 576system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 577system.cpu1.icache.writebacks::total 280 # number of writebacks 578system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 579system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 580system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 581system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 582system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 583system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 594system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses 595system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses 596system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency 597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency 598system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency 599system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency 600system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency 601system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency | 565system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 566system.cpu1.icache.writebacks::total 280 # number of writebacks 567system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 568system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 569system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 570system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 571system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 572system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 583system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses 584system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses 585system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency 586system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency 587system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency 588system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency 589system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency 590system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency |
| 602system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 603system.cpu2.numCycles 527130 # number of cpu cycles simulated 604system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 605system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 606system.cpu2.committedInsts 168244 # Number of instructions committed 607system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed 608system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses 609system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 610system.cpu2.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 734system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency 735system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency 736system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 591system.cpu2.numCycles 527130 # number of cpu cycles simulated 592system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 593system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 594system.cpu2.committedInsts 168244 # Number of instructions committed 595system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed 596system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses 597system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 598system.cpu2.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 722system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency 723system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency 724system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 725system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 726system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 727system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 728system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 729system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 742system.cpu2.dcache.fast_writes 0 # number of fast writes performed 743system.cpu2.dcache.cache_copies 0 # number of cache copies performed | |
| 744system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses 745system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 746system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses 747system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses 748system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 749system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 750system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses 751system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 776system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency 777system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency 778system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency 779system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency 780system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency 781system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency 782system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency 783system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency | 730system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses 731system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 732system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses 733system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses 734system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 735system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 736system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses 737system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 762system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency 763system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency 764system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency 765system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency 766system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency 767system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency 768system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency 769system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency |
| 784system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 785system.cpu2.icache.tags.replacements 280 # number of replacements 786system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use 787system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. 788system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 789system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. 790system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor 792system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 835system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency 836system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency 837system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 770system.cpu2.icache.tags.replacements 280 # number of replacements 771system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use 772system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. 773system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 774system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. 775system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 776system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor 777system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 820system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency 821system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency 822system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 823system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 824system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 825system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 826system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 827system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 843system.cpu2.icache.fast_writes 0 # number of fast writes performed 844system.cpu2.icache.cache_copies 0 # number of cache copies performed | |
| 845system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 846system.cpu2.icache.writebacks::total 280 # number of writebacks 847system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 848system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 849system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 850system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 851system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 852system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 863system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses 864system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses 865system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency 866system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency 867system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency 868system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency 869system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency 870system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency | 828system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 829system.cpu2.icache.writebacks::total 280 # number of writebacks 830system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 831system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 832system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 833system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 834system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 835system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 846system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses 847system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses 848system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency 849system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency 850system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency 851system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency 852system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency 853system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency |
| 871system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 872system.cpu3.numCycles 527131 # number of cpu cycles simulated 873system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 874system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 875system.cpu3.committedInsts 165809 # Number of instructions committed 876system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed 877system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses 878system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 879system.cpu3.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 1003system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency 1004system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency 1005system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1009system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 854system.cpu3.numCycles 527131 # number of cpu cycles simulated 855system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 856system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 857system.cpu3.committedInsts 165809 # Number of instructions committed 858system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed 859system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses 860system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 861system.cpu3.num_func_calls 637 # number of times a function call or return occured --- 123 unchanged lines hidden (view full) --- 985system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency 986system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency 987system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 988system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 989system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 990system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 991system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 992system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1011system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu3.dcache.cache_copies 0 # number of cache copies performed | |
| 1013system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses 1014system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses 1015system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses 1016system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 1017system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 1018system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1019system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses 1020system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 1045system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency 1046system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency 1047system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency 1048system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency 1049system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency 1050system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency 1051system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency 1052system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency | 993system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses 994system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses 995system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses 996system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 997system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 998system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 999system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses 1000system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses --- 24 unchanged lines hidden (view full) --- 1025system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency 1026system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency 1027system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency 1028system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency 1029system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency 1030system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency 1031system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency 1032system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency |
| 1053system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1054system.cpu3.icache.tags.replacements 281 # number of replacements 1055system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use 1056system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. 1057system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1058system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks. 1059system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1060system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor 1061system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1104system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1105system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency 1106system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1107system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1108system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1109system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1110system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1111system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1033system.cpu3.icache.tags.replacements 281 # number of replacements 1034system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use 1035system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. 1036system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1037system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks. 1038system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1039system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor 1040system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1083system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1084system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency 1085system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1086system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1087system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1088system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1089system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1090system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1112system.cpu3.icache.fast_writes 0 # number of fast writes performed 1113system.cpu3.icache.cache_copies 0 # number of cache copies performed | |
| 1114system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1115system.cpu3.icache.writebacks::total 281 # number of writebacks 1116system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1117system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1118system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1119system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1120system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1121system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 1132system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses 1133system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses 1134system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency 1135system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency 1136system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1137system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1138system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1139system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency | 1091system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1092system.cpu3.icache.writebacks::total 281 # number of writebacks 1093system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1094system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1095system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1096system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1097system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1098system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 1109system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses 1110system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses 1111system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency 1112system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency 1113system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1114system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1115system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1116system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency |
| 1140system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1141system.l2c.tags.replacements 0 # number of replacements 1142system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use 1143system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1144system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1145system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1146system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1147system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor 1148system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor --- 239 unchanged lines hidden (view full) --- 1388system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency 1389system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency 1390system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1391system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1392system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1393system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1394system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1395system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1117system.l2c.tags.replacements 0 # number of replacements 1118system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use 1119system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1120system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1121system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1122system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1123system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor 1124system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor --- 239 unchanged lines hidden (view full) --- 1364system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency 1365system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency 1366system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1367system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1368system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1369system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1370system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1371system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1396system.l2c.fast_writes 0 # number of fast writes performed 1397system.l2c.cache_copies 0 # number of cache copies performed | |
| 1398system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 1399system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits 1400system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits 1401system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 1402system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 1403system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits 1404system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits 1405system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits --- 155 unchanged lines hidden (view full) --- 1561system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1562system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency 1563system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency 1564system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency 1565system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency 1566system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency 1567system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency 1568system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency | 1372system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 1373system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits 1374system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits 1375system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 1376system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 1377system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits 1378system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits 1379system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits --- 155 unchanged lines hidden (view full) --- 1535system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1536system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency 1537system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency 1538system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency 1539system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency 1540system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency 1541system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency 1542system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency |
| 1569system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1570system.membus.trans_dist::ReadResp 430 # Transaction distribution 1571system.membus.trans_dist::UpgradeReq 271 # Transaction distribution 1572system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1573system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1574system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1575system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) 1576system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) --- 88 unchanged lines hidden --- | 1543system.membus.trans_dist::ReadResp 430 # Transaction distribution 1544system.membus.trans_dist::UpgradeReq 271 # Transaction distribution 1545system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1546system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1547system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1548system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) 1549system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) 1550system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) --- 88 unchanged lines hidden --- |