| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000260 # Number of seconds simulated 4sim_ticks 260073500 # Number of ticks simulated 5final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000261 # Number of seconds simulated 4sim_ticks 260712500 # Number of ticks simulated 5final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1077387 # Simulator instruction rate (inst/s) 8host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 425087977 # Simulator tick rate (ticks/s) 10host_mem_usage 303432 # Number of bytes of host memory used 11host_seconds 0.61 # Real time elapsed on the host 12sim_insts 659129 # Number of instructions simulated 13sim_ops 659129 # Number of ops (including micro ops) simulated | 7host_inst_rate 1018019 # Simulator instruction rate (inst/s) 8host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 401917302 # Simulator tick rate (ticks/s) 10host_mem_usage 306320 # Number of bytes of host memory used 11host_seconds 0.65 # Real time elapsed on the host 12sim_insts 660333 # Number of instructions simulated 13sim_ops 660333 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory --- 9 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory --- 9 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory |
| 39system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s) |
| 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls | 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 64system.cpu0.numCycles 520147 # number of cpu cycles simulated | 64system.cpu0.numCycles 521425 # number of cpu cycles simulated |
| 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 67system.cpu0.committedInsts 157434 # Number of instructions committed 68system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses | 67system.cpu0.committedInsts 157788 # Number of instructions committed 68system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses |
| 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured | 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured |
| 72system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls 73system.cpu0.num_int_insts 108448 # number of integer instructions | 72system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls 73system.cpu0.num_int_insts 108684 # number of integer instructions |
| 74system.cpu0.num_fp_insts 0 # number of float instructions | 74system.cpu0.num_fp_insts 0 # number of float instructions |
| 75system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read 76system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written | 75system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read 76system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written |
| 77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written | 77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written |
| 79system.cpu0.num_mem_refs 73451 # number of memory refs 80system.cpu0.num_load_insts 48627 # Number of load instructions 81system.cpu0.num_store_insts 24824 # Number of store instructions | 79system.cpu0.num_mem_refs 73628 # number of memory refs 80system.cpu0.num_load_insts 48745 # Number of load instructions 81system.cpu0.num_store_insts 24883 # Number of store instructions |
| 82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles | 82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles |
| 83system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles | 83system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles |
| 84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles | 84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles |
| 86system.cpu0.Branches 26707 # Number of branches fetched 87system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction 88system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction 89system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction 90system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction 91system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction 92system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction 93system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction 94system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction 95system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction 96system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction 97system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction 98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction 99system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction 100system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction 101system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction 102system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction 103system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction 104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction 105system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction 106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction 107system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction 108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction 109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction 110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction 111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction 112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction 113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction 114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction 117system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction 118system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction | 86system.cpu0.Branches 26766 # Number of branches fetched 87system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction 88system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction 89system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction 90system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction 91system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction 92system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction 93system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction 94system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction 95system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction 96system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction 97system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction 98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction 99system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction 100system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction 101system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction 102system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction 103system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction 104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction 105system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction 106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction 107system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction 108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction 109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction 110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction 111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction 112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction 113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction 114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction 117system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction 118system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction |
| 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 121system.cpu0.op_class::total 157496 # Class of executed instruction | 121system.cpu0.op_class::total 157850 # Class of executed instruction |
| 122system.cpu0.dcache.tags.replacements 2 # number of replacements | 122system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 123system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks. | 123system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks. |
| 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. | 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. |
| 126system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks. | 126system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks. |
| 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy | 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy |
| 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id | 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id |
| 135system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses 137system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits | 135system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses 137system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits |
| 141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits | 141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits |
| 143system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits 145system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits 146system.cpu0.dcache.overall_hits::total 73037 # number of overall hits 147system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 148system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses | 143system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits 145system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits 146system.cpu0.dcache.overall_hits::total 73215 # number of overall hits 147system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses 148system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses |
| 149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses | 149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses |
| 153system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 154system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 155system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 156system.cpu0.dcache.overall_misses::total 353 # number of overall misses 157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles 158system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles 159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles 160system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles | 153system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses 154system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses 155system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses 156system.cpu0.dcache.overall_misses::total 352 # number of overall misses 157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles 158system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles 159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles 160system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles |
| 161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles 162system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles | 161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles 162system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles |
| 163system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles 164system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles 165system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles 166system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles 167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses) | 163system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles 164system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles 165system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles 166system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles 167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses) |
| 171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 173system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses 174system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses 175system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses 176system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses 177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses 178system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses 180system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses | 173system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses 174system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses 175system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses 176system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses 177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses 178system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses 180system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses |
| 181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses | 181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses |
| 183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses 184system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses 185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses 186system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses 187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency 188system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency 189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency 190system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency | 183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses 184system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses 185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses 186system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses 187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency 188system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency 189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency 190system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency |
| 191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency 192system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency | 191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency 192system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency |
| 193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency 194system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency | 193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency 194system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency |
| 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 203system.cpu0.dcache.fast_writes 0 # number of fast writes performed 204system.cpu0.dcache.cache_copies 0 # number of cache copies performed 205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 206system.cpu0.dcache.writebacks::total 1 # number of writebacks | 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 203system.cpu0.dcache.fast_writes 0 # number of fast writes performed 204system.cpu0.dcache.cache_copies 0 # number of cache copies performed 205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 206system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 208system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses | 207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses 208system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses |
| 209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses | 209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses |
| 213system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 214system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 215system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 216system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles 218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles 219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles 220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles | 213system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses 214system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses 215system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses 216system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses 217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles 218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles 219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles 220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles |
| 221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles 222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles | 221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles 222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles |
| 223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles 224system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles 225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles 226system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles 227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses 228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses 229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses 230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses | 223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles 224system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles 225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles 226system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles 227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses 228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses 229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses 230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses |
| 231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses | 231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses |
| 233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses 234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses 235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses 236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses 237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency 238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency 239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency 240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency | 233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses 234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses 235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses 236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses 237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency 238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency 239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency 240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency |
| 241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency 242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency | 241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency 242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency |
| 243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency 244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency 245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency 246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency | 243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency 244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency 245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency 246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency |
| 247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 248system.cpu0.icache.tags.replacements 215 # number of replacements | 247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 248system.cpu0.icache.tags.replacements 215 # number of replacements |
| 249system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use 250system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks. | 249system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use 250system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks. |
| 251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. | 251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. |
| 252system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks. | 252system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks. |
| 253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 254system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor 255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy 256system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy | 254system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor 255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy 256system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy |
| 257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id | 257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id |
| 261system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses 262system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses 263system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits 264system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits 265system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits 266system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits 267system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits 268system.cpu0.icache.overall_hits::total 157030 # number of overall hits | 261system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses 262system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses 263system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits 264system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits 265system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits 266system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits 267system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits 268system.cpu0.icache.overall_hits::total 157384 # number of overall hits |
| 269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 274system.cpu0.icache.overall_misses::total 467 # number of overall misses | 269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 274system.cpu0.icache.overall_misses::total 467 # number of overall misses |
| 275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles 276system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles 277system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles 278system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles 279system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles 280system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles 281system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses) 282system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses) 283system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses 284system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses 285system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses 286system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses 287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses 288system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses 289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses 290system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses 291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses 292system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses 293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency 294system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency 295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency 296system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency 297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency 298system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency | 275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles 276system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles 277system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles 278system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles 279system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles 280system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles 281system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses) 282system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses) 283system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses 284system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses 285system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses 286system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses 287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses 288system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses 289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses 290system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses 291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses 292system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses 293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency 294system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency 295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency 296system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency 297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency 298system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency |
| 299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu0.icache.fast_writes 0 # number of fast writes performed 306system.cpu0.icache.cache_copies 0 # number of cache copies performed 307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 308system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 309system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 310system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 311system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 312system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses | 299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu0.icache.fast_writes 0 # number of fast writes performed 306system.cpu0.icache.cache_copies 0 # number of cache copies performed 307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 308system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 309system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 310system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 311system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 312system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses |
| 313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles 314system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles 315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles 316system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles 317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles 318system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles 319system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses 320system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses 321system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses 322system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses 323system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses 324system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses 325system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency 326system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency 327system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency 328system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency 329system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency 330system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency | 313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles 314system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles 315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles 316system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles 317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles 318system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles 319system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses 320system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses 321system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses 322system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses 323system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses 324system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses 325system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency 326system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency 327system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency 328system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency 329system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency 330system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency |
| 331system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 331system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 332system.cpu1.numCycles 520147 # number of cpu cycles simulated | 332system.cpu1.numCycles 521425 # number of cpu cycles simulated |
| 333system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 334system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 333system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 334system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 335system.cpu1.committedInsts 165571 # Number of instructions committed 336system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed 337system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses | 335system.cpu1.committedInsts 168182 # Number of instructions committed 336system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed 337system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses |
| 338system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 339system.cpu1.num_func_calls 637 # number of times a function call or return occured | 338system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 339system.cpu1.num_func_calls 637 # number of times a function call or return occured |
| 340system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls 341system.cpu1.num_int_insts 111555 # number of integer instructions | 340system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls 341system.cpu1.num_int_insts 110851 # number of integer instructions |
| 342system.cpu1.num_fp_insts 0 # number of float instructions | 342system.cpu1.num_fp_insts 0 # number of float instructions |
| 343system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read 344system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written | 343system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read 344system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written |
| 345system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 346system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written | 345system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 346system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written |
| 347system.cpu1.num_mem_refs 56707 # number of memory refs 348system.cpu1.num_load_insts 41448 # Number of load instructions 349system.cpu1.num_store_insts 15259 # Number of store instructions 350system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles 351system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles 352system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles 353system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles 354system.cpu1.Branches 32668 # Number of branches fetched 355system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction 356system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction 357system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction 358system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction 359system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction 360system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction 361system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction 362system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction 363system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction 364system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction 365system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction 366system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction 367system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction 368system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction 369system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction 370system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction 371system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction 372system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction 373system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction 374system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction 375system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction 376system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction 377system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction 378system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction 379system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction 380system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction 381system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction 382system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction 383system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction 384system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction 385system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction 386system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction | 347system.cpu1.num_mem_refs 54346 # number of memory refs 348system.cpu1.num_load_insts 41092 # Number of load instructions 349system.cpu1.num_store_insts 13254 # Number of store instructions 350system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles 351system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles 352system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles 353system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles 354system.cpu1.Branches 34327 # Number of branches fetched 355system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction 356system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction 357system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction 358system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction 359system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction 360system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction 361system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction 362system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction 363system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction 364system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction 365system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction 366system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction 367system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction 368system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction 369system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction 370system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction 371system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction 372system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction 373system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction 374system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction 375system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction 376system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction 377system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction 378system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction 379system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction 380system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction 381system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction 382system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction 383system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction 384system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction 385system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction 386system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction |
| 387system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 388system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 387system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 388system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 389system.cpu1.op_class::total 165603 # Class of executed instruction | 389system.cpu1.op_class::total 168214 # Class of executed instruction |
| 390system.cpu1.dcache.tags.replacements 0 # number of replacements | 390system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 391system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use 392system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks. | 391system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use 392system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks. |
| 393system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. | 393system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. |
| 394system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks. | 394system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks. |
| 395system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 395system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 396system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor 397system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy 398system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy | 396system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor 397system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy 398system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy |
| 399system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 400system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 401system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 402system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id | 399system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 400system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 401system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 402system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id |
| 403system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses 404system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses 405system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits 406system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits 407system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits 408system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits 409system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 410system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 411system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits 412system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits 413system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits 414system.cpu1.dcache.overall_hits::total 56366 # number of overall hits 415system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses 416system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses 417system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses 418system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses 419system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses 420system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses 421system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses 422system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses 423system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses 424system.cpu1.dcache.overall_misses::total 265 # number of overall misses 425system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles 426system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles 427system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles 428system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles 429system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles 430system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles 431system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles 432system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles 433system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles 434system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles 435system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses) 436system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses) 437system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses) 438system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses) 439system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) 440system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 441system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses 442system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses 443system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses 444system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses 445system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses 446system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses 447system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses 448system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses 449system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses 450system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 451system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses 452system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses 453system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses 454system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses 455system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency 456system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency 457system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency 458system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency 459system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency 460system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency 461system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency 462system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency 463system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency 464system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency | 403system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses 404system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses 405system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits 406system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits 407system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits 408system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits 409system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 410system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 411system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits 412system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits 413system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits 414system.cpu1.dcache.overall_hits::total 53996 # number of overall hits 415system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses 416system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses 417system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses 418system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses 419system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 420system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 421system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses 422system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses 423system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses 424system.cpu1.dcache.overall_misses::total 271 # number of overall misses 425system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles 426system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles 427system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles 428system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles 429system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles 430system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles 431system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles 432system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles 433system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles 434system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles 435system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses) 436system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses) 437system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses) 438system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses) 439system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) 440system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 441system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses 442system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses 443system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses 444system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses 445system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses 446system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses 447system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses 448system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses 449system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses 450system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 451system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses 452system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses 453system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses 454system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses 455system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency 456system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency 457system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency 458system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency 459system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency 460system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency 461system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency 462system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency 463system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency 464system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency |
| 465system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 466system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 467system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 468system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 469system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 470system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 471system.cpu1.dcache.fast_writes 0 # number of fast writes performed 472system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 465system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 466system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 467system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 468system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 469system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 470system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 471system.cpu1.dcache.fast_writes 0 # number of fast writes performed 472system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 473system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses 474system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses 475system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses 476system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 477system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses 478system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 479system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses 480system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 481system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses 482system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 483system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles 484system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles 485system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles 486system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles 487system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles 488system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles 489system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles 490system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles 491system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles 492system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles 493system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses 494system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses 495system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses 496system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses 497system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses 498system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 499system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses 500system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses 501system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses 502system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses 503system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency 504system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency 505system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency 506system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency 507system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency 508system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency 509system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency 510system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency 511system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency 512system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency | 473system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses 474system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 475system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses 476system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 477system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 478system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 479system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses 480system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 481system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses 482system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 483system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles 484system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles 485system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles 486system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles 487system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles 488system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles 489system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles 490system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles 491system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles 492system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles 493system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses 494system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses 495system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses 496system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses 497system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses 498system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 499system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses 500system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses 501system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses 502system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses 503system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency 504system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency 505system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency 506system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency 507system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency 508system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency 509system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency 510system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency 511system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency 512system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency |
| 513system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu1.icache.tags.replacements 280 # number of replacements | 513system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu1.icache.tags.replacements 280 # number of replacements |
| 515system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use 516system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks. | 515system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use 516system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks. |
| 517system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. | 517system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. |
| 518system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks. | 518system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks. |
| 519system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 519system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 520system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor 521system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy 522system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy | 520system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor 521system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy 522system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy |
| 523system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 524system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 525system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 526system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 527system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id | 523system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 524system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 525system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 526system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 527system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id |
| 528system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses 529system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses 530system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits 531system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits 532system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits 533system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits 534system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits 535system.cpu1.icache.overall_hits::total 165238 # number of overall hits | 528system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses 529system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses 530system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits 531system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits 532system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits 533system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits 534system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits 535system.cpu1.icache.overall_hits::total 167849 # number of overall hits |
| 536system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 537system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 538system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 539system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 540system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 541system.cpu1.icache.overall_misses::total 366 # number of overall misses | 536system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 537system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 538system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 539system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 540system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 541system.cpu1.icache.overall_misses::total 366 # number of overall misses |
| 542system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles 543system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles 544system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles 545system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles 546system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles 547system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles 548system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses) 549system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses) 550system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses 551system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses 552system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses 553system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses 554system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses 555system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses 556system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses 557system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses 558system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses 559system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses 560system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency 561system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency 562system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency 563system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency 564system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency 565system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency | 542system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles 543system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles 544system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles 545system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles 546system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles 547system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles 548system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses) 549system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses) 550system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses 551system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses 552system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses 553system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses 554system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses 555system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses 556system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses 557system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses 558system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses 559system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses 560system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency 561system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency 562system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency 563system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency 564system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency 565system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency |
| 566system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu1.icache.fast_writes 0 # number of fast writes performed 573system.cpu1.icache.cache_copies 0 # number of cache copies performed 574system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 575system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 576system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 577system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 578system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 579system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 566system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu1.icache.fast_writes 0 # number of fast writes performed 573system.cpu1.icache.cache_copies 0 # number of cache copies performed 574system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 575system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 576system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 577system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 578system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 579system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 580system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles 581system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles 582system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles 583system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles 584system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles 585system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles 586system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses 587system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses 588system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses 589system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses 590system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses 591system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses 592system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency 593system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency 594system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency 595system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency 596system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency 597system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency | 580system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles 581system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles 582system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles 583system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles 584system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles 585system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles 586system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses 587system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses 588system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses 589system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses 590system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses 591system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses 592system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency 593system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency 594system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency 595system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency 596system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency 597system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency |
| 598system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 598system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 599system.cpu2.numCycles 520146 # number of cpu cycles simulated | 599system.cpu2.numCycles 521424 # number of cpu cycles simulated |
| 600system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 601system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 600system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 601system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 602system.cpu2.committedInsts 160598 # Number of instructions committed 603system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed 604system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses | 602system.cpu2.committedInsts 165155 # Number of instructions committed 603system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed 604system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses |
| 605system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 606system.cpu2.num_func_calls 637 # number of times a function call or return occured | 605system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 606system.cpu2.num_func_calls 637 # number of times a function call or return occured |
| 607system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls 608system.cpu2.num_int_insts 111601 # number of integer instructions | 607system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls 608system.cpu2.num_int_insts 110249 # number of integer instructions |
| 609system.cpu2.num_fp_insts 0 # number of float instructions | 609system.cpu2.num_fp_insts 0 # number of float instructions |
| 610system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read 611system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written | 610system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read 611system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written |
| 612system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 613system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written | 612system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 613system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written |
| 614system.cpu2.num_mem_refs 59264 # number of memory refs 615system.cpu2.num_load_insts 41473 # Number of load instructions 616system.cpu2.num_store_insts 17791 # Number of store instructions 617system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles 618system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles 619system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles 620system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles 621system.cpu2.Branches 30158 # Number of branches fetched 622system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction 623system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction 624system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction 625system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction 626system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction 627system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction 628system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction 629system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction 630system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction 631system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction 632system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction 633system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction 634system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction 635system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction 636system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction 637system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction 638system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction 639system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction 640system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction 641system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction 642system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction 643system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction 644system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction 645system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction 646system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction 647system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction 648system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction 649system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction 650system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction 651system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction 652system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction 653system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction | 614system.cpu2.num_mem_refs 54956 # number of memory refs 615system.cpu2.num_load_insts 40791 # Number of load instructions 616system.cpu2.num_store_insts 14165 # Number of store instructions 617system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles 618system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles 619system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles 620system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles 621system.cpu2.Branches 33115 # Number of branches fetched 622system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction 623system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction 624system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction 625system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction 626system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction 627system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction 628system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction 629system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction 630system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction 631system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction 632system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction 633system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction 634system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction 635system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction 636system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction 637system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction 638system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction 639system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction 640system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction 641system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction 642system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction 643system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction 644system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction 645system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction 646system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction 647system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction 648system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction 649system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction 650system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction 651system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction 652system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction 653system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction |
| 654system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 655system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 654system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 655system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 656system.cpu2.op_class::total 160630 # Class of executed instruction | 656system.cpu2.op_class::total 165187 # Class of executed instruction |
| 657system.cpu2.dcache.tags.replacements 0 # number of replacements | 657system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 658system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use 659system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks. | 658system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use 659system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks. |
| 660system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. | 660system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. |
| 661system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks. | 661system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks. |
| 662system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 662system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 663system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor 664system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy 665system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy | 663system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor 664system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy 665system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy |
| 666system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 667system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 668system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 669system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id | 666system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 667system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 668system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 669system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id |
| 670system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses 671system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses 672system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits 673system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits 674system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits 675system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits 676system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 677system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits 678system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits 679system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits 680system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits 681system.cpu2.dcache.overall_hits::total 58928 # number of overall hits 682system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses 683system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses 684system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses 685system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses 686system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 687system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 688system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses 689system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses 690system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses 691system.cpu2.dcache.overall_misses::total 261 # number of overall misses 692system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles 693system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles 694system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles 695system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles 696system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles 697system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles 698system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles 699system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles 700system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles 701system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles 702system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses) 703system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses) 704system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses) 705system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses) 706system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses) 707system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 708system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses 709system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses 710system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses 711system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses 712system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses 713system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses 714system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses 715system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses 716system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses 717system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses 718system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses 719system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses 720system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses 721system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses 722system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency 723system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency 724system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency 725system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency 726system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency 727system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency 728system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency 729system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency 730system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency 731system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency | 670system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses 671system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses 672system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits 673system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits 674system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits 675system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits 676system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 677system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 678system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits 679system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits 680system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits 681system.cpu2.dcache.overall_hits::total 54608 # number of overall hits 682system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses 683system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses 684system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses 685system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses 686system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses 687system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses 688system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 689system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 690system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 691system.cpu2.dcache.overall_misses::total 269 # number of overall misses 692system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles 693system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles 694system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles 695system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles 696system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles 697system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles 698system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles 699system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles 700system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles 701system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles 702system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses) 703system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses) 704system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses) 705system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses) 706system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 707system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 708system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses 709system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses 710system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses 711system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses 712system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses 713system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses 714system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses 715system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses 716system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses 717system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 718system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses 719system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses 720system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses 721system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses 722system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency 723system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency 724system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency 725system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency 726system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency 727system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency 728system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency 729system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency 730system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency 731system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency |
| 732system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu2.dcache.fast_writes 0 # number of fast writes performed 739system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 732system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu2.dcache.fast_writes 0 # number of fast writes performed 739system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 740system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses 741system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses 742system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses 743system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses 744system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses 745system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 746system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses 747system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses 748system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses 749system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses 750system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles 751system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles 752system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles 753system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles 754system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles 755system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles 756system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles 757system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles 758system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles 759system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles 760system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses 761system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses 762system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses 763system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses 764system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses 765system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses 766system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses 767system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses 768system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses 769system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses 770system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency 771system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency 772system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency 773system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency 774system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency 775system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency 776system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency 777system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency 778system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency 779system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency | 740system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 741system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 742system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 743system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 744system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses 745system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 746system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses 747system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 748system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses 749system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 750system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles 751system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles 752system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles 753system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles 754system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles 755system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles 756system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles 757system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles 758system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles 759system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles 760system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses 761system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses 762system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses 763system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses 764system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses 765system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 766system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses 767system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses 768system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses 769system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses 770system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency 771system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency 772system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency 773system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency 774system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency 775system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency 776system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency 777system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency 778system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency 779system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency |
| 780system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 781system.cpu2.icache.tags.replacements 280 # number of replacements | 780system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 781system.cpu2.icache.tags.replacements 280 # number of replacements |
| 782system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use 783system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks. | 782system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use 783system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks. |
| 784system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. | 784system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. |
| 785system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks. | 785system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks. |
| 786system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 786system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 787system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor 788system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy 789system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy | 787system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor 788system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy 789system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy |
| 790system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 791system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 792system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 793system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 794system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id | 790system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 791system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 792system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 793system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 794system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id |
| 795system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses 796system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses 797system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits 798system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits 799system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits 800system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits 801system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits 802system.cpu2.icache.overall_hits::total 160265 # number of overall hits | 795system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses 796system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses 797system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits 798system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits 799system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits 800system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits 801system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits 802system.cpu2.icache.overall_hits::total 164822 # number of overall hits |
| 803system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 804system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 805system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 806system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 807system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 808system.cpu2.icache.overall_misses::total 366 # number of overall misses | 803system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 804system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 805system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 806system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 807system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 808system.cpu2.icache.overall_misses::total 366 # number of overall misses |
| 809system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles 810system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles 811system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles 812system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles 813system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles 814system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles 815system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses) 816system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses) 817system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses 818system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses 819system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses 820system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses 821system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses 822system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses 823system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses 824system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses 825system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses 826system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses 827system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency 828system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency 829system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency 830system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency 831system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency 832system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency | 809system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles 810system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles 811system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles 812system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles 813system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles 814system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles 815system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses) 816system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses) 817system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses 818system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses 819system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses 820system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses 821system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses 822system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses 823system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses 824system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses 825system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses 826system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses 827system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency 828system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency 829system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency 830system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency 831system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency 832system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency |
| 833system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 834system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 835system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 836system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 837system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 838system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 839system.cpu2.icache.fast_writes 0 # number of fast writes performed 840system.cpu2.icache.cache_copies 0 # number of cache copies performed 841system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 842system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 843system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 844system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 845system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 846system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 833system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 834system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 835system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 836system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 837system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 838system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 839system.cpu2.icache.fast_writes 0 # number of fast writes performed 840system.cpu2.icache.cache_copies 0 # number of cache copies performed 841system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 842system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 843system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 844system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 845system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 846system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 847system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles 848system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles 849system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles 850system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles 851system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles 852system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles 853system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses 854system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses 855system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses 856system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses 857system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses 858system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses 859system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency 860system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency 861system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency 862system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency 863system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency 864system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency | 847system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles 848system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles 849system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles 850system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles 851system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles 852system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles 853system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses 854system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses 855system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses 856system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses 857system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses 858system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses 859system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency 860system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency 861system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency 862system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency 863system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency 864system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency |
| 865system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 865system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 866system.cpu3.numCycles 520146 # number of cpu cycles simulated | 866system.cpu3.numCycles 521424 # number of cpu cycles simulated |
| 867system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 868system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 867system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 868system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 869system.cpu3.committedInsts 175526 # Number of instructions committed 870system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed 871system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses | 869system.cpu3.committedInsts 169208 # Number of instructions committed 870system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed 871system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses |
| 872system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 873system.cpu3.num_func_calls 637 # number of times a function call or return occured | 872system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 873system.cpu3.num_func_calls 637 # number of times a function call or return occured |
| 874system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls 875system.cpu3.num_int_insts 107877 # number of integer instructions | 874system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls 875system.cpu3.num_int_insts 110441 # number of integer instructions |
| 876system.cpu3.num_fp_insts 0 # number of float instructions | 876system.cpu3.num_fp_insts 0 # number of float instructions |
| 877system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read 878system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written | 877system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read 878system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written |
| 879system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 880system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written | 879system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 880system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written |
| 881system.cpu3.num_mem_refs 46213 # number of memory refs 882system.cpu3.num_load_insts 39592 # Number of load instructions 883system.cpu3.num_store_insts 6621 # Number of store instructions 884system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles 885system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles 886system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles 887system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles 888system.cpu3.Branches 39491 # Number of branches fetched 889system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction 890system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction 891system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction 892system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction 893system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction 894system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction 895system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction 896system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction 897system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction 898system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction 899system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction 900system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction 901system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction 902system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction 903system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction 904system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction 905system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction 906system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction 907system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction 908system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction 909system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction 910system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction 911system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction 912system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction 913system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction 914system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction 915system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction 916system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction 917system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction 918system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction 919system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction 920system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction | 881system.cpu3.num_mem_refs 53219 # number of memory refs 882system.cpu3.num_load_insts 40883 # Number of load instructions 883system.cpu3.num_store_insts 12336 # Number of store instructions 884system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles 885system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles 886system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles 887system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles 888system.cpu3.Branches 35047 # Number of branches fetched 889system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction 890system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction 891system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction 892system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction 893system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction 894system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction 895system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction 896system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction 897system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction 898system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction 899system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction 900system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction 901system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction 902system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction 903system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction 904system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction 905system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction 906system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction 907system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction 908system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction 909system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction 910system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction 911system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction 912system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction 913system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction 914system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction 915system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction 916system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction 917system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction 918system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction 919system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction 920system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction |
| 921system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 922system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 921system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 922system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 923system.cpu3.op_class::total 175558 # Class of executed instruction | 923system.cpu3.op_class::total 169240 # Class of executed instruction |
| 924system.cpu3.dcache.tags.replacements 0 # number of replacements | 924system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 925system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use 926system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks. | 925system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use 926system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks. |
| 927system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. | 927system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. |
| 928system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks. | 928system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks. |
| 929system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 929system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 930system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor 931system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy 932system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy | 930system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor 931system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy 932system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy |
| 933system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 934system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 935system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 936system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id | 933system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 934system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 935system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 936system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id |
| 937system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses 938system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses 939system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits 940system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits 941system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits 942system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits 943system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits 944system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits 945system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits 946system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits 947system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits 948system.cpu3.dcache.overall_hits::total 45837 # number of overall hits 949system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses 950system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses 951system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 952system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 953system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses 954system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses 955system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses 956system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses 957system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses 958system.cpu3.dcache.overall_misses::total 287 # number of overall misses 959system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles 960system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles 961system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles 962system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles 963system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles 964system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles 965system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles 966system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles 967system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles 968system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles 969system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses) 970system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses) 971system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses) 972system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses) 973system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) 974system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) 975system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses 976system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses 977system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses 978system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses 979system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses 980system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses 981system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses 982system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses 983system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses 984system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses 985system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses 986system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses 987system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses 988system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses 989system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency 990system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency 991system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency 992system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency 993system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency 994system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency 995system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency 996system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency 997system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency 998system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency | 937system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses 938system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses 939system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits 940system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits 941system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits 942system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits 943system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 944system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 945system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits 946system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits 947system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits 948system.cpu3.dcache.overall_hits::total 52867 # number of overall hits 949system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses 950system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses 951system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses 952system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses 953system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 954system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses 955system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses 956system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses 957system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses 958system.cpu3.dcache.overall_misses::total 270 # number of overall misses 959system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles 960system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles 961system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles 962system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles 963system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles 964system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles 965system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles 966system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles 967system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles 968system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles 969system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses) 970system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses) 971system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses) 972system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses) 973system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 974system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 975system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses 976system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses 977system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses 978system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses 979system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses 980system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses 981system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses 982system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses 983system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses 984system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses 985system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses 986system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses 987system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses 988system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses 989system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency 990system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency 991system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency 992system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency 993system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency 994system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency 995system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency 996system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency 997system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency 998system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency |
| 999system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1000system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1001system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1002system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1003system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1004system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1005system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1006system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 999system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1000system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1001system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1002system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1003system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1004system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1005system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1006system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 1007system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses 1008system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses 1009system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1010system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1011system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses 1012system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses 1013system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses 1014system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses 1015system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses 1016system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses 1017system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles 1018system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles 1019system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles 1020system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles 1021system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles 1022system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles 1023system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles 1024system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles 1025system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles 1026system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles 1027system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses 1028system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses 1029system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses 1030system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses 1031system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses 1032system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses 1033system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses 1034system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses 1035system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses 1036system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses 1037system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency 1038system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency 1039system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency 1040system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency 1041system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency 1042system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency 1043system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency 1044system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency 1045system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency 1046system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency | 1007system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 1008system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 1009system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 1010system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1011system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 1012system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 1013system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses 1014system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 1015system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses 1016system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 1017system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles 1018system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles 1019system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles 1020system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles 1021system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles 1022system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles 1023system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles 1024system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles 1025system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles 1026system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles 1027system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses 1028system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses 1029system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses 1030system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses 1031system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses 1032system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses 1033system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses 1034system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses 1035system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses 1036system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses 1037system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency 1038system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency 1039system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency 1040system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency 1041system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency 1042system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency 1043system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency 1044system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency 1045system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency 1046system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency |
| 1047system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1048system.cpu3.icache.tags.replacements 281 # number of replacements | 1047system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1048system.cpu3.icache.tags.replacements 281 # number of replacements |
| 1049system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use 1050system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks. | 1049system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use 1050system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks. |
| 1051system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. | 1051system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. |
| 1052system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks. | 1052system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks. |
| 1053system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1053system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1054system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor 1055system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy 1056system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy | 1054system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor 1055system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy 1056system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy |
| 1057system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1058system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 1059system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1060system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1061system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id | 1057system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1058system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 1059system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1060system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1061system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id |
| 1062system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses 1063system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses 1064system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits 1065system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits 1066system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits 1067system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits 1068system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits 1069system.cpu3.icache.overall_hits::total 175192 # number of overall hits | 1062system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses 1063system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses 1064system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits 1065system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits 1066system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits 1067system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits 1068system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits 1069system.cpu3.icache.overall_hits::total 168874 # number of overall hits |
| 1070system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1071system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1072system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1073system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1074system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1075system.cpu3.icache.overall_misses::total 367 # number of overall misses | 1070system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1071system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1072system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1073system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1074system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1075system.cpu3.icache.overall_misses::total 367 # number of overall misses |
| 1076system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles 1077system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles 1078system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles 1079system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles 1080system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles 1081system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles 1082system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses) 1083system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses) 1084system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses 1085system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses 1086system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses 1087system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses 1088system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses 1089system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses 1090system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses 1091system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses 1092system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses 1093system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses 1094system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency 1095system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency 1096system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency 1097system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency 1098system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency 1099system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency | 1076system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles 1077system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles 1078system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles 1079system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles 1080system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles 1081system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles 1082system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses) 1083system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses) 1084system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses 1085system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses 1086system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses 1087system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses 1088system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses 1089system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses 1090system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses 1091system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses 1092system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses 1093system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses 1094system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency 1095system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency 1096system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency 1097system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency 1098system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency 1099system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency |
| 1100system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1101system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1102system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1103system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1104system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1105system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1106system.cpu3.icache.fast_writes 0 # number of fast writes performed 1107system.cpu3.icache.cache_copies 0 # number of cache copies performed 1108system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1109system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1110system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1111system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1112system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1113system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses | 1100system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1101system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1102system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1103system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1104system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1105system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1106system.cpu3.icache.fast_writes 0 # number of fast writes performed 1107system.cpu3.icache.cache_copies 0 # number of cache copies performed 1108system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1109system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1110system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1111system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1112system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1113system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses |
| 1114system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles 1115system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles 1116system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles 1117system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles 1118system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles 1119system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles 1120system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses 1121system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses 1122system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses 1123system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses 1124system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses 1125system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses 1126system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency 1127system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency 1128system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency 1129system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency 1130system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency 1131system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency | 1114system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5004500 # number of ReadReq MSHR miss cycles 1115system.cpu3.icache.ReadReq_mshr_miss_latency::total 5004500 # number of ReadReq MSHR miss cycles 1116system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5004500 # number of demand (read+write) MSHR miss cycles 1117system.cpu3.icache.demand_mshr_miss_latency::total 5004500 # number of demand (read+write) MSHR miss cycles 1118system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5004500 # number of overall MSHR miss cycles 1119system.cpu3.icache.overall_mshr_miss_latency::total 5004500 # number of overall MSHR miss cycles 1120system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for ReadReq accesses 1121system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002169 # mshr miss rate for ReadReq accesses 1122system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for demand accesses 1123system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses 1124system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses 1125system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses 1126system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency 1127system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency 1128system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency 1129system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency 1130system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency 1131system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency |
| 1132system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1133system.l2c.tags.replacements 0 # number of replacements | 1132system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1133system.l2c.tags.replacements 0 # number of replacements |
| 1134system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use | 1134system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use |
| 1135system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. 1136system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1137system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. 1138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1135system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. 1136system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1137system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. 1138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1139system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor 1140system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor 1141system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor 1142system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor 1143system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor 1144system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor 1145system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor 1146system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor 1147system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor | 1139system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor 1140system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor 1141system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor 1142system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor 1143system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor 1144system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor 1145system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor 1146system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor 1147system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor |
| 1148system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy | 1148system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy |
| 1149system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy | 1149system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy |
| 1150system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy 1151system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy 1152system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 1153system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy 1154system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy 1155system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy | 1150system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy 1151system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy 1152system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 1153system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy 1154system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy 1155system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy |
| 1156system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 1157system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy | 1156system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1157system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy |
| 1158system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1159system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1160system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1161system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id | 1158system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1159system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1160system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1161system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id |
| 1162system.l2c.tags.tag_accesses 19677 # Number of tag accesses 1163system.l2c.tags.data_accesses 19677 # Number of data accesses | 1162system.l2c.tags.tag_accesses 19669 # Number of tag accesses 1163system.l2c.tags.data_accesses 19669 # Number of data accesses |
| 1164system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 1165system.l2c.Writeback_hits::total 1 # number of Writeback hits 1166system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1167system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1168system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1169system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1170system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits 1171system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits --- 17 unchanged lines hidden (view full) --- 1189system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1190system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1191system.l2c.overall_hits::cpu2.inst 302 # number of overall hits 1192system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1193system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 1194system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1195system.l2c.overall_hits::total 1220 # number of overall hits 1196system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses | 1164system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 1165system.l2c.Writeback_hits::total 1 # number of Writeback hits 1166system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1167system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1168system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1169system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1170system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits 1171system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits --- 17 unchanged lines hidden (view full) --- 1189system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1190system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1191system.l2c.overall_hits::cpu2.inst 302 # number of overall hits 1192system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1193system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 1194system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1195system.l2c.overall_hits::total 1220 # number of overall hits 1196system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses |
| 1197system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 1198system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses 1199system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses 1200system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses | 1197system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 1198system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 1199system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses 1200system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses |
| 1201system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1202system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1203system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1204system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1205system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1206system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1207system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1208system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses --- 19 unchanged lines hidden (view full) --- 1228system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1229system.l2c.overall_misses::cpu2.inst 64 # number of overall misses 1230system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1231system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 1232system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1233system.l2c.overall_misses::total 592 # number of overall misses 1234system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles 1235system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles | 1201system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1202system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1203system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1204system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1205system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1206system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1207system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1208system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses --- 19 unchanged lines hidden (view full) --- 1228system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1229system.l2c.overall_misses::cpu2.inst 64 # number of overall misses 1230system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1231system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 1232system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1233system.l2c.overall_misses::total 592 # number of overall misses 1234system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles 1235system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles |
| 1236system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles | 1236system.l2c.ReadExReq_miss_latency::cpu2.data 795500 # number of ReadExReq miss cycles |
| 1237system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles | 1237system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles |
| 1238system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles 1239system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles | 1238system.l2c.ReadExReq_miss_latency::total 7472000 # number of ReadExReq miss cycles 1239system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14963500 # number of ReadCleanReq miss cycles |
| 1240system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles | 1240system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles |
| 1241system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles 1242system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles 1243system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles | 1241system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3340500 # number of ReadCleanReq miss cycles 1242system.l2c.ReadCleanReq_miss_latency::cpu3.inst 446500 # number of ReadCleanReq miss cycles 1243system.l2c.ReadCleanReq_miss_latency::total 19490500 # number of ReadCleanReq miss cycles |
| 1244system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles 1245system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles 1246system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles 1247system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles 1248system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles | 1244system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles 1245system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles 1246system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles 1247system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles 1248system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles |
| 1249system.l2c.demand_miss_latency::cpu0.inst 14964000 # number of demand (read+write) miss cycles | 1249system.l2c.demand_miss_latency::cpu0.inst 14963500 # number of demand (read+write) miss cycles |
| 1250system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles 1251system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles 1252system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles | 1250system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles 1251system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles 1252system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles |
| 1253system.l2c.demand_miss_latency::cpu2.inst 3341500 # number of demand (read+write) miss cycles 1254system.l2c.demand_miss_latency::cpu2.data 1216000 # number of demand (read+write) miss cycles 1255system.l2c.demand_miss_latency::cpu3.inst 453500 # number of demand (read+write) miss cycles | 1253system.l2c.demand_miss_latency::cpu2.inst 3340500 # number of demand (read+write) miss cycles 1254system.l2c.demand_miss_latency::cpu2.data 1214500 # number of demand (read+write) miss cycles 1255system.l2c.demand_miss_latency::cpu3.inst 446500 # number of demand (read+write) miss cycles |
| 1256system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles | 1256system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles |
| 1257system.l2c.demand_miss_latency::total 31066000 # number of demand (read+write) miss cycles 1258system.l2c.overall_miss_latency::cpu0.inst 14964000 # number of overall miss cycles | 1257system.l2c.demand_miss_latency::total 31056000 # number of demand (read+write) miss cycles 1258system.l2c.overall_miss_latency::cpu0.inst 14963500 # number of overall miss cycles |
| 1259system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles 1260system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles 1261system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles | 1259system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles 1260system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles 1261system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles |
| 1262system.l2c.overall_miss_latency::cpu2.inst 3341500 # number of overall miss cycles 1263system.l2c.overall_miss_latency::cpu2.data 1216000 # number of overall miss cycles 1264system.l2c.overall_miss_latency::cpu3.inst 453500 # number of overall miss cycles | 1262system.l2c.overall_miss_latency::cpu2.inst 3340500 # number of overall miss cycles 1263system.l2c.overall_miss_latency::cpu2.data 1214500 # number of overall miss cycles 1264system.l2c.overall_miss_latency::cpu3.inst 446500 # number of overall miss cycles |
| 1265system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles | 1265system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles |
| 1266system.l2c.overall_miss_latency::total 31066000 # number of overall miss cycles | 1266system.l2c.overall_miss_latency::total 31056000 # number of overall miss cycles |
| 1267system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1268system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1269system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) | 1267system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 1268system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 1269system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) |
| 1270system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 1271system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) 1272system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) 1273system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) | 1270system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 1271system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 1272system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) 1273system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) |
| 1274system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1275system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 1276system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 1277system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1278system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1279system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 1280system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 1281system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 1303system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 1304system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 1305system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1306system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1307system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1308system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1309system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1310system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 1274system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1275system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 1276system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 1277system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1278system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1279system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 1280system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 1281system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 1303system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 1304system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 1305system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1306system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1307system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1308system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1309system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1310system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 1311system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses | 1311system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses |
| 1312system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1313system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1314system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1315system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1316system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1317system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 1318system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 1319system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses --- 19 unchanged lines hidden (view full) --- 1339system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses 1340system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses 1341system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses 1342system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 1343system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 1344system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 1345system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency 1346system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency | 1312system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1313system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1314system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1315system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1316system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1317system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 1318system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 1319system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses --- 19 unchanged lines hidden (view full) --- 1339system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses 1340system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses 1341system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses 1342system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 1343system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 1344system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 1345system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency 1346system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency |
| 1347system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency | 1347system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53033.333333 # average ReadExReq miss latency |
| 1348system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency | 1348system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency |
| 1349system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency 1350system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency | 1349system.l2c.ReadExReq_avg_miss_latency::total 52619.718310 # average ReadExReq miss latency 1350system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52503.508772 # average ReadCleanReq miss latency |
| 1351system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency | 1351system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency |
| 1352system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500 # average ReadCleanReq miss latency 1353system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889 # average ReadCleanReq miss latency 1354system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667 # average ReadCleanReq miss latency | 1352system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52195.312500 # average ReadCleanReq miss latency 1353system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 49611.111111 # average ReadCleanReq miss latency 1354system.l2c.ReadCleanReq_avg_miss_latency::total 52393.817204 # average ReadCleanReq miss latency |
| 1355system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency 1356system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency 1357system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency 1358system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency 1359system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency | 1355system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency 1356system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency 1357system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency 1358system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency 1359system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency |
| 1360system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency | 1360system.l2c.demand_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency |
| 1361system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency 1362system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency 1363system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency | 1361system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency 1362system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency 1363system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency |
| 1364system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency 1365system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency 1366system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency | 1364system.l2c.demand_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency 1365system.l2c.demand_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency 1366system.l2c.demand_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency |
| 1367system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency | 1367system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency |
| 1368system.l2c.demand_avg_miss_latency::total 52476.351351 # average overall miss latency 1369system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency | 1368system.l2c.demand_avg_miss_latency::total 52459.459459 # average overall miss latency 1369system.l2c.overall_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency |
| 1370system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency 1371system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency 1372system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency | 1370system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency 1371system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency 1372system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency |
| 1373system.l2c.overall_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency 1374system.l2c.overall_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency 1375system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency | 1373system.l2c.overall_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency 1374system.l2c.overall_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency 1375system.l2c.overall_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency |
| 1376system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency | 1376system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency |
| 1377system.l2c.overall_avg_miss_latency::total 52476.351351 # average overall miss latency | 1377system.l2c.overall_avg_miss_latency::total 52459.459459 # average overall miss latency |
| 1378system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1379system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1380system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1381system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1382system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1383system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1384system.l2c.fast_writes 0 # number of fast writes performed 1385system.l2c.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 1395system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 1396system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 1397system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 1398system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits 1399system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits 1400system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 1401system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1402system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses | 1378system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1379system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1380system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1381system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1382system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1383system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1384system.l2c.fast_writes 0 # number of fast writes performed 1385system.l2c.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 1395system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 1396system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 1397system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 1398system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits 1399system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits 1400system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 1401system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1402system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses |
| 1403system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses 1404system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses 1405system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses 1406system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses | 1403system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses 1404system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 1405system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses 1406system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses |
| 1407system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1408system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses 1409system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses 1410system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1411system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1412system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses 1413system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 14 # number of ReadCleanReq MSHR misses 1414system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses --- 17 unchanged lines hidden (view full) --- 1432system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 1433system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses 1434system.l2c.overall_mshr_misses::cpu1.data 16 # number of overall MSHR misses 1435system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses 1436system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses 1437system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1438system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 1439system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses | 1407system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1408system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses 1409system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses 1410system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1411system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1412system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses 1413system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 14 # number of ReadCleanReq MSHR misses 1414system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses --- 17 unchanged lines hidden (view full) --- 1432system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 1433system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses 1434system.l2c.overall_mshr_misses::cpu1.data 16 # number of overall MSHR misses 1435system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses 1436system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses 1437system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1438system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 1439system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses |
| 1440system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1194000 # number of UpgradeReq MSHR miss cycles 1441system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765000 # number of UpgradeReq MSHR miss cycles 1442system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 850000 # number of UpgradeReq MSHR miss cycles 1443system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 479492 # number of UpgradeReq MSHR miss cycles 1444system.l2c.UpgradeReq_mshr_miss_latency::total 3288492 # number of UpgradeReq MSHR miss cycles | 1440system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1222000 # number of UpgradeReq MSHR miss cycles 1441system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 700497 # number of UpgradeReq MSHR miss cycles 1442system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 700497 # number of UpgradeReq MSHR miss cycles 1443system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 698998 # number of UpgradeReq MSHR miss cycles 1444system.l2c.UpgradeReq_mshr_miss_latency::total 3321992 # number of UpgradeReq MSHR miss cycles |
| 1445system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207500 # number of ReadExReq MSHR miss cycles 1446system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595000 # number of ReadExReq MSHR miss cycles | 1445system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207500 # number of ReadExReq MSHR miss cycles 1446system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595000 # number of ReadExReq MSHR miss cycles |
| 1447system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 647000 # number of ReadExReq MSHR miss cycles | 1447system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 645500 # number of ReadExReq MSHR miss cycles |
| 1448system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 604000 # number of ReadExReq MSHR miss cycles | 1448system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 604000 # number of ReadExReq MSHR miss cycles |
| 1449system.l2c.ReadExReq_mshr_miss_latency::total 6053500 # number of ReadExReq MSHR miss cycles 1450system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12114000 # number of ReadCleanReq MSHR miss cycles | 1449system.l2c.ReadExReq_mshr_miss_latency::total 6052000 # number of ReadExReq MSHR miss cycles 1450system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12113500 # number of ReadCleanReq MSHR miss cycles |
| 1451system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 600000 # number of ReadCleanReq MSHR miss cycles 1452system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2295500 # number of ReadCleanReq MSHR miss cycles 1453system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 42500 # number of ReadCleanReq MSHR miss cycles | 1451system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 600000 # number of ReadCleanReq MSHR miss cycles 1452system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2295500 # number of ReadCleanReq MSHR miss cycles 1453system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 42500 # number of ReadCleanReq MSHR miss cycles |
| 1454system.l2c.ReadCleanReq_mshr_miss_latency::total 15052000 # number of ReadCleanReq MSHR miss cycles | 1454system.l2c.ReadCleanReq_mshr_miss_latency::total 15051500 # number of ReadCleanReq MSHR miss cycles |
| 1455system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 2805000 # number of ReadSharedReq MSHR miss cycles 1456system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 85000 # number of ReadSharedReq MSHR miss cycles 1457system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 297500 # number of ReadSharedReq MSHR miss cycles 1458system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 42500 # number of ReadSharedReq MSHR miss cycles 1459system.l2c.ReadSharedReq_mshr_miss_latency::total 3230000 # number of ReadSharedReq MSHR miss cycles | 1455system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 2805000 # number of ReadSharedReq MSHR miss cycles 1456system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 85000 # number of ReadSharedReq MSHR miss cycles 1457system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 297500 # number of ReadSharedReq MSHR miss cycles 1458system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 42500 # number of ReadSharedReq MSHR miss cycles 1459system.l2c.ReadSharedReq_mshr_miss_latency::total 3230000 # number of ReadSharedReq MSHR miss cycles |
| 1460system.l2c.demand_mshr_miss_latency::cpu0.inst 12114000 # number of demand (read+write) MSHR miss cycles | 1460system.l2c.demand_mshr_miss_latency::cpu0.inst 12113500 # number of demand (read+write) MSHR miss cycles |
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| 1465system.l2c.demand_mshr_miss_latency::cpu2.data 944500 # number of demand (read+write) MSHR miss cycles | 1465system.l2c.demand_mshr_miss_latency::cpu2.data 943000 # number of demand (read+write) MSHR miss cycles |
| 1466system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles 1467system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # number of demand (read+write) MSHR miss cycles | 1466system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles 1467system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # number of demand (read+write) MSHR miss cycles |
| 1468system.l2c.demand_mshr_miss_latency::total 24335500 # number of demand (read+write) MSHR miss cycles 1469system.l2c.overall_mshr_miss_latency::cpu0.inst 12114000 # number of overall MSHR miss cycles | 1468system.l2c.demand_mshr_miss_latency::total 24333500 # number of demand (read+write) MSHR miss cycles 1469system.l2c.overall_mshr_miss_latency::cpu0.inst 12113500 # number of overall MSHR miss cycles |
| 1470system.l2c.overall_mshr_miss_latency::cpu0.data 7012500 # number of overall MSHR miss cycles 1471system.l2c.overall_mshr_miss_latency::cpu1.inst 600000 # number of overall MSHR miss cycles 1472system.l2c.overall_mshr_miss_latency::cpu1.data 680000 # number of overall MSHR miss cycles 1473system.l2c.overall_mshr_miss_latency::cpu2.inst 2295500 # number of overall MSHR miss cycles | 1470system.l2c.overall_mshr_miss_latency::cpu0.data 7012500 # number of overall MSHR miss cycles 1471system.l2c.overall_mshr_miss_latency::cpu1.inst 600000 # number of overall MSHR miss cycles 1472system.l2c.overall_mshr_miss_latency::cpu1.data 680000 # number of overall MSHR miss cycles 1473system.l2c.overall_mshr_miss_latency::cpu2.inst 2295500 # number of overall MSHR miss cycles |
| 1474system.l2c.overall_mshr_miss_latency::cpu2.data 944500 # number of overall MSHR miss cycles | 1474system.l2c.overall_mshr_miss_latency::cpu2.data 943000 # number of overall MSHR miss cycles |
| 1475system.l2c.overall_mshr_miss_latency::cpu3.inst 42500 # number of overall MSHR miss cycles 1476system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles | 1475system.l2c.overall_mshr_miss_latency::cpu3.inst 42500 # number of overall MSHR miss cycles 1476system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles |
| 1477system.l2c.overall_mshr_miss_latency::total 24335500 # number of overall MSHR miss cycles | 1477system.l2c.overall_mshr_miss_latency::total 24333500 # number of overall MSHR miss cycles |
| 1478system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1479system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1480system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1481system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 1478system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1479system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1480system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1481system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 1482system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses | 1482system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses |
| 1483system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1484system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1485system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1486system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1487system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1488system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1489system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for ReadCleanReq accesses 1490system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses --- 17 unchanged lines hidden (view full) --- 1508system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1509system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses 1510system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses 1511system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses 1512system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses 1513system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1514system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1515system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses | 1483system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1484system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1485system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1486system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1487system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1488system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1489system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for ReadCleanReq accesses 1490system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses --- 17 unchanged lines hidden (view full) --- 1508system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1509system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses 1510system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses 1511system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses 1512system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses 1513system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1514system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1515system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses |
| 1516system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency 1517system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency 1518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency 1519system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency 1520system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency | 1516system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency 1517system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency 1518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency 1519system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency 1520system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency |
| 1521system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency 1522system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency | 1521system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency 1522system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency |
| 1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency | 1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency |
| 1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency | 1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency |
| 1525system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency 1526system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency | 1525system.l2c.ReadExReq_avg_mshr_miss_latency::total 42619.718310 # average ReadExReq mshr miss latency 1526system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average ReadCleanReq mshr miss latency |
| 1527system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency 1528system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency 1529system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency | 1527system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency 1528system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency 1529system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency |
| 1530system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency | 1530system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42518.361582 # average ReadCleanReq mshr miss latency |
| 1531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency 1532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency 1533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency 1534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency 1535system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency | 1531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency 1532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency 1533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency 1534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency 1535system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency |
| 1536system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency | 1536system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency |
| 1537system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency 1538system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency 1539system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency 1540system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency | 1537system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency 1538system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency 1539system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency 1540system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency |
| 1541system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency | 1541system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency |
| 1542system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency 1543system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency | 1542system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency 1543system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency |
| 1544system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency 1545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency | 1544system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency 1545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency |
| 1546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency 1547system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency 1548system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency 1549system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency | 1546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency 1547system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency 1548system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency 1549system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency |
| 1550system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency | 1550system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency |
| 1551system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency 1552system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency | 1551system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency 1552system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency |
| 1553system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency | 1553system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency |
| 1554system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1555system.membus.trans_dist::ReadResp 430 # Transaction distribution | 1554system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1555system.membus.trans_dist::ReadResp 430 # Transaction distribution |
| 1556system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 1557system.membus.trans_dist::UpgradeResp 77 # Transaction distribution | 1556system.membus.trans_dist::UpgradeReq 271 # Transaction distribution 1557system.membus.trans_dist::UpgradeResp 76 # Transaction distribution |
| 1558system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1559system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1560system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution | 1558system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1559system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1560system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution |
| 1561system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) | 1561system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) |
| 1563system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1564system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1565system.membus.snoops 261 # Total snoops (count) | 1563system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1564system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1565system.membus.snoops 261 # Total snoops (count) |
| 1566system.membus.snoop_fanout::samples 914 # Request fanout histogram | 1566system.membus.snoop_fanout::samples 913 # Request fanout histogram |
| 1567system.membus.snoop_fanout::mean 0 # Request fanout histogram 1568system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1569system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1567system.membus.snoop_fanout::mean 0 # Request fanout histogram 1568system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1569system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1570system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram | 1570system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram |
| 1571system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1572system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1573system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1574system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1571system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1572system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1573system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1574system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1575system.membus.snoop_fanout::total 914 # Request fanout histogram 1576system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks) | 1575system.membus.snoop_fanout::total 913 # Request fanout histogram 1576system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks) |
| 1577system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) | 1577system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 1578system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks) | 1578system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks) |
| 1579system.membus.respLayer1.utilization 1.1 # Layer utilization (%) | 1579system.membus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 1580system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution | 1580system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter. 1581system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1582system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1583system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1584system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1585system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1586system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution |
| 1581system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 1582system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution | 1587system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 1588system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution |
| 1583system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1584system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution | 1589system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution 1590system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution |
| 1585system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 1586system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 1587system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution | 1591system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 1592system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 1593system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution |
| 1588system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution | 1594system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution |
| 1589system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) | 1595system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) |
| 1590system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) | 1596system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) |
| 1591system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) | 1597system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) |
| 1592system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) 1593system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes) 1594system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) 1595system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) 1596system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) 1597system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes) | 1598system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) 1599system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) 1600system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) 1601system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes) 1602system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) 1603system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes) |
| 1598system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 1599system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1600system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 1601system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1602system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 1603system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1604system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 1605system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1606system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) | 1604system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 1605system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1606system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 1607system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1608system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 1609system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1610system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 1611system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1612system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) |
| 1607system.toL2Bus.snoops 1037 # Total snoops (count) 1608system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram 1609system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 1610system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 1613system.toL2Bus.snoops 1034 # Total snoops (count) 1614system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram 1615system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram 1616system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram |
| 1611system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1617system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1612system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1613system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1614system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1615system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1616system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1617system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 1618system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 1619system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram | 1618system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram 1619system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram 1620system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram 1621system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram 1622system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1623system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1624system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1625system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram |
| 1620system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1621system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1626system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1627system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1622system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 1623system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 1624system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram 1625system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks) | 1628system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1629system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1630system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram 1631system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks) |
| 1626system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 1627system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 1628system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) | 1632system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 1633system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 1634system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) |
| 1629system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks) | 1635system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks) |
| 1630system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1631system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) 1632system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) | 1636system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1637system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) 1638system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) |
| 1633system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks) | 1639system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks) |
| 1634system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1635system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) 1636system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) | 1640system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1641system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) 1642system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) |
| 1637system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks) | 1643system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks) |
| 1638system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1639system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) 1640system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) | 1644system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1645system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) 1646system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) |
| 1641system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks) | 1647system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks) |
| 1642system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1643 1644---------- End Simulation Statistics ---------- | 1648system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1649 1650---------- End Simulation Statistics ---------- |