1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000263 # Number of seconds simulated
4sim_ticks 262793500 # Number of ticks simulated
5final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.000260 # Number of seconds simulated
4sim_ticks 260037500 # Number of ticks simulated
5final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1021127 # Simulator instruction rate (inst/s)
8host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 404381057 # Simulator tick rate (ticks/s)
10host_mem_usage 299844 # Number of bytes of host memory used
11host_seconds 0.65 # Real time elapsed on the host
12sim_insts 663567 # Number of instructions simulated
13sim_ops 663567 # Number of ops (including micro ops) simulated
| 7host_inst_rate 961598 # Simulator instruction rate (inst/s)
8host_op_rate 961579 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 379344878 # Simulator tick rate (ticks/s)
10host_mem_usage 302744 # Number of bytes of host memory used
11host_seconds 0.69 # Real time elapsed on the host
12sim_insts 659142 # Number of instructions simulated
13sim_ops 659142 # Number of ops (including micro ops) simulated
|
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
| 14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
|
18system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory
| 18system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
|
24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
| 24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
|
26system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory
| 26system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
|
29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
| 29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
|
32system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
| 32system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
|
38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
| 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
|
39system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
62system.membus.trans_dist::ReadReq 430 # Transaction distribution
63system.membus.trans_dist::ReadResp 430 # Transaction distribution
64system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
65system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
66system.membus.trans_dist::ReadExReq 208 # Transaction distribution
67system.membus.trans_dist::ReadExResp 142 # Transaction distribution
68system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
69system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
70system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
71system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
72system.membus.snoops 261 # Total snoops (count)
73system.membus.snoop_fanout::samples 915 # Request fanout histogram
74system.membus.snoop_fanout::mean 0 # Request fanout histogram
75system.membus.snoop_fanout::stdev 0 # Request fanout histogram
76system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
77system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
78system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
79system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
80system.membus.snoop_fanout::min_value 0 # Request fanout histogram
81system.membus.snoop_fanout::max_value 0 # Request fanout histogram
82system.membus.snoop_fanout::total 915 # Request fanout histogram
83system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks)
84system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
85system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks)
86system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
| 39system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s)
|
87system.cpu_clk_domain.clock 500 # Clock period in ticks
| 62system.cpu_clk_domain.clock 500 # Clock period in ticks
|
| 63system.cpu0.workload.num_syscalls 89 # Number of system calls
64system.cpu0.numCycles 520075 # number of cpu cycles simulated
65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
67system.cpu0.committedInsts 157392 # Number of instructions committed
68system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed
69system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses
70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
71system.cpu0.num_func_calls 390 # number of times a function call or return occured
72system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls
73system.cpu0.num_int_insts 108420 # number of integer instructions
74system.cpu0.num_fp_insts 0 # number of float instructions
75system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read
76system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written
77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
79system.cpu0.num_mem_refs 73430 # number of memory refs
80system.cpu0.num_load_insts 48613 # Number of load instructions
81system.cpu0.num_store_insts 24817 # Number of store instructions
82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
83system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles
84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
86system.cpu0.Branches 26700 # Number of branches fetched
87system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction
88system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction
89system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction
90system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction
91system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction
92system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction
93system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction
94system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction
95system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction
96system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction
97system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction
98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction
99system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction
100system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction
101system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction
102system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction
103system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction
104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction
105system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction
106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction
107system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction
108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction
109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction
110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction
111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction
112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction
113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction
114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction
115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction
116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction
117system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction
118system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction
119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
121system.cpu0.op_class::total 157454 # Class of executed instruction
122system.cpu0.dcache.tags.replacements 2 # number of replacements
123system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use
124system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks.
125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
126system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks.
127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor
129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy
130system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy
131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
135system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses
136system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses
137system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits
138system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits
139system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits
140system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits
141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
143system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits
144system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits
145system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits
146system.cpu0.dcache.overall_hits::total 73016 # number of overall hits
147system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
148system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
153system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
154system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
155system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
156system.cpu0.dcache.overall_misses::total 353 # number of overall misses
157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles
158system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles
159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles
160system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles
161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles
162system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles
163system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles
164system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles
165system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles
166system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles
167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses)
168system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses)
169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses)
170system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses)
171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
173system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses
174system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses
175system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses
176system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses
177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses
178system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses
179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses
180system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses
181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses
184system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses
185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses
186system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses
187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency
188system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency
189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency
190system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency
191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency
192system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency
193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency
194system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency
195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency
196system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency
197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
203system.cpu0.dcache.fast_writes 0 # number of fast writes performed
204system.cpu0.dcache.cache_copies 0 # number of cache copies performed
205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
206system.cpu0.dcache.writebacks::total 1 # number of writebacks
207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
208system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
213system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
214system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
215system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
216system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles
218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles
219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles
220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles
221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles
222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles
223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles
224system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles
225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles
226system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles
227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses
228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses
229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses
230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses
231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses
234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses
235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses
236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses
237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency
238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency
239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency
240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency
241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency
242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency
243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency
244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency
245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency
246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency
247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
248system.cpu0.icache.tags.replacements 215 # number of replacements
249system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use
250system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks.
251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
252system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks.
253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
254system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor
255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy
256system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy
257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
261system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses
262system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses
263system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits
264system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits
265system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits
266system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits
267system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits
268system.cpu0.icache.overall_hits::total 156988 # number of overall hits
269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
274system.cpu0.icache.overall_misses::total 467 # number of overall misses
275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles
276system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles
277system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles
278system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles
279system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles
280system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles
281system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses)
282system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses)
283system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses
284system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses
285system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses
286system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses
287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses
288system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses
289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses
290system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses
291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses
292system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses
293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency
294system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency
295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency
296system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency
297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency
298system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency
299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu0.icache.fast_writes 0 # number of fast writes performed
306system.cpu0.icache.cache_copies 0 # number of cache copies performed
307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
308system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
309system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
310system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
311system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
312system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles
314system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles
315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles
316system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles
317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles
318system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles
319system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses
320system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses
321system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses
322system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses
323system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses
324system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses
325system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency
326system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency
327system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency
328system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency
329system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency
330system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency
331system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
332system.cpu1.numCycles 520075 # number of cpu cycles simulated
333system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
334system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
335system.cpu1.committedInsts 168980 # Number of instructions committed
336system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed
337system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses
338system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
339system.cpu1.num_func_calls 637 # number of times a function call or return occured
340system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls
341system.cpu1.num_int_insts 110320 # number of integer instructions
342system.cpu1.num_fp_insts 0 # number of float instructions
343system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read
344system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written
345system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
346system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
347system.cpu1.num_mem_refs 53149 # number of memory refs
348system.cpu1.num_load_insts 40825 # Number of load instructions
349system.cpu1.num_store_insts 12324 # Number of store instructions
350system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles
351system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles
352system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles
353system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles
354system.cpu1.Branches 34992 # Number of branches fetched
355system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction
356system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction
357system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction
358system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction
359system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction
360system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction
361system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction
362system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction
363system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction
364system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction
365system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction
366system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction
367system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction
368system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction
369system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction
370system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction
371system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction
372system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction
373system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction
374system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction
375system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction
376system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction
377system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction
378system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction
379system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction
380system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction
381system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction
382system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction
383system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction
384system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction
385system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction
386system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction
387system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
388system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
389system.cpu1.op_class::total 169012 # Class of executed instruction
390system.cpu1.dcache.tags.replacements 0 # number of replacements
391system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use
392system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks.
393system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
394system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks.
395system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
396system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor
397system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy
398system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy
399system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
400system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
401system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
402system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
403system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses
404system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses
405system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits
406system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits
407system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits
408system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits
409system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
410system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
411system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits
412system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits
413system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits
414system.cpu1.dcache.overall_hits::total 52799 # number of overall hits
415system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses
416system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses
417system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses
418system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses
419system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
420system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
421system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses
422system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses
423system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses
424system.cpu1.dcache.overall_misses::total 270 # number of overall misses
425system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles
426system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles
427system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles
428system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles
429system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles
430system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles
431system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles
432system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles
433system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles
434system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles
435system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses)
436system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses)
437system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses)
438system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses)
439system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
440system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
441system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses
442system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses
443system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses
444system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses
445system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses
446system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses
447system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses
448system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses
449system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses
450system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses
451system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses
452system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses
453system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses
454system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses
455system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency
456system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency
457system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency
458system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency
459system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency
460system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency
461system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency
462system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency
463system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency
464system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency
465system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
466system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
467system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
468system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
469system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
470system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
471system.cpu1.dcache.fast_writes 0 # number of fast writes performed
472system.cpu1.dcache.cache_copies 0 # number of cache copies performed
473system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses
474system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
475system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
476system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
477system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
478system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
479system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
480system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
481system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
482system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
483system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles
484system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles
485system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles
486system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles
487system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles
488system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles
489system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles
490system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles
491system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles
492system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles
493system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses
494system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses
495system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses
496system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses
497system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
498system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses
499system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses
500system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses
501system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses
502system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses
503system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency
504system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency
505system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency
506system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency
507system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency
508system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency
509system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency
510system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency
511system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency
512system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency
513system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
514system.cpu1.icache.tags.replacements 280 # number of replacements
515system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use
516system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks.
517system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
518system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks.
519system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
520system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor
521system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy
522system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy
523system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
524system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
525system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
526system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
527system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
528system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses
529system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses
530system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits
531system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits
532system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits
533system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits
534system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits
535system.cpu1.icache.overall_hits::total 168647 # number of overall hits
536system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
537system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
538system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
539system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
540system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
541system.cpu1.icache.overall_misses::total 366 # number of overall misses
542system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles
543system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles
544system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles
545system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles
546system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles
547system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles
548system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses)
549system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses)
550system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses
551system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses
552system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses
553system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses
554system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses
555system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses
556system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses
557system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses
558system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses
559system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses
560system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency
561system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency
562system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency
563system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency
564system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency
565system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency
566system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
567system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
568system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
569system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
570system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
571system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
572system.cpu1.icache.fast_writes 0 # number of fast writes performed
573system.cpu1.icache.cache_copies 0 # number of cache copies performed
574system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
575system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
576system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
577system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
578system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
579system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
580system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles
581system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles
582system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles
583system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles
584system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles
585system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles
586system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses
587system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses
588system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses
589system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses
590system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses
591system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses
592system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency
593system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency
594system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency
595system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency
596system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency
597system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency
598system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
599system.cpu2.numCycles 520075 # number of cpu cycles simulated
600system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
601system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
602system.cpu2.committedInsts 164869 # Number of instructions committed
603system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed
604system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses
605system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
606system.cpu2.num_func_calls 637 # number of times a function call or return occured
607system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls
608system.cpu2.num_int_insts 110069 # number of integer instructions
609system.cpu2.num_fp_insts 0 # number of float instructions
610system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read
611system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written
612system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
613system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
614system.cpu2.num_mem_refs 54829 # number of memory refs
615system.cpu2.num_load_insts 40701 # Number of load instructions
616system.cpu2.num_store_insts 14128 # Number of store instructions
617system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles
618system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles
619system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles
620system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles
621system.cpu2.Branches 33062 # Number of branches fetched
622system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction
623system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction
624system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction
625system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction
626system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction
627system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction
628system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction
629system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction
630system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction
631system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction
632system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction
633system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction
634system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction
635system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction
636system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction
637system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction
638system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction
639system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction
640system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction
641system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction
642system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction
643system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction
644system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction
645system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction
646system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction
647system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction
648system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction
649system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction
650system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction
651system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction
652system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction
653system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction
654system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
655system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
656system.cpu2.op_class::total 164901 # Class of executed instruction
657system.cpu2.dcache.tags.replacements 0 # number of replacements
658system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use
659system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks.
660system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
661system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks.
662system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
663system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor
664system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy
665system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy
666system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
667system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
668system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
669system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
670system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses
671system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses
672system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits
673system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits
674system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits
675system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits
676system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
677system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
678system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits
679system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits
680system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits
681system.cpu2.dcache.overall_hits::total 54483 # number of overall hits
682system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses
683system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses
684system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses
685system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses
686system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
687system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
688system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses
689system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses
690system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses
691system.cpu2.dcache.overall_misses::total 267 # number of overall misses
692system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles
693system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles
694system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles
695system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles
696system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles
697system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles
698system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles
699system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles
700system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles
701system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles
702system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses)
703system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses)
704system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses)
705system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses)
706system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
707system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
708system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses
709system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses
710system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses
711system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses
712system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses
713system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses
714system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses
715system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses
716system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses
717system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
718system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses
719system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses
720system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses
721system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses
722system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency
723system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency
724system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency
725system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency
726system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency
727system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency
728system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency
729system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency
730system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency
731system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency
732system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
733system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
734system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
735system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
736system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
737system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
738system.cpu2.dcache.fast_writes 0 # number of fast writes performed
739system.cpu2.dcache.cache_copies 0 # number of cache copies performed
740system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses
741system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
742system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
743system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
744system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
745system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
746system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
747system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
748system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
749system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
750system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles
751system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles
752system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles
753system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles
754system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles
755system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles
756system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles
757system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles
758system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles
759system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles
760system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses
761system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses
762system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses
763system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses
764system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses
765system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
766system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses
767system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses
768system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses
769system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses
770system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency
771system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency
772system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency
773system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency
774system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency
775system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency
776system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency
777system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency
778system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency
779system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency
780system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
781system.cpu2.icache.tags.replacements 280 # number of replacements
782system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use
783system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks.
784system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
785system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks.
786system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
787system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor
788system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy
789system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy
790system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
791system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
792system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
793system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
794system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
795system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses
796system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses
797system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits
798system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits
799system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits
800system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits
801system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits
802system.cpu2.icache.overall_hits::total 164536 # number of overall hits
803system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
804system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
805system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
806system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
807system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
808system.cpu2.icache.overall_misses::total 366 # number of overall misses
809system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles
810system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles
811system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles
812system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles
813system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles
814system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles
815system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses)
816system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses)
817system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses
818system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses
819system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses
820system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses
821system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses
822system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses
823system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses
824system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
825system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses
826system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses
827system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency
828system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency
829system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency
830system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency
831system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency
832system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency
833system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
834system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
835system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
836system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
837system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
838system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
839system.cpu2.icache.fast_writes 0 # number of fast writes performed
840system.cpu2.icache.cache_copies 0 # number of cache copies performed
841system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
842system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
843system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
844system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
845system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
846system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
847system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles
848system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles
849system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles
850system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles
851system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles
852system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles
853system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
854system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
855system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses
856system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
857system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
858system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
859system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency
860system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency
861system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency
862system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency
863system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency
864system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency
865system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
866system.cpu3.numCycles 520075 # number of cpu cycles simulated
867system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
868system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
869system.cpu3.committedInsts 167901 # Number of instructions committed
870system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed
871system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses
872system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
873system.cpu3.num_func_calls 637 # number of times a function call or return occured
874system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls
875system.cpu3.num_int_insts 110672 # number of integer instructions
876system.cpu3.num_fp_insts 0 # number of float instructions
877system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read
878system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written
879system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
880system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
881system.cpu3.num_mem_refs 54219 # number of memory refs
882system.cpu3.num_load_insts 41000 # Number of load instructions
883system.cpu3.num_store_insts 13219 # Number of store instructions
884system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles
885system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles
886system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles
887system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles
888system.cpu3.Branches 34277 # Number of branches fetched
889system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction
890system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction
891system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction
892system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction
893system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction
894system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction
895system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction
896system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction
897system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction
898system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction
899system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction
900system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction
901system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction
902system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction
903system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction
904system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction
905system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction
906system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction
907system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction
908system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction
909system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction
910system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction
911system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction
912system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction
913system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction
914system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction
915system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction
916system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction
917system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction
918system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction
919system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction
920system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction
921system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
922system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
923system.cpu3.op_class::total 167933 # Class of executed instruction
924system.cpu3.dcache.tags.replacements 0 # number of replacements
925system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use
926system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks.
927system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
928system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks.
929system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
930system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor
931system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy
932system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy
933system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
934system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
935system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
936system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
937system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses
938system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses
939system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits
940system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits
941system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits
942system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits
943system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
944system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
945system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits
946system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits
947system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits
948system.cpu3.dcache.overall_hits::total 53870 # number of overall hits
949system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses
950system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses
951system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses
952system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses
953system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
954system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
955system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses
956system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses
957system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses
958system.cpu3.dcache.overall_misses::total 268 # number of overall misses
959system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles
960system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles
961system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles
962system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles
963system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles
964system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles
965system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles
966system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles
967system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles
968system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles
969system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses)
970system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses)
971system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses)
972system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses)
973system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
974system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
975system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses
976system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses
977system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses
978system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses
979system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses
980system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses
981system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses
982system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses
983system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses
984system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
985system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses
986system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses
987system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses
988system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses
989system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency
990system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency
991system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency
992system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency
993system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency
994system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency
995system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency
996system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency
997system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency
998system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency
999system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1000system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1001system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1002system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1003system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1004system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1005system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1006system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1007system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
1008system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
1009system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses
1010system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
1011system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
1012system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
1013system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses
1014system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1015system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses
1016system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1017system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles
1018system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles
1019system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles
1020system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles
1021system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles
1022system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles
1023system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles
1024system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles
1025system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles
1026system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles
1027system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses
1028system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses
1029system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses
1030system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses
1031system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses
1032system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
1033system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses
1034system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses
1035system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses
1036system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses
1037system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency
1038system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency
1039system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency
1040system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency
1041system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency
1042system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency
1043system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency
1044system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency
1045system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency
1046system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency
1047system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1048system.cpu3.icache.tags.replacements 281 # number of replacements
1049system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use
1050system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks.
1051system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1052system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks.
1053system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1054system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor
1055system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy
1056system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy
1057system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1058system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1059system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1060system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1061system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1062system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses
1063system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses
1064system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits
1065system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits
1066system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits
1067system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits
1068system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits
1069system.cpu3.icache.overall_hits::total 167567 # number of overall hits
1070system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1071system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1072system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1073system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1074system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1075system.cpu3.icache.overall_misses::total 367 # number of overall misses
1076system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles
1077system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles
1078system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles
1079system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles
1080system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles
1081system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles
1082system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses)
1083system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses)
1084system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses
1085system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses
1086system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses
1087system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses
1088system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses
1089system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses
1090system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses
1091system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses
1092system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses
1093system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses
1094system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency
1095system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency
1096system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency
1097system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency
1098system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency
1099system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency
1100system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1101system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1102system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1103system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1104system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1105system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1106system.cpu3.icache.fast_writes 0 # number of fast writes performed
1107system.cpu3.icache.cache_copies 0 # number of cache copies performed
1108system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1109system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1110system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1111system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1112system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1113system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1114system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles
1115system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles
1116system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles
1117system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles
1118system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles
1119system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles
1120system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses
1121system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses
1122system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses
1123system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses
1124system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses
1125system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses
1126system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency
1127system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency
1128system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency
1129system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency
1130system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency
1131system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency
1132system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
88system.l2c.tags.replacements 0 # number of replacements
| 1133system.l2c.tags.replacements 0 # number of replacements
|
89system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use
| 1134system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use
|
90system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
91system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
92system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
93system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1135system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
1136system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
1137system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
1138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
94system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor
95system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor
96system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor
97system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor
98system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor
99system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor
100system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor
101system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor
102system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor
| 1139system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor
1140system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor
1141system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor
1142system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor
1143system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor
1144system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor
1145system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor
1146system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor
1147system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor
|
103system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
| 1148system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
104system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy
105system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
106system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
107system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy
108system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy
109system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
110system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy
| 1149system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy
1150system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy
1151system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
1152system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy
1153system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy
1154system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy
1155system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
|
111system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
| 1156system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
|
112system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy
| 1157system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy
|
113system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
114system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
115system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
116system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
117system.l2c.tags.tag_accesses 15709 # Number of tag accesses
118system.l2c.tags.data_accesses 15709 # Number of data accesses
119system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
120system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
| 1158system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
1159system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
1160system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
1161system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
1162system.l2c.tags.tag_accesses 15709 # Number of tag accesses
1163system.l2c.tags.data_accesses 15709 # Number of data accesses
1164system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
1165system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
121system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
122system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
123system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
124system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
| 1166system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits
1167system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
1168system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits
1169system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits
|
125system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
126system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
127system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
128system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
129system.l2c.Writeback_hits::total 1 # number of Writeback hits
130system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
131system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
132system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
133system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
| 1170system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
1171system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
1172system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
1173system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
1174system.l2c.Writeback_hits::total 1 # number of Writeback hits
1175system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
1176system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
1177system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
1178system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
134system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
135system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
136system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
137system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
| 1179system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
1180system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
1181system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits
1182system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
|
138system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
139system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
140system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
141system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
142system.l2c.overall_hits::cpu0.data 5 # number of overall hits
| 1183system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
1184system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
1185system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
1186system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
1187system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
143system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
144system.l2c.overall_hits::cpu1.data 3 # number of overall hits
145system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
146system.l2c.overall_hits::cpu2.data 9 # number of overall hits
| 1188system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
1189system.l2c.overall_hits::cpu1.data 9 # number of overall hits
1190system.l2c.overall_hits::cpu2.inst 302 # number of overall hits
1191system.l2c.overall_hits::cpu2.data 3 # number of overall hits
|
147system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
148system.l2c.overall_hits::cpu3.data 9 # number of overall hits
149system.l2c.overall_hits::total 1220 # number of overall hits
150system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
151system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
| 1192system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
1193system.l2c.overall_hits::cpu3.data 9 # number of overall hits
1194system.l2c.overall_hits::total 1220 # number of overall hits
1195system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
1196system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
|
152system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
153system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
154system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
155system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
| 1197system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses
1198system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses
1199system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses
1200system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses
|
156system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
157system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
158system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
159system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
| 1201system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
1202system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
1203system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
1204system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
160system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
161system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses
162system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
| 1205system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
1206system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
1207system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses
|
163system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
164system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
| 1208system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
1209system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
165system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
166system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
| 1210system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
1211system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
|
167system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
168system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
169system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
170system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
| 1212system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
1213system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
1214system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
1215system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
171system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
172system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
173system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
174system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
| 1216system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
1217system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
1218system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses
1219system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
|
175system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
176system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
177system.l2c.demand_misses::total 592 # number of demand (read+write) misses
178system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
179system.l2c.overall_misses::cpu0.data 165 # number of overall misses
| 1220system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
1221system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
1222system.l2c.demand_misses::total 592 # number of demand (read+write) misses
1223system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
1224system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
180system.l2c.overall_misses::cpu1.inst 66 # number of overall misses
181system.l2c.overall_misses::cpu1.data 23 # number of overall misses
182system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
183system.l2c.overall_misses::cpu2.data 16 # number of overall misses
| 1225system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
1226system.l2c.overall_misses::cpu1.data 16 # number of overall misses
1227system.l2c.overall_misses::cpu2.inst 64 # number of overall misses
1228system.l2c.overall_misses::cpu2.data 23 # number of overall misses
|
184system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
185system.l2c.overall_misses::cpu3.data 16 # number of overall misses
186system.l2c.overall_misses::total 592 # number of overall misses
| 1229system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
1230system.l2c.overall_misses::cpu3.data 16 # number of overall misses
1231system.l2c.overall_misses::total 592 # number of overall misses
|
187system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles
188system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles
189system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles
190system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles
191system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles
192system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
193system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles
194system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles
195system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles
196system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles
197system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles
198system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
199system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles
200system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles
201system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles
202system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles
203system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles
204system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles
205system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles
206system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
207system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles
208system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles
209system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles
210system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles
211system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles
212system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles
213system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles
214system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles
215system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
216system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles
217system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles
218system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles
| 1232system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles
1233system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles
1234system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles
1235system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles
1236system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles
1237system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles
1238system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles
1239system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles
1240system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles
1241system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles
1242system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles
1243system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles
1244system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles
1245system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles
1246system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles
1247system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles
1248system.l2c.demand_miss_latency::cpu1.inst 714500 # number of demand (read+write) miss cycles
1249system.l2c.demand_miss_latency::cpu1.data 848000 # number of demand (read+write) miss cycles
1250system.l2c.demand_miss_latency::cpu2.inst 3356500 # number of demand (read+write) miss cycles
1251system.l2c.demand_miss_latency::cpu2.data 1211500 # number of demand (read+write) miss cycles
1252system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles
1253system.l2c.demand_miss_latency::cpu3.data 843500 # number of demand (read+write) miss cycles
1254system.l2c.demand_miss_latency::total 31057500 # number of demand (read+write) miss cycles
1255system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles
1256system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles
1257system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles
1258system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles
1259system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles
1260system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles
1261system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles
1262system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles
1263system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles
|
219system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
220system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
221system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
222system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
223system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses)
224system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
225system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses)
226system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
227system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
228system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
229system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
230system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
| 1264system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
1265system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
1266system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
1267system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
1268system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses)
1269system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
1270system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses)
1271system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
1272system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
1273system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
1274system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
1275system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
231system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses)
232system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses)
233system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
| 1276system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
1277system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
1278system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
|
234system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
235system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
| 1279system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
1280system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
|
236system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses)
237system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses)
| 1281system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
1282system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
|
238system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
239system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
240system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
241system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
242system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
| 1283system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
1284system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
1285system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
1286system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
1287system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
|
243system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses
| 1288system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
244system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
| 1289system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
|
245system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
| 1290system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
|
246system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
247system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
248system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
249system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
250system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
251system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
| 1291system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
1292system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
1293system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
1294system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
1295system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
1296system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
|
252system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses
| 1297system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
253system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
| 1298system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
|
254system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
| 1299system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
|
255system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
256system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
257system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
258system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
259system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
| 1300system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
1301system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
1302system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
1303system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
1304system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
|
260system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses
261system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses
262system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses
263system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses
| 1305system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses
1306system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses
1307system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses
1308system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses
|
264system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses
265system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses
266system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses
267system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
268system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
269system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
270system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
271system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses
272system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
273system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
274system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
275system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
276system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
277system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
278system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
| 1309system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses
1310system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses
1311system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses
1312system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
1313system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1314system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
1315system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
1316system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses
1317system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1318system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1319system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1320system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1321system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1322system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
1323system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
|
279system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses
280system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses
281system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses
282system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses
| 1324system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
1325system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
1326system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses
1327system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
|
283system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
284system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
285system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses
286system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
287system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
| 1328system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
1329system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
1330system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses
1331system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
1332system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
|
288system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses
289system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses
290system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses
291system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses
| 1333system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
1334system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
1335system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses
1336system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
|
292system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
293system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
294system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
| 1337system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
1338system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
1339system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
|
295system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency
296system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency
297system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency
298system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency
299system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency
300system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
301system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency
302system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency
303system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency
304system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency
305system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency
306system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
307system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency
308system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency
309system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
310system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
311system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
312system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
313system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
314system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
315system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
316system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
317system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency
318system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency
319system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
320system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
321system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
322system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
323system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
324system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency
325system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
326system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency
| 1340system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386 # average ReadReq miss latency
1341system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency
1342system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286 # average ReadReq miss latency
1343system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency
1344system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500 # average ReadReq miss latency
1345system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency
1346system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889 # average ReadReq miss latency
1347system.l2c.ReadReq_avg_miss_latency::cpu3.data 51750 # average ReadReq miss latency
1348system.l2c.ReadReq_avg_miss_latency::total 52410 # average ReadReq miss latency
1349system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency
1350system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143 # average ReadExReq miss latency
1351system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667 # average ReadExReq miss latency
1352system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency
1353system.l2c.ReadExReq_avg_miss_latency::total 52626.760563 # average ReadExReq miss latency
1354system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency
1355system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency
1356system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency
1357system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency
1358system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency
1359system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency
1360system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency
1361system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency
1362system.l2c.demand_avg_miss_latency::total 52461.993243 # average overall miss latency
1363system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency
1364system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency
1365system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency
1366system.l2c.overall_avg_miss_latency::cpu1.data 53000 # average overall miss latency
1367system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency
1368system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency
1369system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency
1370system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency
1371system.l2c.overall_avg_miss_latency::total 52461.993243 # average overall miss latency
|
327system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
328system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
329system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
330system.l2c.blocked::no_targets 0 # number of cycles access was blocked
331system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
332system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333system.l2c.fast_writes 0 # number of fast writes performed
334system.l2c.cache_copies 0 # number of cache copies performed
335system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
336system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
| 1372system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1373system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1374system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1375system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1376system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1377system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1378system.l2c.fast_writes 0 # number of fast writes performed
1379system.l2c.cache_copies 0 # number of cache copies performed
1380system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
1381system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
|
337system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits
338system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits
339system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits
| 1382system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
1383system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits
1384system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits
|
340system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
341system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
342system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
| 1385system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
1386system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
1387system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
|
343system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits
344system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
345system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
| 1388system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
1389system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits
1390system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
|
346system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
347system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
348system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
| 1391system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
1392system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
1393system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
|
349system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits
350system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
351system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
| 1394system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
1395system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits
1396system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
|
352system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
353system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
354system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
| 1397system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
1398system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
1399system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
|
355system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses
356system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
357system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses
358system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
359system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses
360system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses
| 1400system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses
1401system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
1402system.l2c.ReadReq_mshr_misses::cpu2.inst 61 # number of ReadReq MSHR misses
1403system.l2c.ReadReq_mshr_misses::cpu2.data 8 # number of ReadReq MSHR misses
1404system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses
1405system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
|
361system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
362system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
| 1406system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
1407system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
|
363system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses
364system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses
365system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
| 1408system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses
1409system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
1410system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses
|
366system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
367system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
| 1411system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
1412system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
|
368system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses
369system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses
| 1413system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
1414system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
|
370system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
371system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
372system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
373system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
| 1415system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
1416system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
1417system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
1418system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
|
374system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses
375system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
376system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses
377system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses
378system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses
379system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses
| 1419system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses
1420system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
1421system.l2c.demand_mshr_misses::cpu2.inst 61 # number of demand (read+write) MSHR misses
1422system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses
1423system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
1424system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
|
380system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
381system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
382system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
| 1425system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
1426system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
1427system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
|
383system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses
384system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
385system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses
386system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses
387system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses
388system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses
| 1428system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses
1429system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
1430system.l2c.overall_mshr_misses::cpu2.inst 61 # number of overall MSHR misses
1431system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses
1432system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
1433system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
|
389system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
| 1434system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
390system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles
391system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
392system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles
393system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles
394system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles
395system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
396system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles
397system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles
398system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles
399system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles
400system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles
401system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles
402system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles
403system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles
404system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles
405system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles
406system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles
407system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles
408system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles
409system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles
410system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles
411system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles
412system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles
413system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles
414system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles
415system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles
416system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles
417system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles
418system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles
419system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles
420system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles
421system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles
422system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles
423system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles
424system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles
425system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles
426system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles
| 1435system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11542500 # number of ReadReq MSHR miss cycles
1436system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2673000 # number of ReadReq MSHR miss cycles
1437system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 283500 # number of ReadReq MSHR miss cycles
1438system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40500 # number of ReadReq MSHR miss cycles
1439system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2475000 # number of ReadReq MSHR miss cycles
1440system.l2c.ReadReq_mshr_miss_latency::cpu2.data 324000 # number of ReadReq MSHR miss cycles
1441system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40500 # number of ReadReq MSHR miss cycles
1442system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40500 # number of ReadReq MSHR miss cycles
1443system.l2c.ReadReq_mshr_miss_latency::total 17419500 # number of ReadReq MSHR miss cycles
1444system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1134000 # number of UpgradeReq MSHR miss cycles
1445system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 649996 # number of UpgradeReq MSHR miss cycles
1446system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 648000 # number of UpgradeReq MSHR miss cycles
1447system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 688500 # number of UpgradeReq MSHR miss cycles
1448system.l2c.UpgradeReq_mshr_miss_latency::total 3120496 # number of UpgradeReq MSHR miss cycles
1449system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4009500 # number of ReadExReq MSHR miss cycles
1450system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 575500 # number of ReadExReq MSHR miss cycles
1451system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 611500 # number of ReadExReq MSHR miss cycles
1452system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 571000 # number of ReadExReq MSHR miss cycles
1453system.l2c.ReadExReq_mshr_miss_latency::total 5767500 # number of ReadExReq MSHR miss cycles
1454system.l2c.demand_mshr_miss_latency::cpu0.inst 11542500 # number of demand (read+write) MSHR miss cycles
1455system.l2c.demand_mshr_miss_latency::cpu0.data 6682500 # number of demand (read+write) MSHR miss cycles
1456system.l2c.demand_mshr_miss_latency::cpu1.inst 283500 # number of demand (read+write) MSHR miss cycles
1457system.l2c.demand_mshr_miss_latency::cpu1.data 616000 # number of demand (read+write) MSHR miss cycles
1458system.l2c.demand_mshr_miss_latency::cpu2.inst 2475000 # number of demand (read+write) MSHR miss cycles
1459system.l2c.demand_mshr_miss_latency::cpu2.data 935500 # number of demand (read+write) MSHR miss cycles
1460system.l2c.demand_mshr_miss_latency::cpu3.inst 40500 # number of demand (read+write) MSHR miss cycles
1461system.l2c.demand_mshr_miss_latency::cpu3.data 611500 # number of demand (read+write) MSHR miss cycles
1462system.l2c.demand_mshr_miss_latency::total 23187000 # number of demand (read+write) MSHR miss cycles
1463system.l2c.overall_mshr_miss_latency::cpu0.inst 11542500 # number of overall MSHR miss cycles
1464system.l2c.overall_mshr_miss_latency::cpu0.data 6682500 # number of overall MSHR miss cycles
1465system.l2c.overall_mshr_miss_latency::cpu1.inst 283500 # number of overall MSHR miss cycles
1466system.l2c.overall_mshr_miss_latency::cpu1.data 616000 # number of overall MSHR miss cycles
1467system.l2c.overall_mshr_miss_latency::cpu2.inst 2475000 # number of overall MSHR miss cycles
1468system.l2c.overall_mshr_miss_latency::cpu2.data 935500 # number of overall MSHR miss cycles
1469system.l2c.overall_mshr_miss_latency::cpu3.inst 40500 # number of overall MSHR miss cycles
1470system.l2c.overall_mshr_miss_latency::cpu3.data 611500 # number of overall MSHR miss cycles
1471system.l2c.overall_mshr_miss_latency::total 23187000 # number of overall MSHR miss cycles
|
427system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
428system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
| 1472system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
1473system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
|
429system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
430system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses
431system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses
432system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses
433system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses
434system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses
| 1474system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses
1475system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses
1476system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for ReadReq accesses
1477system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadReq accesses
1478system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses
1479system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses
|
435system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
436system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
437system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
438system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
439system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
440system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
441system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
442system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
443system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
444system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
445system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
446system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
447system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
| 1480system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
1481system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
1482system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
1483system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
1484system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
1485system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
1486system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1487system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1488system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1489system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1490system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1491system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
1492system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
448system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses
449system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses
450system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses
451system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses
452system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses
453system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses
| 1493system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses
1494system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
1495system.l2c.demand_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for demand accesses
1496system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses
1497system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
1498system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
|
454system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
455system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
456system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
| 1499system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
1500system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
1501system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
457system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
458system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses
459system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses
460system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses
461system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses
462system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses
| 1502system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses
1503system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
1504system.l2c.overall_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for overall accesses
1505system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses
1506system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
1507system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
|
463system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
| 1508system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
464system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency
465system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
466system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency
467system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
468system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
469system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
470system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
471system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
472system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency
473system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
474system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency
475system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency
477system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency
478system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency
479system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency
480system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency
481system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
482system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency
483system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
484system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
485system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
486system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
487system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
488system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
489system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
490system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
491system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
492system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
493system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
494system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
495system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
496system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
497system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
498system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
499system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
500system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
| 1509system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency
1510system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency
1511system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40500 # average ReadReq mshr miss latency
1512system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency
1513system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average ReadReq mshr miss latency
1514system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadReq mshr miss latency
1515system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40500 # average ReadReq mshr miss latency
1516system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadReq mshr miss latency
1517system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116 # average ReadReq mshr miss latency
1518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40500 # average UpgradeReq mshr miss latency
1519system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency
1520system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency
1521system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency
1522system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency
1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency
1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency
1525system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency
1526system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency
1527system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency
1528system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
1529system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
1530system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency
1531system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency
1532system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency
1533system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency
1534system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency
1535system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency
1536system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency
1537system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
1538system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
1539system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency
1540system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency
1541system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency
1542system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency
1543system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency
1544system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency
1545system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency
|
501system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
| 1546system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
502system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
503system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
| 1547system.membus.trans_dist::ReadReq 430 # Transaction distribution
1548system.membus.trans_dist::ReadResp 430 # Transaction distribution
1549system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
1550system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
1551system.membus.trans_dist::ReadExReq 208 # Transaction distribution
1552system.membus.trans_dist::ReadExResp 142 # Transaction distribution
1553system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
1554system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
1555system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
1556system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
1557system.membus.snoops 261 # Total snoops (count)
1558system.membus.snoop_fanout::samples 914 # Request fanout histogram
1559system.membus.snoop_fanout::mean 0 # Request fanout histogram
1560system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1561system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1562system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram
1563system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1564system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1565system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1566system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1567system.membus.snoop_fanout::total 914 # Request fanout histogram
1568system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks)
1569system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
1570system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks)
1571system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
1572system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution
1573system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution
|
504system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
505system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
506system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
507system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
508system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
509system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
510system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
511system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
| 1574system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
1575system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
1576system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
1577system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
1578system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
1579system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
1580system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
1581system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
|
512system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
| 1582system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
|
513system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
| 1583system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
|
514system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
| 1584system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
|
515system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes)
| 1585system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes)
|
516system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes)
517system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes)
| 1586system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
1587system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes)
|
518system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
519system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
520system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
| 1588system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
1589system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
1590system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
521system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
| 1591system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
522system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
| 1592system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
523system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
| 1593system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
524system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
525system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
526system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
| 1594system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
1595system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1596system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
|
527system.toL2Bus.snoops 1037 # Total snoops (count)
528system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram
| 1597system.toL2Bus.snoops 1029 # Total snoops (count)
1598system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram
|
529system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
530system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
531system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
532system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
533system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
534system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
535system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
536system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
537system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
538system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
| 1599system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
1600system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
1601system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1602system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1603system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1604system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1605system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1606system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1607system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
1608system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
|
539system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram
| 1609system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram
|
540system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
541system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
542system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
543system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
| 1610system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
1611system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1612system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
1613system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
|
544system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram
545system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks)
| 1614system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram
1615system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks)
|
546system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
| 1616system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
547system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks)
548system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
549system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks)
550system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
551system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks)
552system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%)
553system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks)
554system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
555system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks)
556system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%)
557system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks)
558system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
559system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks)
560system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%)
561system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks)
562system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%)
563system.cpu0.workload.num_syscalls 89 # Number of system calls
564system.cpu0.numCycles 525587 # number of cpu cycles simulated
565system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
566system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
567system.cpu0.committedInsts 158574 # Number of instructions committed
568system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed
569system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses
570system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
571system.cpu0.num_func_calls 390 # number of times a function call or return occured
572system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls
573system.cpu0.num_int_insts 109208 # number of integer instructions
574system.cpu0.num_fp_insts 0 # number of float instructions
575system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read
576system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written
577system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
578system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
579system.cpu0.num_mem_refs 74021 # number of memory refs
580system.cpu0.num_load_insts 49007 # Number of load instructions
581system.cpu0.num_store_insts 25014 # Number of store instructions
582system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
583system.cpu0.num_busy_cycles 525586.998000 # Number of busy cycles
584system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
585system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
586system.cpu0.Branches 26897 # Number of branches fetched
587system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction
588system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction
589system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
590system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
591system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
592system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction
593system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction
594system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction
595system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction
596system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction
597system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction
598system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction
599system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction
600system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction
601system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction
602system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction
603system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction
604system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction
605system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction
606system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction
607system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction
608system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction
609system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction
610system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction
611system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction
612system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction
613system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction
614system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
615system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
616system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
617system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction
618system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction
619system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
620system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
621system.cpu0.op_class::total 158636 # Class of executed instruction
622system.cpu0.icache.tags.replacements 215 # number of replacements
623system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use
624system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks.
625system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
626system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks.
627system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
628system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor
629system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy
630system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy
631system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
632system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
633system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
634system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
635system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses
636system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses
637system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits
638system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits
639system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits
640system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits
641system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits
642system.cpu0.icache.overall_hits::total 158170 # number of overall hits
643system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
644system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
645system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
646system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
647system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
648system.cpu0.icache.overall_misses::total 467 # number of overall misses
649system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles
650system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles
651system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles
652system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles
653system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles
654system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles
655system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses)
656system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses)
657system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses
658system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses
659system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses
660system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses
661system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses
662system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses
663system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses
664system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses
665system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses
666system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses
667system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency
668system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency
669system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
670system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency
671system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
672system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency
673system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
674system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
676system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
677system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679system.cpu0.icache.fast_writes 0 # number of fast writes performed
680system.cpu0.icache.cache_copies 0 # number of cache copies performed
681system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
682system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
683system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
684system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
685system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
686system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
687system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles
688system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles
689system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles
690system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles
691system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles
692system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles
693system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses
694system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses
695system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses
696system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses
697system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses
698system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses
699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency
700system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency
701system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
702system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
703system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
704system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
705system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
706system.cpu0.dcache.tags.replacements 2 # number of replacements
707system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use
708system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks.
709system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
710system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks.
711system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
712system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor
713system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy
714system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy
715system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
716system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
717system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
718system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
719system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses
720system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses
721system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits
722system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits
723system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits
724system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits
725system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
726system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
727system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits
728system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits
729system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits
730system.cpu0.dcache.overall_hits::total 73607 # number of overall hits
731system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
732system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
733system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
734system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
735system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
736system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
737system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
738system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
739system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
740system.cpu0.dcache.overall_misses::total 353 # number of overall misses
741system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles
742system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles
743system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles
744system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles
745system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles
746system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles
747system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles
748system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles
749system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles
750system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles
751system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses)
752system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses)
753system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses)
754system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses)
755system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
756system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
757system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses
758system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses
759system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses
760system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses
761system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses
762system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses
763system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses
764system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses
765system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
766system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
767system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses
768system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses
769system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses
770system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses
771system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency
772system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency
773system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency
774system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency
775system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency
776system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency
777system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
778system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency
779system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
780system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency
781system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
784system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
785system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787system.cpu0.dcache.fast_writes 0 # number of fast writes performed
788system.cpu0.dcache.cache_copies 0 # number of cache copies performed
789system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
790system.cpu0.dcache.writebacks::total 1 # number of writebacks
791system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
792system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
793system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
794system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
795system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
796system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
797system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
798system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
799system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
800system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
801system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles
802system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles
803system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles
804system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles
805system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles
806system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles
807system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles
808system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles
809system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles
810system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles
811system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses
812system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses
813system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses
814system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses
815system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
816system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
817system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses
818system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses
819system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses
820system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses
821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency
822system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency
823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency
824system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency
825system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency
826system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency
827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
831system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
832system.cpu1.numCycles 525586 # number of cpu cycles simulated
833system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
834system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
835system.cpu1.committedInsts 163471 # Number of instructions committed
836system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed
837system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses
838system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
839system.cpu1.num_func_calls 637 # number of times a function call or return occured
840system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls
841system.cpu1.num_int_insts 111731 # number of integer instructions
842system.cpu1.num_fp_insts 0 # number of float instructions
843system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read
844system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written
845system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
846system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
847system.cpu1.num_mem_refs 58020 # number of memory refs
848system.cpu1.num_load_insts 41540 # Number of load instructions
849system.cpu1.num_store_insts 16480 # Number of store instructions
850system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles
851system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles
852system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles
853system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
854system.cpu1.Branches 31528 # Number of branches fetched
855system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction
856system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction
857system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction
858system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction
859system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction
860system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction
861system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction
862system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction
863system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction
864system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction
865system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction
866system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction
867system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction
868system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction
869system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction
870system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction
871system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction
872system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction
873system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction
874system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction
875system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction
876system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction
877system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction
878system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction
879system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction
880system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction
881system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction
882system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction
883system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction
884system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction
885system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction
886system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction
887system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
888system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
889system.cpu1.op_class::total 163503 # Class of executed instruction
890system.cpu1.icache.tags.replacements 280 # number of replacements
891system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use
892system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks.
893system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
894system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks.
895system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
896system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor
897system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy
898system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy
899system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
900system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
901system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
902system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
903system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
904system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses
905system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses
906system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits
907system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits
908system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits
909system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits
910system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits
911system.cpu1.icache.overall_hits::total 163138 # number of overall hits
912system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
913system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
914system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
915system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
916system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
917system.cpu1.icache.overall_misses::total 366 # number of overall misses
918system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles
919system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles
920system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles
921system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles
922system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles
923system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles
924system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses)
925system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses)
926system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses
927system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses
928system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses
929system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses
930system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses
931system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses
932system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses
933system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses
934system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses
935system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses
936system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency
937system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency
938system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
939system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency
940system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
941system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency
942system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
943system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
944system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
945system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
946system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
947system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
948system.cpu1.icache.fast_writes 0 # number of fast writes performed
949system.cpu1.icache.cache_copies 0 # number of cache copies performed
950system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
951system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
952system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
953system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
954system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
955system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
956system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles
957system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles
958system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles
959system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles
960system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles
961system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles
962system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses
963system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
964system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses
965system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses
966system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses
967system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses
968system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency
969system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency
970system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
971system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
972system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
973system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
974system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
975system.cpu1.dcache.tags.replacements 0 # number of replacements
976system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use
977system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks.
978system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
979system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks.
980system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
981system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor
982system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy
983system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy
984system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
985system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
986system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
987system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
988system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses
989system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses
990system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits
991system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits
992system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits
993system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits
994system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
995system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
996system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits
997system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits
998system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits
999system.cpu1.dcache.overall_hits::total 57685 # number of overall hits
1000system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses
1001system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses
1002system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
1003system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
1004system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses
1005system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses
1006system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses
1007system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses
1008system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses
1009system.cpu1.dcache.overall_misses::total 263 # number of overall misses
1010system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles
1011system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles
1012system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles
1013system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles
1014system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles
1015system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles
1016system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles
1017system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles
1018system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles
1019system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles
1020system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses)
1021system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses)
1022system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses)
1023system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses)
1024system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
1025system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
1026system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses
1027system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses
1028system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses
1029system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses
1030system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses
1031system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses
1032system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses
1033system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses
1034system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses
1035system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses
1036system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses
1037system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses
1038system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses
1039system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses
1040system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency
1041system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency
1042system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency
1043system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency
1044system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency
1045system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency
1046system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
1047system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency
1048system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
1049system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency
1050system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1051system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1052system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1053system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1054system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1055system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1056system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1057system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1058system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses
1059system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
1060system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
1061system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
1062system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses
1063system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
1064system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
1065system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
1066system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
1067system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
1068system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles
1069system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles
1070system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles
1071system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles
1072system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles
1073system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles
1074system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles
1075system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles
1076system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles
1077system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles
1078system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses
1079system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses
1080system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses
1081system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses
1082system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses
1083system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses
1084system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses
1085system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses
1086system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses
1087system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses
1088system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency
1089system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency
1090system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency
1091system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency
1092system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency
1093system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency
1094system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
1095system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
1096system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
1097system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
1098system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1099system.cpu2.numCycles 525586 # number of cpu cycles simulated
1100system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1101system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1102system.cpu2.committedInsts 164866 # Number of instructions committed
1103system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed
1104system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses
1105system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
1106system.cpu2.num_func_calls 637 # number of times a function call or return occured
1107system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls
1108system.cpu2.num_int_insts 112988 # number of integer instructions
1109system.cpu2.num_fp_insts 0 # number of float instructions
1110system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read
1111system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written
1112system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
1113system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
1114system.cpu2.num_mem_refs 59208 # number of memory refs
1115system.cpu2.num_load_insts 42171 # Number of load instructions
1116system.cpu2.num_store_insts 17037 # Number of store instructions
1117system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles
1118system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles
1119system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles
1120system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles
1121system.cpu2.Branches 31596 # Number of branches fetched
1122system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction
1123system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction
1124system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction
1125system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction
1126system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction
1127system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction
1128system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction
1129system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction
1130system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction
1131system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction
1132system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction
1133system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction
1134system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction
1135system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction
1136system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction
1137system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction
1138system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction
1139system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction
1140system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction
1141system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction
1142system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction
1143system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction
1144system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction
1145system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction
1146system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction
1147system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction
1148system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction
1149system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction
1150system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction
1151system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction
1152system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction
1153system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction
1154system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1155system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1156system.cpu2.op_class::total 164898 # Class of executed instruction
1157system.cpu2.icache.tags.replacements 280 # number of replacements
1158system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use
1159system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks.
1160system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
1161system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks.
1162system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1163system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor
1164system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy
1165system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy
1166system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1167system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1168system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1169system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1170system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1171system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses
1172system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses
1173system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits
1174system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits
1175system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits
1176system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits
1177system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits
1178system.cpu2.icache.overall_hits::total 164533 # number of overall hits
1179system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
1180system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
1181system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
1182system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
1183system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
1184system.cpu2.icache.overall_misses::total 366 # number of overall misses
1185system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles
1186system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles
1187system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles
1188system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles
1189system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles
1190system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles
1191system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses)
1192system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses)
1193system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses
1194system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses
1195system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses
1196system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses
1197system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses
1198system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses
1199system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses
1200system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
1201system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses
1202system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses
1203system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency
1204system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency
1205system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
1206system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency
1207system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
1208system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency
1209system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1210system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1211system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1212system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1213system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1214system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1215system.cpu2.icache.fast_writes 0 # number of fast writes performed
1216system.cpu2.icache.cache_copies 0 # number of cache copies performed
1217system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
1218system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
1219system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
1220system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
1221system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
1222system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
1223system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles
1224system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles
1225system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles
1226system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles
1227system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles
1228system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles
1229system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
1230system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
1231system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses
1232system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
1233system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
1234system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
1235system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency
1236system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency
1237system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
1238system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1239system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
1240system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1241system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1242system.cpu2.dcache.tags.replacements 0 # number of replacements
1243system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use
1244system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks.
1245system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1246system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks.
1247system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1248system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor
1249system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy
1250system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy
1251system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1252system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
1253system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
1254system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1255system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses
1256system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses
1257system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits
1258system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits
1259system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits
1260system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits
1261system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
1262system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
1263system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits
1264system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits
1265system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits
1266system.cpu2.dcache.overall_hits::total 58876 # number of overall hits
1267system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses
1268system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses
1269system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses
1270system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses
1271system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses
1272system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses
1273system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses
1274system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses
1275system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses
1276system.cpu2.dcache.overall_misses::total 262 # number of overall misses
1277system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles
1278system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles
1279system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles
1280system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles
1281system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles
1282system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles
1283system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles
1284system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles
1285system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles
1286system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles
1287system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses)
1288system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses)
1289system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses)
1290system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses)
1291system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses)
1292system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses)
1293system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses
1294system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses
1295system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses
1296system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses
1297system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses
1298system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses
1299system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses
1300system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses
1301system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
1302system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
1303system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses
1304system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses
1305system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses
1306system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses
1307system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency
1308system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency
1309system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency
1310system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency
1311system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency
1312system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency
1313system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
1314system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency
1315system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
1316system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency
1317system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1318system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1319system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1320system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1321system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1322system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1323system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1324system.cpu2.dcache.cache_copies 0 # number of cache copies performed
1325system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses
1326system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
1327system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses
1328system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses
1329system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses
1330system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
1331system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
1332system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
1333system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
1334system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
1335system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles
1336system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles
1337system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles
1338system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles
1339system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles
1340system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles
1341system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles
1342system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles
1343system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles
1344system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles
1345system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses
1346system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses
1347system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses
1348system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses
1349system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses
1350system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses
1351system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses
1352system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses
1353system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses
1354system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses
1355system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency
1356system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency
1357system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency
1358system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency
1359system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency
1360system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency
1361system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
1362system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
1363system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
1364system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
1365system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1366system.cpu3.numCycles 525586 # number of cpu cycles simulated
1367system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1368system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1369system.cpu3.committedInsts 176656 # Number of instructions committed
1370system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed
1371system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses
1372system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
1373system.cpu3.num_func_calls 637 # number of times a function call or return occured
1374system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls
1375system.cpu3.num_int_insts 108218 # number of integer instructions
1376system.cpu3.num_fp_insts 0 # number of float instructions
1377system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read
1378system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written
1379system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
1380system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
1381system.cpu3.num_mem_refs 46164 # number of memory refs
1382system.cpu3.num_load_insts 39753 # Number of load instructions
1383system.cpu3.num_store_insts 6411 # Number of store instructions
1384system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles
1385system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles
1386system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles
1387system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles
1388system.cpu3.Branches 39890 # Number of branches fetched
1389system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction
1390system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction
1391system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction
1392system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction
1393system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction
1394system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction
1395system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction
1396system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction
1397system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction
1398system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction
1399system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction
1400system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction
1401system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction
1402system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction
1403system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction
1404system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction
1405system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction
1406system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction
1407system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction
1408system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction
1409system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction
1410system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction
1411system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction
1412system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction
1413system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction
1414system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction
1415system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction
1416system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction
1417system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction
1418system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction
1419system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction
1420system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction
1421system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1422system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1423system.cpu3.op_class::total 176688 # Class of executed instruction
1424system.cpu3.icache.tags.replacements 281 # number of replacements
1425system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use
1426system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks.
1427system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1428system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks.
1429system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1430system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor
1431system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy
1432system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy
1433system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1434system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1435system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1436system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1437system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1438system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses
1439system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses
1440system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits
1441system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits
1442system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits
1443system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits
1444system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits
1445system.cpu3.icache.overall_hits::total 176322 # number of overall hits
1446system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1447system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1448system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1449system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1450system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1451system.cpu3.icache.overall_misses::total 367 # number of overall misses
1452system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles
1453system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles
1454system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles
1455system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles
1456system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles
1457system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles
1458system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses)
1459system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses)
1460system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses
1461system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses
1462system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses
1463system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses
1464system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses
1465system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses
1466system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses
1467system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses
1468system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses
1469system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses
1470system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency
1471system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency
1472system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency
1473system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency
1474system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency
1475system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency
1476system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1477system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1478system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1479system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1480system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1481system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1482system.cpu3.icache.fast_writes 0 # number of fast writes performed
1483system.cpu3.icache.cache_copies 0 # number of cache copies performed
1484system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1485system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1486system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1487system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1488system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1489system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1490system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles
1491system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles
1492system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles
1493system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles
1494system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles
1495system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles
1496system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses
1497system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses
1498system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses
1499system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses
1500system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses
1501system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses
1502system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency
1503system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency
1504system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
1505system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
1506system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
1507system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
1508system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1509system.cpu3.dcache.tags.replacements 0 # number of replacements
1510system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use
1511system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks.
1512system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1513system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks.
1514system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1515system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor
1516system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy
1517system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy
1518system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1519system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
1520system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
1521system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1522system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses
1523system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses
1524system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits
1525system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits
1526system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits
1527system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits
1528system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
1529system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
1530system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits
1531system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits
1532system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits
1533system.cpu3.dcache.overall_hits::total 45779 # number of overall hits
1534system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses
1535system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses
1536system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
1537system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
1538system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses
1539system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses
1540system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses
1541system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses
1542system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses
1543system.cpu3.dcache.overall_misses::total 288 # number of overall misses
1544system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles
1545system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles
1546system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles
1547system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles
1548system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles
1549system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles
1550system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles
1551system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles
1552system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles
1553system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles
1554system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses)
1555system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses)
1556system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses)
1557system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses)
1558system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses)
1559system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses)
1560system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses
1561system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses
1562system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses
1563system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses
1564system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses
1565system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses
1566system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses
1567system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses
1568system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses
1569system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses
1570system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses
1571system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses
1572system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses
1573system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses
1574system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency
1575system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency
1576system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency
1577system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency
1578system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency
1579system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency
1580system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
1581system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency
1582system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
1583system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency
1584system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1585system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1586system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1587system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1588system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1589system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1590system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1591system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1592system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses
1593system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
1594system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
1595system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
1596system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses
1597system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses
1598system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses
1599system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses
1600system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses
1601system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses
1602system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles
1603system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles
1604system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles
1605system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles
1606system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles
1607system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles
1608system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles
1609system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles
1610system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles
1611system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles
1612system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses
1613system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses
1614system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses
1615system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses
1616system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses
1617system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses
1618system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses
1619system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses
1620system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses
1621system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses
1622system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency
1623system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency
1624system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency
1625system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency
1626system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency
1627system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency
1628system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
1629system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
1630system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
1631system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
1632system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 1617system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
1618system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
1619system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks)
1620system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
1621system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks)
1622system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
1623system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks)
1624system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
1625system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks)
1626system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
1627system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks)
1628system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
1629system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks)
1630system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
1631system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks)
1632system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
|
1633
1634---------- End Simulation Statistics ----------
| 1633
1634---------- End Simulation Statistics ----------
|