| stats.txt (10220:9eab5efc02e8) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated |
| 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 262793500 # Number of ticks simulated 5final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 985745 # Simulator instruction rate (inst/s) 8host_op_rate 985721 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 390370221 # Simulator tick rate (ticks/s) 10host_mem_usage 283880 # Number of bytes of host memory used 11host_seconds 0.67 # Real time elapsed on the host | 7host_inst_rate 1021127 # Simulator instruction rate (inst/s) 8host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 404381057 # Simulator tick rate (ticks/s) 10host_mem_usage 299844 # Number of bytes of host memory used 11host_seconds 0.65 # Real time elapsed on the host |
| 12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory | 12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory |
| 39system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) 62system.membus.throughput 139302763 # Throughput (bytes/s) | 39system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) |
| 63system.membus.trans_dist::ReadReq 430 # Transaction distribution 64system.membus.trans_dist::ReadResp 430 # Transaction distribution 65system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 66system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 67system.membus.trans_dist::ReadExReq 208 # Transaction distribution 68system.membus.trans_dist::ReadExResp 142 # Transaction distribution 69system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 70system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) | 62system.membus.trans_dist::ReadReq 430 # Transaction distribution 63system.membus.trans_dist::ReadResp 430 # Transaction distribution 64system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 65system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 66system.membus.trans_dist::ReadExReq 208 # Transaction distribution 67system.membus.trans_dist::ReadExResp 142 # Transaction distribution 68system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 69system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) |
| 71system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 72system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 73system.membus.data_through_bus 36608 # Total data (bytes) 74system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 75system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) | 70system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 71system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 72system.membus.snoops 261 # Total snoops (count) 73system.membus.snoop_fanout::samples 915 # Request fanout histogram 74system.membus.snoop_fanout::mean 0 # Request fanout histogram 75system.membus.snoop_fanout::stdev 0 # Request fanout histogram 76system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 77system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram 78system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 79system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 80system.membus.snoop_fanout::min_value 0 # Request fanout histogram 81system.membus.snoop_fanout::max_value 0 # Request fanout histogram 82system.membus.snoop_fanout::total 915 # Request fanout histogram 83system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks) |
| 76system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 77system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 78system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 79system.cpu_clk_domain.clock 500 # Clock period in ticks 80system.l2c.tags.replacements 0 # number of replacements | 84system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 85system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 86system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 87system.cpu_clk_domain.clock 500 # Clock period in ticks 88system.l2c.tags.replacements 0 # number of replacements |
| 81system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use | 89system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use |
| 82system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 83system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 84system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 85system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 90system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 91system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 92system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 93system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 86system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor 87system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor 88system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor 89system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor 90system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 92system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor 93system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor 94system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor | 94system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor 95system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor 96system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor 97system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor 98system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor 99system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor 100system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor 101system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor 102system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor |
| 95system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 96system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 97system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 98system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 99system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 102system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy --- 70 unchanged lines hidden (view full) --- 173system.l2c.overall_misses::cpu1.data 23 # number of overall misses 174system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 175system.l2c.overall_misses::cpu2.data 16 # number of overall misses 176system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 177system.l2c.overall_misses::cpu3.data 16 # number of overall misses 178system.l2c.overall_misses::total 592 # number of overall misses 179system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 180system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles | 103system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 104system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 105system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 106system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 107system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 109system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 110system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy --- 70 unchanged lines hidden (view full) --- 181system.l2c.overall_misses::cpu1.data 23 # number of overall misses 182system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 183system.l2c.overall_misses::cpu2.data 16 # number of overall misses 184system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 185system.l2c.overall_misses::cpu3.data 16 # number of overall misses 186system.l2c.overall_misses::total 592 # number of overall misses 187system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles |
| 181system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles | 189system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles |
| 182system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles | 190system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 192system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 194system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles |
| 187system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles 188system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles | 195system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles |
| 189system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 190system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles | 197system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 198system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles |
| 191system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles 192system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles | 199system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles 200system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles |
| 193system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles | 201system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles |
| 194system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles 195system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles | 202system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles |
| 196system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 197system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 198system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles | 204system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 206system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles 207system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles |
| 200system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles | 208system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles |
| 202system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles | 210system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles |
| 203system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles 204system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles | 211system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles |
| 205system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 206system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles | 213system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 214system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 215system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles 216system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles |
| 209system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles 210system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles | 217system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles 218system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles |
| 211system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 212system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 213system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 214system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) --- 62 unchanged lines hidden (view full) --- 281system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 284system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 285system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 286system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency | 219system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 223system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 224system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 225system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 226system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) --- 62 unchanged lines hidden (view full) --- 289system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 290system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 291system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 294system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 295system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 296system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency |
| 289system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency | 297system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency |
| 290system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency 293system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 294system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency | 298system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 299system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 300system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency |
| 295system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency 296system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency | 303system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency 304system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency |
| 297system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 298system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency | 305system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 306system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency |
| 299system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency | 307system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency 308system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency |
| 301system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency | 309system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency |
| 302system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency | 310system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency 311system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency |
| 304system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency | 312system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 313system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 314system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 315system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency |
| 308system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency | 316system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency 317system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency |
| 310system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency | 318system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency |
| 311system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency | 319system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency 320system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency |
| 313system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency | 321system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 322system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 323system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 324system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency |
| 317system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 318system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency | 325system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency 326system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency |
| 319system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 322system.l2c.blocked::no_targets 0 # number of cycles access was blocked 323system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 325system.l2c.fast_writes 0 # number of fast writes performed 326system.l2c.cache_copies 0 # number of cache copies performed --- 61 unchanged lines hidden (view full) --- 388system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles 389system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 390system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 391system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 392system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 393system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 394system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 395system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles | 327system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 328system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 329system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 330system.l2c.blocked::no_targets 0 # number of cycles access was blocked 331system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 332system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 333system.l2c.fast_writes 0 # number of fast writes performed 334system.l2c.cache_copies 0 # number of cache copies performed --- 61 unchanged lines hidden (view full) --- 396system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles 397system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 398system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 399system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 400system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 401system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 402system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 403system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles |
| 396system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles | 404system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles |
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| 400system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles | 408system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles |
| 401system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles | 409system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles |
| 402system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles | 410system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles |
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| 410system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles | 418system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles |
| 411system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles | 419system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles |
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| 418system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles | 426system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles |
| 419system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 421system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 422system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses --- 35 unchanged lines hidden (view full) --- 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 466system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency | 427system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 428system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 429system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 430system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 431system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 432system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 433system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 434system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses --- 35 unchanged lines hidden (view full) --- 470system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 473system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 474system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 475system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency |
| 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency | 478system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency |
| 471system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency 472system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency | 479system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency 480system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency 481system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency |
| 474system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency | 482system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency |
| 475system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency | 483system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency |
| 476system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency | 484system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency |
| 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 481system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 482system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 485system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 490system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 483system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency | 491system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency |
| 484system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency | 492system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency |
| 485system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency | 493system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency |
| 486system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 488system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 489system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency | 494system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 495system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 496system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 497system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 498system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 499system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency |
| 492system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency | 500system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency |
| 493system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 501system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 494system.toL2Bus.throughput 646588875 # Throughput (bytes/s) | |
| 495system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 496system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 497system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 498system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 499system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 500system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 501system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 502system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) 503system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) 504system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 505system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) 506system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 507system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) 508system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) 509system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) 510system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) | 502system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 503system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 504system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 505system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 506system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 507system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 508system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 509system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) 510system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) 511system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 512system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) 513system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 514system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) 515system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) 516system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) 517system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) |
| 511system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 512system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 513system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 514system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 515system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 516system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 517system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 518system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 519system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) 520system.toL2Bus.data_through_bus 116032 # Total data (bytes) 521system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) | 518system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 519system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 520system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 521system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 522system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 523system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 524system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 525system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 526system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) 527system.toL2Bus.snoops 1037 # Total snoops (count) 528system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram 529system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 530system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 531system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 532system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 533system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 534system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 535system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 536system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 537system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 538system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 539system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram 540system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 541system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 542system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 543system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 544system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram |
| 522system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) 523system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 524system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) 525system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 526system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) 527system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 528system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) 529system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) 530system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) 531system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 532system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) 533system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) 534system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) 535system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 536system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) 537system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) 538system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) 539system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) 540system.cpu0.workload.num_syscalls 89 # Number of system calls | 545system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) 546system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 547system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) 548system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 549system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) 550system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 551system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) 552system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) 553system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) 554system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 555system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) 556system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) 557system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) 558system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 559system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) 560system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) 561system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) 562system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) 563system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 541system.cpu0.numCycles 525589 # number of cpu cycles simulated | 564system.cpu0.numCycles 525587 # number of cpu cycles simulated |
| 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 544system.cpu0.committedInsts 158574 # Number of instructions committed 545system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 548system.cpu0.num_func_calls 390 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 109208 # number of integer instructions 551system.cpu0.num_fp_insts 0 # number of float instructions 552system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 556system.cpu0.num_mem_refs 74021 # number of memory refs 557system.cpu0.num_load_insts 49007 # Number of load instructions 558system.cpu0.num_store_insts 25014 # Number of store instructions 559system.cpu0.num_idle_cycles 0 # Number of idle cycles | 565system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 566system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 567system.cpu0.committedInsts 158574 # Number of instructions committed 568system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed 569system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses 570system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 571system.cpu0.num_func_calls 390 # number of times a function call or return occured 572system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls 573system.cpu0.num_int_insts 109208 # number of integer instructions 574system.cpu0.num_fp_insts 0 # number of float instructions 575system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read 576system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written 577system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 578system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 579system.cpu0.num_mem_refs 74021 # number of memory refs 580system.cpu0.num_load_insts 49007 # Number of load instructions 581system.cpu0.num_store_insts 25014 # Number of store instructions 582system.cpu0.num_idle_cycles 0 # Number of idle cycles |
| 560system.cpu0.num_busy_cycles 525589 # Number of busy cycles | 583system.cpu0.num_busy_cycles 525587 # Number of busy cycles |
| 561system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0 # Percentage of idle cycles 563system.cpu0.Branches 26897 # Number of branches fetched 564system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction 565system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction 566system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 567system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 568system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 592system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 593system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 594system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction 595system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction 596system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 597system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 598system.cpu0.op_class::total 158636 # Class of executed instruction 599system.cpu0.icache.tags.replacements 215 # number of replacements | 584system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 585system.cpu0.idle_fraction 0 # Percentage of idle cycles 586system.cpu0.Branches 26897 # Number of branches fetched 587system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction 588system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction 589system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 590system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 591system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 615system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 616system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 617system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction 618system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction 619system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 620system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 621system.cpu0.op_class::total 158636 # Class of executed instruction 622system.cpu0.icache.tags.replacements 215 # number of replacements |
| 600system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use | 623system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use |
| 601system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. 602system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 603system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. 604system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 624system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. 625system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 626system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. 627system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 605system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor | 628system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor |
| 606system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy 607system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy 608system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 609system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 610system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 611system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 612system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses 613system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses --- 62 unchanged lines hidden (view full) --- 676system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency 677system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency 678system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 679system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 680system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 681system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 682system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 683system.cpu0.dcache.tags.replacements 2 # number of replacements | 629system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy 630system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy 631system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 632system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 633system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 634system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 635system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses 636system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses --- 62 unchanged lines hidden (view full) --- 699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency 700system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency 701system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 702system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 703system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 704system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 705system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 706system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 684system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use | 707system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use |
| 685system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. 686system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 687system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. 688system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 708system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. 709system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 710system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. 711system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 689system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor | 712system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor |
| 690system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy 691system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy 692system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 693system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 694system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 695system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 696system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses 697system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses --- 14 unchanged lines hidden (view full) --- 712system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 713system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 714system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 715system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 716system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 717system.cpu0.dcache.overall_misses::total 353 # number of overall misses 718system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles 719system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles | 713system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy 714system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy 715system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 716system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 717system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 718system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 719system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses 720system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses --- 14 unchanged lines hidden (view full) --- 735system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 736system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 737system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 738system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 739system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 740system.cpu0.dcache.overall_misses::total 353 # number of overall misses 741system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles 742system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles |
| 720system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles 721system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles | 743system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles 744system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles |
| 722system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles 723system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles | 745system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles 746system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles |
| 724system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles 725system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles 726system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles 727system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles | 747system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles 748system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles 749system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles 750system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles |
| 728system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) 729system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) 730system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) 731system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) 732system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 733system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 734system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses 735system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 742system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 743system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 744system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses 745system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses 746system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses 747system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses 748system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency 749system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency | 751system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) 752system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) 753system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) 754system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) 755system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 756system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 757system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses 758system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 765system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 766system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 767system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses 768system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses 769system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses 770system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses 771system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency 772system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency |
| 750system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency 751system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency | 773system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency 774system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency |
| 752system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency 753system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency | 775system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency 776system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency |
| 754system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 755system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency 756system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 757system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency | 777system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency 778system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency 779system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency 780system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency |
| 758system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 759system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 760system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 761system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 762system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 763system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 764system.cpu0.dcache.fast_writes 0 # number of fast writes performed 765system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 772system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 773system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 774system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 775system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 776system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 777system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 778system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles 779system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles | 781system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu0.dcache.fast_writes 0 # number of fast writes performed 788system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 795system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 796system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 797system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 798system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 799system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 800system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 801system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles 802system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles |
| 780system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles 781system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles | 803system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles 804system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles |
| 782system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles 783system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles | 805system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles 806system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles |
| 784system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles 785system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles 786system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles 787system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles | 807system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles 808system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles 809system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles 810system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles |
| 788system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses 789system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses 790system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses 791system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses 792system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 793system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 794system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses 795system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses 796system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses 797system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses 798system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency 799system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency | 811system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses 812system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses 813system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses 814system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses 815system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 816system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 817system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses 818system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses 819system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses 820system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses 821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency 822system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency |
| 800system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency 801system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency | 823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency 824system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency |
| 802system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency 803system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency | 825system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency 826system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency |
| 804system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 805system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency 806system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 807system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency | 827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency 828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency 830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency |
| 808system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 831system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu1.numCycles 525588 # number of cpu cycles simulated | 832system.cpu1.numCycles 525586 # number of cpu cycles simulated |
| 810system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 811system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 812system.cpu1.committedInsts 163471 # Number of instructions committed 813system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed 814system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses 815system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 816system.cpu1.num_func_calls 637 # number of times a function call or return occured 817system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls 818system.cpu1.num_int_insts 111731 # number of integer instructions 819system.cpu1.num_fp_insts 0 # number of float instructions 820system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 821system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 822system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 823system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 824system.cpu1.num_mem_refs 58020 # number of memory refs 825system.cpu1.num_load_insts 41540 # Number of load instructions 826system.cpu1.num_store_insts 16480 # Number of store instructions | 833system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 834system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 835system.cpu1.committedInsts 163471 # Number of instructions committed 836system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed 837system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses 838system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 839system.cpu1.num_func_calls 637 # number of times a function call or return occured 840system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls 841system.cpu1.num_int_insts 111731 # number of integer instructions 842system.cpu1.num_fp_insts 0 # number of float instructions 843system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 844system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 845system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 846system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 847system.cpu1.num_mem_refs 58020 # number of memory refs 848system.cpu1.num_load_insts 41540 # Number of load instructions 849system.cpu1.num_store_insts 16480 # Number of store instructions |
| 827system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles 828system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles | 850system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles 851system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles |
| 829system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles 830system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles 831system.cpu1.Branches 31528 # Number of branches fetched 832system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction 833system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction 834system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction 835system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction 836system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 860system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction 861system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction 862system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction 863system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction 864system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 865system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 866system.cpu1.op_class::total 163503 # Class of executed instruction 867system.cpu1.icache.tags.replacements 280 # number of replacements | 852system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles 853system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles 854system.cpu1.Branches 31528 # Number of branches fetched 855system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction 856system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction 857system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction 858system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction 859system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 883system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction 884system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction 885system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction 886system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction 887system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 888system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 889system.cpu1.op_class::total 163503 # Class of executed instruction 890system.cpu1.icache.tags.replacements 280 # number of replacements |
| 868system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use | 891system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use |
| 869system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 870system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 871system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 872system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 892system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 893system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 894system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 895system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 873system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor | 896system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor |
| 874system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 875system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 876system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 877system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 878system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 879system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 880system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 881system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 887system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 888system.cpu1.icache.overall_hits::total 163138 # number of overall hits 889system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 890system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 891system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 892system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 893system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 894system.cpu1.icache.overall_misses::total 366 # number of overall misses | 897system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 898system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 899system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 900system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 901system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 902system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 903system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 904system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 910system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 911system.cpu1.icache.overall_hits::total 163138 # number of overall hits 912system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 913system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 914system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 915system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 916system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 917system.cpu1.icache.overall_misses::total 366 # number of overall misses |
| 895system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles 896system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles 897system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles 898system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles 899system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles 900system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles | 918system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles 919system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles 920system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles 921system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles 922system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles 923system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles |
| 901system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 902system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 903system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 904system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 905system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 906system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 907system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 908system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 909system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 910system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 911system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 912system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses | 924system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 925system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 926system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 927system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 928system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 929system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 930system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 931system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 932system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 933system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 934system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 935system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses |
| 913system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency 914system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency 915system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 916system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency 917system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 918system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency | 936system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency 937system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency 938system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency 939system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency 940system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency 941system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency |
| 919system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 920system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 921system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 922system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 923system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 924system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 925system.cpu1.icache.fast_writes 0 # number of fast writes performed 926system.cpu1.icache.cache_copies 0 # number of cache copies performed 927system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 928system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 929system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 930system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 931system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 932system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 942system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu1.icache.fast_writes 0 # number of fast writes performed 949system.cpu1.icache.cache_copies 0 # number of cache copies performed 950system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 951system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 952system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 953system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 954system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 955system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 933system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles 938system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles | 956system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles 957system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles 958system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles 959system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles 960system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles 961system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles |
| 939system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 940system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 941system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 942system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 943system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 944system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses | 962system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 963system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 964system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 965system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 966system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 967system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses |
| 945system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency 946system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency 947system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 948system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 949system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 950system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency | 968system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency 969system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency 970system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency 971system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency 972system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency 973system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency |
| 951system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 952system.cpu1.dcache.tags.replacements 0 # number of replacements | 974system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 975system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 953system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use | 976system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use |
| 954system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 955system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 956system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 957system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 977system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 978system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 979system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 980system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 958system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor | 981system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor |
| 959system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy 960system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy 961system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 962system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 963system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 964system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 965system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses 966system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses --- 101 unchanged lines hidden (view full) --- 1068system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency 1069system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 1070system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency 1071system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1072system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1073system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1074system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1075system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 982system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy 983system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy 984system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 985system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 986system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 987system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 988system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses 989system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses --- 101 unchanged lines hidden (view full) --- 1091system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency 1092system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 1093system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency 1094system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1095system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1096system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1097system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1098system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1076system.cpu2.numCycles 525588 # number of cpu cycles simulated | 1099system.cpu2.numCycles 525586 # number of cpu cycles simulated |
| 1077system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1078system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1079system.cpu2.committedInsts 164866 # Number of instructions committed 1080system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 1081system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 1082system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 1083system.cpu2.num_func_calls 637 # number of times a function call or return occured 1084system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 1085system.cpu2.num_int_insts 112988 # number of integer instructions 1086system.cpu2.num_fp_insts 0 # number of float instructions 1087system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 1088system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 1089system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 1090system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 1091system.cpu2.num_mem_refs 59208 # number of memory refs 1092system.cpu2.num_load_insts 42171 # Number of load instructions 1093system.cpu2.num_store_insts 17037 # Number of store instructions | 1100system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1101system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1102system.cpu2.committedInsts 164866 # Number of instructions committed 1103system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 1104system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 1105system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 1106system.cpu2.num_func_calls 637 # number of times a function call or return occured 1107system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 1108system.cpu2.num_int_insts 112988 # number of integer instructions 1109system.cpu2.num_fp_insts 0 # number of float instructions 1110system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 1111system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 1112system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 1113system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 1114system.cpu2.num_mem_refs 59208 # number of memory refs 1115system.cpu2.num_load_insts 42171 # Number of load instructions 1116system.cpu2.num_store_insts 17037 # Number of store instructions |
| 1094system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles 1095system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles 1096system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles 1097system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles | 1117system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles 1118system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles 1119system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles 1120system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles |
| 1098system.cpu2.Branches 31596 # Number of branches fetched 1099system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction 1100system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction 1101system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction 1102system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction 1103system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction 1104system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction 1105system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction --- 21 unchanged lines hidden (view full) --- 1127system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction 1128system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction 1129system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction 1130system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction 1131system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1132system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1133system.cpu2.op_class::total 164898 # Class of executed instruction 1134system.cpu2.icache.tags.replacements 280 # number of replacements | 1121system.cpu2.Branches 31596 # Number of branches fetched 1122system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction 1123system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction 1124system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction 1125system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction 1126system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction 1127system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction 1128system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction --- 21 unchanged lines hidden (view full) --- 1150system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction 1151system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction 1152system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction 1153system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction 1154system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1155system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1156system.cpu2.op_class::total 164898 # Class of executed instruction 1157system.cpu2.icache.tags.replacements 280 # number of replacements |
| 1135system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use | 1158system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use |
| 1136system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 1137system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 1138system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 1139system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1159system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 1160system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 1161system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 1162system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1140system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor | 1163system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor |
| 1141system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1142system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1143system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1144system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1145system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1146system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1147system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1148system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 1154system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1155system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1156system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1157system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1158system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1159system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1160system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1161system.cpu2.icache.overall_misses::total 366 # number of overall misses | 1164system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1165system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1166system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1167system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1168system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1169system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1170system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1171system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 1177system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1178system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1179system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1180system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1181system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1182system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1183system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1184system.cpu2.icache.overall_misses::total 366 # number of overall misses |
| 1162system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles 1163system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles 1164system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles 1165system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles 1166system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles 1167system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles | 1185system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles 1186system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles 1187system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles 1188system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles 1189system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles 1190system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles |
| 1168system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1169system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1170system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1171system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1172system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1173system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1174system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1175system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1176system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1177system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1178system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1179system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses | 1191system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1192system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1193system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1194system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1195system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1196system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1197system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1198system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1199system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1200system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1201system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1202system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses |
| 1180system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency 1181system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency 1182system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1183system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency 1184system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1185system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency | 1203system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency 1204system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency 1205system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency 1206system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency 1207system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency 1208system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency |
| 1186system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1187system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1188system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1189system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1190system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1191system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1192system.cpu2.icache.fast_writes 0 # number of fast writes performed 1193system.cpu2.icache.cache_copies 0 # number of cache copies performed 1194system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1195system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1196system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1197system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1198system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1199system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses | 1209system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1210system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1211system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1212system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1213system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1214system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1215system.cpu2.icache.fast_writes 0 # number of fast writes performed 1216system.cpu2.icache.cache_copies 0 # number of cache copies performed 1217system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1218system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1219system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1220system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1221system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1222system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses |
| 1200system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles 1201system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles 1202system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles 1203system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles 1204system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles 1205system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles | 1223system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles 1224system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles 1225system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles 1226system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles 1227system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles 1228system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles |
| 1206system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1207system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1208system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1209system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1210system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1211system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses | 1229system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1230system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1231system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1232system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1233system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1234system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses |
| 1212system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency 1213system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency 1214system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1215system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1216system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1217system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency | 1235system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency 1236system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency 1237system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency 1238system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency 1239system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency 1240system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency |
| 1218system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1219system.cpu2.dcache.tags.replacements 0 # number of replacements | 1241system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1242system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 1220system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use | 1243system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use |
| 1221system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1222system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1223system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1224system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1244system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1245system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1246system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1247system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1225system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor | 1248system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor |
| 1226system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1227system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1228system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1229system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1230system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1231system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1232system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses 1233system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses --- 101 unchanged lines hidden (view full) --- 1335system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency 1336system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1337system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency 1338system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1339system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1340system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1341system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1342system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1249system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1250system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1251system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1252system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1253system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1254system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1255system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses 1256system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses --- 101 unchanged lines hidden (view full) --- 1358system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency 1359system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1360system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency 1361system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1362system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1363system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1364system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1365system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1343system.cpu3.numCycles 525588 # number of cpu cycles simulated | 1366system.cpu3.numCycles 525586 # number of cpu cycles simulated |
| 1344system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1345system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1346system.cpu3.committedInsts 176656 # Number of instructions committed 1347system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1348system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1349system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 1350system.cpu3.num_func_calls 637 # number of times a function call or return occured 1351system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls 1352system.cpu3.num_int_insts 108218 # number of integer instructions 1353system.cpu3.num_fp_insts 0 # number of float instructions 1354system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read 1355system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written 1356system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 1357system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 1358system.cpu3.num_mem_refs 46164 # number of memory refs 1359system.cpu3.num_load_insts 39753 # Number of load instructions 1360system.cpu3.num_store_insts 6411 # Number of store instructions | 1367system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1368system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1369system.cpu3.committedInsts 176656 # Number of instructions committed 1370system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1371system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1372system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 1373system.cpu3.num_func_calls 637 # number of times a function call or return occured 1374system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls 1375system.cpu3.num_int_insts 108218 # number of integer instructions 1376system.cpu3.num_fp_insts 0 # number of float instructions 1377system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read 1378system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written 1379system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 1380system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 1381system.cpu3.num_mem_refs 46164 # number of memory refs 1382system.cpu3.num_load_insts 39753 # Number of load instructions 1383system.cpu3.num_store_insts 6411 # Number of store instructions |
| 1361system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles 1362system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles 1363system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles 1364system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles | 1384system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles 1385system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles 1386system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles 1387system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles |
| 1365system.cpu3.Branches 39890 # Number of branches fetched 1366system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction 1367system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction 1368system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction 1369system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction 1370system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction 1371system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction 1372system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction --- 21 unchanged lines hidden (view full) --- 1394system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction 1395system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction 1396system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction 1397system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction 1398system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1399system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1400system.cpu3.op_class::total 176688 # Class of executed instruction 1401system.cpu3.icache.tags.replacements 281 # number of replacements | 1388system.cpu3.Branches 39890 # Number of branches fetched 1389system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction 1390system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction 1391system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction 1392system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction 1393system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction 1394system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction 1395system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction --- 21 unchanged lines hidden (view full) --- 1417system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction 1418system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction 1419system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction 1420system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction 1421system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1422system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1423system.cpu3.op_class::total 176688 # Class of executed instruction 1424system.cpu3.icache.tags.replacements 281 # number of replacements |
| 1402system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use | 1425system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use |
| 1403system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. 1404system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1405system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. 1406system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1426system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. 1427system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1428system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. 1429system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1407system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor | 1430system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor |
| 1408system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy 1409system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy 1410system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1411system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1412system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1413system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1414system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1415system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses --- 63 unchanged lines hidden (view full) --- 1479system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency 1480system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency 1481system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1482system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1483system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1484system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1485system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1486system.cpu3.dcache.tags.replacements 0 # number of replacements | 1431system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy 1432system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy 1433system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1434system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1435system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1436system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1437system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1438system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses --- 63 unchanged lines hidden (view full) --- 1502system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency 1503system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency 1504system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1505system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1506system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1507system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1508system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1509system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 1487system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use | 1510system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use |
| 1488system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. 1489system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1490system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. 1491system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1511system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. 1512system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1513system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. 1514system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1492system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor 1493system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy 1494system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy | 1515system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor 1516system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy 1517system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy |
| 1495system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1496system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1497system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1498system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1499system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses 1500system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses 1501system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits 1502system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits --- 12 unchanged lines hidden (view full) --- 1515system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses 1516system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses 1517system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses 1518system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses 1519system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses 1520system.cpu3.dcache.overall_misses::total 288 # number of overall misses 1521system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles 1522system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles | 1518system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1519system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1520system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1521system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1522system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses 1523system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses 1524system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits 1525system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits --- 12 unchanged lines hidden (view full) --- 1538system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses 1539system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses 1540system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses 1541system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses 1542system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses 1543system.cpu3.dcache.overall_misses::total 288 # number of overall misses 1544system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles 1545system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles |
| 1523system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles 1524system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles | 1546system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles 1547system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles |
| 1525system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles 1526system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles | 1548system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles 1549system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles |
| 1527system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles 1528system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles 1529system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles 1530system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles | 1550system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles 1551system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles 1552system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles 1553system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles |
| 1531system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) 1532system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) 1533system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) 1534system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) 1535system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) 1536system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) 1537system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses 1538system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 1545system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses 1546system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses 1547system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses 1548system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses 1549system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses 1550system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses 1551system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency 1552system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency | 1554system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) 1555system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) 1556system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) 1557system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) 1558system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) 1559system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) 1560system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses 1561system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 1568system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses 1569system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses 1570system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses 1571system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses 1572system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses 1573system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses 1574system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency 1575system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency |
| 1553system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency 1554system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency | 1576system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency 1577system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency |
| 1555system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency 1556system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency | 1578system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency 1579system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency |
| 1557system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1558system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency 1559system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1560system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency | 1580system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency 1581system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency 1582system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency 1583system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency |
| 1561system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1562system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1563system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1564system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1565system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1566system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1567system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1568system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1573system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses 1574system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses 1575system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses 1576system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses 1577system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses 1578system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses 1579system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles 1580system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles | 1584system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1585system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1586system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1587system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1588system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1589system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1591system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1596system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses 1597system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses 1598system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses 1599system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses 1600system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses 1601system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses 1602system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles 1603system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles |
| 1581system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles 1582system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles | 1604system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles 1605system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles |
| 1583system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles 1584system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles | 1606system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles 1607system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles |
| 1585system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles 1586system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles 1587system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles 1588system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles | 1608system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles 1609system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles 1610system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles 1611system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles |
| 1589system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses 1590system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses 1591system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses 1592system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses 1593system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses 1594system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses 1595system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses 1596system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses 1597system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses 1598system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses 1599system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency 1600system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency | 1612system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses 1613system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses 1614system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses 1615system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses 1616system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses 1617system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses 1618system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses 1619system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses 1620system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses 1621system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses 1622system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency 1623system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency |
| 1601system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency 1602system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency | 1624system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency 1625system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency |
| 1603system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency 1604system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency | 1626system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency 1627system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency |
| 1605system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1606system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency 1607system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1608system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency | 1628system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency 1629system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency 1630system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency 1631system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency |
| 1609system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1610 1611---------- End Simulation Statistics ---------- | 1632system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1633 1634---------- End Simulation Statistics ---------- |