7,11c7,11
< host_inst_rate 681070 # Simulator instruction rate (inst/s)
< host_op_rate 681053 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 269712940 # Simulator tick rate (ticks/s)
< host_mem_usage 243700 # Number of bytes of host memory used
< host_seconds 0.97 # Real time elapsed on the host
---
> host_inst_rate 200508 # Simulator instruction rate (inst/s)
> host_op_rate 200507 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 79406810 # Simulator tick rate (ticks/s)
> host_mem_usage 291148 # Number of bytes of host memory used
> host_seconds 3.31 # Real time elapsed on the host
172,175c172,175
< system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
178c178
< system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
180,181c180,181
< system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
183c183
< system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
186,189c186,189
< system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
192c192
< system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
195,198c195,198
< system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
201c201
< system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
280,283c280,283
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
286c286
< system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
288,289c288,289
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
291c291
< system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
294,297c294,297
< system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
300c300
< system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
303,306c303,306
< system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
309c309
< system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
388,389c388,389
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles
391c391
< system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles
395c395
< system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles
397c397
< system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles
400c400
< system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles
404c404
< system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles
406c406
< system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles
409c409
< system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles
462,463c462,463
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency
465c465
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency
469c469
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
471c471
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
474c474
< system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
478c478
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
480c480
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
483c483
< system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
770,773c770,773
< system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles
< system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles
---
> system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles
> system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
775c775
< system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use
---
> system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use
780c780
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor
795,800c795,800
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles
813,818c813,818
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency
---
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency
833,838c833,838
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles
845,850c845,850
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
881,884c881,884
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles
---
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles
887,890c887,890
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles
911,914c911,914
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency
917,920c917,920
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency
939,942c939,942
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles
---
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles
945,948c945,948
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles
959,962c959,962
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency
---
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency
965,968c965,968
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
988,991c988,991
< system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles
< system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles
< system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles
< system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles
---
> system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles
> system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles
> system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles
> system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
993c993
< system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use
---
> system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use
998c998
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor
1013,1018c1013,1018
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles
1031,1036c1031,1036
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency
---
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency
1051,1056c1051,1056
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles
1063,1068c1063,1068
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
1071c1071
< system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use
---
> system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use
1076c1076
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor
1099,1102c1099,1102
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles
---
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles
1105,1108c1105,1108
< system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles
---
> system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles
1129,1132c1129,1132
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency
---
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency
1135,1138c1135,1138
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency
---
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency
1157,1160c1157,1160
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles
---
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles
1163,1166c1163,1166
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles
---
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles
1177,1180c1177,1180
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency
---
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency
1183,1186c1183,1186
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
---
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
< host_inst_rate 681070 # Simulator instruction rate (inst/s)
< host_op_rate 681053 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 269712940 # Simulator tick rate (ticks/s)
< host_mem_usage 243700 # Number of bytes of host memory used
< host_seconds 0.97 # Real time elapsed on the host
---
> host_inst_rate 200508 # Simulator instruction rate (inst/s)
> host_op_rate 200507 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 79406810 # Simulator tick rate (ticks/s)
> host_mem_usage 291148 # Number of bytes of host memory used
> host_seconds 3.31 # Real time elapsed on the host
172,175c172,175
< system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
178c178
< system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
180,181c180,181
< system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
183c183
< system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
186,189c186,189
< system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
192c192
< system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
195,198c195,198
< system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
201c201
< system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
280,283c280,283
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
286c286
< system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
288,289c288,289
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
291c291
< system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
294,297c294,297
< system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
300c300
< system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
303,306c303,306
< system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
309c309
< system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
388,389c388,389
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles
391c391
< system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles
395c395
< system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles
397c397
< system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles
400c400
< system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles
404c404
< system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles
406c406
< system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles
409c409
< system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles
462,463c462,463
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency
465c465
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency
469c469
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
471c471
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
474c474
< system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
478c478
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency
480c480
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency
483c483
< system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
770,773c770,773
< system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles
< system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles
---
> system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles
> system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
775c775
< system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use
---
> system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use
780c780
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor
795,800c795,800
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles
813,818c813,818
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency
---
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency
833,838c833,838
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles
845,850c845,850
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
881,884c881,884
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles
---
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles
887,890c887,890
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles
911,914c911,914
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency
917,920c917,920
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency
939,942c939,942
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles
---
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles
945,948c945,948
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles
959,962c959,962
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency
---
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency
965,968c965,968
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency
988,991c988,991
< system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles
< system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles
< system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles
< system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles
---
> system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles
> system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles
> system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles
> system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
993c993
< system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use
---
> system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use
998c998
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor
1013,1018c1013,1018
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles
1031,1036c1031,1036
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency
---
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency
1051,1056c1051,1056
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles
1063,1068c1063,1068
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
1071c1071
< system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use
---
> system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use
1076c1076
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor
1099,1102c1099,1102
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles
---
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles
1105,1108c1105,1108
< system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles
---
> system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles
1129,1132c1129,1132
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency
---
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency
1135,1138c1135,1138
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency
---
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency
1157,1160c1157,1160
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles
---
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles
1163,1166c1163,1166
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles
---
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles
1177,1180c1177,1180
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency
---
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency
1183,1186c1183,1186
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency
---
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency