Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

Deleted Added

sdiff udiff text old ( 10892:bd37e25fb3b7 ) new ( 11138:a611a23c8cc2 )

full compact

3,5c3,5
< sim_seconds 0.000260 # Number of seconds simulated
< sim_ticks 260073500 # Number of ticks simulated
< final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000261 # Number of seconds simulated
> sim_ticks 260712500 # Number of ticks simulated
> final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1077387 # Simulator instruction rate (inst/s)
< host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 425087977 # Simulator tick rate (ticks/s)
< host_mem_usage 303432 # Number of bytes of host memory used
< host_seconds 0.61 # Real time elapsed on the host
< sim_insts 659129 # Number of instructions simulated
< sim_ops 659129 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1018019 # Simulator instruction rate (inst/s)
> host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 401917302 # Simulator tick rate (ticks/s)
> host_mem_usage 306320 # Number of bytes of host memory used
> host_seconds 0.65 # Real time elapsed on the host
> sim_insts 660333 # Number of instructions simulated
> sim_ops 660333 # Number of ops (including micro ops) simulated
39,61c39,61
< system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s)
64c64
< system.cpu0.numCycles 520147 # number of cpu cycles simulated
---
> system.cpu0.numCycles 521425 # number of cpu cycles simulated
67,69c67,69
< system.cpu0.committedInsts 157434 # Number of instructions committed
< system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses
---
> system.cpu0.committedInsts 157788 # Number of instructions committed
> system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses
72,73c72,73
< system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 108448 # number of integer instructions
---
> system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 108684 # number of integer instructions
75,76c75,76
< system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written
79,81c79,81
< system.cpu0.num_mem_refs 73451 # number of memory refs
< system.cpu0.num_load_insts 48627 # Number of load instructions
< system.cpu0.num_store_insts 24824 # Number of store instructions
---
> system.cpu0.num_mem_refs 73628 # number of memory refs
> system.cpu0.num_load_insts 48745 # Number of load instructions
> system.cpu0.num_store_insts 24883 # Number of store instructions
83c83
< system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles
---
> system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles
86,118c86,118
< system.cpu0.Branches 26707 # Number of branches fetched
< system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction
< system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction
< system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction
< system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction
< system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction
---
> system.cpu0.Branches 26766 # Number of branches fetched
> system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction
> system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction
> system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction
> system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction
> system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction
121c121
< system.cpu0.op_class::total 157496 # Class of executed instruction
---
> system.cpu0.op_class::total 157850 # Class of executed instruction
123,124c123,124
< system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks.
126c126
< system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks.
128,130c128,130
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy
135,140c135,140
< system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits
143,148c143,148
< system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits
< system.cpu0.dcache.overall_hits::total 73037 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
---
> system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits
> system.cpu0.dcache.overall_hits::total 73215 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses
153,160c153,160
< system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
< system.cpu0.dcache.overall_misses::total 353 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles
---
> system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses
> system.cpu0.dcache.overall_misses::total 352 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles
163,170c163,170
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses)
173,180c173,180
< system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses
183,190c183,190
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency
193,196c193,196
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency
207,208c207,208
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
---
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses
213,220c213,220
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles
223,230c223,230
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses
233,240c233,240
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency
243,246c243,246
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency
249,250c249,250
< system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks.
---
> system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks.
252c252
< system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks.
254,256c254,256
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy
261,268c261,268
< system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits
< system.cpu0.icache.overall_hits::total 157030 # number of overall hits
---
> system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits
> system.cpu0.icache.overall_hits::total 157384 # number of overall hits
275,298c275,298
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency
---
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency
313,330c313,330
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
332c332
< system.cpu1.numCycles 520147 # number of cpu cycles simulated
---
> system.cpu1.numCycles 521425 # number of cpu cycles simulated
335,337c335,337
< system.cpu1.committedInsts 165571 # Number of instructions committed
< system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses
---
> system.cpu1.committedInsts 168182 # Number of instructions committed
> system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses
340,341c340,341
< system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 111555 # number of integer instructions
---
> system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 110851 # number of integer instructions
343,344c343,344
< system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written
347,386c347,386
< system.cpu1.num_mem_refs 56707 # number of memory refs
< system.cpu1.num_load_insts 41448 # Number of load instructions
< system.cpu1.num_store_insts 15259 # Number of store instructions
< system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles
< system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles
< system.cpu1.Branches 32668 # Number of branches fetched
< system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction
< system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction
< system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction
< system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction
< system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction
---
> system.cpu1.num_mem_refs 54346 # number of memory refs
> system.cpu1.num_load_insts 41092 # Number of load instructions
> system.cpu1.num_store_insts 13254 # Number of store instructions
> system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles
> system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles
> system.cpu1.Branches 34327 # Number of branches fetched
> system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction
> system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction
> system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction
> system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction
> system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction
389c389
< system.cpu1.op_class::total 165603 # Class of executed instruction
---
> system.cpu1.op_class::total 168214 # Class of executed instruction
391,392c391,392
< system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks.
394c394
< system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks.
396,398c396,398
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy
403,464c403,464
< system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits
< system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
< system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits
< system.cpu1.dcache.overall_hits::total 56366 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
< system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
< system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses
< system.cpu1.dcache.overall_misses::total 265 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles
< system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency
< system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency
---
> system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits
> system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
> system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits
> system.cpu1.dcache.overall_hits::total 53996 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses
> system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
> system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses
> system.cpu1.dcache.overall_misses::total 271 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles
> system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency
> system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency
473,512c473,512
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
< system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency
< system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency
---
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
> system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency
> system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency
515,516c515,516
< system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks.
518c518
< system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks.
520,522c520,522
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy
528,535c528,535
< system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits
< system.cpu1.icache.overall_hits::total 165238 # number of overall hits
---
> system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits
> system.cpu1.icache.overall_hits::total 167849 # number of overall hits
542,565c542,565
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency
580,597c580,597
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
599c599
< system.cpu2.numCycles 520146 # number of cpu cycles simulated
---
> system.cpu2.numCycles 521424 # number of cpu cycles simulated
602,604c602,604
< system.cpu2.committedInsts 160598 # Number of instructions committed
< system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed
< system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses
---
> system.cpu2.committedInsts 165155 # Number of instructions committed
> system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed
> system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses
607,608c607,608
< system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls
< system.cpu2.num_int_insts 111601 # number of integer instructions
---
> system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls
> system.cpu2.num_int_insts 110249 # number of integer instructions
610,611c610,611
< system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read
< system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written
---
> system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read
> system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written
614,653c614,653
< system.cpu2.num_mem_refs 59264 # number of memory refs
< system.cpu2.num_load_insts 41473 # Number of load instructions
< system.cpu2.num_store_insts 17791 # Number of store instructions
< system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles
< system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles
< system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles
< system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles
< system.cpu2.Branches 30158 # Number of branches fetched
< system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction
< system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction
< system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction
< system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction
< system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction
---
> system.cpu2.num_mem_refs 54956 # number of memory refs
> system.cpu2.num_load_insts 40791 # Number of load instructions
> system.cpu2.num_store_insts 14165 # Number of store instructions
> system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles
> system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles
> system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles
> system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles
> system.cpu2.Branches 33115 # Number of branches fetched
> system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction
> system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction
> system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction
> system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction
656c656
< system.cpu2.op_class::total 160630 # Class of executed instruction
---
> system.cpu2.op_class::total 165187 # Class of executed instruction
658,659c658,659
< system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks.
661c661
< system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks.
663,665c663,665
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy
670,731c670,731
< system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits
< system.cpu2.dcache.overall_hits::total 58928 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses
< system.cpu2.dcache.overall_misses::total 261 # number of overall misses
< system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles
< system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles
< system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles
< system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles
< system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles
< system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles
< system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles
< system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses)
< system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency
< system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency
< system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency
< system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency
< system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency
< system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency
< system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency
---
> system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits
> system.cpu2.dcache.overall_hits::total 54608 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
> system.cpu2.dcache.overall_misses::total 269 # number of overall misses
> system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles
> system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles
> system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles
> system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles
> system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles
> system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles
> system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles
> system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
> system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency
> system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency
> system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency
> system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency
> system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency
> system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency
> system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency
740,779c740,779
< system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses
< system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses
< system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses
< system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
< system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses
< system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses
< system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses
< system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles
< system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles
< system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses
< system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses
< system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses
< system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses
< system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency
< system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency
< system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency
< system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency
< system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency
< system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency
---
> system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
> system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
> system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
> system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
> system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
> system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses
> system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
> system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles
> system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles
> system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
> system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses
> system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses
> system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses
> system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency
> system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency
> system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency
> system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency
> system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency
> system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency
782,783c782,783
< system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks.
785c785
< system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks.
787,789c787,789
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy
795,802c795,802
< system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits
< system.cpu2.icache.overall_hits::total 160265 # number of overall hits
---
> system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits
> system.cpu2.icache.overall_hits::total 164822 # number of overall hits
809,832c809,832
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses
< system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses
< system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses
< system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses
< system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses
< system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses
> system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses
> system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses
> system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses
> system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses
> system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency
847,864c847,864
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses
< system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses
< system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses
< system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses
< system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses
> system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses
> system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses
> system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses
> system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
866c866
< system.cpu3.numCycles 520146 # number of cpu cycles simulated
---
> system.cpu3.numCycles 521424 # number of cpu cycles simulated
869,871c869,871
< system.cpu3.committedInsts 175526 # Number of instructions committed
< system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed
< system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses
---
> system.cpu3.committedInsts 169208 # Number of instructions committed
> system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed
> system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses
874,875c874,875
< system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls
< system.cpu3.num_int_insts 107877 # number of integer instructions
---
> system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls
> system.cpu3.num_int_insts 110441 # number of integer instructions
877,878c877,878
< system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read
< system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written
---
> system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read
> system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written
881,920c881,920
< system.cpu3.num_mem_refs 46213 # number of memory refs
< system.cpu3.num_load_insts 39592 # Number of load instructions
< system.cpu3.num_store_insts 6621 # Number of store instructions
< system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles
< system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles
< system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles
< system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles
< system.cpu3.Branches 39491 # Number of branches fetched
< system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction
< system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction
< system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction
< system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction
< system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction
---
> system.cpu3.num_mem_refs 53219 # number of memory refs
> system.cpu3.num_load_insts 40883 # Number of load instructions
> system.cpu3.num_store_insts 12336 # Number of store instructions
> system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles
> system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles
> system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles
> system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles
> system.cpu3.Branches 35047 # Number of branches fetched
> system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction
> system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction
> system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction
> system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction
> system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction
923c923
< system.cpu3.op_class::total 175558 # Class of executed instruction
---
> system.cpu3.op_class::total 169240 # Class of executed instruction
925,926c925,926
< system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks.
928c928
< system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks.
930,932c930,932
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy
937,998c937,998
< system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits
< system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
< system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
< system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits
< system.cpu3.dcache.overall_hits::total 45837 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses
< system.cpu3.dcache.overall_misses::total 287 # number of overall misses
< system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles
< system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles
< system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles
< system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency
< system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency
< system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency
---
> system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits
> system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
> system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
> system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits
> system.cpu3.dcache.overall_hits::total 52867 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses
> system.cpu3.dcache.overall_misses::total 270 # number of overall misses
> system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles
> system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles
> system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles
> system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency
> system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency
> system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency
1007,1046c1007,1046
< system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses
< system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
< system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses
< system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
< system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses
< system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses
< system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses
< system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles
< system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses
< system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses
< system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses
< system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses
< system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency
< system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency
< system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency
---
> system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
> system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
> system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
> system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
> system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
> system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses
> system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
> system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles
> system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses
> system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses
> system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses
> system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses
> system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency
> system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency
> system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency
1049,1050c1049,1050
< system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks.
1052c1052
< system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks.
1054,1056c1054,1056
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy
1062,1069c1062,1069
< system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits
< system.cpu3.icache.overall_hits::total 175192 # number of overall hits
---
> system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits
> system.cpu3.icache.overall_hits::total 168874 # number of overall hits
1076,1099c1076,1099
< system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles
< system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles
< system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles
< system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles
< system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles
< system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses
< system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses
< system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses
< system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses
< system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses
< system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency
< system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency
< system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency
< system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency
< system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency
---
> system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles
> system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles
> system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles
> system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles
> system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles
> system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses
> system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses
> system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses
> system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses
> system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses
> system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency
> system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency
> system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency
> system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency
> system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency
1114,1131c1114,1131
< system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles
< system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles
< system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses
< system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses
< system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses
< system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses
< system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency
< system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency
< system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency
< system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency
---
> system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5004500 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_latency::total 5004500 # number of ReadReq MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5004500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.demand_mshr_miss_latency::total 5004500 # number of demand (read+write) MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5004500 # number of overall MSHR miss cycles
> system.cpu3.icache.overall_mshr_miss_latency::total 5004500 # number of overall MSHR miss cycles
> system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002169 # mshr miss rate for ReadReq accesses
> system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for demand accesses
> system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses
> system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses
> system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency
> system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency
> system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency
> system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency
1134c1134
< system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use
1139,1147c1139,1147
< system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor
1149c1149
< system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy
1156,1157c1156,1157
< system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy
1162,1163c1162,1163
< system.l2c.tags.tag_accesses 19677 # Number of tag accesses
< system.l2c.tags.data_accesses 19677 # Number of data accesses
---
> system.l2c.tags.tag_accesses 19669 # Number of tag accesses
> system.l2c.tags.data_accesses 19669 # Number of data accesses
1197,1200c1197,1200
< system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
1236c1236
< system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu2.data 795500 # number of ReadExReq miss cycles
1238,1239c1238,1239
< system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::total 7472000 # number of ReadExReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14963500 # number of ReadCleanReq miss cycles
1241,1243c1241,1243
< system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles
---
> system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3340500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu3.inst 446500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::total 19490500 # number of ReadCleanReq miss cycles
1249c1249
< system.l2c.demand_miss_latency::cpu0.inst 14964000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 14963500 # number of demand (read+write) miss cycles
1253,1255c1253,1255
< system.l2c.demand_miss_latency::cpu2.inst 3341500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu2.data 1216000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu3.inst 453500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu2.inst 3340500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu2.data 1214500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu3.inst 446500 # number of demand (read+write) miss cycles
1257,1258c1257,1258
< system.l2c.demand_miss_latency::total 31066000 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 14964000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::total 31056000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 14963500 # number of overall miss cycles
1262,1264c1262,1264
< system.l2c.overall_miss_latency::cpu2.inst 3341500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu2.data 1216000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu3.inst 453500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu2.inst 3340500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu2.data 1214500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu3.inst 446500 # number of overall miss cycles
1266c1266
< system.l2c.overall_miss_latency::total 31066000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 31056000 # number of overall miss cycles
1270,1273c1270,1273
< system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
1311c1311
< system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses
1347c1347
< system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53033.333333 # average ReadExReq miss latency
1349,1350c1349,1350
< system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::total 52619.718310 # average ReadExReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52503.508772 # average ReadCleanReq miss latency
1352,1354c1352,1354
< system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667 # average ReadCleanReq miss latency
---
> system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52195.312500 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 49611.111111 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::total 52393.817204 # average ReadCleanReq miss latency
1360c1360
< system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency
1364,1366c1364,1366
< system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency
1368,1369c1368,1369
< system.l2c.demand_avg_miss_latency::total 52476.351351 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 52459.459459 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency
1373,1375c1373,1375
< system.l2c.overall_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency
1377c1377
< system.l2c.overall_avg_miss_latency::total 52476.351351 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 52459.459459 # average overall miss latency
1403,1406c1403,1406
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
1440,1444c1440,1444
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1194000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 850000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 479492 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 3288492 # number of UpgradeReq MSHR miss cycles
---
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1222000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 700497 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 700497 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 698998 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 3321992 # number of UpgradeReq MSHR miss cycles
1447c1447
< system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 647000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 645500 # number of ReadExReq MSHR miss cycles
1449,1450c1449,1450
< system.l2c.ReadExReq_mshr_miss_latency::total 6053500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12114000 # number of ReadCleanReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 6052000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12113500 # number of ReadCleanReq MSHR miss cycles
1454c1454
< system.l2c.ReadCleanReq_mshr_miss_latency::total 15052000 # number of ReadCleanReq MSHR miss cycles
---
> system.l2c.ReadCleanReq_mshr_miss_latency::total 15051500 # number of ReadCleanReq MSHR miss cycles
1460c1460
< system.l2c.demand_mshr_miss_latency::cpu0.inst 12114000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 12113500 # number of demand (read+write) MSHR miss cycles
1465c1465
< system.l2c.demand_mshr_miss_latency::cpu2.data 944500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu2.data 943000 # number of demand (read+write) MSHR miss cycles
1468,1469c1468,1469
< system.l2c.demand_mshr_miss_latency::total 24335500 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 12114000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 24333500 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 12113500 # number of overall MSHR miss cycles
1474c1474
< system.l2c.overall_mshr_miss_latency::cpu2.data 944500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu2.data 943000 # number of overall MSHR miss cycles
1477c1477
< system.l2c.overall_mshr_miss_latency::total 24335500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 24333500 # number of overall MSHR miss cycles
1482c1482
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses
1516,1520c1516,1520
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency
---
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency
1523c1523
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency
1525,1526c1525,1526
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 42619.718310 # average ReadExReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average ReadCleanReq mshr miss latency
1530c1530
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency
---
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42518.361582 # average ReadCleanReq mshr miss latency
1536c1536
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
1541c1541
< system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
1544,1545c1544,1545
< system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
1550c1550
< system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
1553c1553
< system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
1556,1557c1556,1557
< system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 271 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
1561,1562c1561,1562
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes)
1566c1566
< system.membus.snoop_fanout::samples 914 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 913 # Request fanout histogram
1570c1570
< system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram
1575,1576c1575,1576
< system.membus.snoop_fanout::total 914 # Request fanout histogram
< system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 913 # Request fanout histogram
> system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks)
1578c1578
< system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks)
1580c1580,1586
< system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution
1583,1584c1589,1590
< system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
---
> system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution
1588c1594
< system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution
1590c1596
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
1592,1597c1598,1603
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes)
1607,1610c1613,1616
< system.toL2Bus.snoops 1037 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.toL2Bus.snoops 1034 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram
1612,1619c1618,1625
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
1622,1625c1628,1631
< system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
< system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks)
1629c1635
< system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks)
1633c1639
< system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks)
1637c1643
< system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks)
1641c1647
< system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks)