4,5c4,5
< sim_ticks 262794500 # Number of ticks simulated
< final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 262793500 # Number of ticks simulated
> final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 985745 # Simulator instruction rate (inst/s)
< host_op_rate 985721 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 390370221 # Simulator tick rate (ticks/s)
< host_mem_usage 283880 # Number of bytes of host memory used
< host_seconds 0.67 # Real time elapsed on the host
---
> host_inst_rate 1021127 # Simulator instruction rate (inst/s)
> host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 404381057 # Simulator tick rate (ticks/s)
> host_mem_usage 299844 # Number of bytes of host memory used
> host_seconds 0.65 # Real time elapsed on the host
39,62c39,61
< system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s)
< system.membus.throughput 139302763 # Throughput (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
71,75c70,83
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36608 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 261 # Total snoops (count)
> system.membus.snoop_fanout::samples 915 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 915 # Request fanout histogram
> system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks)
81c89
< system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use
86,94c94,102
< system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor
181c189
< system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles
187,188c195,196
< system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles
191,192c199,200
< system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles
194,195c202,203
< system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles
200,201c208,209
< system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles
203,204c211,212
< system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles
209,210c217,218
< system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles
289c297
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency
295,296c303,304
< system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency
299,300c307,308
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency
302,303c310,311
< system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
308,309c316,317
< system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency
311,312c319,320
< system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
317,318c325,326
< system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency
396c404
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles
400c408
< system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles
402c410
< system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles
409c417
< system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles
411c419
< system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles
418c426
< system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles
470c478
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency
474c482
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency
476c484
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
483c491
< system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
485c493
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
492c500
< system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
494d501
< system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
511,521c518,544
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 116032 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes)
---
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 1037 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram
541c564
< system.cpu0.numCycles 525589 # number of cpu cycles simulated
---
> system.cpu0.numCycles 525587 # number of cpu cycles simulated
560c583
< system.cpu0.num_busy_cycles 525589 # Number of busy cycles
---
> system.cpu0.num_busy_cycles 525587 # Number of busy cycles
600c623
< system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use
605c628
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor
684c707
< system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use
---
> system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use
689c712
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor
720,721c743,744
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles
724,727c747,750
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles
750,751c773,774
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency
754,757c777,780
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency
780,781c803,804
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles
784,787c807,810
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles
800,801c823,824
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency
804,807c827,830
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
809c832
< system.cpu1.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu1.numCycles 525586 # number of cpu cycles simulated
827,828c850,851
< system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles
< system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles
---
> system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles
> system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles
868c891
< system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use
---
> system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use
873c896
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor
895,900c918,923
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles
913,918c936,941
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency
---
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency
933,938c956,961
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles
945,950c968,973
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
953c976
< system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use
---
> system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use
958c981
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor
1076c1099
< system.cpu2.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu2.numCycles 525586 # number of cpu cycles simulated
1094,1097c1117,1120
< system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles
< system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles
< system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles
< system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
---
> system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles
> system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles
> system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles
> system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles
1135c1158
< system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use
---
> system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use
1140c1163
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor
1162,1167c1185,1190
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles
1180,1185c1203,1208
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency
---
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency
1200,1205c1223,1228
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles
1212,1217c1235,1240
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1220c1243
< system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use
---
> system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use
1225c1248
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor
1343c1366
< system.cpu3.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu3.numCycles 525586 # number of cpu cycles simulated
1361,1364c1384,1387
< system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles
< system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles
< system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles
< system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles
---
> system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles
> system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles
> system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles
> system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles
1402c1425
< system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use
---
> system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use
1407c1430
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor
1487c1510
< system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use
---
> system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use
1492,1494c1515,1517
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy
1523,1524c1546,1547
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles
---
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles
1527,1530c1550,1553
< system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles
---
> system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles
1553,1554c1576,1577
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency
---
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency
1557,1560c1580,1583
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency
---
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency
1581,1582c1604,1605
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles
---
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles
1585,1588c1608,1611
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles
---
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles
1601,1602c1624,1625
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency
---
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency
1605,1608c1628,1631
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
---
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
< sim_ticks 262794500 # Number of ticks simulated
< final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 262793500 # Number of ticks simulated
> final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 985745 # Simulator instruction rate (inst/s)
< host_op_rate 985721 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 390370221 # Simulator tick rate (ticks/s)
< host_mem_usage 283880 # Number of bytes of host memory used
< host_seconds 0.67 # Real time elapsed on the host
---
> host_inst_rate 1021127 # Simulator instruction rate (inst/s)
> host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 404381057 # Simulator tick rate (ticks/s)
> host_mem_usage 299844 # Number of bytes of host memory used
> host_seconds 0.65 # Real time elapsed on the host
39,62c39,61
< system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s)
< system.membus.throughput 139302763 # Throughput (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
71,75c70,83
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36608 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 261 # Total snoops (count)
> system.membus.snoop_fanout::samples 915 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 915 # Request fanout histogram
> system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks)
81c89
< system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use
86,94c94,102
< system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor
181c189
< system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles
187,188c195,196
< system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles
191,192c199,200
< system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles
194,195c202,203
< system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles
200,201c208,209
< system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles
203,204c211,212
< system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles
209,210c217,218
< system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles
289c297
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency
295,296c303,304
< system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency
299,300c307,308
< system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency
302,303c310,311
< system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
308,309c316,317
< system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency
311,312c319,320
< system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency
317,318c325,326
< system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency
396c404
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles
400c408
< system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles
402c410
< system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles
409c417
< system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles
411c419
< system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles
418c426
< system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles
470c478
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency
474c482
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency
476c484
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
483c491
< system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
485c493
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency
492c500
< system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency
494d501
< system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
511,521c518,544
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 116032 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes)
---
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 1037 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram
541c564
< system.cpu0.numCycles 525589 # number of cpu cycles simulated
---
> system.cpu0.numCycles 525587 # number of cpu cycles simulated
560c583
< system.cpu0.num_busy_cycles 525589 # Number of busy cycles
---
> system.cpu0.num_busy_cycles 525587 # Number of busy cycles
600c623
< system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use
605c628
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor
684c707
< system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use
---
> system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use
689c712
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor
720,721c743,744
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles
724,727c747,750
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles
750,751c773,774
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency
754,757c777,780
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency
780,781c803,804
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles
784,787c807,810
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles
800,801c823,824
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency
804,807c827,830
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency
809c832
< system.cpu1.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu1.numCycles 525586 # number of cpu cycles simulated
827,828c850,851
< system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles
< system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles
---
> system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles
> system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles
868c891
< system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use
---
> system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use
873c896
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor
895,900c918,923
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles
---
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles
913,918c936,941
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency
---
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency
933,938c956,961
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles
945,950c968,973
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency
953c976
< system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use
---
> system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use
958c981
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor
1076c1099
< system.cpu2.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu2.numCycles 525586 # number of cpu cycles simulated
1094,1097c1117,1120
< system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles
< system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles
< system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles
< system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
---
> system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles
> system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles
> system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles
> system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles
1135c1158
< system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use
---
> system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use
1140c1163
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor
1162,1167c1185,1190
< system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles
< system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles
< system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles
< system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles
< system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles
< system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles
---
> system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles
> system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles
> system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles
> system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles
> system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles
> system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles
1180,1185c1203,1208
< system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency
< system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency
< system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
< system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency
< system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency
---
> system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency
> system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency
> system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
> system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency
> system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency
1200,1205c1223,1228
< system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles
< system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles
---
> system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles
> system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles
1212,1217c1235,1240
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency
< system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency
< system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency
---
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency
> system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency
> system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency
1220c1243
< system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use
---
> system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use
1225c1248
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor
1343c1366
< system.cpu3.numCycles 525588 # number of cpu cycles simulated
---
> system.cpu3.numCycles 525586 # number of cpu cycles simulated
1361,1364c1384,1387
< system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles
< system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles
< system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles
< system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles
---
> system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles
> system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles
> system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles
> system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles
1402c1425
< system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use
---
> system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use
1407c1430
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor
1487c1510
< system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use
---
> system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use
1492,1494c1515,1517
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy
1523,1524c1546,1547
< system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles
< system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles
---
> system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles
> system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles
1527,1530c1550,1553
< system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles
< system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles
< system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles
< system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles
---
> system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles
> system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles
> system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles
> system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles
1553,1554c1576,1577
< system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency
< system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency
---
> system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency
> system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency
1557,1560c1580,1583
< system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
< system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
< system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency
---
> system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
> system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency
> system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency
1581,1582c1604,1605
< system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles
< system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles
---
> system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles
> system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles
1585,1588c1608,1611
< system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles
< system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles
---
> system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles
> system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles
1601,1602c1624,1625
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency
< system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency
---
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency
> system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency
1605,1608c1628,1631
< system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
< system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
---
> system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency
> system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency