Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

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stats.txt (9838:43d22d746e7a)	stats.txt (9988:0b2e590c85be)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 681070 # Simulator instruction rate (inst/s) 8host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 269712940 # Simulator tick rate (ticks/s) 10host_mem_usage 243700 # Number of bytes of host memory used 11host_seconds 0.97 # Real time elapsed on the host	7host_inst_rate 200508 # Simulator instruction rate (inst/s) 8host_op_rate 200507 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 79406810 # Simulator tick rate (ticks/s) 10host_mem_usage 291148 # Number of bytes of host memory used 11host_seconds 3.31 # Real time elapsed on the host
12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) 60system.membus.throughput 139302763 # Throughput (bytes/s) 61system.membus.trans_dist::ReadReq 430 # Transaction distribution 62system.membus.trans_dist::ReadResp 430 # Transaction distribution 63system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 64system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 65system.membus.trans_dist::ReadExReq 208 # Transaction distribution 66system.membus.trans_dist::ReadExResp 142 # Transaction distribution 67system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 68system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) 69system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 70system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 71system.membus.data_through_bus 36608 # Total data (bytes) 72system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 73system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) 74system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 75system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 76system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 77system.l2c.tags.replacements 0 # number of replacements 78system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use 79system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 80system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 81system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 82system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor 84system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor 85system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor 86system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor 87system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor 88system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 89system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor 90system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor 92system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 93system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 94system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 95system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 96system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 97system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 98system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 99system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy 102system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 103system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 104system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 105system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 106system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 107system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 108system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 109system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 110system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 111system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 112system.l2c.Writeback_hits::total 1 # number of Writeback hits 113system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 114system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 115system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 116system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 117system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 118system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 119system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits 120system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 121system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 122system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 123system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 124system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 125system.l2c.overall_hits::cpu0.data 5 # number of overall hits 126system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 127system.l2c.overall_hits::cpu1.data 3 # number of overall hits 128system.l2c.overall_hits::cpu2.inst 354 # number of overall hits 129system.l2c.overall_hits::cpu2.data 9 # number of overall hits 130system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 131system.l2c.overall_hits::cpu3.data 9 # number of overall hits 132system.l2c.overall_hits::total 1220 # number of overall hits 133system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 134system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 135system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 136system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 137system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 138system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 139system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 140system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 141system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 142system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 143system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 144system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 145system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 146system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 147system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 148system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 149system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 150system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 151system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 152system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 153system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 154system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 155system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 156system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 157system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses 158system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 159system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 160system.l2c.demand_misses::total 592 # number of demand (read+write) misses 161system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 162system.l2c.overall_misses::cpu0.data 165 # number of overall misses 163system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 164system.l2c.overall_misses::cpu1.data 23 # number of overall misses 165system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 166system.l2c.overall_misses::cpu2.data 16 # number of overall misses 167system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 168system.l2c.overall_misses::cpu3.data 16 # number of overall misses 169system.l2c.overall_misses::total 592 # number of overall misses 170system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 171system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles	12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory 22system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) 60system.membus.throughput 139302763 # Throughput (bytes/s) 61system.membus.trans_dist::ReadReq 430 # Transaction distribution 62system.membus.trans_dist::ReadResp 430 # Transaction distribution 63system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 64system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 65system.membus.trans_dist::ReadExReq 208 # Transaction distribution 66system.membus.trans_dist::ReadExResp 142 # Transaction distribution 67system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 68system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) 69system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 70system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 71system.membus.data_through_bus 36608 # Total data (bytes) 72system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 73system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) 74system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 75system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 76system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 77system.l2c.tags.replacements 0 # number of replacements 78system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use 79system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 80system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 81system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 82system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor 84system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor 85system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor 86system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor 87system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor 88system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 89system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor 90system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor 92system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 93system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 94system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 95system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 96system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 97system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 98system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 99system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy 102system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 103system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 104system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 105system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 106system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 107system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 108system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 109system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 110system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 111system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 112system.l2c.Writeback_hits::total 1 # number of Writeback hits 113system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 114system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 115system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 116system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 117system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 118system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 119system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits 120system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 121system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 122system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 123system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 124system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 125system.l2c.overall_hits::cpu0.data 5 # number of overall hits 126system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 127system.l2c.overall_hits::cpu1.data 3 # number of overall hits 128system.l2c.overall_hits::cpu2.inst 354 # number of overall hits 129system.l2c.overall_hits::cpu2.data 9 # number of overall hits 130system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 131system.l2c.overall_hits::cpu3.data 9 # number of overall hits 132system.l2c.overall_hits::total 1220 # number of overall hits 133system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 134system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 135system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 136system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 137system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 138system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 139system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 140system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 141system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 142system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 143system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 144system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 145system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 146system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 147system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 148system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 149system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 150system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 151system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 152system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 153system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 154system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 155system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 156system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 157system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses 158system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 159system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 160system.l2c.demand_misses::total 592 # number of demand (read+write) misses 161system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 162system.l2c.overall_misses::cpu0.data 165 # number of overall misses 163system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 164system.l2c.overall_misses::cpu1.data 23 # number of overall misses 165system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 166system.l2c.overall_misses::cpu2.data 16 # number of overall misses 167system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 168system.l2c.overall_misses::cpu3.data 16 # number of overall misses 169system.l2c.overall_misses::total 592 # number of overall misses 170system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 171system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles
172system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles 173system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles 174system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles 175system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles	172system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles 173system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 174system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 175system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles
176system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 177system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles	176system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 177system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles
178system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles	178system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles
179system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles	179system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles
180system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles 181system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles	180system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 181system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles
182system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles	182system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles
183system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles	183system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles
184system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 185system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles	184system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 185system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles
186system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles 187system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles 188system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles 189system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles	186system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles 187system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 188system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 189system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles
190system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 191system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles	190system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 191system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles
192system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles	192system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles
193system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 194system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles	193system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 194system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles
195system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles 196system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles 197system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles 198system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles	195system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles 196system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 197system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 198system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles
199system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 200system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles	199system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 200system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles
201system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles	201system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles
202system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 203system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 204system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 205system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 206system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 207system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 208system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 209system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 210system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 211system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 212system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 213system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 214system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) 215system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 216system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 217system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 218system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 219system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 220system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 221system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 222system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 223system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 224system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 225system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 226system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses 227system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 228system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 229system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 230system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 231system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 232system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 233system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 234system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 235system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses 236system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 237system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 238system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 239system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 240system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 241system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 242system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 243system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 244system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses 245system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 246system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses 247system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 248system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses 249system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses 250system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 251system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 252system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 253system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 254system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses 255system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 256system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 257system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 258system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 259system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 260system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 261system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 262system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 263system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses 264system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 265system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses 266system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 267system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 268system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses 269system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 270system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 271system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 272system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 273system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 274system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 275system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 276system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 277system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 278system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 279system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency	202system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 203system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 204system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 205system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 206system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 207system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 208system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 209system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 210system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 211system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 212system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 213system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 214system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) 215system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 216system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 217system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 218system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 219system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 220system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 221system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 222system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 223system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 224system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 225system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 226system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses 227system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 228system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 229system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 230system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 231system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 232system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 233system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 234system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 235system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses 236system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 237system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 238system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 239system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 240system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 241system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 242system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 243system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 244system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses 245system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 246system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses 247system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 248system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses 249system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses 250system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 251system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 252system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 253system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 254system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses 255system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 256system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 257system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 258system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 259system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 260system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 261system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 262system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 263system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses 264system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 265system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses 266system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 267system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 268system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses 269system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 270system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 271system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 272system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 273system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 274system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 275system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 276system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 277system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 278system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 279system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency
280system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency 281system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency 282system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency 283system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency	280system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency 281system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 282system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 283system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency
284system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 285system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency	284system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 285system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency
286system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency	286system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency
287system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency	287system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency
288system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency 289system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency	288system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 289system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency
290system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency	290system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency
291system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency	291system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency
292system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 293system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency	292system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 293system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
294system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency 295system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency 296system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency 297system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency	294system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 295system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 296system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 297system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
298system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 299system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency	298system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 299system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
300system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency	300system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency
301system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency	301system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency
303system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency 304system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency 305system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency 306system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency	303system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 304system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 305system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 306system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency
307system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency	307system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency
309system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency	309system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency
310system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 313system.l2c.blocked::no_targets 0 # number of cycles access was blocked 314system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.l2c.fast_writes 0 # number of fast writes performed 317system.l2c.cache_copies 0 # number of cache copies performed 318system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 319system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 320system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits 321system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits 322system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits 323system.l2c.ReadReq_mshr_hits::total 20 # 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