Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

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stats.txt (8835:7c68f84d7c4e)	stats.txt (8983:8800b05e1cb3)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000262 # Number of seconds simulated 4sim_ticks 262298000 # Number of ticks simulated 5final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1330969 # Simulator instruction rate (inst/s) 8host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 527074583 # Simulator tick rate (ticks/s) 10host_mem_usage 221728 # Number of bytes of host memory used 11host_seconds 0.50 # Real time elapsed on the host	7host_inst_rate 323904 # Simulator instruction rate (inst/s) 8host_op_rate 323899 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 128274037 # Simulator tick rate (ticks/s) 10host_mem_usage 231956 # Number of bytes of host memory used 11host_seconds 2.05 # Real time elapsed on the host
12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 36608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 572 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) 23system.cpu0.workload.num_syscalls 89 # Number of system calls 24system.cpu0.numCycles 524596 # number of cpu cycles simulated 25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu0.committedInsts 158353 # Number of instructions committed 28system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed 29system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses 30system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 31system.cpu0.num_func_calls 390 # number of times a function call or return occured 32system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls 33system.cpu0.num_int_insts 109064 # number of integer instructions 34system.cpu0.num_fp_insts 0 # number of float instructions 35system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read 36system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written 37system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 38system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 39system.cpu0.num_mem_refs 73905 # number of memory refs 40system.cpu0.num_load_insts 48930 # Number of load instructions 41system.cpu0.num_store_insts 24975 # Number of store instructions 42system.cpu0.num_idle_cycles 0 # Number of idle cycles 43system.cpu0.num_busy_cycles 524596 # Number of busy cycles 44system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 45system.cpu0.idle_fraction 0 # Percentage of idle cycles 46system.cpu0.icache.replacements 215 # number of replacements 47system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use 48system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. 49system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 50system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. 51system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 52system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor 53system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy 54system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy 55system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits 56system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits 57system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits 58system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits 59system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits 60system.cpu0.icache.overall_hits::total 157949 # number of overall hits 61system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 62system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 63system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 64system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 65system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 66system.cpu0.icache.overall_misses::total 467 # number of overall misses 67system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles 68system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles 69system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles 70system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles 71system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles 72system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles 73system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) 74system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) 75system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses 76system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses 77system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses 78system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses 79system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses 80system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses 81system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses 82system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency 83system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 84system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 85system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked	12sim_insts 662307 # Number of instructions simulated 13sim_ops 662307 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 36608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 572 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) 23system.cpu0.workload.num_syscalls 89 # Number of system calls 24system.cpu0.numCycles 524596 # number of cpu cycles simulated 25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu0.committedInsts 158353 # Number of instructions committed 28system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed 29system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses 30system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 31system.cpu0.num_func_calls 390 # number of times a function call or return occured 32system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls 33system.cpu0.num_int_insts 109064 # number of integer instructions 34system.cpu0.num_fp_insts 0 # number of float instructions 35system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read 36system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written 37system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 38system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 39system.cpu0.num_mem_refs 73905 # number of memory refs 40system.cpu0.num_load_insts 48930 # Number of load instructions 41system.cpu0.num_store_insts 24975 # Number of store instructions 42system.cpu0.num_idle_cycles 0 # Number of idle cycles 43system.cpu0.num_busy_cycles 524596 # Number of busy cycles 44system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 45system.cpu0.idle_fraction 0 # Percentage of idle cycles 46system.cpu0.icache.replacements 215 # number of replacements 47system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use 48system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. 49system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 50system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. 51system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 52system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor 53system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy 54system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy 55system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits 56system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits 57system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits 58system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits 59system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits 60system.cpu0.icache.overall_hits::total 157949 # number of overall hits 61system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 62system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 63system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 64system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 65system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 66system.cpu0.icache.overall_misses::total 467 # number of overall misses 67system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles 68system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles 69system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles 70system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles 71system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles 72system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles 73system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) 74system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) 75system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses 76system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses 77system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses 78system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses 79system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses 80system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses 81system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses 82system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency 83system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 84system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency 85system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
89system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 90system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	89system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
91system.cpu0.icache.fast_writes 0 # number of fast writes performed 92system.cpu0.icache.cache_copies 0 # number of cache copies performed 93system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 94system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 95system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 96system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 97system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 98system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 99system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles 100system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 101system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles 102system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles 103system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles 104system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles 105system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses 106system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses 107system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses 108system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency 109system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 110system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 111system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu0.dcache.replacements 9 # number of replacements 113system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use 114system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. 115system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 116system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. 117system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 118system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor 119system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy 120system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy 121system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits 122system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits 123system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits 124system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits 125system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 126system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 127system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits 128system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits 129system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits 130system.cpu0.dcache.overall_hits::total 73499 # number of overall hits 131system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses 132system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 133system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 134system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 135system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 136system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 137system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses 138system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses 139system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses 140system.cpu0.dcache.overall_misses::total 345 # number of overall misses 141system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles 142system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles 143system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles 144system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles 145system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles 146system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles 147system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles 148system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles 149system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles 150system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles 151system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) 152system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) 153system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) 154system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) 155system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 156system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 157system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses 158system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses 159system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses 160system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses 161system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses 162system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses 163system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 164system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses 165system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses 166system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency 167system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency 168system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency 169system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 170system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 171system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked	91system.cpu0.icache.fast_writes 0 # number of fast writes performed 92system.cpu0.icache.cache_copies 0 # number of cache copies performed 93system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 94system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 95system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 96system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 97system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 98system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 99system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles 100system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 101system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles 102system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles 103system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles 104system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles 105system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses 106system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses 107system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses 108system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency 109system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 110system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency 111system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu0.dcache.replacements 9 # number of replacements 113system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use 114system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. 115system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 116system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. 117system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 118system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor 119system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy 120system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy 121system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits 122system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits 123system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits 124system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits 125system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 126system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 127system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits 128system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits 129system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits 130system.cpu0.dcache.overall_hits::total 73499 # number of overall hits 131system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses 132system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses 133system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 134system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 135system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 136system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 137system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses 138system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses 139system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses 140system.cpu0.dcache.overall_misses::total 345 # number of overall misses 141system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles 142system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles 143system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles 144system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles 145system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles 146system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles 147system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles 148system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles 149system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles 150system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles 151system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) 152system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) 153system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) 154system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) 155system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 156system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 157system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses 158system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses 159system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses 160system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses 161system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses 162system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses 163system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 164system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses 165system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses 166system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency 167system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency 168system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency 169system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 170system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency 171system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
175system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 176system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	175system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 179system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 180system.cpu0.dcache.writebacks::total 6 # number of writebacks 181system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses 182system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 183system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 184system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 185system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 186system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 187system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses 188system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses 189system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses 190system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses 191system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles 192system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles 193system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles 194system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles 195system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles 196system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles 197system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles 198system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles 199system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles 200system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles 201system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses 202system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses 203system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 204system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses 205system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses 206system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency 207system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency 208system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency 209system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency 210system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency 211system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 212system.cpu1.numCycles 524596 # number of cpu cycles simulated 213system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 214system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 215system.cpu1.committedInsts 172325 # Number of instructions committed 216system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed 217system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses 218system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 219system.cpu1.num_func_calls 637 # number of times a function call or return occured 220system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls 221system.cpu1.num_int_insts 107932 # number of integer instructions 222system.cpu1.num_fp_insts 0 # number of float instructions 223system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read 224system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written 225system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 226system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 227system.cpu1.num_mem_refs 47898 # number of memory refs 228system.cpu1.num_load_insts 39616 # Number of load instructions 229system.cpu1.num_store_insts 8282 # Number of store instructions 230system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles 231system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles 232system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles 233system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles 234system.cpu1.icache.replacements 280 # number of replacements 235system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use 236system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. 237system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. 238system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. 239system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 240system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor 241system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy 242system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy 243system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits 244system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits 245system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits 246system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits 247system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits 248system.cpu1.icache.overall_hits::total 171992 # number of overall hits 249system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 250system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 251system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 252system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 253system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 254system.cpu1.icache.overall_misses::total 366 # number of overall misses 255system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles 256system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles 257system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles 258system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles 259system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles 260system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles 261system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) 262system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) 263system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses 264system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses 265system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses 266system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses 267system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses 268system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses 269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses 270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency 271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 273system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked	177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 179system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 180system.cpu0.dcache.writebacks::total 6 # number of writebacks 181system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses 182system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 183system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 184system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 185system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 186system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 187system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses 188system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses 189system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses 190system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses 191system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles 192system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles 193system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles 194system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles 195system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles 196system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles 197system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles 198system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles 199system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles 200system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles 201system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses 202system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses 203system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 204system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses 205system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses 206system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency 207system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency 208system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency 209system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency 210system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency 211system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 212system.cpu1.numCycles 524596 # number of cpu cycles simulated 213system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 214system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 215system.cpu1.committedInsts 172325 # Number of instructions committed 216system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed 217system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses 218system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 219system.cpu1.num_func_calls 637 # number of times a function call or return occured 220system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls 221system.cpu1.num_int_insts 107932 # number of integer instructions 222system.cpu1.num_fp_insts 0 # number of float instructions 223system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read 224system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written 225system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 226system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 227system.cpu1.num_mem_refs 47898 # number of memory refs 228system.cpu1.num_load_insts 39616 # Number of load instructions 229system.cpu1.num_store_insts 8282 # Number of store instructions 230system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles 231system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles 232system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles 233system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles 234system.cpu1.icache.replacements 280 # number of replacements 235system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use 236system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. 237system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. 238system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. 239system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 240system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor 241system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy 242system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy 243system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits 244system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits 245system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits 246system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits 247system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits 248system.cpu1.icache.overall_hits::total 171992 # number of overall hits 249system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 250system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 251system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 252system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 253system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 254system.cpu1.icache.overall_misses::total 366 # number of overall misses 255system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles 256system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles 257system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles 258system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles 259system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles 260system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles 261system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) 262system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) 263system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses 264system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses 265system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses 266system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses 267system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses 268system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses 269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses 270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency 271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency 273system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
277system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 278system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	277system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279system.cpu1.icache.fast_writes 0 # number of fast writes performed 280system.cpu1.icache.cache_copies 0 # number of cache copies performed 281system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 282system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 283system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 284system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 285system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 286system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 287system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles 288system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles 289system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles 290system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles 291system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles 292system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles 293system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses 294system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses 295system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses 296system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency 297system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency 298system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency 299system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 300system.cpu1.dcache.replacements 2 # number of replacements 301system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use 302system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. 303system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. 304system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. 305system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 306system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor 307system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy 308system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy 309system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits 310system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits 311system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits 312system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits 313system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits 314system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits 315system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits 316system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits 317system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits 318system.cpu1.dcache.overall_hits::total 47527 # number of overall hits 319system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses 320system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses 321system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses 322system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses 323system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses 324system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses 325system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses 326system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses 327system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses 328system.cpu1.dcache.overall_misses::total 279 # number of overall misses 329system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles 330system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles 331system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles 332system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles 333system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles 334system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles 335system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles 336system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles 337system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles 338system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles 339system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) 340system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) 341system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) 342system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) 343system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) 344system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) 345system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses 346system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses 347system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses 348system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses 349system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses 350system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses 351system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses 352system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses 353system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses 354system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency 355system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency 356system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency 357system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 358system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked	279system.cpu1.icache.fast_writes 0 # number of fast writes performed 280system.cpu1.icache.cache_copies 0 # number of cache copies performed 281system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 282system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 283system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 284system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 285system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 286system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 287system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles 288system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles 289system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles 290system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles 291system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles 292system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles 293system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses 294system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses 295system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses 296system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency 297system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency 298system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency 299system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 300system.cpu1.dcache.replacements 2 # number of replacements 301system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use 302system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. 303system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. 304system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. 305system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 306system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor 307system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy 308system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy 309system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits 310system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits 311system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits 312system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits 313system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits 314system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits 315system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits 316system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits 317system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits 318system.cpu1.dcache.overall_hits::total 47527 # number of overall hits 319system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses 320system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses 321system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses 322system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses 323system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses 324system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses 325system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses 326system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses 327system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses 328system.cpu1.dcache.overall_misses::total 279 # number of overall misses 329system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles 330system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles 331system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles 332system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles 333system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles 334system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles 335system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles 336system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles 337system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles 338system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles 339system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) 340system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) 341system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) 342system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) 343system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) 344system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) 345system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses 346system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses 347system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses 348system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses 349system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses 350system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses 351system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses 352system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses 353system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses 354system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency 355system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency 356system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency 357system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 358system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
363system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 364system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	363system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
365system.cpu1.dcache.fast_writes 0 # number of fast writes performed 366system.cpu1.dcache.cache_copies 0 # number of cache copies performed 367system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 368system.cpu1.dcache.writebacks::total 1 # number of writebacks 369system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses 370system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses 371system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses 372system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses 373system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses 374system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses 375system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses 376system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 377system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses 378system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses 379system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles 380system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles 381system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles 382system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles 383system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles 384system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles 385system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles 386system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles 387system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles 388system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles 389system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses 390system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses 391system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses 392system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses 393system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses 394system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency 395system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency 396system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency 397system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency 398system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency 399system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu2.numCycles 524596 # number of cpu cycles simulated 401system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu2.committedInsts 165499 # Number of instructions committed 404system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed 405system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses 406system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 407system.cpu2.num_func_calls 637 # number of times a function call or return occured 408system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls 409system.cpu2.num_int_insts 112355 # number of integer instructions 410system.cpu2.num_fp_insts 0 # number of float instructions 411system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read 412system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written 413system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 414system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 415system.cpu2.num_mem_refs 57941 # number of memory refs 416system.cpu2.num_load_insts 41852 # Number of load instructions 417system.cpu2.num_store_insts 16089 # Number of store instructions 418system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles 419system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles 420system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles 421system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles 422system.cpu2.icache.replacements 280 # number of replacements 423system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use 424system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. 425system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. 426system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. 427system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 428system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor 429system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy 430system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy 431system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits 432system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits 433system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits 434system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits 435system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits 436system.cpu2.icache.overall_hits::total 165166 # number of overall hits 437system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 438system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 439system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 440system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 441system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 442system.cpu2.icache.overall_misses::total 366 # number of overall misses 443system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles 444system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles 445system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles 446system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles 447system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles 448system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles 449system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) 450system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) 451system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses 452system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses 453system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses 454system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses 455system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses 456system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses 457system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses 458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency 459system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 460system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 461system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked	365system.cpu1.dcache.fast_writes 0 # number of fast writes performed 366system.cpu1.dcache.cache_copies 0 # number of cache copies performed 367system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 368system.cpu1.dcache.writebacks::total 1 # number of writebacks 369system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses 370system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses 371system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses 372system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses 373system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses 374system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses 375system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses 376system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 377system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses 378system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses 379system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles 380system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles 381system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles 382system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles 383system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles 384system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles 385system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles 386system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles 387system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles 388system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles 389system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses 390system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses 391system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses 392system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses 393system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses 394system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency 395system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency 396system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency 397system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency 398system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency 399system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu2.numCycles 524596 # number of cpu cycles simulated 401system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 402system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 403system.cpu2.committedInsts 165499 # Number of instructions committed 404system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed 405system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses 406system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 407system.cpu2.num_func_calls 637 # number of times a function call or return occured 408system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls 409system.cpu2.num_int_insts 112355 # number of integer instructions 410system.cpu2.num_fp_insts 0 # number of float instructions 411system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read 412system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written 413system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 414system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 415system.cpu2.num_mem_refs 57941 # number of memory refs 416system.cpu2.num_load_insts 41852 # Number of load instructions 417system.cpu2.num_store_insts 16089 # Number of store instructions 418system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles 419system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles 420system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles 421system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles 422system.cpu2.icache.replacements 280 # number of replacements 423system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use 424system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. 425system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. 426system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. 427system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 428system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor 429system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy 430system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy 431system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits 432system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits 433system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits 434system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits 435system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits 436system.cpu2.icache.overall_hits::total 165166 # number of overall hits 437system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 438system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 439system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 440system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 441system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 442system.cpu2.icache.overall_misses::total 366 # number of overall misses 443system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles 444system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles 445system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles 446system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles 447system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles 448system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles 449system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) 450system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) 451system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses 452system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses 453system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses 454system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses 455system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses 456system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses 457system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses 458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency 459system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 460system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency 461system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
465system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 466system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	465system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
467system.cpu2.icache.fast_writes 0 # number of fast writes performed 468system.cpu2.icache.cache_copies 0 # number of cache copies performed 469system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 470system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 471system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 472system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 473system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 474system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 475system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles 476system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles 477system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles 478system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles 479system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles 480system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles 481system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses 482system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses 483system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses 484system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency 485system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 486system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 487system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu2.dcache.replacements 2 # number of replacements 489system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use 490system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. 491system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. 492system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. 493system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor 495system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy 496system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy 497system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits 498system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits 499system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits 500system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits 501system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 502system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 503system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits 504system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits 505system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits 506system.cpu2.dcache.overall_hits::total 57604 # number of overall hits 507system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses 508system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses 509system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 510system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 511system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses 512system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses 513system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses 514system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses 515system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses 516system.cpu2.dcache.overall_misses::total 265 # number of overall misses 517system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles 518system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles 519system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles 520system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles 521system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles 522system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles 523system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles 524system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles 525system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles 526system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles 527system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) 528system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) 529system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) 530system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) 531system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 532system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 533system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses 534system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses 535system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses 536system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses 537system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses 538system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses 539system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses 540system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses 541system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses 542system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency 543system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency 544system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency 545system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency 546system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency 547system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked	467system.cpu2.icache.fast_writes 0 # number of fast writes performed 468system.cpu2.icache.cache_copies 0 # number of cache copies performed 469system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 470system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 471system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 472system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 473system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 474system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 475system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles 476system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles 477system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles 478system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles 479system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles 480system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles 481system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses 482system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses 483system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses 484system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency 485system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 486system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency 487system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu2.dcache.replacements 2 # number of replacements 489system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use 490system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. 491system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. 492system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. 493system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor 495system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy 496system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy 497system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits 498system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits 499system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits 500system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits 501system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 502system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 503system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits 504system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits 505system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits 506system.cpu2.dcache.overall_hits::total 57604 # number of overall hits 507system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses 508system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses 509system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 510system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 511system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses 512system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses 513system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses 514system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses 515system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses 516system.cpu2.dcache.overall_misses::total 265 # number of overall misses 517system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles 518system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles 519system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles 520system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles 521system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles 522system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles 523system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles 524system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles 525system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles 526system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles 527system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) 528system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) 529system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) 530system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) 531system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) 532system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 533system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses 534system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses 535system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses 536system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses 537system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses 538system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses 539system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses 540system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses 541system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses 542system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency 543system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency 544system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency 545system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency 546system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency 547system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
551system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 552system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	551system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
553system.cpu2.dcache.fast_writes 0 # number of fast writes performed 554system.cpu2.dcache.cache_copies 0 # number of cache copies performed 555system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 556system.cpu2.dcache.writebacks::total 1 # number of writebacks 557system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses 558system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses 559system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 560system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 561system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses 562system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 563system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses 564system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 565system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses 566system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 567system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles 568system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles 569system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles 570system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles 571system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles 572system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 573system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles 574system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles 575system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles 576system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles 577system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses 578system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses 579system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses 580system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses 581system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses 582system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency 583system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency 584system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency 585system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency 586system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency 587system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu3.numCycles 524596 # number of cpu cycles simulated 589system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 590system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 591system.cpu3.committedInsts 166130 # Number of instructions committed 592system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed 593system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses 594system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 595system.cpu3.num_func_calls 637 # number of times a function call or return occured 596system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls 597system.cpu3.num_int_insts 112098 # number of integer instructions 598system.cpu3.num_fp_insts 0 # number of float instructions 599system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read 600system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written 601system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 602system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 603system.cpu3.num_mem_refs 57243 # number of memory refs 604system.cpu3.num_load_insts 41720 # Number of load instructions 605system.cpu3.num_store_insts 15523 # Number of store instructions 606system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles 607system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles 608system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles 609system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles 610system.cpu3.icache.replacements 281 # number of replacements 611system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use 612system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. 613system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. 614system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. 615system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 616system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor 617system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy 618system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy 619system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits 620system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits 621system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits 622system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits 623system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits 624system.cpu3.icache.overall_hits::total 165796 # number of overall hits 625system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 626system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 627system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 628system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 629system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 630system.cpu3.icache.overall_misses::total 367 # number of overall misses 631system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles 632system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles 633system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles 634system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles 635system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles 636system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles 637system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) 638system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) 639system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses 640system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses 641system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses 642system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses 643system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses 644system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses 645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses 646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency 647system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 648system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 649system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked	553system.cpu2.dcache.fast_writes 0 # number of fast writes performed 554system.cpu2.dcache.cache_copies 0 # number of cache copies performed 555system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 556system.cpu2.dcache.writebacks::total 1 # number of writebacks 557system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses 558system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses 559system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 560system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 561system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses 562system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 563system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses 564system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 565system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses 566system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 567system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles 568system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles 569system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles 570system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles 571system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles 572system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles 573system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles 574system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles 575system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles 576system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles 577system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses 578system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses 579system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses 580system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses 581system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses 582system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency 583system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency 584system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency 585system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency 586system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency 587system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu3.numCycles 524596 # number of cpu cycles simulated 589system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 590system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 591system.cpu3.committedInsts 166130 # Number of instructions committed 592system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed 593system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses 594system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 595system.cpu3.num_func_calls 637 # number of times a function call or return occured 596system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls 597system.cpu3.num_int_insts 112098 # number of integer instructions 598system.cpu3.num_fp_insts 0 # number of float instructions 599system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read 600system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written 601system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 602system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 603system.cpu3.num_mem_refs 57243 # number of memory refs 604system.cpu3.num_load_insts 41720 # Number of load instructions 605system.cpu3.num_store_insts 15523 # Number of store instructions 606system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles 607system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles 608system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles 609system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles 610system.cpu3.icache.replacements 281 # number of replacements 611system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use 612system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. 613system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. 614system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. 615system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 616system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor 617system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy 618system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy 619system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits 620system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits 621system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits 622system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits 623system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits 624system.cpu3.icache.overall_hits::total 165796 # number of overall hits 625system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 626system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 627system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 628system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 629system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 630system.cpu3.icache.overall_misses::total 367 # number of overall misses 631system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles 632system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles 633system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles 634system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles 635system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles 636system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles 637system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) 638system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) 639system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses 640system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses 641system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses 642system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses 643system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses 644system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses 645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses 646system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency 647system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 648system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency 649system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
653system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 654system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	653system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
655system.cpu3.icache.fast_writes 0 # number of fast writes performed 656system.cpu3.icache.cache_copies 0 # number of cache copies performed 657system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 658system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 659system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 660system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 661system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 662system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 663system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles 664system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles 665system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles 666system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles 667system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles 668system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles 669system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses 670system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses 671system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses 672system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency 673system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency 674system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency 675system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu3.dcache.replacements 2 # number of replacements 677system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use 678system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. 679system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. 680system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. 681system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 682system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor 683system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy 684system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy 685system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits 686system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits 687system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits 688system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits 689system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 690system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 691system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits 692system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits 693system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits 694system.cpu3.dcache.overall_hits::total 56903 # number of overall hits 695system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 696system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 697system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses 698system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses 699system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 700system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 701system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses 702system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses 703system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses 704system.cpu3.dcache.overall_misses::total 265 # number of overall misses 705system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles 706system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles 707system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles 708system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles 709system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles 710system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles 711system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles 712system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles 713system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles 714system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles 715system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) 716system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) 717system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) 718system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) 719system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) 720system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 721system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses 722system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses 723system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses 724system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses 725system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses 726system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses 727system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses 728system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses 729system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses 730system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency 731system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency 732system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency 733system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 734system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 735system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked	655system.cpu3.icache.fast_writes 0 # number of fast writes performed 656system.cpu3.icache.cache_copies 0 # number of cache copies performed 657system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 658system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 659system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 660system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 661system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 662system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 663system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles 664system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles 665system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles 666system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles 667system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles 668system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles 669system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses 670system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses 671system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses 672system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency 673system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency 674system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency 675system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu3.dcache.replacements 2 # number of replacements 677system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use 678system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. 679system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. 680system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. 681system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 682system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor 683system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy 684system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy 685system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits 686system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits 687system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits 688system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits 689system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 690system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 691system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits 692system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits 693system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits 694system.cpu3.dcache.overall_hits::total 56903 # number of overall hits 695system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 696system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 697system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses 698system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses 699system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 700system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 701system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses 702system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses 703system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses 704system.cpu3.dcache.overall_misses::total 265 # number of overall misses 705system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles 706system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles 707system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles 708system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles 709system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles 710system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles 711system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles 712system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles 713system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles 714system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles 715system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) 716system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) 717system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) 718system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) 719system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) 720system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 721system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses 722system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses 723system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses 724system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses 725system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses 726system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses 727system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses 728system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses 729system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses 730system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency 731system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency 732system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency 733system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 734system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency 735system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
739system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 740system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	739system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741system.cpu3.dcache.fast_writes 0 # number of fast writes performed 742system.cpu3.dcache.cache_copies 0 # number of cache copies performed 743system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 744system.cpu3.dcache.writebacks::total 1 # number of writebacks 745system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses 746system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 747system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses 748system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 749system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 750system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 751system.cpu3.dcache.demand_mshr_misses::cpu3.data 265 # number of demand (read+write) MSHR misses 752system.cpu3.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 753system.cpu3.dcache.overall_mshr_misses::cpu3.data 265 # number of overall MSHR misses 754system.cpu3.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 755system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2098000 # number of ReadReq MSHR miss cycles 756system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles 757system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1756000 # number of WriteReq MSHR miss cycles 758system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles 759system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles 760system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles 761system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles 762system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles 763system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles 764system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles 765system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses 766system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses 767system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses 768system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses 769system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses 770system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency 771system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency 772system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency 773system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency 774system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency 775system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.l2c.replacements 0 # number of replacements 777system.l2c.tagsinuse 353.886259 # Cycle average of tags in use 778system.l2c.total_refs 1223 # Total number of references to valid blocks. 779system.l2c.sampled_refs 434 # Sample count of references to valid blocks. 780system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. 781system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 782system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor 783system.l2c.occ_blocks::cpu0.inst 231.859183 # Average occupied blocks per requestor 784system.l2c.occ_blocks::cpu0.data 54.220360 # Average occupied blocks per requestor 785system.l2c.occ_blocks::cpu1.inst 51.601293 # Average occupied blocks per requestor 786system.l2c.occ_blocks::cpu1.data 6.129067 # Average occupied blocks per requestor 787system.l2c.occ_blocks::cpu2.inst 1.914986 # Average occupied blocks per requestor 788system.l2c.occ_blocks::cpu2.data 0.831600 # Average occupied blocks per requestor 789system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor 790system.l2c.occ_blocks::cpu3.data 0.844646 # Average occupied blocks per requestor 791system.l2c.occ_percent::writebacks 0.000085 # Average percentage of cache occupancy 792system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy 793system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 794system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 795system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy 796system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 797system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 798system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy 799system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 800system.l2c.occ_percent::total 0.005400 # Average percentage of cache occupancy 801system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 802system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 803system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 804system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits 805system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 806system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits 807system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 808system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 809system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits 810system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits 811system.l2c.Writeback_hits::total 9 # number of Writeback hits 812system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 813system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 814system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 815system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 816system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 817system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 818system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits 819system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 820system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 821system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 822system.l2c.demand_hits::total 1226 # number of demand (read+write) hits 823system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 824system.l2c.overall_hits::cpu0.data 5 # number of overall hits 825system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 826system.l2c.overall_hits::cpu1.data 5 # number of overall hits 827system.l2c.overall_hits::cpu2.inst 354 # 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number of demand (read+write) miss cycles 894system.l2c.demand_miss_latency::cpu3.data 827000 # number of demand (read+write) miss cycles 895system.l2c.demand_miss_latency::total 30715000 # number of demand (read+write) miss cycles 896system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles 897system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles 898system.l2c.overall_miss_latency::cpu1.inst 3416000 # number of overall miss cycles 899system.l2c.overall_miss_latency::cpu1.data 1194000 # number of overall miss cycles 900system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles 901system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles 902system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles 903system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles 904system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles 905system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 906system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 907system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 908system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) 909system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 910system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) 911system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 912system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) 913system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) 914system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) 915system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) 916system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 917system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) 918system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 919system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) 920system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) 921system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 922system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 923system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 924system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 925system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 926system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 927system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 928system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 929system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses 930system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 931system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses 932system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 933system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses 934system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses 935system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 936system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 937system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 938system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses 939system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 940system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses 941system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 942system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses 943system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses 944system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 945system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 946system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 947system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses 948system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 949system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses 950system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 951system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses 952system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 953system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 954system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 955system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 956system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 957system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 958system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 959system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 960system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 961system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 962system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 963system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses 964system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 965system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses 966system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 967system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses 968system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 969system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 970system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 971system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses 972system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 973system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses 974system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 975system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses 976system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency 977system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency 978system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency 979system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency 980system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency 981system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency 982system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency 983system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency 984system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency 985system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency 986system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency 987system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 988system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency 989system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 990system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency 991system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 992system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency 993system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 994system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 995system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 996system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency 997system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 998system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency 999system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency 1000system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency 1001system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency 1002system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency 1003system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1004system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1005system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1006system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency 1007system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.l2c.blocked::no_targets 0 # number of cycles access was blocked	741system.cpu3.dcache.fast_writes 0 # number of fast writes performed 742system.cpu3.dcache.cache_copies 0 # number of cache copies performed 743system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 744system.cpu3.dcache.writebacks::total 1 # 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mshr miss rate for WriteReq accesses 767system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses 768system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses 769system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses 770system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency 771system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency 772system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency 773system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency 774system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency 775system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.l2c.replacements 0 # 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number of ReadReq accesses(hits+misses) 908system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) 909system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 910system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) 911system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 912system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) 913system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) 914system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) 915system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) 916system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 917system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) 918system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 919system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) 920system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) 921system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 922system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 923system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 924system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 925system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 926system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 927system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 928system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 929system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses 930system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 931system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses 932system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 933system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses 934system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses 935system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 936system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 937system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 938system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses 939system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 940system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses 941system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 942system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses 943system.l2c.overall_accesses::total 1818 # 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miss rate for overall accesses 969system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 970system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 971system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses 972system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 973system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses 974system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 975system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses 976system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency 977system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency 978system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency 979system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency 980system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency 981system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency 982system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency 983system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency 984system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency 985system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency 986system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency 987system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency 988system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency 989system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency 990system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency 991system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # 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average overall miss latency 1003system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency 1004system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency 1005system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency 1006system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency 1007system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1008system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1009system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1010system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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1013system.l2c.fast_writes 0 # number of fast writes performed 1014system.l2c.cache_copies 0 # number of cache copies performed 1015system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1016system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 1017system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits 1018system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits 1019system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits 1020system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 1021system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 1022system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 1023system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits 1024system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits 1025system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 1026system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 1027system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 1028system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 1029system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits 1030system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits 1031system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 1032system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1033system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses 1034system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses 1035system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses 1036system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses 1037system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses 1038system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses 1039system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses 1040system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 1041system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1042system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses 1043system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses 1044system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 1045system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses 1046system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses 1047system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1048system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses 1049system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses 1050system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1051system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1052system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 1053system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses 1054system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses 1055system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses 1056system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses 1057system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses 1058system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses 1059system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses 1060system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 1061system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 1062system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 1063system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses 1064system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses 1065system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses 1066system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses 1067system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1068system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 1069system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 1070system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11402000 # number of ReadReq MSHR miss cycles 1071system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles 1072system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2360000 # number of ReadReq MSHR miss cycles 1073system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles 1074system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 361000 # number of ReadReq MSHR miss cycles 1075system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles 1076system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles 1077system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles 1078system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles 1079system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 1080system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles 1081system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles 1082system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles 1083system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles 1084system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles 1085system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles 1086system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles 1087system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles 1088system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles 1089system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles 1090system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles 1091system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles 1092system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles 1093system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles 1094system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles 1095system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles 1096system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles 1097system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles 1098system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles 1099system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles 1100system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles 1101system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles 1102system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles 1103system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles 1104system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles 1105system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles 1106system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles 1107system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1108system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1109system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1110system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses 1111system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses 1112system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses 1113system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1114system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses 1115system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1116system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1117system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1118system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 1119system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1120system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1121system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1122system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1123system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1124system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1125system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1126system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses 1127system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses 1128system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses 1129system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1130system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses 1131system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1132system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1133system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1134system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses 1135system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses 1136system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses 1137system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1138system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses 1139system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency 1140system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1141system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1142system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 1143system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency 1144system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1145system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1146system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 1147system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1148system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1149system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1150system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency 1151system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1152system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency 1153system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1154system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 1155system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1156system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1157system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1158system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1159system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1160system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1161system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1162system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 1163system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1164system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1165system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1166system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1167system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1168system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1169system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1170system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 1171system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1172 1173---------- End Simulation Statistics ----------	1013system.l2c.fast_writes 0 # number of fast writes performed 1014system.l2c.cache_copies 0 # number of cache copies performed 1015system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1016system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 1017system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits 1018system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits 1019system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits 1020system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 1021system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 1022system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 1023system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits 1024system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits 1025system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 1026system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 1027system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 1028system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 1029system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits 1030system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits 1031system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 1032system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 1033system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses 1034system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses 1035system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses 1036system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses 1037system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses 1038system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses 1039system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses 1040system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 1041system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1042system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses 1043system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses 1044system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 1045system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses 1046system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses 1047system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1048system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses 1049system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses 1050system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1051system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1052system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 1053system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses 1054system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses 1055system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses 1056system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses 1057system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses 1058system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses 1059system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses 1060system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 1061system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 1062system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 1063system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses 1064system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses 1065system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses 1066system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses 1067system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1068system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 1069system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 1070system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11402000 # number of ReadReq MSHR miss cycles 1071system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles 1072system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2360000 # number of ReadReq MSHR miss cycles 1073system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles 1074system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 361000 # number of ReadReq MSHR miss cycles 1075system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles 1076system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles 1077system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles 1078system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles 1079system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 1080system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles 1081system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles 1082system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles 1083system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles 1084system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles 1085system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles 1086system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles 1087system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles 1088system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles 1089system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles 1090system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles 1091system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles 1092system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles 1093system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles 1094system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles 1095system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles 1096system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles 1097system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles 1098system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles 1099system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles 1100system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles 1101system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles 1102system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles 1103system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles 1104system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles 1105system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles 1106system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles 1107system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 1108system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 1109system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 1110system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses 1111system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses 1112system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses 1113system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses 1114system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses 1115system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1116system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1117system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1118system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 1119system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1120system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1121system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1122system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1123system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1124system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1125system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 1126system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses 1127system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses 1128system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses 1129system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1130system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses 1131system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1132system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1133system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 1134system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses 1135system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses 1136system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses 1137system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1138system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses 1139system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency 1140system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 1141system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 1142system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 1143system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency 1144system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 1145system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 1146system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 1147system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 1148system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency 1149system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 1150system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency 1151system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency 1152system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency 1153system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency 1154system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 1155system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1156system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1157system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1158system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1159system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1160system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1161system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1162system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 1163system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency 1164system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency 1165system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 1166system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency 1167system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency 1168system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency 1169system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 1170system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 1171system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1172 1173---------- End Simulation Statistics ----------