Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

stats.txt (11687:b3d5f0e9e258)	stats.txt (11754:c209cb86278a)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 263409500 # Number of ticks simulated 5final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 263409500 # Number of ticks simulated 5final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 919692 # Simulator instruction rate (inst/s) 8host_op_rate 919679 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 364903746 # Simulator tick rate (ticks/s) 10host_mem_usage 263368 # Number of bytes of host memory used 11host_seconds 0.72 # Real time elapsed on the host	7host_inst_rate 870162 # Simulator instruction rate (inst/s) 8host_op_rate 870149 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 345251596 # Simulator tick rate (ticks/s) 10host_mem_usage 264052 # Number of bytes of host memory used 11host_seconds 0.76 # Real time elapsed on the host
12sim_insts 663871 # Number of instructions simulated 13sim_ops 663871 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 25system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 31system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 40system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) 63system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls 66system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 67system.cpu0.numCycles 526819 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 158244 # Number of instructions committed 71system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured 75system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls 76system.cpu0.num_int_insts 108988 # number of integer instructions 77system.cpu0.num_fp_insts 0 # number of float instructions 78system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read 79system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written 80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 73856 # number of memory refs 83system.cpu0.num_load_insts 48897 # Number of load instructions 84system.cpu0.num_store_insts 24959 # Number of store instructions 85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 86system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles 87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 89system.cpu0.Branches 26842 # Number of branches fetched 90system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction 91system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction 92system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 93system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 94system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 95system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 96system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 97system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 98system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction 99system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 100system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction 101system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 102system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 103system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 104system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 105system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 106system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 107system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 108system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 109system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 110system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 111system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 112system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 113system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 114system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 119system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 122system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction 123system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction 124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 128system.cpu0.op_class::total 158306 # Class of executed instruction 129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 130system.cpu0.dcache.tags.replacements 2 # number of replacements 131system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use 132system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. 133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 134system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. 135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor 137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy 138system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy 139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 141system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 143system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses 144system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses 145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 146system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits 147system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits 148system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits 149system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits 150system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 151system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 152system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits 153system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits 154system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits 155system.cpu0.dcache.overall_hits::total 73442 # number of overall hits 156system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 157system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 158system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 159system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 160system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 161system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 162system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 163system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 164system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 165system.cpu0.dcache.overall_misses::total 353 # number of overall misses 166system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles 167system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles 168system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles 169system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles 170system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles 171system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles 172system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles 173system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles 174system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles 175system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles 176system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) 177system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) 178system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) 179system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) 180system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 181system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 182system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses 183system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses 184system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses 185system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses 186system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses 187system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses 188system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses 189system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses 190system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 191system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 192system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses 193system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses 194system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses 195system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses 196system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency 197system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency 198system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency 199system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency 200system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency 201system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency 202system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 203system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency 204system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 205system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency 206system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 209system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 210system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 211system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 212system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 213system.cpu0.dcache.writebacks::total 1 # number of writebacks 214system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 215system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 216system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 217system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 218system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 219system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 220system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 221system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 222system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 223system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 224system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles 225system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles 226system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles 227system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles 228system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles 229system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles 230system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles 231system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles 232system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles 233system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles 234system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses 235system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses 236system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses 237system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses 238system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 239system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 240system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses 241system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses 242system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses 243system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses 244system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency 245system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency 246system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency 247system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency 248system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 249system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 250system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 251system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 252system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 253system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 254system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 255system.cpu0.icache.tags.replacements 215 # number of replacements 256system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use 257system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. 258system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 259system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. 260system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 261system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor 262system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy 263system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy 264system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 265system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 266system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 267system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 268system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses 269system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses 270system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 271system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits 272system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits 273system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits 274system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits 275system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits 276system.cpu0.icache.overall_hits::total 157840 # number of overall hits 277system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 278system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 279system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 280system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 281system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 282system.cpu0.icache.overall_misses::total 467 # number of overall misses 283system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles 284system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles 285system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles 286system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles 287system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles 288system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles 289system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) 290system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) 291system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses 292system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses 293system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses 294system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses 295system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 296system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 297system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 298system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 299system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 300system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 301system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency 302system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency 303system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 304system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency 305system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 306system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency 307system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 308system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 309system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 310system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 311system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 312system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 313system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 314system.cpu0.icache.writebacks::total 215 # number of writebacks 315system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 316system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 317system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 318system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 319system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 320system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 321system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles 322system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles 323system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles 324system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles 325system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles 326system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles 327system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 328system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 329system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 330system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 331system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 332system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 333system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency 334system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency 335system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 336system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 337system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 338system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 339system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 340system.cpu1.numCycles 526818 # number of cpu cycles simulated 341system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 343system.cpu1.committedInsts 169340 # Number of instructions committed 344system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed 345system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses 346system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 347system.cpu1.num_func_calls 637 # number of times a function call or return occured 348system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls 349system.cpu1.num_int_insts 111465 # number of integer instructions 350system.cpu1.num_fp_insts 0 # number of float instructions 351system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read 352system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written 353system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 354system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 355system.cpu1.num_mem_refs 54688 # number of memory refs 356system.cpu1.num_load_insts 41399 # Number of load instructions 357system.cpu1.num_store_insts 13289 # Number of store instructions 358system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles 359system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles 360system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles 361system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles 362system.cpu1.Branches 34599 # Number of branches fetched 363system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction 364system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction 365system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction 366system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction 367system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction 368system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction 369system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction 370system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction 371system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction 372system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction 373system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction 374system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction 375system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction 376system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction 377system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction 378system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction 379system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction 380system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction 381system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction 382system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction 383system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction 384system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction 385system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction 386system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction 387system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction 388system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction 389system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction 390system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction 391system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction 392system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 393system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 394system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 395system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction 396system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction 397system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 398system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 399system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 400system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 401system.cpu1.op_class::total 169372 # Class of executed instruction 402system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 403system.cpu1.dcache.tags.replacements 0 # number of replacements 404system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use 405system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. 406system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 407system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. 408system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 409system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor 410system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy 411system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy 412system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 413system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 414system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 415system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 416system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses 417system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses 418system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 419system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits 420system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits 421system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits 422system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits 423system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 424system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 425system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits 426system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits 427system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits 428system.cpu1.dcache.overall_hits::total 54340 # number of overall hits 429system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses 430system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses 431system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 432system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 433system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 434system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 435system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses 436system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses 437system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses 438system.cpu1.dcache.overall_misses::total 269 # number of overall misses 439system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles 440system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles 441system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles 442system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles 443system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles 444system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles 445system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles 446system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles 447system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles 448system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles 449system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) 450system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) 451system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) 452system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) 453system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) 454system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 455system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses 456system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses 457system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses 458system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses 459system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses 460system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses 461system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses 462system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses 463system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses 464system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 465system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses 466system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses 467system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses 468system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses 469system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency 470system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency 471system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency 472system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency 473system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency 474system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency 475system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 476system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency 477system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 478system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency 479system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 480system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 481system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 482system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 483system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 484system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 485system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses 486system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses 487system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 488system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 489system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 490system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 491system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses 492system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 493system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses 494system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 495system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles 496system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles 497system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles 498system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles 499system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles 500system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles 501system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles 502system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles 503system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles 504system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles 505system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses 506system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses 507system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses 508system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses 509system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses 510system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 511system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses 512system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses 513system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses 514system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses 515system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency 516system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency 517system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency 518system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency 519system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency 520system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency 521system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 522system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 523system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 524system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 525system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 526system.cpu1.icache.tags.replacements 280 # number of replacements 527system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use 528system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. 529system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 530system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. 531system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 532system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor 533system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy 534system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy 535system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 536system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 537system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 538system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 539system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 540system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses 541system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses 542system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 543system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits 544system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits 545system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits 546system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits 547system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits 548system.cpu1.icache.overall_hits::total 169007 # number of overall hits 549system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 550system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 551system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 552system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 553system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 554system.cpu1.icache.overall_misses::total 366 # number of overall misses 555system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles 556system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles 557system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles 558system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles 559system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles 560system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles 561system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) 562system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) 563system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses 564system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses 565system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses 566system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses 567system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses 568system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses 569system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses 570system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses 571system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses 572system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses 573system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency 574system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency 575system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 576system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency 577system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 578system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency 579system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 586system.cpu1.icache.writebacks::total 280 # number of writebacks 587system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 588system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 589system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 590system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 591system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 592system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 593system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles 594system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles 595system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles 596system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles 597system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles 598system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles 599system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses 600system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses 601system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses 602system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses 603system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses 604system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses 605system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency 606system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency 607system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 608system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 609system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 610system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 611system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 612system.cpu2.numCycles 526819 # number of cpu cycles simulated 613system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 614system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 615system.cpu2.committedInsts 165892 # Number of instructions committed 616system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed 617system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses 618system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 619system.cpu2.num_func_calls 637 # number of times a function call or return occured 620system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls 621system.cpu2.num_int_insts 110657 # number of integer instructions 622system.cpu2.num_fp_insts 0 # number of float instructions 623system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read 624system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written 625system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 626system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 627system.cpu2.num_mem_refs 55200 # number of memory refs 628system.cpu2.num_load_insts 40995 # Number of load instructions 629system.cpu2.num_store_insts 14205 # Number of store instructions 630system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles 631system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles 632system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles 633system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles 634system.cpu2.Branches 33279 # Number of branches fetched 635system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction 636system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction 637system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction 638system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction 639system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction 640system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction 641system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction 642system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction 643system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction 644system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction 645system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction 646system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction 647system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction 648system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction 649system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction 650system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction 651system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction 652system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction 653system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction 654system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction 655system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction 656system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction 657system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction 658system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction 659system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction 660system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction 661system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction 662system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction 663system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction 664system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction 665system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction 666system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction 667system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction 668system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction 669system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 670system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 671system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 672system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 673system.cpu2.op_class::total 165924 # Class of executed instruction 674system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 675system.cpu2.dcache.tags.replacements 0 # number of replacements 676system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use 677system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. 678system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 679system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. 680system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor 682system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy 683system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy 684system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 685system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 686system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 687system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 688system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses 689system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses 690system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 691system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits 692system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits 693system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits 694system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits 695system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 696system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 697system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits 698system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits 699system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits 700system.cpu2.dcache.overall_hits::total 54855 # number of overall hits 701system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses 702system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses 703system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 704system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 705system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses 706system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses 707system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses 708system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses 709system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses 710system.cpu2.dcache.overall_misses::total 267 # number of overall misses 711system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles 712system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles 713system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles 714system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles 715system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles 716system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles 717system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles 718system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles 719system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles 720system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles 721system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) 722system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) 723system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) 724system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) 725system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 726system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 727system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses 728system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses 729system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses 730system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses 731system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses 732system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses 733system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses 734system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses 735system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses 736system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 737system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses 738system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses 739system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses 740system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses 741system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency 742system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency 743system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency 744system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency 745system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency 746system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency 747system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 748system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency 749system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 750system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency 751system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 758system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 759system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 760system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 761system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses 762system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 763system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 764system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 765system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 766system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 767system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles 768system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles 769system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles 770system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles 771system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles 772system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles 773system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles 774system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles 775system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles 776system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles 777system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses 778system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses 779system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses 780system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses 781system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses 782system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 783system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses 784system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses 785system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses 786system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses 787system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency 788system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency 789system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency 790system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency 791system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency 792system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency 793system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 794system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 795system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 796system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 797system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 798system.cpu2.icache.tags.replacements 280 # number of replacements 799system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use 800system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. 801system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 802system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. 803system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 804system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor 805system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy 806system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy 807system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 808system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 809system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 810system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 811system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 812system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses 813system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses 814system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 815system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits 816system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits 817system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits 818system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits 819system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits 820system.cpu2.icache.overall_hits::total 165559 # number of overall hits 821system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 822system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 823system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 824system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 825system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 826system.cpu2.icache.overall_misses::total 366 # number of overall misses 827system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles 828system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles 829system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles 830system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles 831system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles 832system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles 833system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) 834system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) 835system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses 836system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses 837system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses 838system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses 839system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses 840system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses 841system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses 842system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses 843system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses 844system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses 845system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency 846system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency 847system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 848system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency 849system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 850system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency 851system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 852system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 853system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 854system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 855system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 856system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 857system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 858system.cpu2.icache.writebacks::total 280 # number of writebacks 859system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 860system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 861system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 862system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 863system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 864system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 865system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles 866system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles 867system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles 868system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles 869system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles 870system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles 871system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses 872system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses 873system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses 874system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses 875system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses 876system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses 877system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency 878system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency 879system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 880system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 881system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 882system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 883system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 884system.cpu3.numCycles 526818 # number of cpu cycles simulated 885system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 886system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 887system.cpu3.committedInsts 170395 # Number of instructions committed 888system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed 889system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses 890system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 891system.cpu3.num_func_calls 637 # number of times a function call or return occured 892system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls 893system.cpu3.num_int_insts 111057 # number of integer instructions 894system.cpu3.num_fp_insts 0 # number of float instructions 895system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read 896system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written 897system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 898system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 899system.cpu3.num_mem_refs 53550 # number of memory refs 900system.cpu3.num_load_insts 41191 # Number of load instructions 901system.cpu3.num_store_insts 12359 # Number of store instructions 902system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles 903system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles 904system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles 905system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles 906system.cpu3.Branches 35332 # Number of branches fetched 907system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction 908system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction 909system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction 910system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction 911system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction 912system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction 913system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction 914system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction 915system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction 916system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction 917system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction 918system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction 919system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction 920system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction 921system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction 922system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction 923system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction 924system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction 925system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction 926system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction 927system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction 928system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction 929system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction 930system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction 931system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction 932system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction 933system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction 934system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction 935system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction 936system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction 937system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction 938system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction 939system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction 940system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction 941system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 942system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 943system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 944system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 945system.cpu3.op_class::total 170427 # Class of executed instruction 946system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 947system.cpu3.dcache.tags.replacements 0 # number of replacements 948system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use 949system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. 950system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 951system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. 952system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 953system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor 954system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy 955system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy 956system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 957system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 958system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 959system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 960system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses 961system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses 962system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 963system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits 964system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits 965system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits 966system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits 967system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 968system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 969system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits 970system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits 971system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits 972system.cpu3.dcache.overall_hits::total 53200 # number of overall hits 973system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses 974system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses 975system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 976system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 977system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 978system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses 979system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 980system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 981system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 982system.cpu3.dcache.overall_misses::total 268 # number of overall misses 983system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles 984system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles 985system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles 986system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles 987system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles 988system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles 989system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles 990system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles 991system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles 992system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles 993system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) 994system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) 995system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) 996system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) 997system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 998system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 999system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses 1000system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses 1001system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses 1002system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses 1003system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses 1004system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses 1005system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses 1006system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses 1007system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses 1008system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses 1009system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses 1010system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses 1011system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses 1012system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses 1013system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency 1014system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency 1015system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency 1016system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency 1017system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency 1018system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency 1019system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 1020system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency 1021system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 1022system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency 1023system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1024system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1025system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1026system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1027system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1028system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1029system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 1030system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 1031system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1032system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1033system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 1034system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 1035system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 1036system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1037system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 1038system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1039system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles 1040system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles 1041system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles 1042system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles 1043system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles 1044system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles 1045system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles 1046system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles 1047system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles 1048system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles 1049system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses 1050system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses 1051system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses 1052system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses 1053system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses 1054system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses 1055system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses 1056system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses 1057system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses 1058system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses 1059system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency 1060system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency 1061system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency 1062system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency 1063system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency 1064system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency 1065system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 1066system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 1067system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 1068system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 1069system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1070system.cpu3.icache.tags.replacements 281 # number of replacements 1071system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use 1072system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. 1073system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1074system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. 1075system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1076system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor 1077system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy 1078system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy 1079system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1080system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 1081system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1082system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1083system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1084system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses 1085system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses 1086system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1087system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits 1088system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits 1089system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits 1090system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits 1091system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits 1092system.cpu3.icache.overall_hits::total 170061 # number of overall hits 1093system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1094system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1095system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1096system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1097system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1098system.cpu3.icache.overall_misses::total 367 # number of overall misses 1099system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles 1100system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles 1101system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles 1102system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles 1103system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles 1104system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles 1105system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) 1106system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) 1107system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses 1108system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses 1109system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses 1110system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses 1111system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses 1112system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 1113system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses 1114system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 1115system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses 1116system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 1117system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency 1118system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency 1119system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 1120system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency 1121system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 1122system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency 1123system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1124system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1125system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1126system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1127system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1128system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1129system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1130system.cpu3.icache.writebacks::total 281 # number of writebacks 1131system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1132system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1133system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1134system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1135system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1136system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1137system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles 1138system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles 1139system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles 1140system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles 1141system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles 1142system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles 1143system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses 1144system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 1145system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses 1146system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 1147system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses 1148system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 1149system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency 1150system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency 1151system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 1152system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 1153system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 1154system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 1155system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1156system.l2c.tags.replacements 0 # number of replacements 1157system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use 1158system.l2c.tags.total_refs 1794 # Total number of references to valid blocks. 1159system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. 1160system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. 1161system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1162system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor 1163system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor 1164system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor 1165system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor 1166system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor 1167system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor 1168system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor 1169system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor 1170system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy 1171system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy 1172system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy 1173system.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy 1174system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy 1175system.l2c.tags.occ_percent::cpu2.data 0.000265 # Average percentage of cache occupancy 1176system.l2c.tags.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy 1177system.l2c.tags.occ_percent::cpu3.data 0.000161 # Average percentage of cache occupancy 1178system.l2c.tags.occ_percent::total 0.007182 # Average percentage of cache occupancy 1179system.l2c.tags.occ_task_id_blocks::1024 572 # Occupied blocks per task id 1180system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1181system.l2c.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id 1182system.l2c.tags.occ_task_id_percent::1024 0.008728 # Percentage of cache occupancy per task id 1183system.l2c.tags.tag_accesses 19676 # Number of tag accesses 1184system.l2c.tags.data_accesses 19676 # Number of data accesses 1185system.l2c.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1186system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1187system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1188system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1189system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1190system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits 1191system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits 1192system.l2c.UpgradeReq_hits::cpu2.data 16 # number of UpgradeReq hits 1193system.l2c.UpgradeReq_hits::cpu3.data 17 # number of UpgradeReq hits 1194system.l2c.UpgradeReq_hits::total 79 # number of UpgradeReq hits 1195system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1196system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1197system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 1198system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 1199system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 1200system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 1201system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 1202system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 1203system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 1204system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 1205system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 1206system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 1207system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 1208system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 1209system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 1210system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 1211system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 1212system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 1213system.l2c.demand_hits::total 1218 # number of demand (read+write) hits 1214system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 1215system.l2c.overall_hits::cpu0.data 5 # number of overall hits 1216system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1217system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1218system.l2c.overall_hits::cpu2.inst 301 # number of overall hits 1219system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1220system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 1221system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1222system.l2c.overall_hits::total 1218 # number of overall hits 1223system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1224system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1225system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1226system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1227system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1228system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1229system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1230system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 1231system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 1232system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 1233system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 1234system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 1235system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 1236system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 1237system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 1238system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1239system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1240system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 1241system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 1242system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 1243system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 1244system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 1245system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 1246system.l2c.demand_misses::total 594 # number of demand (read+write) misses 1247system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1248system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1249system.l2c.overall_misses::cpu1.inst 14 # number of overall misses 1250system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1251system.l2c.overall_misses::cpu2.inst 65 # number of overall misses 1252system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1253system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 1254system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1255system.l2c.overall_misses::total 594 # number of overall misses 1256system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles 1257system.l2c.ReadExReq_miss_latency::cpu1.data 851500 # number of ReadExReq miss cycles 1258system.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles 1259system.l2c.ReadExReq_miss_latency::cpu3.data 861000 # number of ReadExReq miss cycles 1260system.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles 1261system.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251000 # number of ReadCleanReq miss cycles 1262system.l2c.ReadCleanReq_miss_latency::cpu1.inst 845000 # number of ReadCleanReq miss cycles 1263system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885000 # 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number of demand (read+write) MSHR miss cycles 1472system.l2c.demand_mshr_miss_latency::cpu1.inst 510000 # number of demand (read+write) MSHR miss cycles 1473system.l2c.demand_mshr_miss_latency::cpu1.data 762000 # number of demand (read+write) MSHR miss cycles 1474system.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles 1475system.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles 1476system.l2c.demand_mshr_miss_latency::cpu3.inst 50500 # number of demand (read+write) MSHR miss cycles 1477system.l2c.demand_mshr_miss_latency::cpu3.data 771500 # number of demand (read+write) MSHR miss cycles 1478system.l2c.demand_mshr_miss_latency::total 28924000 # number of demand (read+write) MSHR miss cycles 1479system.l2c.overall_mshr_miss_latency::cpu0.inst 14401000 # number of overall MSHR miss cycles 1480system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles 1481system.l2c.overall_mshr_miss_latency::cpu1.inst 510000 # number of overall MSHR miss cycles 1482system.l2c.overall_mshr_miss_latency::cpu1.data 762000 # number of overall MSHR miss cycles 1483system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles 1484system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles 1485system.l2c.overall_mshr_miss_latency::cpu3.inst 50500 # number of overall MSHR miss cycles 1486system.l2c.overall_mshr_miss_latency::cpu3.data 771500 # number of overall MSHR miss cycles 1487system.l2c.overall_mshr_miss_latency::total 28924000 # number of overall MSHR miss cycles 1488system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1489system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1490system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1491system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1492system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1493system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1494system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses 1495system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 1496system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses 1497system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 1498system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 1499system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1500system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 1501system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1502system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 1503system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1504system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1505system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses 1506system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 1507system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 1508system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 1509system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1510system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 1511system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1512system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1513system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1514system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses 1515system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1516system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 1517system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 1518system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1519system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1520system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1521system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency 1522system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency 1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency 1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency 1525system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency 1526system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency 1527system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency 1528system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency 1529system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency 1530system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency 1531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency 1532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency 1533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency 1534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency 1535system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency 1536system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 1537system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1538system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 1539system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 1540system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1541system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1542system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 1543system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 1544system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 1545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 1546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1547system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 1548system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 1549system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1550system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1551system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 1552system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 1553system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 1554system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. 1555system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1556system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1557system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1558system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1559system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1560system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1561system.membus.trans_dist::ReadResp 430 # Transaction distribution 1562system.membus.trans_dist::UpgradeReq 195 # Transaction distribution 1563system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1564system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1565system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1566system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.snoops 261 # Total snoops (count) 1571system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1572system.membus.snoop_fanout::samples 839 # Request fanout histogram 1573system.membus.snoop_fanout::mean 0 # Request fanout histogram 1574system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1575system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1576system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram 1577system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1578system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1579system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1580system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1581system.membus.snoop_fanout::total 839 # Request fanout histogram 1582system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) 1583system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1584system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 1585system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1586system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter.	12sim_insts 663871 # Number of instructions simulated 13sim_ops 663871 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 25system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 31system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 40system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) 63system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls 66system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 67system.cpu0.numCycles 526819 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 158244 # Number of instructions committed 71system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured 75system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls 76system.cpu0.num_int_insts 108988 # number of integer instructions 77system.cpu0.num_fp_insts 0 # number of float instructions 78system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read 79system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written 80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 73856 # number of memory refs 83system.cpu0.num_load_insts 48897 # Number of load instructions 84system.cpu0.num_store_insts 24959 # Number of store instructions 85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 86system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles 87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 89system.cpu0.Branches 26842 # Number of branches fetched 90system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction 91system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction 92system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 93system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 94system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 95system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 96system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 97system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 98system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction 99system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 100system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction 101system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 102system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 103system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 104system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 105system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 106system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 107system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 108system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 109system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 110system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 111system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 112system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 113system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 114system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 119system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 122system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction 123system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction 124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 128system.cpu0.op_class::total 158306 # Class of executed instruction 129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 130system.cpu0.dcache.tags.replacements 2 # number of replacements 131system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use 132system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. 133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 134system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. 135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor 137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy 138system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy 139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 141system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 143system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses 144system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses 145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 146system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits 147system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits 148system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits 149system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits 150system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 151system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 152system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits 153system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits 154system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits 155system.cpu0.dcache.overall_hits::total 73442 # number of overall hits 156system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 157system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 158system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 159system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 160system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 161system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 162system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 163system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 164system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 165system.cpu0.dcache.overall_misses::total 353 # number of overall misses 166system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles 167system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles 168system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles 169system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles 170system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles 171system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles 172system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles 173system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles 174system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles 175system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles 176system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) 177system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) 178system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) 179system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) 180system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 181system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 182system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses 183system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses 184system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses 185system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses 186system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses 187system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses 188system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses 189system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses 190system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 191system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 192system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses 193system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses 194system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses 195system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses 196system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency 197system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency 198system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency 199system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency 200system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency 201system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency 202system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 203system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency 204system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency 205system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency 206system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 209system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 210system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 211system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 212system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 213system.cpu0.dcache.writebacks::total 1 # number of writebacks 214system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 215system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 216system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 217system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 218system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 219system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 220system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 221system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 222system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 223system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 224system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles 225system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles 226system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles 227system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles 228system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles 229system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles 230system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles 231system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles 232system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles 233system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles 234system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses 235system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses 236system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses 237system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses 238system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 239system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 240system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses 241system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses 242system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses 243system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses 244system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency 245system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency 246system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency 247system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency 248system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency 249system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency 250system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 251system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 252system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency 253system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency 254system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 255system.cpu0.icache.tags.replacements 215 # number of replacements 256system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use 257system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. 258system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 259system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. 260system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 261system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor 262system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy 263system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy 264system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 265system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 266system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 267system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 268system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses 269system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses 270system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 271system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits 272system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits 273system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits 274system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits 275system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits 276system.cpu0.icache.overall_hits::total 157840 # number of overall hits 277system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 278system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 279system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 280system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 281system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 282system.cpu0.icache.overall_misses::total 467 # number of overall misses 283system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles 284system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles 285system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles 286system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles 287system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles 288system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles 289system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) 290system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) 291system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses 292system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses 293system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses 294system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses 295system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 296system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 297system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 298system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 299system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 300system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 301system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency 302system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency 303system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 304system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency 305system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency 306system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency 307system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 308system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 309system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 310system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 311system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 312system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 313system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 314system.cpu0.icache.writebacks::total 215 # number of writebacks 315system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 316system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 317system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 318system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 319system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 320system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 321system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles 322system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles 323system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles 324system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles 325system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles 326system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles 327system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 328system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 329system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 330system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 331system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 332system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 333system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency 334system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency 335system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 336system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 337system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency 338system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency 339system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 340system.cpu1.numCycles 526818 # number of cpu cycles simulated 341system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 342system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 343system.cpu1.committedInsts 169340 # Number of instructions committed 344system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed 345system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses 346system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 347system.cpu1.num_func_calls 637 # number of times a function call or return occured 348system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls 349system.cpu1.num_int_insts 111465 # number of integer instructions 350system.cpu1.num_fp_insts 0 # number of float instructions 351system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read 352system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written 353system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 354system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 355system.cpu1.num_mem_refs 54688 # number of memory refs 356system.cpu1.num_load_insts 41399 # Number of load instructions 357system.cpu1.num_store_insts 13289 # Number of store instructions 358system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles 359system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles 360system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles 361system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles 362system.cpu1.Branches 34599 # Number of branches fetched 363system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction 364system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction 365system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction 366system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction 367system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction 368system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction 369system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction 370system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction 371system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction 372system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction 373system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction 374system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction 375system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction 376system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction 377system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction 378system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction 379system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction 380system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction 381system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction 382system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction 383system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction 384system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction 385system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction 386system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction 387system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction 388system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction 389system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction 390system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction 391system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction 392system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction 393system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction 394system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction 395system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction 396system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction 397system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 398system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 399system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 400system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 401system.cpu1.op_class::total 169372 # Class of executed instruction 402system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 403system.cpu1.dcache.tags.replacements 0 # number of replacements 404system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use 405system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. 406system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 407system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. 408system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 409system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor 410system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy 411system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy 412system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 413system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 414system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 415system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 416system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses 417system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses 418system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 419system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits 420system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits 421system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits 422system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits 423system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 424system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 425system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits 426system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits 427system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits 428system.cpu1.dcache.overall_hits::total 54340 # number of overall hits 429system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses 430system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses 431system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses 432system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses 433system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 434system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 435system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses 436system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses 437system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses 438system.cpu1.dcache.overall_misses::total 269 # number of overall misses 439system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles 440system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles 441system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles 442system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles 443system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles 444system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles 445system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles 446system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles 447system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles 448system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles 449system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) 450system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) 451system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) 452system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) 453system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) 454system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 455system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses 456system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses 457system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses 458system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses 459system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses 460system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses 461system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses 462system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses 463system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses 464system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 465system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses 466system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses 467system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses 468system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses 469system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency 470system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency 471system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency 472system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency 473system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency 474system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency 475system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 476system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency 477system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency 478system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency 479system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 480system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 481system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 482system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 483system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 484system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 485system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses 486system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses 487system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 488system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 489system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 490system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 491system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses 492system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 493system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses 494system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 495system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles 496system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles 497system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles 498system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles 499system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles 500system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles 501system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles 502system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles 503system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles 504system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles 505system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses 506system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses 507system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses 508system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses 509system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses 510system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 511system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses 512system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses 513system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses 514system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses 515system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency 516system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency 517system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency 518system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency 519system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency 520system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency 521system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 522system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 523system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency 524system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency 525system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 526system.cpu1.icache.tags.replacements 280 # number of replacements 527system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use 528system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. 529system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 530system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. 531system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 532system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor 533system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy 534system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy 535system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 536system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 537system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 538system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 539system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 540system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses 541system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses 542system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 543system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits 544system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits 545system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits 546system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits 547system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits 548system.cpu1.icache.overall_hits::total 169007 # number of overall hits 549system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 550system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 551system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 552system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 553system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 554system.cpu1.icache.overall_misses::total 366 # number of overall misses 555system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles 556system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles 557system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles 558system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles 559system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles 560system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles 561system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) 562system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) 563system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses 564system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses 565system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses 566system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses 567system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses 568system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses 569system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses 570system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses 571system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses 572system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses 573system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency 574system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency 575system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 576system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency 577system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency 578system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency 579system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 586system.cpu1.icache.writebacks::total 280 # number of writebacks 587system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 588system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 589system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 590system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 591system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 592system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 593system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles 594system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles 595system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles 596system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles 597system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles 598system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles 599system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses 600system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses 601system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses 602system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses 603system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses 604system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses 605system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency 606system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency 607system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 608system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 609system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency 610system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency 611system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 612system.cpu2.numCycles 526819 # number of cpu cycles simulated 613system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 614system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 615system.cpu2.committedInsts 165892 # Number of instructions committed 616system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed 617system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses 618system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 619system.cpu2.num_func_calls 637 # number of times a function call or return occured 620system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls 621system.cpu2.num_int_insts 110657 # number of integer instructions 622system.cpu2.num_fp_insts 0 # number of float instructions 623system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read 624system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written 625system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 626system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 627system.cpu2.num_mem_refs 55200 # number of memory refs 628system.cpu2.num_load_insts 40995 # Number of load instructions 629system.cpu2.num_store_insts 14205 # Number of store instructions 630system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles 631system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles 632system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles 633system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles 634system.cpu2.Branches 33279 # Number of branches fetched 635system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction 636system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction 637system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction 638system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction 639system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction 640system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction 641system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction 642system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction 643system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction 644system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction 645system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction 646system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction 647system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction 648system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction 649system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction 650system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction 651system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction 652system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction 653system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction 654system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction 655system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction 656system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction 657system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction 658system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction 659system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction 660system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction 661system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction 662system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction 663system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction 664system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction 665system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction 666system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction 667system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction 668system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction 669system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 670system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 671system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 672system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 673system.cpu2.op_class::total 165924 # Class of executed instruction 674system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 675system.cpu2.dcache.tags.replacements 0 # number of replacements 676system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use 677system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. 678system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 679system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. 680system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor 682system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy 683system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy 684system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 685system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 686system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 687system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 688system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses 689system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses 690system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 691system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits 692system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits 693system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits 694system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits 695system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 696system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 697system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits 698system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits 699system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits 700system.cpu2.dcache.overall_hits::total 54855 # number of overall hits 701system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses 702system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses 703system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 704system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 705system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses 706system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses 707system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses 708system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses 709system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses 710system.cpu2.dcache.overall_misses::total 267 # number of overall misses 711system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles 712system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles 713system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles 714system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles 715system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles 716system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles 717system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles 718system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles 719system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles 720system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles 721system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) 722system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) 723system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) 724system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) 725system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 726system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 727system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses 728system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses 729system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses 730system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses 731system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses 732system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses 733system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses 734system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses 735system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses 736system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 737system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses 738system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses 739system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses 740system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses 741system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency 742system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency 743system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency 744system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency 745system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency 746system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency 747system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 748system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency 749system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency 750system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency 751system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 758system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 759system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 760system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 761system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses 762system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 763system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 764system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 765system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 766system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 767system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles 768system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles 769system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles 770system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles 771system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles 772system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles 773system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles 774system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles 775system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles 776system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles 777system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses 778system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses 779system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses 780system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses 781system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses 782system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 783system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses 784system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses 785system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses 786system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses 787system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency 788system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency 789system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency 790system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency 791system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency 792system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency 793system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 794system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 795system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency 796system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency 797system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 798system.cpu2.icache.tags.replacements 280 # number of replacements 799system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use 800system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. 801system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 802system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. 803system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 804system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor 805system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy 806system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy 807system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 808system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 809system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 810system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 811system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 812system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses 813system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses 814system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 815system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits 816system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits 817system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits 818system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits 819system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits 820system.cpu2.icache.overall_hits::total 165559 # number of overall hits 821system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 822system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 823system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 824system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 825system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 826system.cpu2.icache.overall_misses::total 366 # number of overall misses 827system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles 828system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles 829system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles 830system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles 831system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles 832system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles 833system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) 834system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) 835system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses 836system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses 837system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses 838system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses 839system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses 840system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses 841system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses 842system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses 843system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses 844system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses 845system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency 846system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency 847system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 848system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency 849system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency 850system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency 851system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 852system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 853system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 854system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 855system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 856system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 857system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 858system.cpu2.icache.writebacks::total 280 # number of writebacks 859system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 860system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 861system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 862system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 863system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 864system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 865system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles 866system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles 867system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles 868system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles 869system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles 870system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles 871system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses 872system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses 873system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses 874system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses 875system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses 876system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses 877system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency 878system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency 879system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 880system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 881system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency 882system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency 883system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states 884system.cpu3.numCycles 526818 # number of cpu cycles simulated 885system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 886system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 887system.cpu3.committedInsts 170395 # Number of instructions committed 888system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed 889system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses 890system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 891system.cpu3.num_func_calls 637 # number of times a function call or return occured 892system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls 893system.cpu3.num_int_insts 111057 # number of integer instructions 894system.cpu3.num_fp_insts 0 # number of float instructions 895system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read 896system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written 897system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 898system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 899system.cpu3.num_mem_refs 53550 # number of memory refs 900system.cpu3.num_load_insts 41191 # Number of load instructions 901system.cpu3.num_store_insts 12359 # Number of store instructions 902system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles 903system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles 904system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles 905system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles 906system.cpu3.Branches 35332 # Number of branches fetched 907system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction 908system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction 909system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction 910system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction 911system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction 912system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction 913system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction 914system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction 915system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction 916system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction 917system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction 918system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction 919system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction 920system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction 921system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction 922system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction 923system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction 924system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction 925system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction 926system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction 927system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction 928system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction 929system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction 930system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction 931system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction 932system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction 933system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction 934system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction 935system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction 936system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction 937system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction 938system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction 939system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction 940system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction 941system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 942system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 943system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 944system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 945system.cpu3.op_class::total 170427 # Class of executed instruction 946system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 947system.cpu3.dcache.tags.replacements 0 # number of replacements 948system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use 949system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. 950system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 951system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. 952system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 953system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor 954system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy 955system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy 956system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 957system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 958system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 959system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 960system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses 961system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses 962system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 963system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits 964system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits 965system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits 966system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits 967system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 968system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 969system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits 970system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits 971system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits 972system.cpu3.dcache.overall_hits::total 53200 # number of overall hits 973system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses 974system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses 975system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 976system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 977system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 978system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses 979system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 980system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 981system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 982system.cpu3.dcache.overall_misses::total 268 # number of overall misses 983system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles 984system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles 985system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles 986system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles 987system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles 988system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles 989system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles 990system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles 991system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles 992system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles 993system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) 994system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) 995system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) 996system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) 997system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 998system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 999system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses 1000system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses 1001system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses 1002system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses 1003system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses 1004system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses 1005system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses 1006system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses 1007system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses 1008system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses 1009system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses 1010system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses 1011system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses 1012system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses 1013system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency 1014system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency 1015system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency 1016system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency 1017system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency 1018system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency 1019system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 1020system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency 1021system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency 1022system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency 1023system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1024system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1025system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1026system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1027system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1028system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1029system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 1030system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 1031system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1032system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1033system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 1034system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 1035system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 1036system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1037system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 1038system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1039system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles 1040system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles 1041system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles 1042system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles 1043system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles 1044system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles 1045system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles 1046system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles 1047system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles 1048system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles 1049system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses 1050system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses 1051system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses 1052system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses 1053system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses 1054system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses 1055system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses 1056system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses 1057system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses 1058system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses 1059system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency 1060system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency 1061system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency 1062system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency 1063system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency 1064system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency 1065system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 1066system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 1067system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency 1068system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency 1069system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1070system.cpu3.icache.tags.replacements 281 # number of replacements 1071system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use 1072system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. 1073system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1074system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. 1075system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1076system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor 1077system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy 1078system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy 1079system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1080system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 1081system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1082system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1083system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1084system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses 1085system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses 1086system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1087system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits 1088system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits 1089system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits 1090system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits 1091system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits 1092system.cpu3.icache.overall_hits::total 170061 # number of overall hits 1093system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1094system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1095system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1096system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1097system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1098system.cpu3.icache.overall_misses::total 367 # number of overall misses 1099system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles 1100system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles 1101system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles 1102system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles 1103system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles 1104system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles 1105system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) 1106system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) 1107system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses 1108system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses 1109system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses 1110system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses 1111system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses 1112system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses 1113system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses 1114system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses 1115system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses 1116system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 1117system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency 1118system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency 1119system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 1120system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency 1121system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency 1122system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency 1123system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1124system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1125system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1126system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1127system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1128system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1129system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1130system.cpu3.icache.writebacks::total 281 # number of writebacks 1131system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1132system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1133system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1134system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1135system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1136system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1137system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles 1138system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles 1139system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles 1140system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles 1141system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles 1142system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles 1143system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses 1144system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses 1145system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses 1146system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses 1147system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses 1148system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses 1149system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency 1150system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency 1151system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 1152system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 1153system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency 1154system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency 1155system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1156system.l2c.tags.replacements 0 # number of replacements 1157system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use 1158system.l2c.tags.total_refs 1794 # Total number of references to valid blocks. 1159system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. 1160system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. 1161system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1162system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor 1163system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor 1164system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor 1165system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor 1166system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor 1167system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor 1168system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor 1169system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor 1170system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy 1171system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy 1172system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy 1173system.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy 1174system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy 1175system.l2c.tags.occ_percent::cpu2.data 0.000265 # Average percentage of cache occupancy 1176system.l2c.tags.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy 1177system.l2c.tags.occ_percent::cpu3.data 0.000161 # Average percentage of cache occupancy 1178system.l2c.tags.occ_percent::total 0.007182 # Average percentage of cache occupancy 1179system.l2c.tags.occ_task_id_blocks::1024 572 # Occupied blocks per task id 1180system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1181system.l2c.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id 1182system.l2c.tags.occ_task_id_percent::1024 0.008728 # Percentage of cache occupancy per task id 1183system.l2c.tags.tag_accesses 19676 # Number of tag accesses 1184system.l2c.tags.data_accesses 19676 # Number of data accesses 1185system.l2c.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1186system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1187system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1188system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1189system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1190system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits 1191system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits 1192system.l2c.UpgradeReq_hits::cpu2.data 16 # number of UpgradeReq hits 1193system.l2c.UpgradeReq_hits::cpu3.data 17 # number of UpgradeReq hits 1194system.l2c.UpgradeReq_hits::total 79 # number of UpgradeReq hits 1195system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1196system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1197system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 1198system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 1199system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 1200system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 1201system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 1202system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 1203system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 1204system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 1205system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 1206system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 1207system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 1208system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 1209system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 1210system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 1211system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 1212system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 1213system.l2c.demand_hits::total 1218 # number of demand (read+write) hits 1214system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 1215system.l2c.overall_hits::cpu0.data 5 # number of overall hits 1216system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1217system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1218system.l2c.overall_hits::cpu2.inst 301 # number of overall hits 1219system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1220system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 1221system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1222system.l2c.overall_hits::total 1218 # number of overall hits 1223system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1224system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1225system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1226system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1227system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1228system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1229system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1230system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 1231system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 1232system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 1233system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 1234system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 1235system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 1236system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 1237system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 1238system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1239system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1240system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 1241system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 1242system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 1243system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 1244system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 1245system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 1246system.l2c.demand_misses::total 594 # number of demand (read+write) misses 1247system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1248system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1249system.l2c.overall_misses::cpu1.inst 14 # number of overall misses 1250system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1251system.l2c.overall_misses::cpu2.inst 65 # number of overall misses 1252system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1253system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 1254system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1255system.l2c.overall_misses::total 594 # number of overall misses 1256system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles 1257system.l2c.ReadExReq_miss_latency::cpu1.data 851500 # number of ReadExReq miss cycles 1258system.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles 1259system.l2c.ReadExReq_miss_latency::cpu3.data 861000 # number of ReadExReq miss cycles 1260system.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles 1261system.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251000 # number of ReadCleanReq miss cycles 1262system.l2c.ReadCleanReq_miss_latency::cpu1.inst 845000 # number of ReadCleanReq miss cycles 1263system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885000 # number of ReadCleanReq miss cycles 1264system.l2c.ReadCleanReq_miss_latency::cpu3.inst 552500 # number of ReadCleanReq miss cycles 1265system.l2c.ReadCleanReq_miss_latency::total 22533500 # number of ReadCleanReq miss cycles 1266system.l2c.ReadSharedReq_miss_latency::cpu0.data 3993500 # number of ReadSharedReq miss cycles 1267system.l2c.ReadSharedReq_miss_latency::cpu1.data 120000 # number of ReadSharedReq miss cycles 1268system.l2c.ReadSharedReq_miss_latency::cpu2.data 484000 # number of ReadSharedReq miss cycles 1269system.l2c.ReadSharedReq_miss_latency::cpu3.data 120500 # number of ReadSharedReq miss cycles 1270system.l2c.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles 1271system.l2c.demand_miss_latency::cpu0.inst 17251000 # number of demand (read+write) miss cycles 1272system.l2c.demand_miss_latency::cpu0.data 9984500 # number of demand (read+write) miss cycles 1273system.l2c.demand_miss_latency::cpu1.inst 845000 # number of demand (read+write) miss cycles 1274system.l2c.demand_miss_latency::cpu1.data 971500 # number of demand (read+write) miss cycles 1275system.l2c.demand_miss_latency::cpu2.inst 3885000 # number of demand (read+write) miss cycles 1276system.l2c.demand_miss_latency::cpu2.data 1395000 # number of demand (read+write) miss cycles 1277system.l2c.demand_miss_latency::cpu3.inst 552500 # number of demand (read+write) miss cycles 1278system.l2c.demand_miss_latency::cpu3.data 981500 # number of demand (read+write) miss cycles 1279system.l2c.demand_miss_latency::total 35866000 # number of demand (read+write) miss cycles 1280system.l2c.overall_miss_latency::cpu0.inst 17251000 # number of overall miss cycles 1281system.l2c.overall_miss_latency::cpu0.data 9984500 # number of overall miss cycles 1282system.l2c.overall_miss_latency::cpu1.inst 845000 # number of overall miss cycles 1283system.l2c.overall_miss_latency::cpu1.data 971500 # number of overall miss cycles 1284system.l2c.overall_miss_latency::cpu2.inst 3885000 # number of overall miss cycles 1285system.l2c.overall_miss_latency::cpu2.data 1395000 # number of overall miss cycles 1286system.l2c.overall_miss_latency::cpu3.inst 552500 # number of overall miss cycles 1287system.l2c.overall_miss_latency::cpu3.data 981500 # number of overall miss cycles 1288system.l2c.overall_miss_latency::total 35866000 # number of overall miss cycles 1289system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 1290system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 1291system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 1292system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 1293system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 1294system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 1295system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 1296system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) 1297system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 1298system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1299system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 1300system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 1301system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1302system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1303system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 1304system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 1305system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) 1306system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) 1307system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) 1308system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 1309system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) 1310system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) 1311system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) 1312system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) 1313system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 1314system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 1315system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 1316system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 1317system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 1318system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 1319system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 1320system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 1321system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 1322system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 1323system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 1324system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 1325system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 1326system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 1327system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 1328system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 1329system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1330system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1331system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1332system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1333system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1334system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1335system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1336system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 1337system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 1338system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses 1339system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses 1340system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses 1341system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 1342system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses 1343system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses 1344system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses 1345system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses 1346system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 1347system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 1348system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses 1349system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses 1350system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses 1351system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses 1352system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses 1353system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 1354system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses 1355system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 1356system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 1357system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses 1358system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses 1359system.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses 1360system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses 1361system.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses 1362system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 1363system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses 1364system.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency 1365system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60821.428571 # average ReadExReq miss latency 1366system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333 # average ReadExReq miss latency 1367system.l2c.ReadExReq_avg_miss_latency::cpu3.data 61500 # average ReadExReq miss latency 1368system.l2c.ReadExReq_avg_miss_latency::total 60665.492958 # average ReadExReq miss latency 1369system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60529.824561 # average ReadCleanReq miss latency 1370system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 60357.142857 # average ReadCleanReq miss latency 1371system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59769.230769 # average ReadCleanReq miss latency 1372system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55250 # average ReadCleanReq miss latency 1373system.l2c.ReadCleanReq_avg_miss_latency::total 60250 # average ReadCleanReq miss latency 1374system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758 # average ReadSharedReq miss latency 1375system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 60000 # average ReadSharedReq miss latency 1376system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 60500 # average ReadSharedReq miss latency 1377system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 60250 # average ReadSharedReq miss latency 1378system.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487 # average ReadSharedReq miss latency 1379system.l2c.demand_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency 1380system.l2c.demand_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 1381system.l2c.demand_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency 1382system.l2c.demand_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency 1383system.l2c.demand_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency 1384system.l2c.demand_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 1385system.l2c.demand_avg_miss_latency::cpu3.inst 55250 # average overall miss latency 1386system.l2c.demand_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency 1387system.l2c.demand_avg_miss_latency::total 60380.471380 # average overall miss latency 1388system.l2c.overall_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency 1389system.l2c.overall_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency 1390system.l2c.overall_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency 1391system.l2c.overall_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency 1392system.l2c.overall_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency 1393system.l2c.overall_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency 1394system.l2c.overall_avg_miss_latency::cpu3.inst 55250 # average overall miss latency 1395system.l2c.overall_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency 1396system.l2c.overall_avg_miss_latency::total 60380.471380 # average overall miss latency 1397system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1398system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1399system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1400system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1401system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1402system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1403system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 1404system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits 1405system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 9 # number of ReadCleanReq MSHR hits 1406system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 1407system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 1408system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits 1409system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits 1410system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 1411system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 1412system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits 1413system.l2c.demand_mshr_hits::cpu3.inst 9 # number of demand (read+write) MSHR hits 1414system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits 1415system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 1416system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 1417system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 1418system.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits 1419system.l2c.overall_mshr_hits::cpu3.inst 9 # number of overall MSHR hits 1420system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits 1421system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits 1422system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 1423system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses 1424system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses 1425system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 1426system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 1427system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses 1428system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10 # number of ReadCleanReq MSHR misses 1429system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 58 # number of ReadCleanReq MSHR misses 1430system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 1 # number of ReadCleanReq MSHR misses 1431system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses 1432system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses 1433system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses 1434system.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses 1435system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses 1436system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses 1437system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 1438system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses 1439system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses 1440system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses 1441system.l2c.demand_mshr_misses::cpu2.inst 58 # number of demand (read+write) MSHR misses 1442system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses 1443system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses 1444system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses 1445system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 1446system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 1447system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 1448system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses 1449system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses 1450system.l2c.overall_mshr_misses::cpu2.inst 58 # number of overall MSHR misses 1451system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses 1452system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses 1453system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 1454system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 1455system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5001000 # number of ReadExReq MSHR miss cycles 1456system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 711500 # number of ReadExReq MSHR miss cycles 1457system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 761000 # number of ReadExReq MSHR miss cycles 1458system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 721000 # number of ReadExReq MSHR miss cycles 1459system.l2c.ReadExReq_mshr_miss_latency::total 7194500 # number of ReadExReq MSHR miss cycles 1460system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14401000 # number of ReadCleanReq MSHR miss cycles 1461system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 510000 # number of ReadCleanReq MSHR miss cycles 1462system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2929500 # number of ReadCleanReq MSHR miss cycles 1463system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 50500 # number of ReadCleanReq MSHR miss cycles 1464system.l2c.ReadCleanReq_mshr_miss_latency::total 17891000 # number of ReadCleanReq MSHR miss cycles 1465system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3333500 # number of ReadSharedReq MSHR miss cycles 1466system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 50500 # number of ReadSharedReq MSHR miss cycles 1467system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 404000 # number of ReadSharedReq MSHR miss cycles 1468system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 50500 # number of ReadSharedReq MSHR miss cycles 1469system.l2c.ReadSharedReq_mshr_miss_latency::total 3838500 # number of ReadSharedReq MSHR miss cycles 1470system.l2c.demand_mshr_miss_latency::cpu0.inst 14401000 # number of demand (read+write) MSHR miss cycles 1471system.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles 1472system.l2c.demand_mshr_miss_latency::cpu1.inst 510000 # number of demand (read+write) MSHR miss cycles 1473system.l2c.demand_mshr_miss_latency::cpu1.data 762000 # number of demand (read+write) MSHR miss cycles 1474system.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles 1475system.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles 1476system.l2c.demand_mshr_miss_latency::cpu3.inst 50500 # number of demand (read+write) MSHR miss cycles 1477system.l2c.demand_mshr_miss_latency::cpu3.data 771500 # number of demand (read+write) MSHR miss cycles 1478system.l2c.demand_mshr_miss_latency::total 28924000 # number of demand (read+write) MSHR miss cycles 1479system.l2c.overall_mshr_miss_latency::cpu0.inst 14401000 # number of overall MSHR miss cycles 1480system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles 1481system.l2c.overall_mshr_miss_latency::cpu1.inst 510000 # number of overall MSHR miss cycles 1482system.l2c.overall_mshr_miss_latency::cpu1.data 762000 # number of overall MSHR miss cycles 1483system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles 1484system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles 1485system.l2c.overall_mshr_miss_latency::cpu3.inst 50500 # number of overall MSHR miss cycles 1486system.l2c.overall_mshr_miss_latency::cpu3.data 771500 # number of overall MSHR miss cycles 1487system.l2c.overall_mshr_miss_latency::total 28924000 # number of overall MSHR miss cycles 1488system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1489system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1490system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1491system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1492system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1493system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1494system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses 1495system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 1496system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses 1497system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 1498system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 1499system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1500system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 1501system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1502system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 1503system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1504system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1505system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses 1506system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 1507system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 1508system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 1509system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses 1510system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 1511system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1512system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1513system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1514system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses 1515system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1516system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 1517system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 1518system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses 1519system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1520system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1521system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency 1522system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency 1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency 1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency 1525system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency 1526system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency 1527system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency 1528system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency 1529system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency 1530system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency 1531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency 1532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency 1533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency 1534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency 1535system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency 1536system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 1537system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1538system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 1539system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 1540system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1541system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1542system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 1543system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 1544system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 1545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency 1546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency 1547system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency 1548system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency 1549system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency 1550system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency 1551system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency 1552system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency 1553system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency 1554system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. 1555system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1556system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1557system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1558system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1559system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1560system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1561system.membus.trans_dist::ReadResp 430 # Transaction distribution 1562system.membus.trans_dist::UpgradeReq 195 # Transaction distribution 1563system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1564system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1565system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1566system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.snoops 261 # Total snoops (count) 1571system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1572system.membus.snoop_fanout::samples 839 # Request fanout histogram 1573system.membus.snoop_fanout::mean 0 # Request fanout histogram 1574system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1575system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1576system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram 1577system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1578system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1579system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1580system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1581system.membus.snoop_fanout::total 839 # Request fanout histogram 1582system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) 1583system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1584system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) 1585system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1586system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter.
1587system.toL2Bus.snoop_filter.hit_single_requests 1097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1588system.toL2Bus.snoop_filter.hit_multi_requests 1878 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.	1587system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1588system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1589system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1590system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1591system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1592system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1593system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 1594system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1595system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 1596system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1597system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1598system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 1599system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 1600system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution 1601system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 1602system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution 1603system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 1604system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) 1605system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1606system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 1607system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1608system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 1609system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) 1610system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) 1611system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) 1612system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 1613system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1614system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1615system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1616system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1617system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1618system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) 1619system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1620system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) 1621system.toL2Bus.snoops 1028 # Total snoops (count) 1622system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) 1623system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram	1589system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1590system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1591system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1592system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states 1593system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 1594system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1595system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution 1596system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1597system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 1598system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 1599system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution 1600system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution 1601system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 1602system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution 1603system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 1604system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) 1605system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1606system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 1607system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) 1608system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 1609system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) 1610system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) 1611system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) 1612system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 1613system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1614system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1615system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1616system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) 1617system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1618system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) 1619system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1620system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) 1621system.toL2Bus.snoops 1028 # Total snoops (count) 1622system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) 1623system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram
1624system.toL2Bus.snoop_fanout::mean 1.282631 # Request fanout histogram 1625system.toL2Bus.snoop_fanout::stdev 1.164624 # Request fanout histogram	1624system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram 1625system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram
1626system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1627system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram	1626system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1627system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram
1628system.toL2Bus.snoop_fanout::1 771 26.41% 60.74% # Request fanout histogram 1629system.toL2Bus.snoop_fanout::2 465 15.93% 76.67% # Request fanout histogram 1630system.toL2Bus.snoop_fanout::3 681 23.33% 100.00% # Request fanout histogram	1628system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram 1629system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram 1630system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram
1631system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1632system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1633system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1634system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1635system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1636system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1637system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1638system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1639system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram 1640system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) 1641system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1642system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 1643system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1644system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) 1645system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1646system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) 1647system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 1648system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) 1649system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1650system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 1651system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 1652system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) 1653system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1654system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) 1655system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1656system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) 1657system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1658 1659---------- End Simulation Statistics ----------	1631system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1632system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1633system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1634system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1635system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1636system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1637system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1638system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1639system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram 1640system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) 1641system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1642system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) 1643system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1644system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) 1645system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1646system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) 1647system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 1648system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) 1649system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1650system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 1651system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 1652system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) 1653system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1654system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) 1655system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1656system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) 1657system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1658 1659---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000263 # Number of seconds simulated
4sim_ticks 263409500 # Number of ticks simulated
5final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 919692 # Simulator instruction rate (inst/s)
8host_op_rate 919679 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 364903746 # Simulator tick rate (ticks/s)
10host_mem_usage 263368 # Number of bytes of host memory used
11host_seconds 0.72 # Real time elapsed on the host

7host_inst_rate 870162 # Simulator instruction rate (inst/s)
8host_op_rate 870149 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 345251596 # Simulator tick rate (ticks/s)
10host_mem_usage 264052 # Number of bytes of host memory used
11host_seconds 0.76 # Real time elapsed on the host

12sim_insts 663871 # Number of instructions simulated
13sim_ops 663871 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
25system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
39system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s)
63system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
64system.cpu_clk_domain.clock 500 # Clock period in ticks
65system.cpu0.workload.num_syscalls 89 # Number of system calls
66system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states
67system.cpu0.numCycles 526819 # number of cpu cycles simulated
68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu0.committedInsts 158244 # Number of instructions committed
71system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed
72system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses
73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
74system.cpu0.num_func_calls 390 # number of times a function call or return occured
75system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls
76system.cpu0.num_int_insts 108988 # number of integer instructions
77system.cpu0.num_fp_insts 0 # number of float instructions
78system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read
79system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written
80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
82system.cpu0.num_mem_refs 73856 # number of memory refs
83system.cpu0.num_load_insts 48897 # Number of load instructions
84system.cpu0.num_store_insts 24959 # Number of store instructions
85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
86system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles
87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
89system.cpu0.Branches 26842 # Number of branches fetched
90system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction
91system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction
92system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
93system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
94system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
95system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction
96system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction
97system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction
98system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction
99system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction
100system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction
101system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction
102system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction
103system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction
104system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction
105system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction
106system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction
107system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction
108system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction
109system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction
110system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction
111system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction
112system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction
113system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction
114system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction
115system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction
116system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction
117system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction
118system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction
119system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
122system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction
123system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction
124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
128system.cpu0.op_class::total 158306 # Class of executed instruction
129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
130system.cpu0.dcache.tags.replacements 2 # number of replacements
131system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use
132system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks.
133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
134system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks.
135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor
137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy
138system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy
139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
141system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
143system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses
144system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses
145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
146system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits
147system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits
148system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits
149system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits
150system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
151system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
152system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits
153system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits
154system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits
155system.cpu0.dcache.overall_hits::total 73442 # number of overall hits
156system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
157system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
158system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
159system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
160system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
161system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
162system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
163system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
164system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
165system.cpu0.dcache.overall_misses::total 353 # number of overall misses
166system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles
167system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles
168system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles
169system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles
170system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles
171system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles
172system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles
173system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles
174system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles
175system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles
176system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses)
177system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses)
178system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses)
179system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses)
180system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
181system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
182system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses
183system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses
184system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses
185system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses
186system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses
187system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses
188system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses
189system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses
190system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
191system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
192system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses
193system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses
194system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses
195system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses
196system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency
197system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency
198system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency
199system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency
200system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency
201system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency
202system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency
203system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency
204system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency
205system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency
206system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
207system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
208system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
209system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
210system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
211system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
212system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
213system.cpu0.dcache.writebacks::total 1 # number of writebacks
214system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
215system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
216system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
217system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
218system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
219system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
220system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
221system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
222system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
223system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
224system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles
225system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles
226system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles
227system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles
228system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles
229system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles
230system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles
231system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles
232system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles
233system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles
234system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses
235system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses
236system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses
237system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses
238system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
239system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
240system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses
241system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses
242system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses
243system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses
244system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency
245system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency
246system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency
247system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency
248system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency
249system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency
250system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency
251system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency
252system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency
253system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency
254system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
255system.cpu0.icache.tags.replacements 215 # number of replacements
256system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use
257system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks.
258system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
259system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks.
260system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
261system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor
262system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy
263system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy
264system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
265system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
266system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
267system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
268system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses
269system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses
270system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
271system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits
272system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits
273system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits
274system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits
275system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits
276system.cpu0.icache.overall_hits::total 157840 # number of overall hits
277system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
278system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
279system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
280system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
281system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
282system.cpu0.icache.overall_misses::total 467 # number of overall misses
283system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles
284system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles
285system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles
286system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles
287system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles
288system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles
289system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses)
290system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses)
291system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses
292system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses
293system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses
294system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses
295system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses
296system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses
297system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses
298system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses
299system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses
300system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses
301system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency
302system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency
303system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency
304system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency
305system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency
306system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency
307system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
308system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
309system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
310system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
311system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
312system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
313system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
314system.cpu0.icache.writebacks::total 215 # number of writebacks
315system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
316system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
317system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
318system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
319system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
320system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
321system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles
322system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles
323system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles
324system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles
325system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles
326system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles
327system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses
328system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses
329system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses
330system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses
331system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses
332system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses
333system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency
334system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency
335system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency
336system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency
337system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency
338system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency
339system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states
340system.cpu1.numCycles 526818 # number of cpu cycles simulated
341system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
342system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
343system.cpu1.committedInsts 169340 # Number of instructions committed
344system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed
345system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses
346system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
347system.cpu1.num_func_calls 637 # number of times a function call or return occured
348system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls
349system.cpu1.num_int_insts 111465 # number of integer instructions
350system.cpu1.num_fp_insts 0 # number of float instructions
351system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read
352system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written
353system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
354system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
355system.cpu1.num_mem_refs 54688 # number of memory refs
356system.cpu1.num_load_insts 41399 # Number of load instructions
357system.cpu1.num_store_insts 13289 # Number of store instructions
358system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles
359system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles
360system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles
361system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles
362system.cpu1.Branches 34599 # Number of branches fetched
363system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction
364system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction
365system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction
366system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction
367system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction
368system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction
369system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction
370system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction
371system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction
372system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction
373system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction
374system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction
375system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction
376system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction
377system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction
378system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction
379system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction
380system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction
381system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction
382system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction
383system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction
384system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction
385system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction
386system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction
387system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction
388system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction
389system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction
390system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction
391system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction
392system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction
393system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction
394system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction
395system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction
396system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction
397system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
398system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
399system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
400system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
401system.cpu1.op_class::total 169372 # Class of executed instruction
402system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
403system.cpu1.dcache.tags.replacements 0 # number of replacements
404system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use
405system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks.
406system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
407system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks.
408system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
409system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor
410system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy
411system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy
412system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
413system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
414system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
415system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
416system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses
417system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses
418system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
419system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits
420system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits
421system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits
422system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits
423system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
424system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
425system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits
426system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits
427system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits
428system.cpu1.dcache.overall_hits::total 54340 # number of overall hits
429system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses
430system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses
431system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses
432system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses
433system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
434system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
435system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses
436system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses
437system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses
438system.cpu1.dcache.overall_misses::total 269 # number of overall misses
439system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles
440system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles
441system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles
442system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles
443system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles
444system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles
445system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles
446system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles
447system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles
448system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles
449system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses)
450system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses)
451system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses)
452system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses)
453system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
454system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
455system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses
456system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses
457system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses
458system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses
459system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses
460system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses
461system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses
462system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses
463system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses
464system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
465system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses
466system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses
467system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses
468system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses
469system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency
470system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency
471system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency
472system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency
473system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency
474system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency
475system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency
476system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency
477system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency
478system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency
479system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
480system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
481system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
482system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
483system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
484system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
485system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses
486system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
487system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
488system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
489system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
490system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
491system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses
492system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
493system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses
494system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
495system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles
496system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles
497system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles
498system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles
499system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles
500system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles
501system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles
502system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles
503system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles
504system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles
505system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses
506system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses
507system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses
508system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses
509system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses
510system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
511system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses
512system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses
513system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses
514system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses
515system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency
516system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency
517system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency
518system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency
519system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency
520system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency
521system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency
522system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency
523system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency
524system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency
525system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
526system.cpu1.icache.tags.replacements 280 # number of replacements
527system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use
528system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks.
529system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
530system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks.
531system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
532system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor
533system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy
534system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy
535system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
536system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
537system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
538system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
539system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
540system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses
541system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses
542system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
543system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits
544system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits
545system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits
546system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits
547system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits
548system.cpu1.icache.overall_hits::total 169007 # number of overall hits
549system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
550system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
551system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
552system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
553system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
554system.cpu1.icache.overall_misses::total 366 # number of overall misses
555system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles
556system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles
557system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles
558system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles
559system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles
560system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles
561system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses)
562system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses)
563system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses
564system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses
565system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses
566system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses
567system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses
568system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses
569system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses
570system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses
571system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses
572system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses
573system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency
574system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency
575system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency
576system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency
577system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency
578system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency
579system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
580system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
581system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
582system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
583system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
584system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
585system.cpu1.icache.writebacks::writebacks 280 # number of writebacks
586system.cpu1.icache.writebacks::total 280 # number of writebacks
587system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
588system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
589system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
590system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
591system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
592system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
593system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles
594system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles
595system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles
596system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles
597system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles
598system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles
599system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses
600system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses
601system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses
602system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses
603system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses
604system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses
605system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency
606system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency
607system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency
608system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency
609system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency
610system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency
611system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states
612system.cpu2.numCycles 526819 # number of cpu cycles simulated
613system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
614system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
615system.cpu2.committedInsts 165892 # Number of instructions committed
616system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed
617system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses
618system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
619system.cpu2.num_func_calls 637 # number of times a function call or return occured
620system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls
621system.cpu2.num_int_insts 110657 # number of integer instructions
622system.cpu2.num_fp_insts 0 # number of float instructions
623system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read
624system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written
625system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
626system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
627system.cpu2.num_mem_refs 55200 # number of memory refs
628system.cpu2.num_load_insts 40995 # Number of load instructions
629system.cpu2.num_store_insts 14205 # Number of store instructions
630system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles
631system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles
632system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles
633system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles
634system.cpu2.Branches 33279 # Number of branches fetched
635system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction
636system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction
637system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction
638system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction
639system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction
640system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction
641system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction
642system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction
643system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction
644system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction
645system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction
646system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction
647system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction
648system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction
649system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction
650system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction
651system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction
652system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction
653system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction
654system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction
655system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction
656system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction
657system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction
658system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction
659system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction
660system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction
661system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction
662system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction
663system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction
664system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction
665system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction
666system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction
667system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction
668system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction
669system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
670system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
671system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
672system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
673system.cpu2.op_class::total 165924 # Class of executed instruction
674system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
675system.cpu2.dcache.tags.replacements 0 # number of replacements
676system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use
677system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks.
678system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
679system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks.
680system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
681system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor
682system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy
683system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy
684system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
685system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
686system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
687system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
688system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses
689system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses
690system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
691system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits
692system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits
693system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits
694system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits
695system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
696system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
697system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits
698system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits
699system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits
700system.cpu2.dcache.overall_hits::total 54855 # number of overall hits
701system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses
702system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses
703system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
704system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
705system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
706system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
707system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses
708system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses
709system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses
710system.cpu2.dcache.overall_misses::total 267 # number of overall misses
711system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles
712system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles
713system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles
714system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
715system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles
716system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles
717system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles
718system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles
719system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles
720system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles
721system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses)
722system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses)
723system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses)
724system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses)
725system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
726system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
727system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses
728system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses
729system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses
730system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses
731system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses
732system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses
733system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses
734system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses
735system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses
736system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
737system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses
738system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses
739system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses
740system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses
741system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency
742system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency
743system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency
744system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency
745system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency
746system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency
747system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency
748system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency
749system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency
750system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency
751system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
752system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
753system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
754system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
755system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
756system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
757system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
758system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
759system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
760system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
761system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
762system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
763system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
764system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
765system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
766system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
767system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles
768system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles
769system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles
770system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles
771system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles
772system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles
773system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles
774system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles
775system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles
776system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles
777system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses
778system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses
779system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses
780system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses
781system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses
782system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
783system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses
784system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses
785system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses
786system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses
787system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency
788system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency
789system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency
790system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency
791system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency
792system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency
793system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency
794system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency
795system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency
796system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency
797system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
798system.cpu2.icache.tags.replacements 280 # number of replacements
799system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use
800system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks.
801system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
802system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks.
803system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
804system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor
805system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy
806system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy
807system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
808system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
809system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
810system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
811system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
812system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses
813system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses
814system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
815system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits
816system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits
817system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits
818system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits
819system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits
820system.cpu2.icache.overall_hits::total 165559 # number of overall hits
821system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
822system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
823system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
824system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
825system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
826system.cpu2.icache.overall_misses::total 366 # number of overall misses
827system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles
828system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles
829system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles
830system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles
831system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles
832system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles
833system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses)
834system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses)
835system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses
836system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses
837system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses
838system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses
839system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses
840system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses
841system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses
842system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses
843system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses
844system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses
845system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency
846system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency
847system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency
848system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency
849system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency
850system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency
851system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
852system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
853system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
854system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
855system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
856system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
857system.cpu2.icache.writebacks::writebacks 280 # number of writebacks
858system.cpu2.icache.writebacks::total 280 # number of writebacks
859system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
860system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
861system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
862system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
863system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
864system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
865system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles
866system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles
867system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles
868system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles
869system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles
870system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles
871system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses
872system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses
873system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses
874system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses
875system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses
876system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses
877system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency
878system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency
879system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency
880system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency
881system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency
882system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency
883system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states
884system.cpu3.numCycles 526818 # number of cpu cycles simulated
885system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
886system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
887system.cpu3.committedInsts 170395 # Number of instructions committed
888system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed
889system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses
890system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
891system.cpu3.num_func_calls 637 # number of times a function call or return occured
892system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls
893system.cpu3.num_int_insts 111057 # number of integer instructions
894system.cpu3.num_fp_insts 0 # number of float instructions
895system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read
896system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written
897system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
898system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
899system.cpu3.num_mem_refs 53550 # number of memory refs
900system.cpu3.num_load_insts 41191 # Number of load instructions
901system.cpu3.num_store_insts 12359 # Number of store instructions
902system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles
903system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles
904system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles
905system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles
906system.cpu3.Branches 35332 # Number of branches fetched
907system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction
908system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction
909system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction
910system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction
911system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction
912system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction
913system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction
914system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction
915system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction
916system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction
917system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction
918system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction
919system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction
920system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction
921system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction
922system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction
923system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction
924system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction
925system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction
926system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction
927system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction
928system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction
929system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction
930system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction
931system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction
932system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction
933system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction
934system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction
935system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction
936system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction
937system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction
938system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction
939system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction
940system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction
941system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
942system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
943system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
944system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
945system.cpu3.op_class::total 170427 # Class of executed instruction
946system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
947system.cpu3.dcache.tags.replacements 0 # number of replacements
948system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use
949system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks.
950system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
951system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks.
952system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
953system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor
954system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy
955system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy
956system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
957system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
958system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
959system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
960system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses
961system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses
962system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
963system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits
964system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits
965system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits
966system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits
967system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
968system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
969system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits
970system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits
971system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits
972system.cpu3.dcache.overall_hits::total 53200 # number of overall hits
973system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses
974system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses
975system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
976system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
977system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
978system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
979system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses
980system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses
981system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses
982system.cpu3.dcache.overall_misses::total 268 # number of overall misses
983system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles
984system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles
985system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles
986system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles
987system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles
988system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles
989system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles
990system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles
991system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles
992system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles
993system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses)
994system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses)
995system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses)
996system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses)
997system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
998system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
999system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses
1000system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses
1001system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses
1002system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses
1003system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses
1004system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses
1005system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses
1006system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses
1007system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses
1008system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses
1009system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses
1010system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses
1011system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses
1012system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses
1013system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency
1014system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency
1015system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency
1016system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency
1017system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency
1018system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency
1019system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency
1020system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency
1021system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency
1022system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency
1023system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1024system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1025system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1026system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1027system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1028system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1029system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
1030system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
1031system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
1032system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
1033system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
1034system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
1035system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses
1036system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1037system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses
1038system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1039system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles
1040system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles
1041system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles
1042system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles
1043system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles
1044system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles
1045system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles
1046system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles
1047system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles
1048system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles
1049system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses
1050system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses
1051system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses
1052system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses
1053system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses
1054system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses
1055system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses
1056system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses
1057system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses
1058system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses
1059system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency
1060system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency
1061system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency
1062system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency
1063system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency
1064system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency
1065system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency
1066system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency
1067system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency
1068system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency
1069system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1070system.cpu3.icache.tags.replacements 281 # number of replacements
1071system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use
1072system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks.
1073system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1074system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks.
1075system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1076system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor
1077system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy
1078system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy
1079system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1080system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
1081system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
1082system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1083system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1084system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses
1085system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses
1086system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1087system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits
1088system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits
1089system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits
1090system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits
1091system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits
1092system.cpu3.icache.overall_hits::total 170061 # number of overall hits
1093system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1094system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1095system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1096system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1097system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1098system.cpu3.icache.overall_misses::total 367 # number of overall misses
1099system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles
1100system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles
1101system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles
1102system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles
1103system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles
1104system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles
1105system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses)
1106system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses)
1107system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses
1108system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses
1109system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses
1110system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses
1111system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses
1112system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses
1113system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses
1114system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses
1115system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses
1116system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses
1117system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency
1118system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency
1119system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency
1120system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency
1121system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency
1122system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency
1123system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1124system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1125system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1126system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1127system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1128system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1129system.cpu3.icache.writebacks::writebacks 281 # number of writebacks
1130system.cpu3.icache.writebacks::total 281 # number of writebacks
1131system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1132system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1133system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1134system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1135system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1136system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1137system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles
1138system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
1139system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles
1140system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles
1141system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles
1142system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles
1143system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses
1144system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses
1145system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses
1146system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses
1147system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses
1148system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses
1149system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency
1150system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency
1151system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency
1152system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency
1153system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency
1154system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency
1155system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1156system.l2c.tags.replacements 0 # number of replacements
1157system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use
1158system.l2c.tags.total_refs 1794 # Total number of references to valid blocks.
1159system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks.
1160system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks.
1161system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1162system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor
1163system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor
1164system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor
1165system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor
1166system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor
1167system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor
1168system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor
1169system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor
1170system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy
1171system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy
1172system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
1173system.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy
1174system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy
1175system.l2c.tags.occ_percent::cpu2.data 0.000265 # Average percentage of cache occupancy
1176system.l2c.tags.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy
1177system.l2c.tags.occ_percent::cpu3.data 0.000161 # Average percentage of cache occupancy
1178system.l2c.tags.occ_percent::total 0.007182 # Average percentage of cache occupancy
1179system.l2c.tags.occ_task_id_blocks::1024 572 # Occupied blocks per task id
1180system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
1181system.l2c.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
1182system.l2c.tags.occ_task_id_percent::1024 0.008728 # Percentage of cache occupancy per task id
1183system.l2c.tags.tag_accesses 19676 # Number of tag accesses
1184system.l2c.tags.data_accesses 19676 # Number of data accesses
1185system.l2c.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1186system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
1187system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
1188system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
1189system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
1190system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits
1191system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
1192system.l2c.UpgradeReq_hits::cpu2.data 16 # number of UpgradeReq hits
1193system.l2c.UpgradeReq_hits::cpu3.data 17 # number of UpgradeReq hits
1194system.l2c.UpgradeReq_hits::total 79 # number of UpgradeReq hits
1195system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits
1196system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits
1197system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits
1198system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits
1199system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits
1200system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
1201system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
1202system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits
1203system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
1204system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
1205system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
1206system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
1207system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
1208system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
1209system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits
1210system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
1211system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
1212system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
1213system.l2c.demand_hits::total 1218 # number of demand (read+write) hits
1214system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
1215system.l2c.overall_hits::cpu0.data 5 # number of overall hits
1216system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
1217system.l2c.overall_hits::cpu1.data 9 # number of overall hits
1218system.l2c.overall_hits::cpu2.inst 301 # number of overall hits
1219system.l2c.overall_hits::cpu2.data 3 # number of overall hits
1220system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
1221system.l2c.overall_hits::cpu3.data 9 # number of overall hits
1222system.l2c.overall_hits::total 1218 # number of overall hits
1223system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
1224system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
1225system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
1226system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
1227system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
1228system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses
1229system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses
1230system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses
1231system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses
1232system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses
1233system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
1234system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses
1235system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses
1236system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
1237system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses
1238system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
1239system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
1240system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
1241system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
1242system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses
1243system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
1244system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses
1245system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
1246system.l2c.demand_misses::total 594 # number of demand (read+write) misses
1247system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
1248system.l2c.overall_misses::cpu0.data 165 # number of overall misses
1249system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
1250system.l2c.overall_misses::cpu1.data 16 # number of overall misses
1251system.l2c.overall_misses::cpu2.inst 65 # number of overall misses
1252system.l2c.overall_misses::cpu2.data 23 # number of overall misses
1253system.l2c.overall_misses::cpu3.inst 10 # number of overall misses
1254system.l2c.overall_misses::cpu3.data 16 # number of overall misses
1255system.l2c.overall_misses::total 594 # number of overall misses
1256system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles
1257system.l2c.ReadExReq_miss_latency::cpu1.data 851500 # number of ReadExReq miss cycles
1258system.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles
1259system.l2c.ReadExReq_miss_latency::cpu3.data 861000 # number of ReadExReq miss cycles
1260system.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles
1261system.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251000 # number of ReadCleanReq miss cycles
1262system.l2c.ReadCleanReq_miss_latency::cpu1.inst 845000 # number of ReadCleanReq miss cycles
1263system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885000 # number of ReadCleanReq miss cycles
1264system.l2c.ReadCleanReq_miss_latency::cpu3.inst 552500 # number of ReadCleanReq miss cycles
1265system.l2c.ReadCleanReq_miss_latency::total 22533500 # number of ReadCleanReq miss cycles
1266system.l2c.ReadSharedReq_miss_latency::cpu0.data 3993500 # number of ReadSharedReq miss cycles
1267system.l2c.ReadSharedReq_miss_latency::cpu1.data 120000 # number of ReadSharedReq miss cycles
1268system.l2c.ReadSharedReq_miss_latency::cpu2.data 484000 # number of ReadSharedReq miss cycles
1269system.l2c.ReadSharedReq_miss_latency::cpu3.data 120500 # number of ReadSharedReq miss cycles
1270system.l2c.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles
1271system.l2c.demand_miss_latency::cpu0.inst 17251000 # number of demand (read+write) miss cycles
1272system.l2c.demand_miss_latency::cpu0.data 9984500 # number of demand (read+write) miss cycles
1273system.l2c.demand_miss_latency::cpu1.inst 845000 # number of demand (read+write) miss cycles
1274system.l2c.demand_miss_latency::cpu1.data 971500 # number of demand (read+write) miss cycles
1275system.l2c.demand_miss_latency::cpu2.inst 3885000 # number of demand (read+write) miss cycles
1276system.l2c.demand_miss_latency::cpu2.data 1395000 # number of demand (read+write) miss cycles
1277system.l2c.demand_miss_latency::cpu3.inst 552500 # number of demand (read+write) miss cycles
1278system.l2c.demand_miss_latency::cpu3.data 981500 # number of demand (read+write) miss cycles
1279system.l2c.demand_miss_latency::total 35866000 # number of demand (read+write) miss cycles
1280system.l2c.overall_miss_latency::cpu0.inst 17251000 # number of overall miss cycles
1281system.l2c.overall_miss_latency::cpu0.data 9984500 # number of overall miss cycles
1282system.l2c.overall_miss_latency::cpu1.inst 845000 # number of overall miss cycles
1283system.l2c.overall_miss_latency::cpu1.data 971500 # number of overall miss cycles
1284system.l2c.overall_miss_latency::cpu2.inst 3885000 # number of overall miss cycles
1285system.l2c.overall_miss_latency::cpu2.data 1395000 # number of overall miss cycles
1286system.l2c.overall_miss_latency::cpu3.inst 552500 # number of overall miss cycles
1287system.l2c.overall_miss_latency::cpu3.data 981500 # number of overall miss cycles
1288system.l2c.overall_miss_latency::total 35866000 # number of overall miss cycles
1289system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
1290system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
1291system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
1292system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
1293system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
1294system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
1295system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
1296system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
1297system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
1298system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
1299system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
1300system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
1301system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
1302system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
1303system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
1304system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses)
1305system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses)
1306system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses)
1307system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses)
1308system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
1309system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses)
1310system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses)
1311system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses)
1312system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses)
1313system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
1314system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
1315system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
1316system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
1317system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
1318system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
1319system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
1320system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
1321system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
1322system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
1323system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
1324system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
1325system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
1326system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
1327system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
1328system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
1329system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
1330system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
1331system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
1332system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
1333system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
1334system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
1335system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1336system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses
1337system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses
1338system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses
1339system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses
1340system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses
1341system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
1342system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses
1343system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses
1344system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses
1345system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses
1346system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
1347system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
1348system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
1349system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
1350system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses
1351system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
1352system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses
1353system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
1354system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses
1355system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
1356system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
1357system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
1358system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
1359system.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses
1360system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
1361system.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses
1362system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
1363system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses
1364system.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency
1365system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60821.428571 # average ReadExReq miss latency
1366system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333 # average ReadExReq miss latency
1367system.l2c.ReadExReq_avg_miss_latency::cpu3.data 61500 # average ReadExReq miss latency
1368system.l2c.ReadExReq_avg_miss_latency::total 60665.492958 # average ReadExReq miss latency
1369system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60529.824561 # average ReadCleanReq miss latency
1370system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 60357.142857 # average ReadCleanReq miss latency
1371system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59769.230769 # average ReadCleanReq miss latency
1372system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55250 # average ReadCleanReq miss latency
1373system.l2c.ReadCleanReq_avg_miss_latency::total 60250 # average ReadCleanReq miss latency
1374system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758 # average ReadSharedReq miss latency
1375system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 60000 # average ReadSharedReq miss latency
1376system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 60500 # average ReadSharedReq miss latency
1377system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 60250 # average ReadSharedReq miss latency
1378system.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487 # average ReadSharedReq miss latency
1379system.l2c.demand_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency
1380system.l2c.demand_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency
1381system.l2c.demand_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency
1382system.l2c.demand_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency
1383system.l2c.demand_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency
1384system.l2c.demand_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency
1385system.l2c.demand_avg_miss_latency::cpu3.inst 55250 # average overall miss latency
1386system.l2c.demand_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency
1387system.l2c.demand_avg_miss_latency::total 60380.471380 # average overall miss latency
1388system.l2c.overall_avg_miss_latency::cpu0.inst 60529.824561 # average overall miss latency
1389system.l2c.overall_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency
1390system.l2c.overall_avg_miss_latency::cpu1.inst 60357.142857 # average overall miss latency
1391system.l2c.overall_avg_miss_latency::cpu1.data 60718.750000 # average overall miss latency
1392system.l2c.overall_avg_miss_latency::cpu2.inst 59769.230769 # average overall miss latency
1393system.l2c.overall_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency
1394system.l2c.overall_avg_miss_latency::cpu3.inst 55250 # average overall miss latency
1395system.l2c.overall_avg_miss_latency::cpu3.data 61343.750000 # average overall miss latency
1396system.l2c.overall_avg_miss_latency::total 60380.471380 # average overall miss latency
1397system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1398system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1399system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1400system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1401system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1402system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1403system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
1404system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits
1405system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 9 # number of ReadCleanReq MSHR hits
1406system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits
1407system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
1408system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits
1409system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
1410system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
1411system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
1412system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits
1413system.l2c.demand_mshr_hits::cpu3.inst 9 # number of demand (read+write) MSHR hits
1414system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
1415system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
1416system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
1417system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
1418system.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits
1419system.l2c.overall_mshr_hits::cpu3.inst 9 # number of overall MSHR hits
1420system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
1421system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits
1422system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
1423system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
1424system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
1425system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
1426system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
1427system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses
1428system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10 # number of ReadCleanReq MSHR misses
1429system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 58 # number of ReadCleanReq MSHR misses
1430system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 1 # number of ReadCleanReq MSHR misses
1431system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses
1432system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses
1433system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses
1434system.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses
1435system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
1436system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses
1437system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
1438system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
1439system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses
1440system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
1441system.l2c.demand_mshr_misses::cpu2.inst 58 # number of demand (read+write) MSHR misses
1442system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses
1443system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
1444system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
1445system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
1446system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
1447system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
1448system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses
1449system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
1450system.l2c.overall_mshr_misses::cpu2.inst 58 # number of overall MSHR misses
1451system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses
1452system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
1453system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
1454system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
1455system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5001000 # number of ReadExReq MSHR miss cycles
1456system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 711500 # number of ReadExReq MSHR miss cycles
1457system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 761000 # number of ReadExReq MSHR miss cycles
1458system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 721000 # number of ReadExReq MSHR miss cycles
1459system.l2c.ReadExReq_mshr_miss_latency::total 7194500 # number of ReadExReq MSHR miss cycles
1460system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14401000 # number of ReadCleanReq MSHR miss cycles
1461system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 510000 # number of ReadCleanReq MSHR miss cycles
1462system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2929500 # number of ReadCleanReq MSHR miss cycles
1463system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 50500 # number of ReadCleanReq MSHR miss cycles
1464system.l2c.ReadCleanReq_mshr_miss_latency::total 17891000 # number of ReadCleanReq MSHR miss cycles
1465system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3333500 # number of ReadSharedReq MSHR miss cycles
1466system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 50500 # number of ReadSharedReq MSHR miss cycles
1467system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 404000 # number of ReadSharedReq MSHR miss cycles
1468system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 50500 # number of ReadSharedReq MSHR miss cycles
1469system.l2c.ReadSharedReq_mshr_miss_latency::total 3838500 # number of ReadSharedReq MSHR miss cycles
1470system.l2c.demand_mshr_miss_latency::cpu0.inst 14401000 # number of demand (read+write) MSHR miss cycles
1471system.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles
1472system.l2c.demand_mshr_miss_latency::cpu1.inst 510000 # number of demand (read+write) MSHR miss cycles
1473system.l2c.demand_mshr_miss_latency::cpu1.data 762000 # number of demand (read+write) MSHR miss cycles
1474system.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles
1475system.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles
1476system.l2c.demand_mshr_miss_latency::cpu3.inst 50500 # number of demand (read+write) MSHR miss cycles
1477system.l2c.demand_mshr_miss_latency::cpu3.data 771500 # number of demand (read+write) MSHR miss cycles
1478system.l2c.demand_mshr_miss_latency::total 28924000 # number of demand (read+write) MSHR miss cycles
1479system.l2c.overall_mshr_miss_latency::cpu0.inst 14401000 # number of overall MSHR miss cycles
1480system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles
1481system.l2c.overall_mshr_miss_latency::cpu1.inst 510000 # number of overall MSHR miss cycles
1482system.l2c.overall_mshr_miss_latency::cpu1.data 762000 # number of overall MSHR miss cycles
1483system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles
1484system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles
1485system.l2c.overall_mshr_miss_latency::cpu3.inst 50500 # number of overall MSHR miss cycles
1486system.l2c.overall_mshr_miss_latency::cpu3.data 771500 # number of overall MSHR miss cycles
1487system.l2c.overall_mshr_miss_latency::total 28924000 # number of overall MSHR miss cycles
1488system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
1489system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
1490system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
1491system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
1492system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1493system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses
1494system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses
1495system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses
1496system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses
1497system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses
1498system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses
1499system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses
1500system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses
1501system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses
1502system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses
1503system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
1504system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
1505system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses
1506system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
1507system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses
1508system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses
1509system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
1510system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
1511system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
1512system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
1513system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
1514system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses
1515system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
1516system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses
1517system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses
1518system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
1519system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
1520system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
1521system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency
1522system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency
1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency
1524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency
1525system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency
1526system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency
1527system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency
1528system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency
1529system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency
1530system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency
1531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency
1532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency
1533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency
1534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency
1535system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency
1536system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency
1537system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency
1538system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency
1539system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency
1540system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency
1541system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency
1542system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency
1543system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency
1544system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency
1545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency
1546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency
1547system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency
1548system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency
1549system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency
1550system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency
1551system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency
1552system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency
1553system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency
1554system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter.
1555system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1556system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1557system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1558system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1559system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1560system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1561system.membus.trans_dist::ReadResp 430 # Transaction distribution
1562system.membus.trans_dist::UpgradeReq 195 # Transaction distribution
1563system.membus.trans_dist::ReadExReq 208 # Transaction distribution
1564system.membus.trans_dist::ReadExResp 142 # Transaction distribution
1565system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
1566system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes)
1567system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes)
1568system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
1569system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
1570system.membus.snoops 261 # Total snoops (count)
1571system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1572system.membus.snoop_fanout::samples 839 # Request fanout histogram
1573system.membus.snoop_fanout::mean 0 # Request fanout histogram
1574system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1575system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1576system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram
1577system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1578system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1579system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1580system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1581system.membus.snoop_fanout::total 839 # Request fanout histogram
1582system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks)
1583system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
1584system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks)
1585system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
1586system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter.

1587system.toL2Bus.snoop_filter.hit_single_requests 1097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1588system.toL2Bus.snoop_filter.hit_multi_requests 1878 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1587system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1588system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1589system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1590system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1591system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1592system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
1593system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
1594system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
1595system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution
1596system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
1597system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
1598system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
1599system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution
1600system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution
1601system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
1602system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution
1603system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
1604system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes)
1605system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
1606system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes)
1607system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
1608system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
1609system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes)
1610system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
1611system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes)
1612system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
1613system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
1614system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes)
1615system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1616system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes)
1617system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
1618system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes)
1619system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1620system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes)
1621system.toL2Bus.snoops 1028 # Total snoops (count)
1622system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes)
1623system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram

1624system.toL2Bus.snoop_fanout::mean 1.282631 # Request fanout histogram
1625system.toL2Bus.snoop_fanout::stdev 1.164624 # Request fanout histogram

1624system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram
1625system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram

1626system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1627system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram

1628system.toL2Bus.snoop_fanout::1 771 26.41% 60.74% # Request fanout histogram
1629system.toL2Bus.snoop_fanout::2 465 15.93% 76.67% # Request fanout histogram
1630system.toL2Bus.snoop_fanout::3 681 23.33% 100.00% # Request fanout histogram

1628system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram
1629system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram
1630system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram