Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

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stats.txt (11219:b65d4e878ed2)	stats.txt (11268:8b4b55d79ddd)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000265 # Number of seconds simulated 4sim_ticks 264840500 # Number of ticks simulated 5final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000265 # Number of seconds simulated 4sim_ticks 264840500 # Number of ticks simulated 5final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 154084 # Simulator instruction rate (inst/s) 8host_op_rate 154083 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61608375 # Simulator tick rate (ticks/s) 10host_mem_usage 302100 # Number of bytes of host memory used 11host_seconds 4.30 # Real time elapsed on the host	7host_inst_rate 139043 # Simulator instruction rate (inst/s) 8host_op_rate 139043 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55594555 # Simulator tick rate (ticks/s) 10host_mem_usage 242988 # Number of bytes of host memory used 11host_seconds 4.76 # Real time elapsed on the host
12sim_insts 662366 # Number of instructions simulated 13sim_ops 662366 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls 64system.cpu0.numCycles 529681 # number of cpu cycles simulated 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu0.committedInsts 158238 # Number of instructions committed 68system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured 72system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls 73system.cpu0.num_int_insts 108984 # number of integer instructions 74system.cpu0.num_fp_insts 0 # number of float instructions 75system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read 76system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written 77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 79system.cpu0.num_mem_refs 73853 # number of memory refs 80system.cpu0.num_load_insts 48895 # Number of load instructions 81system.cpu0.num_store_insts 24958 # Number of store instructions 82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 83system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles 84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 86system.cpu0.Branches 26841 # Number of branches fetched 87system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction 88system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction 89system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 90system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 91system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 92system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 93system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 94system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 95system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 96system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 97system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 99system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 100system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 101system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 102system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 103system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 105system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 107system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction 118system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 121system.cpu0.op_class::total 158300 # Class of executed instruction 122system.cpu0.dcache.tags.replacements 2 # number of replacements 123system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 126system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 135system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses 137system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits 141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 143system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits 145system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits 146system.cpu0.dcache.overall_hits::total 73441 # number of overall hits 147system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses 148system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses 149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 153system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses 154system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses 155system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses 156system.cpu0.dcache.overall_misses::total 351 # number of overall misses 157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles 158system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles 159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles 160system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles 161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles 162system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles 163system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles 164system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles 165system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles 166system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles 167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) 171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 173system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses 174system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses 175system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses 176system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses 177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses 178system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses 180system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses 181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses 184system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses 185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses 186system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses 187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency 188system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency 189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency 190system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency 191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency 192system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency 193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency 194system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 203system.cpu0.dcache.fast_writes 0 # number of fast writes performed 204system.cpu0.dcache.cache_copies 0 # number of cache copies performed 205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 206system.cpu0.dcache.writebacks::total 1 # number of writebacks 207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses 208system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses 209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 213system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses 214system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 215system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses 216system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses 217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles 218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles 219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles 220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles 221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles 222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles 223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles 224system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles 225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles 226system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles 227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses 228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses 229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses 230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses 231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses 234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses 235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses 236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses 237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency 238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency 239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency 240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency 241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency 242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency 243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency 244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency 245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency 246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency 247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 248system.cpu0.icache.tags.replacements 215 # number of replacements 249system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use 250system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. 251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 252system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. 253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 254system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor 255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy 256system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy 257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 261system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses 262system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses 263system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits 264system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits 265system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits 266system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits 267system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits 268system.cpu0.icache.overall_hits::total 157834 # number of overall hits 269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 274system.cpu0.icache.overall_misses::total 467 # number of overall misses 275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles 276system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles 277system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles 278system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles 279system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles 280system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles 281system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) 282system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) 283system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses 284system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses 285system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses 286system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses 287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 288system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 290system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 292system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency 294system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency 295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency 296system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency 297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency 298system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency 299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu0.icache.fast_writes 0 # number of fast writes performed 306system.cpu0.icache.cache_copies 0 # number of cache copies performed 307system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 308system.cpu0.icache.writebacks::total 215 # number of writebacks 309system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 310system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 311system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 312system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 313system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 314system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 315system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles 316system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles 317system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles 318system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles 319system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles 320system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles 321system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 322system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 323system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 324system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 325system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 326system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 327system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency 328system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency 329system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency 330system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency 331system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency 332system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency 333system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cpu1.numCycles 529680 # number of cpu cycles simulated 335system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 336system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 337system.cpu1.committedInsts 168829 # Number of instructions committed 338system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed 339system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses 340system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 341system.cpu1.num_func_calls 637 # number of times a function call or return occured 342system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls 343system.cpu1.num_int_insts 111193 # number of integer instructions 344system.cpu1.num_fp_insts 0 # number of float instructions 345system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read 346system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written 347system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 348system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 349system.cpu1.num_mem_refs 54535 # number of memory refs 350system.cpu1.num_load_insts 41264 # Number of load instructions 351system.cpu1.num_store_insts 13271 # Number of store instructions 352system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles 353system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles 354system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles 355system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles 356system.cpu1.Branches 34479 # Number of branches fetched 357system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction 358system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction 359system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction 360system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction 361system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction 362system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction 363system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction 364system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction 365system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction 366system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction 367system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction 368system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction 369system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction 370system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction 371system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction 372system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction 373system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction 374system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction 375system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction 376system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction 377system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction 378system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction 379system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction 380system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction 381system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction 382system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction 383system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction 384system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction 385system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction 386system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction 387system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction 388system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction 389system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 390system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 391system.cpu1.op_class::total 168861 # Class of executed instruction 392system.cpu1.dcache.tags.replacements 0 # number of replacements 393system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use 394system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. 395system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 396system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. 397system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 398system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor 399system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy 400system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy 401system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 402system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 403system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 404system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 405system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses 406system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses 407system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits 408system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits 409system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits 410system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits 411system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 412system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 413system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits 414system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits 415system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits 416system.cpu1.dcache.overall_hits::total 54188 # number of overall hits 417system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses 418system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses 419system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses 420system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses 421system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses 422system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses 423system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses 424system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses 425system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses 426system.cpu1.dcache.overall_misses::total 270 # number of overall misses 427system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles 428system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles 429system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles 430system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles 431system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles 432system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles 433system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles 434system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles 435system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles 436system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles 437system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) 438system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) 439system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses) 440system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses) 441system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) 442system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 443system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses 444system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses 445system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses 446system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses 447system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses 448system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses 449system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses 450system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses 451system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses 452system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses 453system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses 454system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses 455system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses 456system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses 457system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency 458system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency 459system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency 460system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency 461system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency 462system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency 463system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency 464system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency 465system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency 466system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency 467system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 473system.cpu1.dcache.fast_writes 0 # number of fast writes performed 474system.cpu1.dcache.cache_copies 0 # number of cache copies performed 475system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses 476system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 477system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 478system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 479system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses 480system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 481system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses 482system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 483system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses 484system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 485system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles 486system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles 487system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles 488system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles 489system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles 490system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles 491system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles 492system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles 493system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles 494system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles 495system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses 496system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses 497system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses 498system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses 499system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses 500system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses 501system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses 502system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses 503system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses 504system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses 505system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency 506system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency 507system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency 508system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency 509system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency 510system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency 511system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency 512system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency 513system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency 514system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency 515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu1.icache.tags.replacements 280 # number of replacements 517system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use 518system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. 519system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 520system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. 521system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 522system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor 523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy 524system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy 525system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 526system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 527system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 528system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 529system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 530system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses 531system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses 532system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits 533system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits 534system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits 535system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits 536system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits 537system.cpu1.icache.overall_hits::total 168496 # number of overall hits 538system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 539system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 540system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 541system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 542system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 543system.cpu1.icache.overall_misses::total 366 # number of overall misses 544system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles 545system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles 546system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles 547system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles 548system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles 549system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles 550system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) 551system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) 552system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses 553system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses 554system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses 555system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses 556system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses 557system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses 558system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses 559system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses 560system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses 561system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses 562system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency 563system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency 564system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency 565system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency 566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency 567system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency 568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu1.icache.fast_writes 0 # number of fast writes performed 575system.cpu1.icache.cache_copies 0 # number of cache copies performed 576system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 577system.cpu1.icache.writebacks::total 280 # number of writebacks 578system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 579system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 580system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 581system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 582system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 583system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 584system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles 585system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles 586system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles 587system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles 588system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles 589system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles 590system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses 591system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses 592system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses 593system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses 594system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses 595system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses 596system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency 597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency 598system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency 599system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency 600system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency 601system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency 602system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.cpu2.numCycles 529681 # number of cpu cycles simulated 604system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 605system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 606system.cpu2.committedInsts 165415 # Number of instructions committed 607system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed 608system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses 609system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 610system.cpu2.num_func_calls 637 # number of times a function call or return occured 611system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls 612system.cpu2.num_int_insts 110386 # number of integer instructions 613system.cpu2.num_fp_insts 0 # number of float instructions 614system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read 615system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written 616system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 617system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 618system.cpu2.num_mem_refs 55033 # number of memory refs 619system.cpu2.num_load_insts 40858 # Number of load instructions 620system.cpu2.num_store_insts 14175 # Number of store instructions 621system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles 622system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles 623system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles 624system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles 625system.cpu2.Branches 33177 # Number of branches fetched 626system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction 627system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction 628system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction 629system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction 630system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction 631system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction 632system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction 633system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction 634system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction 635system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction 636system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction 637system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction 638system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction 639system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction 640system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction 641system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction 642system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction 643system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction 644system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction 645system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction 646system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction 647system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction 648system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction 649system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction 650system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction 651system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction 652system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction 653system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction 654system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction 655system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction 656system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction 657system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction 658system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 659system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 660system.cpu2.op_class::total 165447 # Class of executed instruction 661system.cpu2.dcache.tags.replacements 0 # number of replacements 662system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use 663system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. 664system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 665system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. 666system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor 668system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy 669system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy 670system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 671system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 672system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 673system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 674system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses 675system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses 676system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits 677system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits 678system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits 679system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits 680system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 681system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 682system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits 683system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits 684system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits 685system.cpu2.dcache.overall_hits::total 54681 # number of overall hits 686system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses 687system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses 688system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses 689system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses 690system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses 691system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses 692system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses 693system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses 694system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses 695system.cpu2.dcache.overall_misses::total 271 # number of overall misses 696system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles 697system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles 698system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles 699system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles 700system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles 701system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles 702system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles 703system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles 704system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles 705system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles 706system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) 707system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) 708system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) 709system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) 710system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) 711system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 712system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses 713system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses 714system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses 715system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses 716system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses 717system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses 718system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses 719system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses 720system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses 721system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 722system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses 723system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses 724system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses 725system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses 726system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency 727system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency 728system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency 729system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency 730system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency 731system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency 732system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency 733system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency 734system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency 735system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency 736system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu2.dcache.fast_writes 0 # number of fast writes performed 743system.cpu2.dcache.cache_copies 0 # number of cache copies performed 744system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses 745system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 746system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 747system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 748system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 749system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 750system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 751system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 752system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 753system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 754system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles 755system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles 756system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles 757system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles 758system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles 759system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles 760system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles 761system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles 762system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles 763system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles 764system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses 765system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses 766system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses 767system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses 768system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses 769system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 770system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses 771system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses 772system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses 773system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses 774system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency 775system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency 776system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency 777system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency 778system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency 779system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 780system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency 781system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency 782system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency 783system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency 784system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu2.icache.tags.replacements 280 # number of replacements 786system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use 787system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. 788system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 789system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. 790system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor 792system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy 793system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy 794system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 795system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 796system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 797system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 798system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 799system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses 800system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses 801system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits 802system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits 803system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits 804system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits 805system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits 806system.cpu2.icache.overall_hits::total 165082 # number of overall hits 807system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 808system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 809system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 810system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 811system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 812system.cpu2.icache.overall_misses::total 366 # number of overall misses 813system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles 814system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles 815system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles 816system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles 817system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles 818system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles 819system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) 820system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) 821system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses 822system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses 823system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses 824system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses 825system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses 826system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses 827system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses 828system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses 829system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses 830system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses 831system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency 832system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency 833system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency 834system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency 835system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency 836system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency 837system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 843system.cpu2.icache.fast_writes 0 # number of fast writes performed 844system.cpu2.icache.cache_copies 0 # number of cache copies performed 845system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 846system.cpu2.icache.writebacks::total 280 # number of writebacks 847system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 848system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 849system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 850system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 851system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 852system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 853system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles 854system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles 855system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles 856system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles 857system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles 858system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles 859system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses 860system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses 861system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses 862system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses 863system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses 864system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses 865system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency 866system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency 867system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency 868system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency 869system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency 870system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency 871system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 872system.cpu3.numCycles 529680 # number of cpu cycles simulated 873system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 874system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 875system.cpu3.committedInsts 169884 # Number of instructions committed 876system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed 877system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses 878system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 879system.cpu3.num_func_calls 637 # number of times a function call or return occured 880system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls 881system.cpu3.num_int_insts 110793 # number of integer instructions 882system.cpu3.num_fp_insts 0 # number of float instructions 883system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read 884system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written 885system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 886system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 887system.cpu3.num_mem_refs 53409 # number of memory refs 888system.cpu3.num_load_insts 41060 # Number of load instructions 889system.cpu3.num_store_insts 12349 # Number of store instructions 890system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles 891system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles 892system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles 893system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles 894system.cpu3.Branches 35208 # Number of branches fetched 895system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction 896system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction 897system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction 898system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction 899system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction 900system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction 901system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction 902system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction 903system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction 904system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction 905system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction 906system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction 907system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction 908system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction 909system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction 910system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction 911system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction 912system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction 913system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction 914system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction 915system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction 916system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction 917system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction 918system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction 919system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction 920system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction 921system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction 922system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 923system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 924system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 925system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction 926system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction 927system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 928system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 929system.cpu3.op_class::total 169916 # Class of executed instruction 930system.cpu3.dcache.tags.replacements 0 # number of replacements 931system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use 932system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. 933system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 934system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. 935system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 936system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor 937system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy 938system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy 939system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 940system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 941system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 942system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 943system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses 944system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses 945system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits 946system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits 947system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits 948system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits 949system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 950system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 951system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits 952system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits 953system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits 954system.cpu3.dcache.overall_hits::total 53061 # number of overall hits 955system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses 956system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses 957system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses 958system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses 959system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses 960system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses 961system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 962system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 963system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 964system.cpu3.dcache.overall_misses::total 268 # number of overall misses 965system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles 966system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles 967system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles 968system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles 969system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles 970system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles 971system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles 972system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles 973system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles 974system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles 975system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) 976system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) 977system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) 978system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) 979system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 980system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 981system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses 982system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses 983system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses 984system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses 985system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses 986system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses 987system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses 988system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses 989system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses 990system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 991system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses 992system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses 993system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses 994system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses 995system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency 996system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency 997system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency 998system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency 999system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency 1000system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency 1001system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency 1002system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency 1003system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency 1004system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency 1005system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1009system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1011system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1013system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses 1014system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1015system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 1016system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1017system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses 1018system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1019system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 1020system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1021system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 1022system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1023system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles 1024system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles 1025system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles 1026system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles 1027system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles 1028system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles 1029system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles 1030system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles 1031system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles 1032system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles 1033system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses 1034system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses 1035system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses 1036system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses 1037system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses 1038system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1039system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses 1040system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses 1041system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses 1042system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses 1043system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency 1044system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency 1045system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency 1046system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency 1047system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency 1048system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency 1049system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency 1050system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency 1051system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency 1052system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency 1053system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1054system.cpu3.icache.tags.replacements 281 # number of replacements 1055system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use 1056system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. 1057system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1058system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. 1059system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1060system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor 1061system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy 1062system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy 1063system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1064system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1065system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1066system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1067system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1068system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses 1069system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses 1070system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits 1071system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits 1072system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits 1073system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits 1074system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits 1075system.cpu3.icache.overall_hits::total 169550 # number of overall hits 1076system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1077system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1078system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1079system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1080system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1081system.cpu3.icache.overall_misses::total 367 # number of overall misses 1082system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5473500 # number of ReadReq miss cycles 1083system.cpu3.icache.ReadReq_miss_latency::total 5473500 # number of ReadReq miss cycles 1084system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 # number of demand (read+write) miss cycles 1085system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles 1086system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles 1087system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles 1088system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) 1089system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) 1090system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses 1091system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses 1092system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses 1093system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses 1094system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses 1095system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses 1096system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses 1097system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses 1098system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses 1099system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses 1100system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency 1101system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency 1102system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1103system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency 1104system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1105system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency 1106system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1107system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1108system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1109system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1110system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1111system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1112system.cpu3.icache.fast_writes 0 # number of fast writes performed 1113system.cpu3.icache.cache_copies 0 # number of cache copies performed 1114system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1115system.cpu3.icache.writebacks::total 281 # number of writebacks 1116system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1117system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1118system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1119system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1120system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1121system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1122system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5106500 # number of ReadReq MSHR miss cycles 1123system.cpu3.icache.ReadReq_mshr_miss_latency::total 5106500 # number of ReadReq MSHR miss cycles 1124system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 # number of demand (read+write) MSHR miss cycles 1125system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles 1126system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles 1127system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles 1128system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses 1129system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses 1130system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses 1131system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses 1132system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses 1133system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses 1134system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency 1135system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency 1136system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1137system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1138system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1139system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1140system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.l2c.tags.replacements 0 # number of replacements 1142system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use 1143system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1144system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1145system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1146system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1147system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor 1148system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor 1149system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor 1150system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor 1151system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor 1152system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor 1153system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor 1154system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor 1155system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor 1156system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 1157system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy 1158system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy 1159system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy 1160system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 1161system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy 1162system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy 1163system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy 1164system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1165system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy 1166system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1167system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1168system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1169system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 1170system.l2c.tags.tag_accesses 19669 # Number of tag accesses 1171system.l2c.tags.data_accesses 19669 # Number of data accesses 1172system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1173system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1174system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1175system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1176system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1177system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1178system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1179system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1180system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 1181system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 1182system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 1183system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 1184system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 1185system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 1186system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 1187system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 1188system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 1189system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 1190system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 1191system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 1192system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 1193system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 1194system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 1195system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 1196system.l2c.demand_hits::total 1218 # number of demand (read+write) hits 1197system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 1198system.l2c.overall_hits::cpu0.data 5 # number of overall hits 1199system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1200system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1201system.l2c.overall_hits::cpu2.inst 301 # number of overall hits 1202system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1203system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 1204system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1205system.l2c.overall_hits::total 1218 # number of overall hits 1206system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 1207system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 1208system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 1209system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses 1210system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 1211system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1212system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1213system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1214system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1215system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1216system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1217system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1218system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 1219system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 1220system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 1221system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 1222system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 1223system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 1224system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 1225system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 1226system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1227system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1228system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 1229system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 1230system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 1231system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 1232system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 1233system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 1234system.l2c.demand_misses::total 594 # number of demand (read+write) misses 1235system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1236system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1237system.l2c.overall_misses::cpu1.inst 14 # number of overall misses 1238system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1239system.l2c.overall_misses::cpu2.inst 65 # number of overall misses 1240system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1241system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 1242system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1243system.l2c.overall_misses::total 594 # number of overall misses 1244system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles 1245system.l2c.ReadExReq_miss_latency::cpu1.data 842000 # number of ReadExReq miss cycles 1246system.l2c.ReadExReq_miss_latency::cpu2.data 896000 # number of ReadExReq miss cycles 1247system.l2c.ReadExReq_miss_latency::cpu3.data 840000 # number of ReadExReq miss cycles 1248system.l2c.ReadExReq_miss_latency::total 8470000 # number of ReadExReq miss cycles 1249system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16964000 # number of ReadCleanReq miss cycles 1250system.l2c.ReadCleanReq_miss_latency::cpu1.inst 821500 # number of ReadCleanReq miss cycles 1251system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3820000 # number of ReadCleanReq miss cycles 1252system.l2c.ReadCleanReq_miss_latency::cpu3.inst 553500 # number of ReadCleanReq miss cycles 1253system.l2c.ReadCleanReq_miss_latency::total 22159000 # number of ReadCleanReq miss cycles 1254system.l2c.ReadSharedReq_miss_latency::cpu0.data 3927500 # number of ReadSharedReq miss cycles 1255system.l2c.ReadSharedReq_miss_latency::cpu1.data 118500 # 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number of demand (read+write) miss cycles 1267system.l2c.demand_miss_latency::total 35269000 # number of demand (read+write) miss cycles 1268system.l2c.overall_miss_latency::cpu0.inst 16964000 # number of overall miss cycles 1269system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles 1270system.l2c.overall_miss_latency::cpu1.inst 821500 # number of overall miss cycles 1271system.l2c.overall_miss_latency::cpu1.data 960500 # number of overall miss cycles 1272system.l2c.overall_miss_latency::cpu2.inst 3820000 # number of overall miss cycles 1273system.l2c.overall_miss_latency::cpu2.data 1372000 # number of overall miss cycles 1274system.l2c.overall_miss_latency::cpu3.inst 553500 # number of overall miss cycles 1275system.l2c.overall_miss_latency::cpu3.data 958000 # number of overall miss cycles 1276system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles 1277system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 1278system.l2c.WritebackDirty_accesses::total 1 # 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number of overall MSHR miss cycles 1485system.l2c.overall_mshr_miss_latency::cpu0.data 8169500 # number of overall MSHR miss cycles 1486system.l2c.overall_mshr_miss_latency::cpu1.inst 351500 # number of overall MSHR miss cycles 1487system.l2c.overall_mshr_miss_latency::cpu1.data 751500 # number of overall MSHR miss cycles 1488system.l2c.overall_mshr_miss_latency::cpu2.inst 2872000 # number of overall MSHR miss cycles 1489system.l2c.overall_mshr_miss_latency::cpu2.data 1142000 # number of overall MSHR miss cycles 1490system.l2c.overall_mshr_miss_latency::cpu3.inst 199000 # number of overall MSHR miss cycles 1491system.l2c.overall_mshr_miss_latency::cpu3.data 749500 # number of overall MSHR miss cycles 1492system.l2c.overall_mshr_miss_latency::total 28349000 # number of overall MSHR miss cycles 1493system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 1494system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 1495system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 1496system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 1497system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses 1498system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 1499system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 1500system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 1501system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 1502system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1503system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses 1504system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses 1505system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses 1506system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses 1507system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses 1508system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses 1509system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1510system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses 1511system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses 1512system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses 1513system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 1514system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 1515system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses 1516system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses 1517system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses 1518system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses 1519system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for demand accesses 1520system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses 1521system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 1522system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 1523system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1524system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses 1525system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1526system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 1527system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 1528system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses 1529system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1530system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1531system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286 # average UpgradeReq mshr miss latency 1532system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000 # average UpgradeReq mshr miss latency 1533system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706 # average UpgradeReq mshr miss latency 1534system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500 # average UpgradeReq mshr miss latency 1535system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474 # average UpgradeReq mshr miss latency 1536system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency 1537system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143 # average ReadExReq mshr miss latency 1538system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333 # average ReadExReq mshr miss latency 1539system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50000 # average ReadExReq mshr miss latency 1540system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324 # average ReadExReq mshr miss latency 1541system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average ReadCleanReq mshr miss latency 1542system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average ReadCleanReq mshr miss latency 1543system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average ReadCleanReq mshr miss latency 1544system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49750 # average ReadCleanReq mshr miss latency 1545system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593 # average ReadCleanReq mshr miss latency 1546system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency 1547system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency 1548system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency 1549system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency 1550system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency 1551system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency 1552system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1553system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency 1554system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency 1555system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency 1556system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency 1557system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency 1558system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency 1559system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency 1560system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency 1561system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1562system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency 1563system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency 1564system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency 1565system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency 1566system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency 1567system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency 1568system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency 1569system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1570system.membus.trans_dist::ReadResp 430 # Transaction distribution 1571system.membus.trans_dist::UpgradeReq 271 # Transaction distribution 1572system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 1573system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1574system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1575system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1576system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) 1578system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.snoops 261 # Total snoops (count) 1581system.membus.snoop_fanout::samples 915 # Request fanout histogram 1582system.membus.snoop_fanout::mean 0 # Request fanout histogram 1583system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1584system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1585system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram 1586system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1587system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1588system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1589system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1590system.membus.snoop_fanout::total 915 # Request fanout histogram 1591system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) 1592system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 1593system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) 1594system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1595system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. 1596system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1597system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1598system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1599system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1600system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1601system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution 1602system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1603system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution 1604system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1605system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution 1606system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution 1607system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution 1608system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution 1609system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 1610system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution 1611system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) 1612system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) 1613system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) 1614system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 1615system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) 1616system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) 1617system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) 1618system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 1619system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) 1620system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) 1621system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1622system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) 1623system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1624system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) 1625system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1626system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) 1627system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1628system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) 1629system.toL2Bus.snoops 1032 # Total snoops (count) 1630system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram 1631system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram 1632system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram 1633system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1634system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram 1635system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram 1636system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram 1637system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram 1638system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1639system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1640system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1641system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1642system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1643system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1644system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1645system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1646system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram 1647system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) 1648system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1649system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) 1650system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1651system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) 1652system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1653system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) 1654system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 1655system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) 1656system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1657system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 1658system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 1659system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) 1660system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1661system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) 1662system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1663system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) 1664system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1665 1666---------- End Simulation Statistics ----------	12sim_insts 662366 # Number of instructions simulated 13sim_ops 662366 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls 64system.cpu0.numCycles 529681 # number of cpu cycles simulated 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu0.committedInsts 158238 # Number of instructions committed 68system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured 72system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls 73system.cpu0.num_int_insts 108984 # number of integer instructions 74system.cpu0.num_fp_insts 0 # number of float instructions 75system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read 76system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written 77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 79system.cpu0.num_mem_refs 73853 # number of memory refs 80system.cpu0.num_load_insts 48895 # Number of load instructions 81system.cpu0.num_store_insts 24958 # Number of store instructions 82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 83system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles 84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 86system.cpu0.Branches 26841 # Number of branches fetched 87system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction 88system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction 89system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction 90system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction 91system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction 92system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction 93system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction 94system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction 95system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction 96system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction 97system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction 98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction 99system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction 100system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction 101system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction 102system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction 103system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction 104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction 105system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction 106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction 107system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction 108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction 109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction 110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction 111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction 112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction 113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction 114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction 117system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction 118system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 121system.cpu0.op_class::total 158300 # Class of executed instruction 122system.cpu0.dcache.tags.replacements 2 # number of replacements 123system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 126system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 135system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses 137system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits 141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 143system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits 145system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits 146system.cpu0.dcache.overall_hits::total 73441 # number of overall hits 147system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses 148system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses 149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 153system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses 154system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses 155system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses 156system.cpu0.dcache.overall_misses::total 351 # number of overall misses 157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles 158system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles 159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles 160system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles 161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles 162system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles 163system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles 164system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles 165system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles 166system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles 167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) 171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 173system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses 174system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses 175system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses 176system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses 177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses 178system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses 180system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses 181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses 184system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses 185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses 186system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses 187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency 188system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency 189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency 190system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency 191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency 192system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency 193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency 194system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency 195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency 196system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency 197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 203system.cpu0.dcache.fast_writes 0 # number of fast writes performed 204system.cpu0.dcache.cache_copies 0 # number of cache copies performed 205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 206system.cpu0.dcache.writebacks::total 1 # number of writebacks 207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses 208system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses 209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 213system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses 214system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 215system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses 216system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses 217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles 218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles 219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles 220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles 221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles 222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles 223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles 224system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles 225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles 226system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles 227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses 228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses 229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses 230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses 231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses 234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses 235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses 236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses 237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency 238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency 239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency 240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency 241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency 242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency 243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency 244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency 245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency 246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency 247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 248system.cpu0.icache.tags.replacements 215 # number of replacements 249system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use 250system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. 251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 252system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. 253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 254system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor 255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy 256system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy 257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 261system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses 262system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses 263system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits 264system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits 265system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits 266system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits 267system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits 268system.cpu0.icache.overall_hits::total 157834 # number of overall hits 269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 274system.cpu0.icache.overall_misses::total 467 # number of overall misses 275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles 276system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles 277system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles 278system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles 279system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles 280system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles 281system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) 282system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) 283system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses 284system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses 285system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses 286system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses 287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses 288system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses 289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses 290system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses 291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses 292system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses 293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency 294system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency 295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency 296system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency 297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency 298system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency 299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu0.icache.fast_writes 0 # number of fast writes performed 306system.cpu0.icache.cache_copies 0 # number of cache copies performed 307system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 308system.cpu0.icache.writebacks::total 215 # number of writebacks 309system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 310system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 311system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 312system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 313system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 314system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 315system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles 316system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles 317system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles 318system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles 319system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles 320system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles 321system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses 322system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses 323system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses 324system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses 325system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses 326system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses 327system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency 328system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency 329system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency 330system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency 331system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency 332system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency 333system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cpu1.numCycles 529680 # number of cpu cycles simulated 335system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 336system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 337system.cpu1.committedInsts 168829 # Number of instructions committed 338system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed 339system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses 340system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 341system.cpu1.num_func_calls 637 # number of times a function call or return occured 342system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls 343system.cpu1.num_int_insts 111193 # number of integer instructions 344system.cpu1.num_fp_insts 0 # number of float instructions 345system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read 346system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written 347system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 348system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 349system.cpu1.num_mem_refs 54535 # number of memory refs 350system.cpu1.num_load_insts 41264 # Number of load instructions 351system.cpu1.num_store_insts 13271 # Number of store instructions 352system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles 353system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles 354system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles 355system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles 356system.cpu1.Branches 34479 # Number of branches fetched 357system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction 358system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction 359system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction 360system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction 361system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction 362system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction 363system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction 364system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction 365system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction 366system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction 367system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction 368system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction 369system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction 370system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction 371system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction 372system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction 373system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction 374system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction 375system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction 376system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction 377system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction 378system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction 379system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction 380system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction 381system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction 382system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction 383system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction 384system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction 385system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction 386system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction 387system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction 388system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction 389system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 390system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 391system.cpu1.op_class::total 168861 # Class of executed instruction 392system.cpu1.dcache.tags.replacements 0 # number of replacements 393system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use 394system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. 395system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 396system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. 397system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 398system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor 399system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy 400system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy 401system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 402system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 403system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 404system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 405system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses 406system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses 407system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits 408system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits 409system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits 410system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits 411system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 412system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 413system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits 414system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits 415system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits 416system.cpu1.dcache.overall_hits::total 54188 # number of overall hits 417system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses 418system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses 419system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses 420system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses 421system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses 422system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses 423system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses 424system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses 425system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses 426system.cpu1.dcache.overall_misses::total 270 # number of overall misses 427system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles 428system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles 429system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles 430system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles 431system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles 432system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles 433system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles 434system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles 435system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles 436system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles 437system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) 438system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) 439system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses) 440system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses) 441system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) 442system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 443system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses 444system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses 445system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses 446system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses 447system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses 448system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses 449system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses 450system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses 451system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses 452system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses 453system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses 454system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses 455system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses 456system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses 457system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency 458system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency 459system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency 460system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency 461system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency 462system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency 463system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency 464system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency 465system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency 466system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency 467system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 473system.cpu1.dcache.fast_writes 0 # number of fast writes performed 474system.cpu1.dcache.cache_copies 0 # number of cache copies performed 475system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses 476system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 477system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 478system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 479system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses 480system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 481system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses 482system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 483system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses 484system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 485system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles 486system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles 487system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles 488system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles 489system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles 490system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles 491system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles 492system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles 493system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles 494system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles 495system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses 496system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses 497system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses 498system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses 499system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses 500system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses 501system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses 502system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses 503system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses 504system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses 505system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency 506system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency 507system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency 508system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency 509system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency 510system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency 511system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency 512system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency 513system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency 514system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency 515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu1.icache.tags.replacements 280 # number of replacements 517system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use 518system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. 519system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 520system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. 521system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 522system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor 523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy 524system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy 525system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 526system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 527system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 528system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 529system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 530system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses 531system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses 532system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits 533system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits 534system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits 535system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits 536system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits 537system.cpu1.icache.overall_hits::total 168496 # number of overall hits 538system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 539system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 540system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 541system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 542system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 543system.cpu1.icache.overall_misses::total 366 # number of overall misses 544system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles 545system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles 546system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles 547system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles 548system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles 549system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles 550system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) 551system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) 552system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses 553system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses 554system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses 555system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses 556system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses 557system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses 558system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses 559system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses 560system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses 561system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses 562system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency 563system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency 564system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency 565system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency 566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency 567system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency 568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu1.icache.fast_writes 0 # number of fast writes performed 575system.cpu1.icache.cache_copies 0 # number of cache copies performed 576system.cpu1.icache.writebacks::writebacks 280 # number of writebacks 577system.cpu1.icache.writebacks::total 280 # number of writebacks 578system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 579system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 580system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 581system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 582system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 583system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 584system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles 585system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles 586system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles 587system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles 588system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles 589system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles 590system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses 591system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses 592system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses 593system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses 594system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses 595system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses 596system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency 597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency 598system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency 599system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency 600system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency 601system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency 602system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.cpu2.numCycles 529681 # number of cpu cycles simulated 604system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 605system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 606system.cpu2.committedInsts 165415 # Number of instructions committed 607system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed 608system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses 609system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 610system.cpu2.num_func_calls 637 # number of times a function call or return occured 611system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls 612system.cpu2.num_int_insts 110386 # number of integer instructions 613system.cpu2.num_fp_insts 0 # number of float instructions 614system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read 615system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written 616system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 617system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 618system.cpu2.num_mem_refs 55033 # number of memory refs 619system.cpu2.num_load_insts 40858 # Number of load instructions 620system.cpu2.num_store_insts 14175 # Number of store instructions 621system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles 622system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles 623system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles 624system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles 625system.cpu2.Branches 33177 # Number of branches fetched 626system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction 627system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction 628system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction 629system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction 630system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction 631system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction 632system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction 633system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction 634system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction 635system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction 636system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction 637system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction 638system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction 639system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction 640system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction 641system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction 642system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction 643system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction 644system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction 645system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction 646system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction 647system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction 648system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction 649system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction 650system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction 651system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction 652system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction 653system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction 654system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction 655system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction 656system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction 657system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction 658system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 659system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 660system.cpu2.op_class::total 165447 # Class of executed instruction 661system.cpu2.dcache.tags.replacements 0 # number of replacements 662system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use 663system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. 664system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 665system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. 666system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor 668system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy 669system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy 670system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 671system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 672system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 673system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 674system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses 675system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses 676system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits 677system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits 678system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits 679system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits 680system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 681system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 682system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits 683system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits 684system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits 685system.cpu2.dcache.overall_hits::total 54681 # number of overall hits 686system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses 687system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses 688system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses 689system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses 690system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses 691system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses 692system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses 693system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses 694system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses 695system.cpu2.dcache.overall_misses::total 271 # number of overall misses 696system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles 697system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles 698system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles 699system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles 700system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles 701system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles 702system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles 703system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles 704system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles 705system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles 706system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) 707system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) 708system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) 709system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) 710system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) 711system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 712system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses 713system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses 714system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses 715system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses 716system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses 717system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses 718system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses 719system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses 720system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses 721system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 722system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses 723system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses 724system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses 725system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses 726system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency 727system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency 728system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency 729system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency 730system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency 731system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency 732system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency 733system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency 734system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency 735system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency 736system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu2.dcache.fast_writes 0 # number of fast writes performed 743system.cpu2.dcache.cache_copies 0 # number of cache copies performed 744system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses 745system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 746system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 747system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 748system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 749system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 750system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 751system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 752system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 753system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 754system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles 755system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles 756system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles 757system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles 758system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles 759system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles 760system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles 761system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles 762system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles 763system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles 764system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses 765system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses 766system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses 767system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses 768system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses 769system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 770system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses 771system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses 772system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses 773system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses 774system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency 775system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency 776system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency 777system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency 778system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency 779system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency 780system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency 781system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency 782system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency 783system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency 784system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cpu2.icache.tags.replacements 280 # number of replacements 786system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use 787system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. 788system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 789system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. 790system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 791system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor 792system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy 793system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy 794system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 795system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 796system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 797system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 798system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 799system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses 800system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses 801system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits 802system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits 803system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits 804system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits 805system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits 806system.cpu2.icache.overall_hits::total 165082 # number of overall hits 807system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 808system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 809system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 810system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 811system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 812system.cpu2.icache.overall_misses::total 366 # number of overall misses 813system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles 814system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles 815system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles 816system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles 817system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles 818system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles 819system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) 820system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) 821system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses 822system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses 823system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses 824system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses 825system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses 826system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses 827system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses 828system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses 829system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses 830system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses 831system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency 832system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency 833system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency 834system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency 835system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency 836system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency 837system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 843system.cpu2.icache.fast_writes 0 # number of fast writes performed 844system.cpu2.icache.cache_copies 0 # number of cache copies performed 845system.cpu2.icache.writebacks::writebacks 280 # number of writebacks 846system.cpu2.icache.writebacks::total 280 # number of writebacks 847system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 848system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 849system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 850system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 851system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 852system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 853system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles 854system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles 855system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles 856system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles 857system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles 858system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles 859system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses 860system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses 861system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses 862system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses 863system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses 864system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses 865system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency 866system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency 867system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency 868system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency 869system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency 870system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency 871system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 872system.cpu3.numCycles 529680 # number of cpu cycles simulated 873system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 874system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 875system.cpu3.committedInsts 169884 # Number of instructions committed 876system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed 877system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses 878system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 879system.cpu3.num_func_calls 637 # number of times a function call or return occured 880system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls 881system.cpu3.num_int_insts 110793 # number of integer instructions 882system.cpu3.num_fp_insts 0 # number of float instructions 883system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read 884system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written 885system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 886system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 887system.cpu3.num_mem_refs 53409 # number of memory refs 888system.cpu3.num_load_insts 41060 # Number of load instructions 889system.cpu3.num_store_insts 12349 # Number of store instructions 890system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles 891system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles 892system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles 893system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles 894system.cpu3.Branches 35208 # Number of branches fetched 895system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction 896system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction 897system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction 898system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction 899system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction 900system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction 901system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction 902system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction 903system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction 904system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction 905system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction 906system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction 907system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction 908system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction 909system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction 910system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction 911system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction 912system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction 913system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction 914system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction 915system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction 916system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction 917system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction 918system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction 919system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction 920system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction 921system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction 922system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction 923system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction 924system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction 925system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction 926system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction 927system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 928system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 929system.cpu3.op_class::total 169916 # Class of executed instruction 930system.cpu3.dcache.tags.replacements 0 # number of replacements 931system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use 932system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. 933system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 934system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. 935system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 936system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor 937system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy 938system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy 939system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 940system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 941system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 942system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 943system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses 944system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses 945system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits 946system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits 947system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits 948system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits 949system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 950system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 951system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits 952system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits 953system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits 954system.cpu3.dcache.overall_hits::total 53061 # number of overall hits 955system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses 956system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses 957system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses 958system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses 959system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses 960system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses 961system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses 962system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses 963system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses 964system.cpu3.dcache.overall_misses::total 268 # number of overall misses 965system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles 966system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles 967system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles 968system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles 969system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles 970system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles 971system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles 972system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles 973system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles 974system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles 975system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) 976system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) 977system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) 978system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) 979system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 980system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 981system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses 982system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses 983system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses 984system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses 985system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses 986system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses 987system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses 988system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses 989system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses 990system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 991system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses 992system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses 993system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses 994system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses 995system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency 996system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency 997system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency 998system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency 999system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency 1000system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency 1001system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency 1002system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency 1003system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency 1004system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency 1005system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1009system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1011system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1013system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses 1014system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1015system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 1016system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1017system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses 1018system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1019system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses 1020system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1021system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses 1022system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1023system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles 1024system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles 1025system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles 1026system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles 1027system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles 1028system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles 1029system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles 1030system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles 1031system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles 1032system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles 1033system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses 1034system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses 1035system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses 1036system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses 1037system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses 1038system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1039system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses 1040system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses 1041system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses 1042system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses 1043system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency 1044system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency 1045system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency 1046system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency 1047system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency 1048system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency 1049system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency 1050system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency 1051system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency 1052system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency 1053system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1054system.cpu3.icache.tags.replacements 281 # number of replacements 1055system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use 1056system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. 1057system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1058system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. 1059system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1060system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor 1061system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy 1062system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy 1063system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1064system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1065system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1066system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1067system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1068system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses 1069system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses 1070system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits 1071system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits 1072system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits 1073system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits 1074system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits 1075system.cpu3.icache.overall_hits::total 169550 # number of overall hits 1076system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1077system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1078system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1079system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1080system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1081system.cpu3.icache.overall_misses::total 367 # number of overall misses 1082system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5473500 # number of ReadReq miss cycles 1083system.cpu3.icache.ReadReq_miss_latency::total 5473500 # number of ReadReq miss cycles 1084system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 # number of demand (read+write) miss cycles 1085system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles 1086system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles 1087system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles 1088system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) 1089system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) 1090system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses 1091system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses 1092system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses 1093system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses 1094system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses 1095system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses 1096system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses 1097system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses 1098system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses 1099system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses 1100system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency 1101system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency 1102system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1103system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency 1104system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency 1105system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency 1106system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1107system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1108system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1109system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1110system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1111system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1112system.cpu3.icache.fast_writes 0 # number of fast writes performed 1113system.cpu3.icache.cache_copies 0 # number of cache copies performed 1114system.cpu3.icache.writebacks::writebacks 281 # number of writebacks 1115system.cpu3.icache.writebacks::total 281 # number of writebacks 1116system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1117system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1118system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1119system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1120system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1121system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1122system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5106500 # number of ReadReq MSHR miss cycles 1123system.cpu3.icache.ReadReq_mshr_miss_latency::total 5106500 # number of ReadReq MSHR miss cycles 1124system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 # number of demand (read+write) MSHR miss cycles 1125system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles 1126system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles 1127system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles 1128system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses 1129system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses 1130system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses 1131system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses 1132system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses 1133system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses 1134system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency 1135system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency 1136system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1137system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1138system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency 1139system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency 1140system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.l2c.tags.replacements 0 # number of replacements 1142system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use 1143system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. 1144system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 1145system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. 1146system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1147system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor 1148system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor 1149system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor 1150system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor 1151system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor 1152system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor 1153system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor 1154system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor 1155system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor 1156system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 1157system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy 1158system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy 1159system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy 1160system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy 1161system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy 1162system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy 1163system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy 1164system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 1165system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy 1166system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 1167system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1168system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 1169system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 1170system.l2c.tags.tag_accesses 19669 # Number of tag accesses 1171system.l2c.tags.data_accesses 19669 # Number of data accesses 1172system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 1173system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 1174system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 1175system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 1176system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1177system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1178system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits 1179system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits 1180system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits 1181system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits 1182system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits 1183system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 1184system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits 1185system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits 1186system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 1187system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 1188system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 1189system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 1190system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits 1191system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits 1192system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits 1193system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits 1194system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 1195system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 1196system.l2c.demand_hits::total 1218 # number of demand (read+write) hits 1197system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 1198system.l2c.overall_hits::cpu0.data 5 # number of overall hits 1199system.l2c.overall_hits::cpu1.inst 352 # number of overall hits 1200system.l2c.overall_hits::cpu1.data 9 # number of overall hits 1201system.l2c.overall_hits::cpu2.inst 301 # number of overall hits 1202system.l2c.overall_hits::cpu2.data 3 # number of overall hits 1203system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 1204system.l2c.overall_hits::cpu3.data 9 # number of overall hits 1205system.l2c.overall_hits::total 1218 # number of overall hits 1206system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 1207system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 1208system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 1209system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses 1210system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 1211system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 1212system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses 1213system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses 1214system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 1215system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 1216system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses 1217system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses 1218system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses 1219system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses 1220system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses 1221system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 1222system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 1223system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 1224system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 1225system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses 1226system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 1227system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 1228system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses 1229system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses 1230system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses 1231system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses 1232system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 1233system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 1234system.l2c.demand_misses::total 594 # number of demand (read+write) misses 1235system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 1236system.l2c.overall_misses::cpu0.data 165 # number of overall misses 1237system.l2c.overall_misses::cpu1.inst 14 # number of overall misses 1238system.l2c.overall_misses::cpu1.data 16 # number of overall misses 1239system.l2c.overall_misses::cpu2.inst 65 # number of overall misses 1240system.l2c.overall_misses::cpu2.data 23 # number of overall misses 1241system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 1242system.l2c.overall_misses::cpu3.data 16 # number of overall misses 1243system.l2c.overall_misses::total 594 # number of overall misses 1244system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles 1245system.l2c.ReadExReq_miss_latency::cpu1.data 842000 # number of ReadExReq miss cycles 1246system.l2c.ReadExReq_miss_latency::cpu2.data 896000 # number of ReadExReq miss cycles 1247system.l2c.ReadExReq_miss_latency::cpu3.data 840000 # number of ReadExReq miss cycles 1248system.l2c.ReadExReq_miss_latency::total 8470000 # number of ReadExReq miss cycles 1249system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16964000 # number of ReadCleanReq miss cycles 1250system.l2c.ReadCleanReq_miss_latency::cpu1.inst 821500 # number of ReadCleanReq miss cycles 1251system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3820000 # number of ReadCleanReq miss cycles 1252system.l2c.ReadCleanReq_miss_latency::cpu3.inst 553500 # number of ReadCleanReq miss cycles 1253system.l2c.ReadCleanReq_miss_latency::total 22159000 # number of ReadCleanReq miss cycles 1254system.l2c.ReadSharedReq_miss_latency::cpu0.data 3927500 # number of ReadSharedReq miss cycles 1255system.l2c.ReadSharedReq_miss_latency::cpu1.data 118500 # number of ReadSharedReq miss cycles 1256system.l2c.ReadSharedReq_miss_latency::cpu2.data 476000 # number of ReadSharedReq miss cycles 1257system.l2c.ReadSharedReq_miss_latency::cpu3.data 118000 # number of ReadSharedReq miss cycles 1258system.l2c.ReadSharedReq_miss_latency::total 4640000 # number of ReadSharedReq miss cycles 1259system.l2c.demand_miss_latency::cpu0.inst 16964000 # number of demand (read+write) miss cycles 1260system.l2c.demand_miss_latency::cpu0.data 9819500 # number of demand (read+write) miss cycles 1261system.l2c.demand_miss_latency::cpu1.inst 821500 # number of demand (read+write) miss cycles 1262system.l2c.demand_miss_latency::cpu1.data 960500 # number of demand (read+write) miss cycles 1263system.l2c.demand_miss_latency::cpu2.inst 3820000 # number of demand (read+write) miss cycles 1264system.l2c.demand_miss_latency::cpu2.data 1372000 # number of demand (read+write) miss cycles 1265system.l2c.demand_miss_latency::cpu3.inst 553500 # number of demand (read+write) miss cycles 1266system.l2c.demand_miss_latency::cpu3.data 958000 # number of demand (read+write) miss cycles 1267system.l2c.demand_miss_latency::total 35269000 # number of demand (read+write) miss cycles 1268system.l2c.overall_miss_latency::cpu0.inst 16964000 # number of overall miss cycles 1269system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles 1270system.l2c.overall_miss_latency::cpu1.inst 821500 # number of overall miss cycles 1271system.l2c.overall_miss_latency::cpu1.data 960500 # number of overall miss cycles 1272system.l2c.overall_miss_latency::cpu2.inst 3820000 # number of overall miss cycles 1273system.l2c.overall_miss_latency::cpu2.data 1372000 # number of overall miss cycles 1274system.l2c.overall_miss_latency::cpu3.inst 553500 # number of overall miss cycles 1275system.l2c.overall_miss_latency::cpu3.data 958000 # number of overall miss cycles 1276system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles 1277system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 1278system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 1279system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 1280system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 1281system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 1282system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) 1283system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 1284system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) 1285system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) 1286system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 1287system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) 1288system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) 1289system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 1290system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 1291system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 1292system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) 1293system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) 1294system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) 1295system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) 1296system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 1297system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) 1298system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) 1299system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) 1300system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) 1301system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 1302system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 1303system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 1304system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 1305system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 1306system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 1307system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 1308system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 1309system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 1310system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 1311system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 1312system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 1313system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 1314system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 1315system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 1316system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 1317system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 1318system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 1319system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 1320system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1321system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 1322system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 1323system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses 1324system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 1325system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 1326system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 1327system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 1328system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1329system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses 1330system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses 1331system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # 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mshr miss rate for overall accesses 1523system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 1524system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses 1525system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses 1526system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses 1527system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses 1528system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses 1529system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses 1530system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 1531system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286 # average UpgradeReq mshr miss latency 1532system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000 # average UpgradeReq mshr miss latency 1533system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706 # average UpgradeReq mshr miss latency 1534system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500 # average UpgradeReq mshr miss latency 1535system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474 # average UpgradeReq mshr miss latency 1536system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency 1537system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143 # average ReadExReq mshr miss latency 1538system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333 # average ReadExReq mshr miss latency 1539system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50000 # average ReadExReq mshr miss latency 1540system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324 # average ReadExReq mshr miss latency 1541system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average ReadCleanReq mshr miss latency 1542system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average ReadCleanReq mshr miss latency 1543system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average ReadCleanReq mshr miss latency 1544system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49750 # average ReadCleanReq mshr miss latency 1545system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593 # average ReadCleanReq mshr miss latency 1546system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency 1547system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency 1548system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency 1549system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency 1550system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency 1551system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency 1552system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1553system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency 1554system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency 1555system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency 1556system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency 1557system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency 1558system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency 1559system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency 1560system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency 1561system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency 1562system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency 1563system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency 1564system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency 1565system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency 1566system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency 1567system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency 1568system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency 1569system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1570system.membus.trans_dist::ReadResp 430 # Transaction distribution 1571system.membus.trans_dist::UpgradeReq 271 # Transaction distribution 1572system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 1573system.membus.trans_dist::ReadExReq 208 # Transaction distribution 1574system.membus.trans_dist::ReadExResp 142 # Transaction distribution 1575system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 1576system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) 1578system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.snoops 261 # Total snoops (count) 1581system.membus.snoop_fanout::samples 915 # Request fanout histogram 1582system.membus.snoop_fanout::mean 0 # Request fanout histogram 1583system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1584system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1585system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram 1586system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1587system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1588system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1589system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1590system.membus.snoop_fanout::total 915 # Request fanout histogram 1591system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) 1592system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 1593system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) 1594system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1595system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. 1596system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1597system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1598system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1599system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1600system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1601system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution 1602system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 1603system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution 1604system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 1605system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution 1606system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution 1607system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution 1608system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution 1609system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution 1610system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution 1611system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) 1612system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) 1613system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) 1614system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 1615system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) 1616system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) 1617system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) 1618system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 1619system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) 1620system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) 1621system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 1622system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) 1623system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1624system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) 1625system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 1626system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) 1627system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 1628system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) 1629system.toL2Bus.snoops 1032 # Total snoops (count) 1630system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram 1631system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram 1632system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram 1633system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1634system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram 1635system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram 1636system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram 1637system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram 1638system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1639system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1640system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1641system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1642system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1643system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1644system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1645system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1646system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram 1647system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) 1648system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1649system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) 1650system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1651system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) 1652system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1653system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) 1654system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) 1655system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) 1656system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) 1657system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) 1658system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) 1659system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) 1660system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1661system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) 1662system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1663system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) 1664system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1665 1666---------- End Simulation Statistics ----------