Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

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stats.txt (10036:80e84beef3bb)	stats.txt (10063:9595c7a1d837)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000263 # Number of seconds simulated 4sim_ticks 262794500 # Number of ticks simulated 5final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 87015 # Simulator instruction rate (inst/s) 8host_op_rate 87015 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34460789 # Simulator tick rate (ticks/s) 10host_mem_usage 249056 # Number of bytes of host memory used 11host_seconds 7.63 # Real time elapsed on the host	7host_inst_rate 160692 # Simulator instruction rate (inst/s) 8host_op_rate 160691 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63638702 # Simulator tick rate (ticks/s) 10host_mem_usage 297424 # Number of bytes of host memory used 11host_seconds 4.13 # Real time elapsed on the host
12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory 24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) 62system.membus.throughput 139302763 # Throughput (bytes/s) 63system.membus.trans_dist::ReadReq 430 # Transaction distribution 64system.membus.trans_dist::ReadResp 430 # Transaction distribution 65system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 66system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 67system.membus.trans_dist::ReadExReq 208 # Transaction distribution 68system.membus.trans_dist::ReadExResp 142 # Transaction distribution 69system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 70system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) 71system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 72system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 73system.membus.data_through_bus 36608 # Total data (bytes) 74system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 75system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) 76system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 77system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 78system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 79system.cpu_clk_domain.clock 500 # Clock period in ticks 80system.l2c.tags.replacements 0 # number of replacements 81system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use 82system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 83system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 84system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 85system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 86system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor 87system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor 88system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor 89system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor 90system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 92system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor 93system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor 94system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor 95system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 96system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 97system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 98system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 99system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 102system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy 103system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 104system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy 105system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 106system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 107system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 108system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 109system.l2c.tags.tag_accesses 15709 # Number of tag accesses 110system.l2c.tags.data_accesses 15709 # Number of data accesses 111system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 119system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 120system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 121system.l2c.Writeback_hits::total 1 # number of Writeback hits 122system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 124system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 125system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 126system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 127system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 128system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits 129system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 130system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 132system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 133system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 134system.l2c.overall_hits::cpu0.data 5 # number of overall hits 135system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 136system.l2c.overall_hits::cpu1.data 3 # number of overall hits 137system.l2c.overall_hits::cpu2.inst 354 # number of overall hits 138system.l2c.overall_hits::cpu2.data 9 # number of overall hits 139system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 140system.l2c.overall_hits::cpu3.data 9 # number of overall hits 141system.l2c.overall_hits::total 1220 # number of overall hits 142system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 143system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 144system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 145system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 146system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 147system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 148system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 151system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 152system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 153system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 154system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 155system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 156system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 157system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 158system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 159system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 160system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 161system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 162system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 163system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 164system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 165system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 169system.l2c.demand_misses::total 592 # number of demand (read+write) misses 170system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 171system.l2c.overall_misses::cpu0.data 165 # number of overall misses 172system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 173system.l2c.overall_misses::cpu1.data 23 # number of overall misses 174system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 175system.l2c.overall_misses::cpu2.data 16 # number of overall misses 176system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 177system.l2c.overall_misses::cpu3.data 16 # number of overall misses 178system.l2c.overall_misses::total 592 # number of overall misses 179system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 180system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles 181system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles 188system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles 189system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 190system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles 191system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles 192system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles 193system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 194system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles 195system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles 196system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 197system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 198system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles 202system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 203system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles 204system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles 205system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 206system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles 210system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles 211system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 212system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 213system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 214system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 220system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 221system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 222system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 223system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) 224system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 227system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 228system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 229system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 230system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 232system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 233system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 234system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 240system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 241system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 242system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 243system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 249system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 250system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 251system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 252system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses 259system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 263system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses 264system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 265system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 266system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 276system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 277system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses 278system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 284system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 285system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 286system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency 293system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 294system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency 295system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency 296system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency 297system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 298system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency 301system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 317system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 318system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency 319system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 322system.l2c.blocked::no_targets 0 # number of cycles access was blocked 323system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 325system.l2c.fast_writes 0 # number of fast writes performed 326system.l2c.cache_copies 0 # number of cache copies performed 327system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 328system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits 330system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits 331system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits 332system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 333system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 334system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 335system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits 336system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits 337system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits 338system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 339system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 340system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 341system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 342system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits 343system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits 344system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 345system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses 346system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses 347system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses 348system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses 349system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses 350system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses 351system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses 352system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses 353system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 354system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses 355system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses 356system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses 357system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses 358system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses 359system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses 360system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses 361system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses 362system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses 363system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses 364system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses 365system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses 366system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses 367system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses 368system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses 369system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses 370system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses 371system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses 372system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses 373system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses 374system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses 375system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses 376system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses 377system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses 378system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses 379system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses 380system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses 381system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses 382system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles 383system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles 384system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles 385system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles 386system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles 387system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles 388system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles 389system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 390system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 391system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 392system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 393system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 394system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 395system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles 396system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles 397system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles 398system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles 399system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles 400system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles 401system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles 402system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles 403system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles 404system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles 405system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles 406system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles 407system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles 408system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles 409system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles 410system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles 411system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles 412system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles 413system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles 414system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles 415system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles 416system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles 417system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles 419system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 421system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 422system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 428system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 429system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 430system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 431system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses 433system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 434system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 435system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 436system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 437system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 438system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 439system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 440system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 441system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 447system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 448system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 449system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses 455system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 466system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency 472system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency 475system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 481system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 482system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 483system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 488system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 489system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency 493system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 494system.toL2Bus.throughput 646588875 # Throughput (bytes/s) 495system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 496system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 497system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 498system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 499system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 500system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 501system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 502system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) 503system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) 504system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 505system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) 506system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 507system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) 508system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) 509system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) 510system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) 511system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 512system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 513system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 514system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 515system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 516system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 517system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 518system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 519system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) 520system.toL2Bus.data_through_bus 116032 # Total data (bytes) 521system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) 522system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) 523system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 524system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) 525system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 526system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) 527system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 528system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) 529system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) 530system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) 531system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 532system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) 533system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) 534system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) 535system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 536system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) 537system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) 538system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) 539system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) 540system.cpu0.workload.num_syscalls 89 # Number of system calls 541system.cpu0.numCycles 525589 # number of cpu cycles simulated 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 544system.cpu0.committedInsts 158574 # Number of instructions committed 545system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 548system.cpu0.num_func_calls 390 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 109208 # number of integer instructions 551system.cpu0.num_fp_insts 0 # number of float instructions 552system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 556system.cpu0.num_mem_refs 74021 # number of memory refs 557system.cpu0.num_load_insts 49007 # Number of load instructions 558system.cpu0.num_store_insts 25014 # Number of store instructions 559system.cpu0.num_idle_cycles 0 # Number of idle cycles 560system.cpu0.num_busy_cycles 525589 # Number of busy cycles 561system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0 # Percentage of idle cycles	12sim_insts 663567 # Number of instructions simulated 13sim_ops 663567 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory 24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) 62system.membus.throughput 139302763 # Throughput (bytes/s) 63system.membus.trans_dist::ReadReq 430 # Transaction distribution 64system.membus.trans_dist::ReadResp 430 # Transaction distribution 65system.membus.trans_dist::UpgradeReq 272 # Transaction distribution 66system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 67system.membus.trans_dist::ReadExReq 208 # Transaction distribution 68system.membus.trans_dist::ReadExResp 142 # Transaction distribution 69system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) 70system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) 71system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) 72system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) 73system.membus.data_through_bus 36608 # Total data (bytes) 74system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 75system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) 76system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 77system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) 78system.membus.respLayer1.utilization 2.1 # Layer utilization (%) 79system.cpu_clk_domain.clock 500 # Clock period in ticks 80system.l2c.tags.replacements 0 # number of replacements 81system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use 82system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 83system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. 84system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. 85system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 86system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor 87system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor 88system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor 89system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor 90system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor 92system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor 93system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor 94system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor 95system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy 96system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy 97system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy 98system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy 99system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy 102system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy 103system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy 104system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy 105system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id 106system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 107system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id 108system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id 109system.l2c.tags.tag_accesses 15709 # Number of tag accesses 110system.l2c.tags.data_accesses 15709 # Number of data accesses 111system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 119system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 120system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 121system.l2c.Writeback_hits::total 1 # number of Writeback hits 122system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 124system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits 125system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 126system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits 127system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 128system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits 129system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 130system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 132system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 133system.l2c.overall_hits::cpu0.inst 182 # number of overall hits 134system.l2c.overall_hits::cpu0.data 5 # number of overall hits 135system.l2c.overall_hits::cpu1.inst 300 # number of overall hits 136system.l2c.overall_hits::cpu1.data 3 # number of overall hits 137system.l2c.overall_hits::cpu2.inst 354 # number of overall hits 138system.l2c.overall_hits::cpu2.data 9 # number of overall hits 139system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 140system.l2c.overall_hits::cpu3.data 9 # number of overall hits 141system.l2c.overall_hits::total 1220 # number of overall hits 142system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses 143system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 144system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses 145system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses 146system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses 147system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses 148system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::total 450 # number of ReadReq misses 151system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 152system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses 153system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 154system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 155system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 156system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 157system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses 158system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses 159system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses 160system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses 161system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses 162system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 163system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses 164system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses 165system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses 169system.l2c.demand_misses::total 592 # number of demand (read+write) misses 170system.l2c.overall_misses::cpu0.inst 285 # number of overall misses 171system.l2c.overall_misses::cpu0.data 165 # number of overall misses 172system.l2c.overall_misses::cpu1.inst 66 # number of overall misses 173system.l2c.overall_misses::cpu1.data 23 # number of overall misses 174system.l2c.overall_misses::cpu2.inst 12 # number of overall misses 175system.l2c.overall_misses::cpu2.data 16 # number of overall misses 176system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 177system.l2c.overall_misses::cpu3.data 16 # number of overall misses 178system.l2c.overall_misses::total 592 # number of overall misses 179system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles 180system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles 181system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles 188system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles 189system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles 190system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles 191system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles 192system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles 193system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles 194system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles 195system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles 196system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles 197system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles 198system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles 202system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles 203system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles 204system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles 205system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles 206system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles 210system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles 211system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 212system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 213system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) 214system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) 220system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 221system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 222system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 223system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) 224system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 227system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 228system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) 229system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) 230system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) 232system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 233system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 234system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 240system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses 241system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 242system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 243system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 249system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses 250system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses 251system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 252system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses 259system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 263system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses 264system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 265system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 266system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses 276system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses 277system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses 278system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses 284system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses 285system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses 286system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency 293system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency 294system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency 295system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency 296system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency 297system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency 298system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency 301system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 302system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency 317system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency 318system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency 319system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 322system.l2c.blocked::no_targets 0 # number of cycles access was blocked 323system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 325system.l2c.fast_writes 0 # number of fast writes performed 326system.l2c.cache_copies 0 # number of cache copies performed 327system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 328system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits 330system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits 331system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits 332system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 333system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 334system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 335system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits 336system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits 337system.l2c.demand_mshr_hits::cpu3.inst 1 # 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number of ReadReq MSHR miss cycles 388system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles 389system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles 390system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles 391system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles 392system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles 393system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles 394system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles 395system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles 396system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles 397system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles 398system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles 399system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles 400system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles 401system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles 402system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles 403system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles 404system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles 405system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles 406system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles 407system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles 408system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles 409system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles 410system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles 411system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles 412system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles 413system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles 414system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles 415system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles 416system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles 417system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles 419system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses 421system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses 422system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses 428system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses 429system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 430system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 431system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses 433system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 434system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 435system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 436system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 437system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 438system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses 439system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses 440system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses 441system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses 447system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses 448system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses 449system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses 455system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses 456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency 466system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency 472system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency 475system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 481system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 482system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 483system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency 488system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency 489system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency 493system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 494system.toL2Bus.throughput 646588875 # Throughput (bytes/s) 495system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution 496system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution 497system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 498system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution 499system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution 500system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution 501system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution 502system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) 503system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) 504system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 505system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) 506system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) 507system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) 508system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) 509system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) 510system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) 511system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 512system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 513system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 514system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 515system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) 516system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 517system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 518system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 519system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) 520system.toL2Bus.data_through_bus 116032 # Total data (bytes) 521system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) 522system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) 523system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 524system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) 525system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 526system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) 527system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 528system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) 529system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) 530system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) 531system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 532system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) 533system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) 534system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) 535system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 536system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) 537system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) 538system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) 539system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) 540system.cpu0.workload.num_syscalls 89 # Number of system calls 541system.cpu0.numCycles 525589 # number of cpu cycles simulated 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 544system.cpu0.committedInsts 158574 # Number of instructions committed 545system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 548system.cpu0.num_func_calls 390 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 109208 # number of integer instructions 551system.cpu0.num_fp_insts 0 # number of float instructions 552system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 556system.cpu0.num_mem_refs 74021 # number of memory refs 557system.cpu0.num_load_insts 49007 # Number of load instructions 558system.cpu0.num_store_insts 25014 # Number of store instructions 559system.cpu0.num_idle_cycles 0 # Number of idle cycles 560system.cpu0.num_busy_cycles 525589 # Number of busy cycles 561system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0 # Percentage of idle cycles
	563system.cpu0.Branches 26897 # Number of branches fetched
563system.cpu0.icache.tags.replacements 215 # number of replacements 564system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use 565system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. 566system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 567system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. 568system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 569system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor 570system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy 571system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy 572system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 573system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 574system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 575system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 576system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses 577system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses 578system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits 579system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits 580system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits 581system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits 582system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits 583system.cpu0.icache.overall_hits::total 158170 # number of overall hits 584system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 585system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 586system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 587system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 588system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 589system.cpu0.icache.overall_misses::total 467 # number of overall misses 590system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles 591system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles 592system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles 593system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles 594system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles 595system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles 596system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) 597system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) 598system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses 599system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses 600system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses 601system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses 602system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses 603system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses 604system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses 605system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses 606system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses 607system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses 608system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency 609system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency 610system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency 611system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency 612system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency 613system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency 614system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 615system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 617system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 618system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 619system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.cpu0.icache.fast_writes 0 # number of fast writes performed 621system.cpu0.icache.cache_copies 0 # number of cache copies performed 622system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 623system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 624system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 625system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 626system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 627system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 628system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles 629system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles 630system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles 631system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles 632system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles 633system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles 634system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses 635system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses 637system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses 638system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses 639system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses 640system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency 642system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 644system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 646system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 647system.cpu0.dcache.tags.replacements 2 # number of replacements 648system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use 649system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. 650system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 651system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. 652system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 653system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor 654system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy 655system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy 656system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 657system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 658system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 659system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 660system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses 661system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses 662system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits 663system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits 664system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits 665system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits 666system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 667system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 668system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits 669system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits 670system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits 671system.cpu0.dcache.overall_hits::total 73607 # number of overall hits 672system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 673system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 674system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 675system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 676system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 677system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 678system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 679system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 680system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 681system.cpu0.dcache.overall_misses::total 353 # number of overall misses 682system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles 683system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles 684system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles 685system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles 686system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles 687system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles 688system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles 689system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles 690system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles 691system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles 692system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) 693system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 697system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 698system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses 706system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 707system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 708system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses 709system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses 710system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses 711system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses 712system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency 713system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency 714system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency 715system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency 716system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency 717system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency 718system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 719system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency 720system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 721system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency 722system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 723system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 724system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 725system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 726system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 727system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 728system.cpu0.dcache.fast_writes 0 # number of fast writes performed 729system.cpu0.dcache.cache_copies 0 # number of cache copies performed 730system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 731system.cpu0.dcache.writebacks::total 1 # number of writebacks 732system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 733system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 734system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 735system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 736system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 737system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 738system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 739system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 740system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 741system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 742system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles 743system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles 744system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles 745system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles 746system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles 747system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles 748system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles 749system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles 750system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles 751system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles 752system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses 753system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses 754system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses 755system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses 756system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 757system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 758system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses 759system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses 760system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses 761system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses 762system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency 764system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency 766system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency 767system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency 768system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 769system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency 770system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 771system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency 772system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 773system.cpu1.numCycles 525588 # number of cpu cycles simulated 774system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 775system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 776system.cpu1.committedInsts 163471 # Number of instructions committed 777system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed 778system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses 779system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 780system.cpu1.num_func_calls 637 # number of times a function call or return occured 781system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls 782system.cpu1.num_int_insts 111731 # number of integer instructions 783system.cpu1.num_fp_insts 0 # number of float instructions 784system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 785system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 786system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 787system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 788system.cpu1.num_mem_refs 58020 # number of memory refs 789system.cpu1.num_load_insts 41540 # Number of load instructions 790system.cpu1.num_store_insts 16480 # Number of store instructions 791system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles 792system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles 793system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles 794system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles	564system.cpu0.icache.tags.replacements 215 # number of replacements 565system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use 566system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. 567system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 568system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. 569system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 570system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor 571system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy 572system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy 573system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 574system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 575system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 576system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 577system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses 578system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses 579system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits 580system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits 581system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits 582system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits 583system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits 584system.cpu0.icache.overall_hits::total 158170 # number of overall hits 585system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 586system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 587system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 588system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 589system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 590system.cpu0.icache.overall_misses::total 467 # number of overall misses 591system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles 592system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles 593system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles 594system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles 595system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles 596system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles 597system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) 598system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) 599system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses 600system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses 601system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses 602system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses 603system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses 604system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses 605system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses 606system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses 607system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses 608system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses 609system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency 610system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency 611system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency 612system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency 613system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency 614system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency 615system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 620system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 621system.cpu0.icache.fast_writes 0 # number of fast writes performed 622system.cpu0.icache.cache_copies 0 # number of cache copies performed 623system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses 624system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses 625system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses 626system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses 627system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses 628system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses 629system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles 630system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles 631system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles 632system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles 633system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles 634system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles 635system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses 637system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses 638system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses 639system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses 640system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency 642system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 644system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency 646system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency 647system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 648system.cpu0.dcache.tags.replacements 2 # number of replacements 649system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use 650system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. 651system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 652system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. 653system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 654system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor 655system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy 656system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy 657system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 658system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 659system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id 660system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 661system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses 662system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses 663system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits 664system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits 665system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits 666system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits 667system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 668system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 669system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits 670system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits 671system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits 672system.cpu0.dcache.overall_hits::total 73607 # number of overall hits 673system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses 674system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses 675system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses 676system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses 677system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 678system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 679system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses 680system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses 681system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses 682system.cpu0.dcache.overall_misses::total 353 # number of overall misses 683system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles 684system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles 685system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles 687system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles 688system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles 689system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles 690system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles 691system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles 692system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles 693system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) 697system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 698system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 699system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses 700system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses 701system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses 702system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses 703system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses 704system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses 706system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses 707system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 708system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 709system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses 710system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses 711system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses 712system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses 713system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency 714system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency 715system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency 716system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency 717system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency 718system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency 719system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 720system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency 721system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency 722system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency 723system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 724system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 725system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 726system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 727system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 728system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 729system.cpu0.dcache.fast_writes 0 # number of fast writes performed 730system.cpu0.dcache.cache_copies 0 # number of cache copies performed 731system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 732system.cpu0.dcache.writebacks::total 1 # number of writebacks 733system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses 734system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 735system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses 736system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses 737system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 738system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 739system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses 740system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 741system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses 742system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 743system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles 744system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles 745system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles 746system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles 747system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles 748system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles 749system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles 750system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles 751system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles 752system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles 753system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses 754system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses 755system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses 756system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses 757system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 758system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses 760system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses 761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses 762system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency 766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency 767system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency 768system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency 769system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 770system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency 771system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency 772system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency 773system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 774system.cpu1.numCycles 525588 # number of cpu cycles simulated 775system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 776system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 777system.cpu1.committedInsts 163471 # Number of instructions committed 778system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed 779system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses 780system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 781system.cpu1.num_func_calls 637 # number of times a function call or return occured 782system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls 783system.cpu1.num_int_insts 111731 # number of integer instructions 784system.cpu1.num_fp_insts 0 # number of float instructions 785system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read 786system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written 787system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 788system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 789system.cpu1.num_mem_refs 58020 # number of memory refs 790system.cpu1.num_load_insts 41540 # Number of load instructions 791system.cpu1.num_store_insts 16480 # Number of store instructions 792system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles 793system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles 794system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles 795system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles
	796system.cpu1.Branches 31528 # Number of branches fetched
795system.cpu1.icache.tags.replacements 280 # number of replacements 796system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use 797system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 798system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 799system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 800system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 801system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor 802system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 803system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 804system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 805system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 806system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 807system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 808system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 809system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses 810system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses 811system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits 812system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits 813system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits 814system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits 815system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 816system.cpu1.icache.overall_hits::total 163138 # number of overall hits 817system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 818system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 819system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 820system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 821system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 822system.cpu1.icache.overall_misses::total 366 # number of overall misses 823system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles 824system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles 825system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles 826system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles 827system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles 828system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles 829system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 830system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 831system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 832system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 833system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 834system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 835system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 836system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 837system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 838system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 839system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 840system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses 841system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency 842system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency 843system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 844system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency 845system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 846system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency 847system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 848system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 849system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 850system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 851system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 852system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 853system.cpu1.icache.fast_writes 0 # number of fast writes performed 854system.cpu1.icache.cache_copies 0 # number of cache copies performed 855system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 856system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 857system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 858system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 859system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 860system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 861system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles 862system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles 863system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles 864system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles 865system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles 866system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles 867system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 868system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 869system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 870system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 871system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 872system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses 873system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency 874system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency 875system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 876system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 877system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 878system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 879system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 880system.cpu1.dcache.tags.replacements 0 # number of replacements 881system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use 882system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 883system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 884system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 885system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 886system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor 887system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy 888system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy 889system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 890system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 891system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 892system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 893system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses 894system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses 895system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits 896system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits 897system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits 898system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits 899system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 900system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 901system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits 902system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits 903system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits 904system.cpu1.dcache.overall_hits::total 57685 # number of overall hits 905system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses 906system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses 907system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses 908system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses 909system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses 910system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses 911system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses 912system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses 913system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses 914system.cpu1.dcache.overall_misses::total 263 # number of overall misses 915system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles 916system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles 917system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles 918system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles 919system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles 920system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles 921system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles 922system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles 923system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles 924system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles 925system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) 926system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) 927system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) 928system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) 929system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) 930system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 931system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses 932system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses 933system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses 934system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses 935system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses 936system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses 937system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses 938system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses 939system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses 940system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses 941system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses 942system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses 943system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses 944system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses 945system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency 946system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency 947system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency 948system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency 949system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency 950system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency 951system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 952system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency 953system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 954system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency 955system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 956system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 957system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 958system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 959system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 960system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 961system.cpu1.dcache.fast_writes 0 # number of fast writes performed 962system.cpu1.dcache.cache_copies 0 # number of cache copies performed 963system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses 964system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 965system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses 966system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 967system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses 968system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 969system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 970system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 971system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 972system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 973system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles 974system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles 975system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles 976system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles 977system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles 978system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles 979system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles 980system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles 981system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles 982system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles 983system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses 984system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses 985system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses 986system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses 987system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses 988system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses 989system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses 990system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses 991system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses 992system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses 993system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency 994system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency 995system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency 996system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency 997system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 998system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency 999system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1000system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1001system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1002system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1003system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1004system.cpu2.numCycles 525588 # number of cpu cycles simulated 1005system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1006system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1007system.cpu2.committedInsts 164866 # Number of instructions committed 1008system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 1009system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 1010system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 1011system.cpu2.num_func_calls 637 # number of times a function call or return occured 1012system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 1013system.cpu2.num_int_insts 112988 # number of integer instructions 1014system.cpu2.num_fp_insts 0 # number of float instructions 1015system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 1016system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 1017system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 1018system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 1019system.cpu2.num_mem_refs 59208 # number of memory refs 1020system.cpu2.num_load_insts 42171 # Number of load instructions 1021system.cpu2.num_store_insts 17037 # Number of store instructions 1022system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles 1023system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles 1024system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles 1025system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles	797system.cpu1.icache.tags.replacements 280 # number of replacements 798system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use 799system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. 800system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 801system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. 802system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 803system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor 804system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy 805system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy 806system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 807system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 808system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 809system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 810system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 811system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses 812system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses 813system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits 814system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits 815system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits 816system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits 817system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits 818system.cpu1.icache.overall_hits::total 163138 # number of overall hits 819system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses 820system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses 821system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses 822system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses 823system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses 824system.cpu1.icache.overall_misses::total 366 # number of overall misses 825system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles 826system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles 827system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles 828system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles 829system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles 830system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles 831system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) 832system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) 833system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses 834system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses 835system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses 836system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses 837system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses 838system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses 839system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses 840system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses 841system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses 842system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses 843system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency 844system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency 845system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 846system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency 847system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency 848system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency 849system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 850system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 851system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 852system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 853system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 854system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 855system.cpu1.icache.fast_writes 0 # number of fast writes performed 856system.cpu1.icache.cache_copies 0 # number of cache copies performed 857system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses 858system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 859system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses 860system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 861system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses 862system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 863system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles 864system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles 865system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles 866system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles 867system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles 868system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles 869system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses 870system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses 871system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses 872system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses 873system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses 874system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses 875system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency 876system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency 877system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 878system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 879system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency 880system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency 881system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 882system.cpu1.dcache.tags.replacements 0 # number of replacements 883system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use 884system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. 885system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 886system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. 887system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 888system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor 889system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy 890system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy 891system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 892system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 893system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 894system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 895system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses 896system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses 897system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits 898system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits 899system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits 900system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits 901system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 902system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 903system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits 904system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits 905system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits 906system.cpu1.dcache.overall_hits::total 57685 # number of overall hits 907system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses 908system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses 909system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses 910system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses 911system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses 912system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses 913system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses 914system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses 915system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses 916system.cpu1.dcache.overall_misses::total 263 # number of overall misses 917system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles 918system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles 919system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles 920system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles 921system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles 922system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles 923system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles 924system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles 925system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles 926system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles 927system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) 928system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) 929system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) 930system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) 931system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) 932system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 933system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses 934system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses 935system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses 936system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses 937system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses 938system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses 939system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses 940system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses 941system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses 942system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses 943system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses 944system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses 945system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses 946system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses 947system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency 948system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency 949system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency 950system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency 951system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency 952system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency 953system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 954system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency 955system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency 956system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency 957system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 958system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 959system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 960system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 961system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 962system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 963system.cpu1.dcache.fast_writes 0 # number of fast writes performed 964system.cpu1.dcache.cache_copies 0 # number of cache copies performed 965system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses 966system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 967system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses 968system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 969system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses 970system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 971system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 972system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 973system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 974system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 975system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles 976system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles 977system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles 978system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles 979system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles 980system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles 981system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles 982system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles 983system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles 984system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles 985system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses 986system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses 987system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses 988system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses 989system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses 990system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses 991system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses 992system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses 993system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses 994system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses 995system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency 996system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency 997system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency 998system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency 999system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency 1000system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency 1001system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1002system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1003system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency 1004system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency 1005system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1006system.cpu2.numCycles 525588 # number of cpu cycles simulated 1007system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1008system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1009system.cpu2.committedInsts 164866 # Number of instructions committed 1010system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed 1011system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses 1012system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 1013system.cpu2.num_func_calls 637 # number of times a function call or return occured 1014system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls 1015system.cpu2.num_int_insts 112988 # number of integer instructions 1016system.cpu2.num_fp_insts 0 # number of float instructions 1017system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read 1018system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written 1019system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 1020system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 1021system.cpu2.num_mem_refs 59208 # number of memory refs 1022system.cpu2.num_load_insts 42171 # Number of load instructions 1023system.cpu2.num_store_insts 17037 # Number of store instructions 1024system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles 1025system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles 1026system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles 1027system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles
	1028system.cpu2.Branches 31596 # Number of branches fetched
1026system.cpu2.icache.tags.replacements 280 # number of replacements 1027system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use 1028system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 1029system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 1030system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 1031system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1032system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor 1033system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1034system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1035system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1036system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1037system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1038system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1039system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1040system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses 1041system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses 1042system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits 1043system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits 1044system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits 1045system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits 1046system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1047system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1048system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1049system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1050system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1051system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1052system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1053system.cpu2.icache.overall_misses::total 366 # number of overall misses 1054system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles 1055system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles 1056system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles 1057system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles 1058system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles 1059system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles 1060system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1061system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1062system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1063system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1064system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1065system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1066system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1067system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1068system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1069system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1070system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1071system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses 1072system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency 1073system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency 1074system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1075system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency 1076system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1077system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency 1078system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu2.icache.fast_writes 0 # number of fast writes performed 1085system.cpu2.icache.cache_copies 0 # number of cache copies performed 1086system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1087system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1088system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1089system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1090system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1091system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 1092system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles 1093system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles 1094system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles 1095system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles 1096system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles 1097system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles 1098system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1099system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1100system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1101system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1102system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1103system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses 1104system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency 1105system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency 1106system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1107system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1108system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1109system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1110system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1111system.cpu2.dcache.tags.replacements 0 # number of replacements 1112system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use 1113system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1114system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1115system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1116system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1117system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor 1118system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1119system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1120system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1121system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1122system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1123system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1124system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses 1125system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses 1126system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits 1127system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits 1128system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits 1129system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits 1130system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 1131system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits 1132system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits 1133system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits 1134system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits 1135system.cpu2.dcache.overall_hits::total 58876 # number of overall hits 1136system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses 1137system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses 1138system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses 1139system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses 1140system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses 1141system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses 1142system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses 1143system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses 1144system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses 1145system.cpu2.dcache.overall_misses::total 262 # number of overall misses 1146system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles 1147system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles 1148system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles 1149system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles 1150system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles 1151system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles 1152system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles 1153system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles 1154system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles 1155system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles 1156system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) 1157system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) 1158system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) 1159system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) 1160system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) 1161system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) 1162system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses 1163system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses 1164system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses 1165system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses 1166system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses 1167system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses 1168system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses 1169system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses 1170system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 1171system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 1172system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses 1173system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses 1174system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses 1175system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses 1176system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency 1177system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency 1178system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency 1179system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency 1180system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency 1181system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency 1182system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1183system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency 1184system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1185system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency 1186system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1187system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1188system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1189system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1190system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1191system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1192system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1193system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1194system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses 1195system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1196system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses 1197system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses 1198system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses 1199system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 1200system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1201system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1202system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1203system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses 1204system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles 1205system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles 1206system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles 1207system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles 1208system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles 1209system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles 1210system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles 1211system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles 1212system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles 1213system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles 1214system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses 1215system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses 1216system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses 1217system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses 1218system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 1219system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 1220system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses 1221system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses 1222system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses 1223system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses 1224system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency 1225system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency 1226system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency 1227system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency 1228system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1229system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency 1230system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1231system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1232system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1233system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1234system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1235system.cpu3.numCycles 525588 # number of cpu cycles simulated 1236system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1237system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1238system.cpu3.committedInsts 176656 # Number of instructions committed 1239system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1240system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1241system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 1242system.cpu3.num_func_calls 637 # number of times a function call or return occured 1243system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls 1244system.cpu3.num_int_insts 108218 # number of integer instructions 1245system.cpu3.num_fp_insts 0 # number of float instructions 1246system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read 1247system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written 1248system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 1249system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 1250system.cpu3.num_mem_refs 46164 # number of memory refs 1251system.cpu3.num_load_insts 39753 # Number of load instructions 1252system.cpu3.num_store_insts 6411 # Number of store instructions 1253system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles 1254system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles 1255system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles 1256system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles	1029system.cpu2.icache.tags.replacements 280 # number of replacements 1030system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use 1031system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. 1032system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. 1033system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. 1034system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1035system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor 1036system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy 1037system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy 1038system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1039system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1040system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1041system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1042system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1043system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses 1044system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses 1045system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits 1046system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits 1047system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits 1048system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits 1049system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits 1050system.cpu2.icache.overall_hits::total 164533 # number of overall hits 1051system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses 1052system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses 1053system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses 1054system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses 1055system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses 1056system.cpu2.icache.overall_misses::total 366 # number of overall misses 1057system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles 1058system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles 1059system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles 1060system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles 1061system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles 1062system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles 1063system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) 1064system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) 1065system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses 1066system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses 1067system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses 1068system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses 1069system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses 1070system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses 1071system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses 1072system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses 1073system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses 1074system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses 1075system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency 1076system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency 1077system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1078system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency 1079system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency 1080system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency 1081system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1082system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1083system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1084system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1085system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1086system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1087system.cpu2.icache.fast_writes 0 # number of fast writes performed 1088system.cpu2.icache.cache_copies 0 # number of cache copies performed 1089system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses 1090system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1091system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses 1092system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses 1093system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses 1094system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses 1095system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles 1096system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles 1097system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles 1098system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles 1099system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles 1100system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles 1101system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses 1102system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses 1103system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses 1104system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses 1105system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses 1106system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses 1107system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency 1108system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency 1109system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1110system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1111system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency 1112system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency 1113system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1114system.cpu2.dcache.tags.replacements 0 # number of replacements 1115system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use 1116system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. 1117system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1118system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. 1119system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1120system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor 1121system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy 1122system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy 1123system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1124system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1125system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1126system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1127system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses 1128system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses 1129system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits 1130system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits 1131system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits 1132system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits 1133system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits 1134system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits 1135system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits 1136system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits 1137system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits 1138system.cpu2.dcache.overall_hits::total 58876 # number of overall hits 1139system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses 1140system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses 1141system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses 1142system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses 1143system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses 1144system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses 1145system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses 1146system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses 1147system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses 1148system.cpu2.dcache.overall_misses::total 262 # number of overall misses 1149system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles 1150system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles 1151system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles 1152system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles 1153system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles 1154system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles 1155system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles 1156system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles 1157system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles 1158system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles 1159system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) 1160system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) 1161system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) 1162system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) 1163system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) 1164system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) 1165system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses 1166system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses 1167system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses 1168system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses 1169system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses 1170system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses 1171system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses 1172system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses 1173system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 1174system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 1175system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses 1176system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses 1177system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses 1178system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses 1179system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency 1180system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency 1181system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency 1182system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency 1183system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency 1184system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency 1185system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1186system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency 1187system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency 1188system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency 1189system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1190system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1191system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1192system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1193system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1194system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1195system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1196system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1197system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses 1198system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1199system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses 1200system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses 1201system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses 1202system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 1203system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1204system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1205system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1206system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses 1207system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles 1208system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles 1209system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles 1210system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles 1211system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles 1212system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles 1213system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles 1214system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles 1215system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles 1216system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles 1217system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses 1218system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses 1219system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses 1220system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses 1221system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses 1222system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses 1223system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses 1224system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses 1225system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses 1226system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses 1227system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency 1228system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency 1229system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency 1230system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency 1231system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency 1232system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency 1233system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1234system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1235system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency 1236system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency 1237system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1238system.cpu3.numCycles 525588 # number of cpu cycles simulated 1239system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1240system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1241system.cpu3.committedInsts 176656 # Number of instructions committed 1242system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed 1243system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses 1244system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 1245system.cpu3.num_func_calls 637 # number of times a function call or return occured 1246system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls 1247system.cpu3.num_int_insts 108218 # number of integer instructions 1248system.cpu3.num_fp_insts 0 # number of float instructions 1249system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read 1250system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written 1251system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 1252system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 1253system.cpu3.num_mem_refs 46164 # number of memory refs 1254system.cpu3.num_load_insts 39753 # Number of load instructions 1255system.cpu3.num_store_insts 6411 # Number of store instructions 1256system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles 1257system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles 1258system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles 1259system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles
	1260system.cpu3.Branches 39890 # Number of branches fetched
1257system.cpu3.icache.tags.replacements 281 # number of replacements 1258system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use 1259system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. 1260system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1261system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. 1262system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1263system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor 1264system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy 1265system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy 1266system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1267system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1268system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1269system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1270system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1271system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses 1272system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses 1273system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits 1274system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits 1275system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits 1276system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits 1277system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits 1278system.cpu3.icache.overall_hits::total 176322 # number of overall hits 1279system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1280system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1281system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1282system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1283system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1284system.cpu3.icache.overall_misses::total 367 # number of overall misses 1285system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles 1286system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles 1287system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles 1288system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles 1289system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles 1290system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles 1291system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) 1292system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) 1293system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses 1294system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses 1295system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses 1296system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses 1297system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses 1298system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses 1299system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses 1300system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses 1301system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses 1302system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses 1303system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency 1304system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency 1305system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency 1306system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency 1307system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency 1308system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency 1309system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1310system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1311system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1312system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1313system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1314system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1315system.cpu3.icache.fast_writes 0 # number of fast writes performed 1316system.cpu3.icache.cache_copies 0 # number of cache copies performed 1317system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1318system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1319system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1320system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1321system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1322system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1323system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles 1324system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles 1325system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles 1326system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles 1327system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles 1328system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles 1329system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses 1330system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses 1331system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses 1332system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses 1333system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses 1334system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses 1335system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency 1336system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency 1337system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1338system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1339system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1340system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1341system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1342system.cpu3.dcache.tags.replacements 0 # number of replacements 1343system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use 1344system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. 1345system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1346system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. 1347system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1348system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor 1349system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy 1350system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy 1351system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1352system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1353system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1354system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1355system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses 1356system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses 1357system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits 1358system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits 1359system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits 1360system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits 1361system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits 1362system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits 1363system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits 1364system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits 1365system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits 1366system.cpu3.dcache.overall_hits::total 45779 # number of overall hits 1367system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses 1368system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses 1369system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 1370system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 1371system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses 1372system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses 1373system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses 1374system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses 1375system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses 1376system.cpu3.dcache.overall_misses::total 288 # number of overall misses 1377system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles 1378system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles 1379system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles 1380system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles 1381system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles 1382system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles 1383system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles 1384system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles 1385system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles 1386system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles 1387system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) 1388system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) 1389system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) 1390system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) 1391system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) 1392system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) 1393system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses 1394system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses 1395system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses 1396system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses 1397system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses 1398system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses 1399system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses 1400system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses 1401system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses 1402system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses 1403system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses 1404system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses 1405system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses 1406system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses 1407system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency 1408system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency 1409system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency 1410system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency 1411system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency 1412system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency 1413system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1414system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency 1415system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1416system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency 1417system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1418system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1419system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1420system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1421system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1422system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1423system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1424system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1425system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses 1426system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses 1427system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1428system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1429system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses 1430system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses 1431system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses 1432system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses 1433system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses 1434system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses 1435system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles 1436system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles 1437system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles 1438system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles 1439system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles 1440system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles 1441system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles 1442system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles 1443system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles 1444system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles 1445system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses 1446system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses 1447system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses 1448system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses 1449system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses 1450system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses 1451system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses 1452system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses 1453system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses 1454system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses 1455system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency 1456system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency 1457system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency 1458system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency 1459system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency 1460system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency 1461system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1462system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency 1463system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1464system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency 1465system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1466 1467---------- End Simulation Statistics ----------	1261system.cpu3.icache.tags.replacements 281 # number of replacements 1262system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use 1263system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. 1264system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 1265system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. 1266system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1267system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor 1268system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy 1269system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy 1270system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id 1271system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1272system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 1273system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1274system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 1275system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses 1276system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses 1277system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits 1278system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits 1279system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits 1280system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits 1281system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits 1282system.cpu3.icache.overall_hits::total 176322 # number of overall hits 1283system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses 1284system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses 1285system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses 1286system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses 1287system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses 1288system.cpu3.icache.overall_misses::total 367 # number of overall misses 1289system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles 1290system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles 1291system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles 1292system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles 1293system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles 1294system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles 1295system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) 1296system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) 1297system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses 1298system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses 1299system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses 1300system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses 1301system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses 1302system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses 1303system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses 1304system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses 1305system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses 1306system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses 1307system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency 1308system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency 1309system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency 1310system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency 1311system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency 1312system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency 1313system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1314system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1315system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1316system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1317system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1318system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1319system.cpu3.icache.fast_writes 0 # number of fast writes performed 1320system.cpu3.icache.cache_copies 0 # number of cache copies performed 1321system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses 1322system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 1323system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses 1324system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 1325system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses 1326system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 1327system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles 1328system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles 1329system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles 1330system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles 1331system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles 1332system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles 1333system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses 1334system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses 1335system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses 1336system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses 1337system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses 1338system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses 1339system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency 1340system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency 1341system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1342system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1343system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency 1344system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency 1345system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1346system.cpu3.dcache.tags.replacements 0 # number of replacements 1347system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use 1348system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. 1349system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1350system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. 1351system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1352system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor 1353system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy 1354system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy 1355system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1356system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 1357system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 1358system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1359system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses 1360system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses 1361system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits 1362system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits 1363system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits 1364system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits 1365system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits 1366system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits 1367system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits 1368system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits 1369system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits 1370system.cpu3.dcache.overall_hits::total 45779 # number of overall hits 1371system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses 1372system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses 1373system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses 1374system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses 1375system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses 1376system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses 1377system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses 1378system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses 1379system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses 1380system.cpu3.dcache.overall_misses::total 288 # number of overall misses 1381system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles 1382system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles 1383system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles 1384system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles 1385system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles 1386system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles 1387system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles 1388system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles 1389system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles 1390system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles 1391system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) 1392system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) 1393system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) 1394system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) 1395system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) 1396system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) 1397system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses 1398system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses 1399system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses 1400system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses 1401system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses 1402system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses 1403system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses 1404system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses 1405system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses 1406system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses 1407system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses 1408system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses 1409system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses 1410system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses 1411system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency 1412system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency 1413system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency 1414system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency 1415system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency 1416system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency 1417system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1418system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency 1419system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency 1420system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency 1421system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1422system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1423system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1424system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 1425system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1426system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1427system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1428system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1429system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses 1430system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses 1431system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 1432system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1433system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses 1434system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses 1435system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses 1436system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses 1437system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses 1438system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses 1439system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles 1440system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles 1441system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles 1442system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles 1443system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles 1444system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles 1445system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles 1446system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles 1447system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles 1448system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles 1449system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses 1450system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses 1451system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses 1452system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses 1453system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses 1454system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses 1455system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses 1456system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses 1457system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses 1458system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses 1459system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency 1460system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency 1461system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency 1462system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency 1463system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency 1464system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency 1465system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1466system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency 1467system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency 1468system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency 1469system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1470 1471---------- End Simulation Statistics ----------