1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000260 # Number of seconds simulated
4sim_ticks 260037500 # Number of ticks simulated
5final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 961598 # Simulator instruction rate (inst/s)
8host_op_rate 961579 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 379344878 # Simulator tick rate (ticks/s)
10host_mem_usage 302744 # Number of bytes of host memory used
11host_seconds 0.69 # Real time elapsed on the host
12sim_insts 659142 # Number of instructions simulated
13sim_ops 659142 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
24system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
38system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
39system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s)
62system.cpu_clk_domain.clock 500 # Clock period in ticks
63system.cpu0.workload.num_syscalls 89 # Number of system calls
64system.cpu0.numCycles 520075 # number of cpu cycles simulated
65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
67system.cpu0.committedInsts 157392 # Number of instructions committed
68system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed
69system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses
70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
71system.cpu0.num_func_calls 390 # number of times a function call or return occured
72system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls
73system.cpu0.num_int_insts 108420 # number of integer instructions
74system.cpu0.num_fp_insts 0 # number of float instructions
75system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read
76system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written
77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
79system.cpu0.num_mem_refs 73430 # number of memory refs
80system.cpu0.num_load_insts 48613 # Number of load instructions
81system.cpu0.num_store_insts 24817 # Number of store instructions
82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
83system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles
84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
86system.cpu0.Branches 26700 # Number of branches fetched
87system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction
88system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction
89system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction
90system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction
91system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction
92system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction
93system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction
94system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction
95system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction
96system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction
97system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction
98system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction
99system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction
100system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction
101system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction
102system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction
103system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction
104system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction
105system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction
106system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction
107system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction
108system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction
109system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction
110system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction
111system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction
112system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction
113system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction
114system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction
115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction
116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction
117system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction
118system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction
119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
121system.cpu0.op_class::total 157454 # Class of executed instruction
122system.cpu0.dcache.tags.replacements 2 # number of replacements
123system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use
124system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks.
125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
126system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks.
127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
128system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor
129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy
130system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy
131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
133system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
135system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses
136system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses
137system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits
138system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits
139system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits
140system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits
141system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
142system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
143system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits
144system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits
145system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits
146system.cpu0.dcache.overall_hits::total 73016 # number of overall hits
147system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
148system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
149system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
150system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
151system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
152system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
153system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
154system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
155system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
156system.cpu0.dcache.overall_misses::total 353 # number of overall misses
157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles
158system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles
159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles
160system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles
161system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles
162system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles
163system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles
164system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles
165system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles
166system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles
167system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses)
168system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses)
169system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses)
170system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses)
171system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
172system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
173system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses
174system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses
175system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses
176system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses
177system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses
178system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses
179system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses
180system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses
181system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
182system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
183system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses
184system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses
185system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses
186system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses
187system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency
188system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency
189system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency
190system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency
191system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency
192system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency
193system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency
194system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency
195system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency
196system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency
197system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
198system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
199system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
200system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
201system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
202system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
203system.cpu0.dcache.fast_writes 0 # number of fast writes performed
204system.cpu0.dcache.cache_copies 0 # number of cache copies performed
205system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
206system.cpu0.dcache.writebacks::total 1 # number of writebacks
207system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
208system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
209system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
210system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
211system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
212system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
213system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
214system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
215system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
216system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles
218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles
219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles
220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles
221system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles
222system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles
223system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles
224system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles
225system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles
226system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles
227system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses
228system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses
229system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses
230system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses
231system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
232system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
233system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses
234system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses
235system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses
236system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses
237system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency
238system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency
239system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency
240system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency
241system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency
242system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency
243system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency
244system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency
245system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency
246system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency
247system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
248system.cpu0.icache.tags.replacements 215 # number of replacements
249system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use
250system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks.
251system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
252system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks.
253system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
254system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor
255system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy
256system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy
257system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
258system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
259system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
260system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
261system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses
262system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses
263system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits
264system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits
265system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits
266system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits
267system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits
268system.cpu0.icache.overall_hits::total 156988 # number of overall hits
269system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
270system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
271system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
272system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
273system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
274system.cpu0.icache.overall_misses::total 467 # number of overall misses
275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles
276system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles
277system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles
278system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles
279system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles
280system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles
281system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses)
282system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses)
283system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses
284system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses
285system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses
286system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses
287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses
288system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses
289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses
290system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses
291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses
292system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses
293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency
294system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency
295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency
296system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency
297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency
298system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency
299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu0.icache.fast_writes 0 # number of fast writes performed
306system.cpu0.icache.cache_copies 0 # number of cache copies performed
307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
308system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
309system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
310system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
311system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
312system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles
314system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles
315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles
316system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles
317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles
318system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles
319system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses
320system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses
321system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses
322system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses
323system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses
324system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses
325system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency
326system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency
327system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency
328system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency
329system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency
330system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency
331system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
332system.cpu1.numCycles 520075 # number of cpu cycles simulated
333system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
334system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
335system.cpu1.committedInsts 168980 # Number of instructions committed
336system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed
337system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses
338system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
339system.cpu1.num_func_calls 637 # number of times a function call or return occured
340system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls
341system.cpu1.num_int_insts 110320 # number of integer instructions
342system.cpu1.num_fp_insts 0 # number of float instructions
343system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read
344system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written
345system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
346system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
347system.cpu1.num_mem_refs 53149 # number of memory refs
348system.cpu1.num_load_insts 40825 # Number of load instructions
349system.cpu1.num_store_insts 12324 # Number of store instructions
350system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles
351system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles
352system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles
353system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles
354system.cpu1.Branches 34992 # Number of branches fetched
355system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction
356system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction
357system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction
358system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction
359system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction
360system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction
361system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction
362system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction
363system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction
364system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction
365system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction
366system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction
367system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction
368system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction
369system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction
370system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction
371system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction
372system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction
373system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction
374system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction
375system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction
376system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction
377system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction
378system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction
379system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction
380system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction
381system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction
382system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction
383system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction
384system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction
385system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction
386system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction
387system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
388system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
389system.cpu1.op_class::total 169012 # Class of executed instruction
390system.cpu1.dcache.tags.replacements 0 # number of replacements
391system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use
392system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks.
393system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
394system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks.
395system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
396system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor
397system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy
398system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy
399system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
400system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
401system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
402system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
403system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses
404system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses
405system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits
406system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits
407system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits
408system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits
409system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
410system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
411system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits
412system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits
413system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits
414system.cpu1.dcache.overall_hits::total 52799 # number of overall hits
415system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses
416system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses
417system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses
418system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses
419system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
420system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
421system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses
422system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses
423system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses
424system.cpu1.dcache.overall_misses::total 270 # number of overall misses
425system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles
426system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles
427system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles
428system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles
429system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles
430system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles
431system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles
432system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles
433system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles
434system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles
435system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses)
436system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses)
437system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses)
438system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses)
439system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
440system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
441system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses
442system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses
443system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses
444system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses
445system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses
446system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses
447system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses
448system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses
449system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses
450system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses
451system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses
452system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses
453system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses
454system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses
455system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency
456system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency
457system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency
458system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency
459system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency
460system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency
461system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency
462system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency
463system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency
464system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency
465system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
466system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
467system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
468system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
469system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
470system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
471system.cpu1.dcache.fast_writes 0 # number of fast writes performed
472system.cpu1.dcache.cache_copies 0 # number of cache copies performed
473system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses
474system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
475system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
476system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
477system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
478system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
479system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
480system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
481system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
482system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
483system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles
484system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles
485system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles
486system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles
487system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles
488system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles
489system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles
490system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles
491system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles
492system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles
493system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses
494system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses
495system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses
496system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses
497system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
498system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses
499system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses
500system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses
501system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses
502system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses
503system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency
504system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency
505system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency
506system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency
507system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency
508system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency
509system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency
510system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency
511system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency
512system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency
513system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
514system.cpu1.icache.tags.replacements 280 # number of replacements
515system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use
516system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks.
517system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
518system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks.
519system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
520system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor
521system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy
522system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy
523system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
524system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
525system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
526system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
527system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
528system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses
529system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses
530system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits
531system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits
532system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits
533system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits
534system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits
535system.cpu1.icache.overall_hits::total 168647 # number of overall hits
536system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
537system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
538system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
539system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
540system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
541system.cpu1.icache.overall_misses::total 366 # number of overall misses
542system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles
543system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles
544system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles
545system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles
546system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles
547system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles
548system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses)
549system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses)
550system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses
551system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses
552system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses
553system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses
554system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses
555system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses
556system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses
557system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses
558system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses
559system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses
560system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency
561system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency
562system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency
563system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency
564system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency
565system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency
566system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
567system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
568system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
569system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
570system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
571system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
572system.cpu1.icache.fast_writes 0 # number of fast writes performed
573system.cpu1.icache.cache_copies 0 # number of cache copies performed
574system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
575system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
576system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
577system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
578system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
579system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
580system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles
581system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles
582system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles
583system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles
584system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles
585system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles
586system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses
587system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses
588system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses
589system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses
590system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses
591system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses
592system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency
593system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency
594system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency
595system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency
596system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency
597system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency
598system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
599system.cpu2.numCycles 520075 # number of cpu cycles simulated
600system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
601system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
602system.cpu2.committedInsts 164869 # Number of instructions committed
603system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed
604system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses
605system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
606system.cpu2.num_func_calls 637 # number of times a function call or return occured
607system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls
608system.cpu2.num_int_insts 110069 # number of integer instructions
609system.cpu2.num_fp_insts 0 # number of float instructions
610system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read
611system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written
612system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
613system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
614system.cpu2.num_mem_refs 54829 # number of memory refs
615system.cpu2.num_load_insts 40701 # Number of load instructions
616system.cpu2.num_store_insts 14128 # Number of store instructions
617system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles
618system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles
619system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles
620system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles
621system.cpu2.Branches 33062 # Number of branches fetched
622system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction
623system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction
624system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction
625system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction
626system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction
627system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction
628system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction
629system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction
630system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction
631system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction
632system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction
633system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction
634system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction
635system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction
636system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction
637system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction
638system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction
639system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction
640system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction
641system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction
642system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction
643system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction
644system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction
645system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction
646system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction
647system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction
648system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction
649system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction
650system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction
651system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction
652system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction
653system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction
654system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
655system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
656system.cpu2.op_class::total 164901 # Class of executed instruction
657system.cpu2.dcache.tags.replacements 0 # number of replacements
658system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use
659system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks.
660system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
661system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks.
662system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
663system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor
664system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy
665system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy
666system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
667system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
668system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
669system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
670system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses
671system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses
672system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits
673system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits
674system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits
675system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits
676system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
677system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
678system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits
679system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits
680system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits
681system.cpu2.dcache.overall_hits::total 54483 # number of overall hits
682system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses
683system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses
684system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses
685system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses
686system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
687system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
688system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses
689system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses
690system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses
691system.cpu2.dcache.overall_misses::total 267 # number of overall misses
692system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles
693system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles
694system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles
695system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles
696system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles
697system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles
698system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles
699system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles
700system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles
701system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles
702system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses)
703system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses)
704system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses)
705system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses)
706system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
707system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
708system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses
709system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses
710system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses
711system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses
712system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses
713system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses
714system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses
715system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses
716system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses
717system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
718system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses
719system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses
720system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses
721system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses
722system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency
723system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency
724system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency
725system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency
726system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency
727system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency
728system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency
729system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency
730system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency
731system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency
732system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
733system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
734system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
735system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
736system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
737system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
738system.cpu2.dcache.fast_writes 0 # number of fast writes performed
739system.cpu2.dcache.cache_copies 0 # number of cache copies performed
740system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses
741system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
742system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
743system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
744system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
745system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
746system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
747system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
748system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
749system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
750system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles
751system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles
752system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles
753system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles
754system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles
755system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles
756system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles
757system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles
758system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles
759system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles
760system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses
761system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses
762system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses
763system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses
764system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses
765system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
766system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses
767system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses
768system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses
769system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses
770system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency
771system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency
772system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency
773system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency
774system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency
775system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency
776system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency
777system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency
778system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency
779system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency
780system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
781system.cpu2.icache.tags.replacements 280 # number of replacements
782system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use
783system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks.
784system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
785system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks.
786system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
787system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor
788system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy
789system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy
790system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
791system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
792system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
793system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
794system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
795system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses
796system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses
797system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits
798system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits
799system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits
800system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits
801system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits
802system.cpu2.icache.overall_hits::total 164536 # number of overall hits
803system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
804system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
805system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
806system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
807system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
808system.cpu2.icache.overall_misses::total 366 # number of overall misses
809system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles
810system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles
811system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles
812system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles
813system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles
814system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles
815system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses)
816system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses)
817system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses
818system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses
819system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses
820system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses
821system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses
822system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses
823system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses
824system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
825system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses
826system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses
827system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency
828system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency
829system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency
830system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency
831system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency
832system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency
833system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
834system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
835system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
836system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
837system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
838system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
839system.cpu2.icache.fast_writes 0 # number of fast writes performed
840system.cpu2.icache.cache_copies 0 # number of cache copies performed
841system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
842system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
843system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
844system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
845system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
846system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
847system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles
848system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles
849system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles
850system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles
851system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles
852system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles
853system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses
854system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
855system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses
856system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
857system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
858system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
859system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency
860system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency
861system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency
862system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency
863system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency
864system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency
865system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
866system.cpu3.numCycles 520075 # number of cpu cycles simulated
867system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
868system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
869system.cpu3.committedInsts 167901 # Number of instructions committed
870system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed
871system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses
872system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
873system.cpu3.num_func_calls 637 # number of times a function call or return occured
874system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls
875system.cpu3.num_int_insts 110672 # number of integer instructions
876system.cpu3.num_fp_insts 0 # number of float instructions
877system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read
878system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written
879system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
880system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
881system.cpu3.num_mem_refs 54219 # number of memory refs
882system.cpu3.num_load_insts 41000 # Number of load instructions
883system.cpu3.num_store_insts 13219 # Number of store instructions
884system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles
885system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles
886system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles
887system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles
888system.cpu3.Branches 34277 # Number of branches fetched
889system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction
890system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction
891system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction
892system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction
893system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction
894system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction
895system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction
896system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction
897system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction
898system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction
899system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction
900system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction
901system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction
902system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction
903system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction
904system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction
905system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction
906system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction
907system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction
908system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction
909system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction
910system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction
911system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction
912system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction
913system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction
914system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction
915system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction
916system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction
917system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction
918system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction
919system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction
920system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction
921system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
922system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
923system.cpu3.op_class::total 167933 # Class of executed instruction
924system.cpu3.dcache.tags.replacements 0 # number of replacements
925system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use
926system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks.
927system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
928system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks.
929system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
930system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor
931system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy
932system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy
933system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
934system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
935system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
936system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
937system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses
938system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses
939system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits
940system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits
941system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits
942system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits
943system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
944system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
945system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits
946system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits
947system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits
948system.cpu3.dcache.overall_hits::total 53870 # number of overall hits
949system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses
950system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses
951system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses
952system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses
953system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
954system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
955system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses
956system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses
957system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses
958system.cpu3.dcache.overall_misses::total 268 # number of overall misses
959system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles
960system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles
961system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles
962system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles
963system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles
964system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles
965system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles
966system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles
967system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles
968system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles
969system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses)
970system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses)
971system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses)
972system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses)
973system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
974system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
975system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses
976system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses
977system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses
978system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses
979system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses
980system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses
981system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses
982system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses
983system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses
984system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
985system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses
986system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses
987system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses
988system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses
989system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency
990system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency
991system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency
992system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency
993system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency
994system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency
995system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency
996system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency
997system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency
998system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency
999system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1000system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1001system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1002system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1003system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1004system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1005system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1006system.cpu3.dcache.cache_copies 0 # number of cache copies performed
1007system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
1008system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
1009system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses
1010system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
1011system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
1012system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
1013system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses
1014system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1015system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses
1016system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1017system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles
1018system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles
1019system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles
1020system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles
1021system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles
1022system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles
1023system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles
1024system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles
1025system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles
1026system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles
1027system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses
1028system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses
1029system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses
1030system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses
1031system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses
1032system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
1033system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses
1034system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses
1035system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses
1036system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses
1037system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency
1038system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency
1039system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency
1040system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency
1041system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency
1042system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency
1043system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency
1044system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency
1045system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency
1046system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency
1047system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1048system.cpu3.icache.tags.replacements 281 # number of replacements
1049system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use
1050system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks.
1051system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
1052system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks.
1053system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1054system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor
1055system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy
1056system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy
1057system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
1058system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1059system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
1060system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1061system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
1062system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses
1063system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses
1064system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits
1065system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits
1066system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits
1067system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits
1068system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits
1069system.cpu3.icache.overall_hits::total 167567 # number of overall hits
1070system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
1071system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
1072system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
1073system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
1074system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
1075system.cpu3.icache.overall_misses::total 367 # number of overall misses
1076system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles
1077system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles
1078system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles
1079system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles
1080system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles
1081system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles
1082system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses)
1083system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses)
1084system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses
1085system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses
1086system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses
1087system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses
1088system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses
1089system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses
1090system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses
1091system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses
1092system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses
1093system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses
1094system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency
1095system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency
1096system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency
1097system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency
1098system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency
1099system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency
1100system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1101system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1102system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1103system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1104system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1105system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1106system.cpu3.icache.fast_writes 0 # number of fast writes performed
1107system.cpu3.icache.cache_copies 0 # number of cache copies performed
1108system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
1109system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
1110system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
1111system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
1112system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
1113system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
1114system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles
1115system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles
1116system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles
1117system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles
1118system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles
1119system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles
1120system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses
1121system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses
1122system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses
1123system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses
1124system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses
1125system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses
1126system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency
1127system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency
1128system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency
1129system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency
1130system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency
1131system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency
1132system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1133system.l2c.tags.replacements 0 # number of replacements
1134system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use
1135system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
1136system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
1137system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
1138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1139system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor
1140system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor
1141system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor
1142system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor
1143system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor
1144system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor
1145system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor
1146system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor
1147system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor
1148system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
1149system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy
1150system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy
1151system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
1152system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy
1153system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy
1154system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy
1155system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
1156system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
1157system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy
1158system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
1159system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
1160system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
1161system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
1162system.l2c.tags.tag_accesses 15709 # Number of tag accesses
1163system.l2c.tags.data_accesses 15709 # Number of data accesses
1164system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
1165system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
1166system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits
1167system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
1168system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits
1169system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits
1170system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
1171system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
1172system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
1173system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
1174system.l2c.Writeback_hits::total 1 # number of Writeback hits
1175system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
1176system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
1177system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
1178system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
1179system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
1180system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
1181system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits
1182system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
1183system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
1184system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
1185system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
1186system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
1187system.l2c.overall_hits::cpu0.data 5 # number of overall hits
1188system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
1189system.l2c.overall_hits::cpu1.data 9 # number of overall hits
1190system.l2c.overall_hits::cpu2.inst 302 # number of overall hits
1191system.l2c.overall_hits::cpu2.data 3 # number of overall hits
1192system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
1193system.l2c.overall_hits::cpu3.data 9 # number of overall hits
1194system.l2c.overall_hits::total 1220 # number of overall hits
1195system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
1196system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
1197system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses
1198system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses
1199system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses
1200system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses
1201system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
1202system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
1203system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
1204system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
1205system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
1206system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
1207system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses
1208system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
1209system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
1210system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
1211system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
1212system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
1213system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
1214system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
1215system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
1216system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
1217system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
1218system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses
1219system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
1220system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
1221system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
1222system.l2c.demand_misses::total 592 # number of demand (read+write) misses
1223system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
1224system.l2c.overall_misses::cpu0.data 165 # number of overall misses
1225system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
1226system.l2c.overall_misses::cpu1.data 16 # number of overall misses
1227system.l2c.overall_misses::cpu2.inst 64 # number of overall misses
1228system.l2c.overall_misses::cpu2.data 23 # number of overall misses
1229system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
1230system.l2c.overall_misses::cpu3.data 16 # number of overall misses
1231system.l2c.overall_misses::total 592 # number of overall misses
1232system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles
1233system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles
1234system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles
1235system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles
1236system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles
1237system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles
1238system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles
1239system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles
1240system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles
1241system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles
1242system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles
1243system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles
1244system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles
1245system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles
1246system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles
1247system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles
1248system.l2c.demand_miss_latency::cpu1.inst 714500 # number of demand (read+write) miss cycles
1249system.l2c.demand_miss_latency::cpu1.data 848000 # number of demand (read+write) miss cycles
1250system.l2c.demand_miss_latency::cpu2.inst 3356500 # number of demand (read+write) miss cycles
1251system.l2c.demand_miss_latency::cpu2.data 1211500 # number of demand (read+write) miss cycles
1252system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles
1253system.l2c.demand_miss_latency::cpu3.data 843500 # number of demand (read+write) miss cycles
1254system.l2c.demand_miss_latency::total 31057500 # number of demand (read+write) miss cycles
1255system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles
1256system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles
1257system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles
1258system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles
1259system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles
1260system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles
1261system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles
1262system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles
1263system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles
1264system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
1265system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
1266system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
1267system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
1268system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses)
1269system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
1270system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses)
1271system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
1272system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
1273system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
1274system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
1275system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
1276system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
1277system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
1278system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
1279system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
1280system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
1281system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
1282system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
1283system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
1284system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
1285system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
1286system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
1287system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
1288system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
1289system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
1290system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
1291system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
1292system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
1293system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
1294system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
1295system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
1296system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
1297system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
1298system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
1299system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
1300system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
1301system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
1302system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
1303system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
1304system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
1305system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses
1306system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses
1307system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses
1308system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses
1309system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses
1310system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses
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1519system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency
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1521system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency
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1523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency
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1525system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency
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1527system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency
1528system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
1529system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
1530system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency
1531system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency
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1537system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
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1541system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency
1542system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency
1543system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency
1544system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency
1545system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency
1546system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1547system.membus.trans_dist::ReadReq 430 # Transaction distribution
1548system.membus.trans_dist::ReadResp 430 # Transaction distribution
1549system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
1550system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
1551system.membus.trans_dist::ReadExReq 208 # Transaction distribution
1552system.membus.trans_dist::ReadExResp 142 # Transaction distribution
1553system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
1554system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
1555system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
1556system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
1557system.membus.snoops 261 # Total snoops (count)
1558system.membus.snoop_fanout::samples 914 # Request fanout histogram
1559system.membus.snoop_fanout::mean 0 # Request fanout histogram
1560system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1561system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1562system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram
1563system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1564system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1565system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1566system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1567system.membus.snoop_fanout::total 914 # Request fanout histogram
1568system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks)
1569system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
1570system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks)
1571system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
1572system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution
1573system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution
1574system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
1575system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
1576system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
1577system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
1578system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
1579system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
1580system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
1581system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
1582system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
1583system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
1584system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
1585system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes)
1586system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
1587system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes)
1588system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
1589system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
1590system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
1591system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1592system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
1593system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
1594system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
1595system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
1596system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
1597system.toL2Bus.snoops 1029 # Total snoops (count)
1598system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram
1599system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
1600system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
1601system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1602system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1603system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1604system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1605system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1606system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1607system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
1608system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
1609system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram
1610system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
1611system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1612system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
1613system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
1614system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram
1615system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks)
1616system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
1617system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
1618system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
1619system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks)
1620system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
1621system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks)
1622system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
1623system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks)
1624system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
1625system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks)
1626system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
1627system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks)
1628system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
1629system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks)
1630system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
1631system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks)
1632system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
1633
1634---------- End Simulation Statistics ----------