config.ini (9055:38f1926fb599) | config.ini (9096:8971a998190a) |
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1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 435 unchanged lines hidden (view full) --- 444mem_side=system.membus.slave[0] 445 446[system.membus] 447type=CoherentBus 448block_size=64 449clock=1000 450header_cycles=1 451use_default_range=false | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 435 unchanged lines hidden (view full) --- 444mem_side=system.membus.slave[0] 445 446[system.membus] 447type=CoherentBus 448block_size=64 449clock=1000 450header_cycles=1 451use_default_range=false |
452width=64 | 452width=8 |
453master=system.physmem.port[0] 454slave=system.l2c.mem_side system.system_port 455 456[system.physmem] 457type=SimpleMemory 458conf_table_reported=false 459file= 460in_addr_map=true --- 5 unchanged lines hidden (view full) --- 466port=system.membus.master[0] 467 468[system.toL2Bus] 469type=CoherentBus 470block_size=64 471clock=1000 472header_cycles=1 473use_default_range=false | 453master=system.physmem.port[0] 454slave=system.l2c.mem_side system.system_port 455 456[system.physmem] 457type=SimpleMemory 458conf_table_reported=false 459file= 460in_addr_map=true --- 5 unchanged lines hidden (view full) --- 466port=system.membus.master[0] 467 468[system.toL2Bus] 469type=CoherentBus 470block_size=64 471clock=1000 472header_cycles=1 473use_default_range=false |
474width=64 | 474width=8 |
475master=system.l2c.cpu_side 476slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 477 | 475master=system.l2c.cpu_side 476slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 477 |