| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 430 unchanged lines hidden (view full) --- 439tgts_per_mshr=16 440trace_addr=0 441two_queue=false 442write_buffers=8 443cpu_side=system.toL2Bus.master[0] 444mem_side=system.membus.slave[0] 445 446[system.membus] | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 430 unchanged lines hidden (view full) --- 439tgts_per_mshr=16 440trace_addr=0 441two_queue=false 442write_buffers=8 443cpu_side=system.toL2Bus.master[0] 444mem_side=system.membus.slave[0] 445 446[system.membus] |
| 447type=Bus | 447type=CoherentBus |
| 448block_size=64 | 448block_size=64 |
| 449bus_id=0 | |
| 450clock=1000 451header_cycles=1 452use_default_range=false 453width=64 454master=system.physmem.port[0] 455slave=system.l2c.mem_side system.system_port 456 457[system.physmem] --- 4 unchanged lines hidden (view full) --- 462latency=30000 463latency_var=0 464null=false 465range=0:134217727 466zero=false 467port=system.membus.master[0] 468 469[system.toL2Bus] | 449clock=1000 450header_cycles=1 451use_default_range=false 452width=64 453master=system.physmem.port[0] 454slave=system.l2c.mem_side system.system_port 455 456[system.physmem] --- 4 unchanged lines hidden (view full) --- 461latency=30000 462latency_var=0 463null=false 464range=0:134217727 465zero=false 466port=system.membus.master[0] 467 468[system.toL2Bus] |
| 470type=Bus | 469type=CoherentBus |
| 471block_size=64 | 470block_size=64 |
| 472bus_id=0 | |
| 473clock=1000 474header_cycles=1 475use_default_range=false 476width=64 477master=system.l2c.cpu_side 478slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 479 | 471clock=1000 472header_cycles=1 473use_default_range=false 474width=64 475master=system.l2c.cpu_side 476slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 477 |