| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 |
| 19physmem=system.physmem | |
| 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 |
| 29system_port=system.membus.port[1] | 28system_port=system.membus.slave[1] |
| 30 31[system.cpu0] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false --- 16 unchanged lines hidden (view full) --- 54system=system 55tracer=system.cpu0.tracer 56workload=system.cpu0.workload 57dcache_port=system.cpu0.dcache.cpu_side 58icache_port=system.cpu0.icache.cpu_side 59 60[system.cpu0.dcache] 61type=BaseCache | 29 30[system.cpu0] 31type=TimingSimpleCPU 32children=dcache dtb icache interrupts itb tracer workload 33checker=Null 34clock=500 35cpu_id=0 36defer_registration=false --- 16 unchanged lines hidden (view full) --- 53system=system 54tracer=system.cpu0.tracer 55workload=system.cpu0.workload 56dcache_port=system.cpu0.dcache.cpu_side 57icache_port=system.cpu0.icache.cpu_side 58 59[system.cpu0.dcache] 60type=BaseCache |
| 62addr_range=0:18446744073709551615 | 61addr_ranges=0:18446744073709551615 |
| 63assoc=4 64block_size=64 65forward_snoops=true 66hash_delay=1 67is_top_level=true 68latency=1000 69max_miss_count=0 70mshrs=4 --- 4 unchanged lines hidden (view full) --- 75size=32768 76subblock_size=0 77system=system 78tgts_per_mshr=8 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu0.dcache_port | 62assoc=4 63block_size=64 64forward_snoops=true 65hash_delay=1 66is_top_level=true 67latency=1000 68max_miss_count=0 69mshrs=4 --- 4 unchanged lines hidden (view full) --- 74size=32768 75subblock_size=0 76system=system 77tgts_per_mshr=8 78trace_addr=0 79two_queue=false 80write_buffers=8 81cpu_side=system.cpu0.dcache_port |
| 83mem_side=system.toL2Bus.port[2] | 82mem_side=system.toL2Bus.slave[1] |
| 84 85[system.cpu0.dtb] 86type=SparcTLB 87size=64 88 89[system.cpu0.icache] 90type=BaseCache | 83 84[system.cpu0.dtb] 85type=SparcTLB 86size=64 87 88[system.cpu0.icache] 89type=BaseCache |
| 91addr_range=0:18446744073709551615 | 90addr_ranges=0:18446744073709551615 |
| 92assoc=1 93block_size=64 94forward_snoops=true 95hash_delay=1 96is_top_level=true 97latency=1000 98max_miss_count=0 99mshrs=4 --- 4 unchanged lines hidden (view full) --- 104size=32768 105subblock_size=0 106system=system 107tgts_per_mshr=8 108trace_addr=0 109two_queue=false 110write_buffers=8 111cpu_side=system.cpu0.icache_port | 91assoc=1 92block_size=64 93forward_snoops=true 94hash_delay=1 95is_top_level=true 96latency=1000 97max_miss_count=0 98mshrs=4 --- 4 unchanged lines hidden (view full) --- 103size=32768 104subblock_size=0 105system=system 106tgts_per_mshr=8 107trace_addr=0 108two_queue=false 109write_buffers=8 110cpu_side=system.cpu0.icache_port |
| 112mem_side=system.toL2Bus.port[1] | 111mem_side=system.toL2Bus.slave[0] |
| 113 114[system.cpu0.interrupts] 115type=SparcInterrupts 116 117[system.cpu0.itb] 118type=SparcTLB 119size=64 120 --- 45 unchanged lines hidden (view full) --- 166system=system 167tracer=system.cpu1.tracer 168workload=system.cpu0.workload 169dcache_port=system.cpu1.dcache.cpu_side 170icache_port=system.cpu1.icache.cpu_side 171 172[system.cpu1.dcache] 173type=BaseCache | 112 113[system.cpu0.interrupts] 114type=SparcInterrupts 115 116[system.cpu0.itb] 117type=SparcTLB 118size=64 119 --- 45 unchanged lines hidden (view full) --- 165system=system 166tracer=system.cpu1.tracer 167workload=system.cpu0.workload 168dcache_port=system.cpu1.dcache.cpu_side 169icache_port=system.cpu1.icache.cpu_side 170 171[system.cpu1.dcache] 172type=BaseCache |
| 174addr_range=0:18446744073709551615 | 173addr_ranges=0:18446744073709551615 |
| 175assoc=4 176block_size=64 177forward_snoops=true 178hash_delay=1 179is_top_level=true 180latency=1000 181max_miss_count=0 182mshrs=4 --- 4 unchanged lines hidden (view full) --- 187size=32768 188subblock_size=0 189system=system 190tgts_per_mshr=8 191trace_addr=0 192two_queue=false 193write_buffers=8 194cpu_side=system.cpu1.dcache_port | 174assoc=4 175block_size=64 176forward_snoops=true 177hash_delay=1 178is_top_level=true 179latency=1000 180max_miss_count=0 181mshrs=4 --- 4 unchanged lines hidden (view full) --- 186size=32768 187subblock_size=0 188system=system 189tgts_per_mshr=8 190trace_addr=0 191two_queue=false 192write_buffers=8 193cpu_side=system.cpu1.dcache_port |
| 195mem_side=system.toL2Bus.port[4] | 194mem_side=system.toL2Bus.slave[3] |
| 196 197[system.cpu1.dtb] 198type=SparcTLB 199size=64 200 201[system.cpu1.icache] 202type=BaseCache | 195 196[system.cpu1.dtb] 197type=SparcTLB 198size=64 199 200[system.cpu1.icache] 201type=BaseCache |
| 203addr_range=0:18446744073709551615 | 202addr_ranges=0:18446744073709551615 |
| 204assoc=1 205block_size=64 206forward_snoops=true 207hash_delay=1 208is_top_level=true 209latency=1000 210max_miss_count=0 211mshrs=4 --- 4 unchanged lines hidden (view full) --- 216size=32768 217subblock_size=0 218system=system 219tgts_per_mshr=8 220trace_addr=0 221two_queue=false 222write_buffers=8 223cpu_side=system.cpu1.icache_port | 203assoc=1 204block_size=64 205forward_snoops=true 206hash_delay=1 207is_top_level=true 208latency=1000 209max_miss_count=0 210mshrs=4 --- 4 unchanged lines hidden (view full) --- 215size=32768 216subblock_size=0 217system=system 218tgts_per_mshr=8 219trace_addr=0 220two_queue=false 221write_buffers=8 222cpu_side=system.cpu1.icache_port |
| 224mem_side=system.toL2Bus.port[3] | 223mem_side=system.toL2Bus.slave[2] |
| 225 226[system.cpu1.interrupts] 227type=SparcInterrupts 228 229[system.cpu1.itb] 230type=SparcTLB 231size=64 232 --- 26 unchanged lines hidden (view full) --- 259system=system 260tracer=system.cpu2.tracer 261workload=system.cpu0.workload 262dcache_port=system.cpu2.dcache.cpu_side 263icache_port=system.cpu2.icache.cpu_side 264 265[system.cpu2.dcache] 266type=BaseCache | 224 225[system.cpu1.interrupts] 226type=SparcInterrupts 227 228[system.cpu1.itb] 229type=SparcTLB 230size=64 231 --- 26 unchanged lines hidden (view full) --- 258system=system 259tracer=system.cpu2.tracer 260workload=system.cpu0.workload 261dcache_port=system.cpu2.dcache.cpu_side 262icache_port=system.cpu2.icache.cpu_side 263 264[system.cpu2.dcache] 265type=BaseCache |
| 267addr_range=0:18446744073709551615 | 266addr_ranges=0:18446744073709551615 |
| 268assoc=4 269block_size=64 270forward_snoops=true 271hash_delay=1 272is_top_level=true 273latency=1000 274max_miss_count=0 275mshrs=4 --- 4 unchanged lines hidden (view full) --- 280size=32768 281subblock_size=0 282system=system 283tgts_per_mshr=8 284trace_addr=0 285two_queue=false 286write_buffers=8 287cpu_side=system.cpu2.dcache_port | 267assoc=4 268block_size=64 269forward_snoops=true 270hash_delay=1 271is_top_level=true 272latency=1000 273max_miss_count=0 274mshrs=4 --- 4 unchanged lines hidden (view full) --- 279size=32768 280subblock_size=0 281system=system 282tgts_per_mshr=8 283trace_addr=0 284two_queue=false 285write_buffers=8 286cpu_side=system.cpu2.dcache_port |
| 288mem_side=system.toL2Bus.port[6] | 287mem_side=system.toL2Bus.slave[5] |
| 289 290[system.cpu2.dtb] 291type=SparcTLB 292size=64 293 294[system.cpu2.icache] 295type=BaseCache | 288 289[system.cpu2.dtb] 290type=SparcTLB 291size=64 292 293[system.cpu2.icache] 294type=BaseCache |
| 296addr_range=0:18446744073709551615 | 295addr_ranges=0:18446744073709551615 |
| 297assoc=1 298block_size=64 299forward_snoops=true 300hash_delay=1 301is_top_level=true 302latency=1000 303max_miss_count=0 304mshrs=4 --- 4 unchanged lines hidden (view full) --- 309size=32768 310subblock_size=0 311system=system 312tgts_per_mshr=8 313trace_addr=0 314two_queue=false 315write_buffers=8 316cpu_side=system.cpu2.icache_port | 296assoc=1 297block_size=64 298forward_snoops=true 299hash_delay=1 300is_top_level=true 301latency=1000 302max_miss_count=0 303mshrs=4 --- 4 unchanged lines hidden (view full) --- 308size=32768 309subblock_size=0 310system=system 311tgts_per_mshr=8 312trace_addr=0 313two_queue=false 314write_buffers=8 315cpu_side=system.cpu2.icache_port |
| 317mem_side=system.toL2Bus.port[5] | 316mem_side=system.toL2Bus.slave[4] |
| 318 319[system.cpu2.interrupts] 320type=SparcInterrupts 321 322[system.cpu2.itb] 323type=SparcTLB 324size=64 325 --- 26 unchanged lines hidden (view full) --- 352system=system 353tracer=system.cpu3.tracer 354workload=system.cpu0.workload 355dcache_port=system.cpu3.dcache.cpu_side 356icache_port=system.cpu3.icache.cpu_side 357 358[system.cpu3.dcache] 359type=BaseCache | 317 318[system.cpu2.interrupts] 319type=SparcInterrupts 320 321[system.cpu2.itb] 322type=SparcTLB 323size=64 324 --- 26 unchanged lines hidden (view full) --- 351system=system 352tracer=system.cpu3.tracer 353workload=system.cpu0.workload 354dcache_port=system.cpu3.dcache.cpu_side 355icache_port=system.cpu3.icache.cpu_side 356 357[system.cpu3.dcache] 358type=BaseCache |
| 360addr_range=0:18446744073709551615 | 359addr_ranges=0:18446744073709551615 |
| 361assoc=4 362block_size=64 363forward_snoops=true 364hash_delay=1 365is_top_level=true 366latency=1000 367max_miss_count=0 368mshrs=4 --- 4 unchanged lines hidden (view full) --- 373size=32768 374subblock_size=0 375system=system 376tgts_per_mshr=8 377trace_addr=0 378two_queue=false 379write_buffers=8 380cpu_side=system.cpu3.dcache_port | 360assoc=4 361block_size=64 362forward_snoops=true 363hash_delay=1 364is_top_level=true 365latency=1000 366max_miss_count=0 367mshrs=4 --- 4 unchanged lines hidden (view full) --- 372size=32768 373subblock_size=0 374system=system 375tgts_per_mshr=8 376trace_addr=0 377two_queue=false 378write_buffers=8 379cpu_side=system.cpu3.dcache_port |
| 381mem_side=system.toL2Bus.port[8] | 380mem_side=system.toL2Bus.slave[7] |
| 382 383[system.cpu3.dtb] 384type=SparcTLB 385size=64 386 387[system.cpu3.icache] 388type=BaseCache | 381 382[system.cpu3.dtb] 383type=SparcTLB 384size=64 385 386[system.cpu3.icache] 387type=BaseCache |
| 389addr_range=0:18446744073709551615 | 388addr_ranges=0:18446744073709551615 |
| 390assoc=1 391block_size=64 392forward_snoops=true 393hash_delay=1 394is_top_level=true 395latency=1000 396max_miss_count=0 397mshrs=4 --- 4 unchanged lines hidden (view full) --- 402size=32768 403subblock_size=0 404system=system 405tgts_per_mshr=8 406trace_addr=0 407two_queue=false 408write_buffers=8 409cpu_side=system.cpu3.icache_port | 389assoc=1 390block_size=64 391forward_snoops=true 392hash_delay=1 393is_top_level=true 394latency=1000 395max_miss_count=0 396mshrs=4 --- 4 unchanged lines hidden (view full) --- 401size=32768 402subblock_size=0 403system=system 404tgts_per_mshr=8 405trace_addr=0 406two_queue=false 407write_buffers=8 408cpu_side=system.cpu3.icache_port |
| 410mem_side=system.toL2Bus.port[7] | 409mem_side=system.toL2Bus.slave[6] |
| 411 412[system.cpu3.interrupts] 413type=SparcInterrupts 414 415[system.cpu3.itb] 416type=SparcTLB 417size=64 418 419[system.cpu3.tracer] 420type=ExeTracer 421 422[system.l2c] 423type=BaseCache | 410 411[system.cpu3.interrupts] 412type=SparcInterrupts 413 414[system.cpu3.itb] 415type=SparcTLB 416size=64 417 418[system.cpu3.tracer] 419type=ExeTracer 420 421[system.l2c] 422type=BaseCache |
| 424addr_range=0:18446744073709551615 | 423addr_ranges=0:18446744073709551615 |
| 425assoc=8 426block_size=64 427forward_snoops=true 428hash_delay=1 429is_top_level=false 430latency=10000 431max_miss_count=0 432mshrs=92 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null 437size=4194304 438subblock_size=0 439system=system 440tgts_per_mshr=16 441trace_addr=0 442two_queue=false 443write_buffers=8 | 424assoc=8 425block_size=64 426forward_snoops=true 427hash_delay=1 428is_top_level=false 429latency=10000 430max_miss_count=0 431mshrs=92 432prefetch_on_access=false 433prefetcher=Null 434prioritizeRequests=false 435repl=Null 436size=4194304 437subblock_size=0 438system=system 439tgts_per_mshr=16 440trace_addr=0 441two_queue=false 442write_buffers=8 |
| 444cpu_side=system.toL2Bus.port[0] 445mem_side=system.membus.port[0] | 443cpu_side=system.toL2Bus.master[0] 444mem_side=system.membus.slave[0] |
| 446 447[system.membus] 448type=Bus 449block_size=64 450bus_id=0 451clock=1000 452header_cycles=1 453use_default_range=false 454width=64 | 445 446[system.membus] 447type=Bus 448block_size=64 449bus_id=0 450clock=1000 451header_cycles=1 452use_default_range=false 453width=64 |
| 455port=system.l2c.mem_side system.system_port system.physmem.port[0] | 454master=system.physmem.port[0] 455slave=system.l2c.mem_side system.system_port |
| 456 457[system.physmem] | 456 457[system.physmem] |
| 458type=PhysicalMemory | 458type=SimpleMemory 459conf_table_reported=false |
| 459file= | 460file= |
| 461in_addr_map=true |
|
| 460latency=30000 461latency_var=0 462null=false 463range=0:134217727 464zero=false | 462latency=30000 463latency_var=0 464null=false 465range=0:134217727 466zero=false |
| 465port=system.membus.port[2] | 467port=system.membus.master[0] |
| 466 467[system.toL2Bus] 468type=Bus 469block_size=64 470bus_id=0 471clock=1000 472header_cycles=1 473use_default_range=false 474width=64 | 468 469[system.toL2Bus] 470type=Bus 471block_size=64 472bus_id=0 473clock=1000 474header_cycles=1 475use_default_range=false 476width=64 |
| 475port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side | 477master=system.l2c.cpu_side 478slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |
| 476 | 479 |