19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[1]
---
> system_port=system.membus.slave[1]
62c61
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
83c82
< mem_side=system.toL2Bus.port[2]
---
> mem_side=system.toL2Bus.slave[1]
91c90
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
112c111
< mem_side=system.toL2Bus.port[1]
---
> mem_side=system.toL2Bus.slave[0]
174c173
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
195c194
< mem_side=system.toL2Bus.port[4]
---
> mem_side=system.toL2Bus.slave[3]
203c202
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
224c223
< mem_side=system.toL2Bus.port[3]
---
> mem_side=system.toL2Bus.slave[2]
267c266
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
288c287
< mem_side=system.toL2Bus.port[6]
---
> mem_side=system.toL2Bus.slave[5]
296c295
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
317c316
< mem_side=system.toL2Bus.port[5]
---
> mem_side=system.toL2Bus.slave[4]
360c359
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
381c380
< mem_side=system.toL2Bus.port[8]
---
> mem_side=system.toL2Bus.slave[7]
389c388
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
410c409
< mem_side=system.toL2Bus.port[7]
---
> mem_side=system.toL2Bus.slave[6]
424c423
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
444,445c443,444
< cpu_side=system.toL2Bus.port[0]
< mem_side=system.membus.port[0]
---
> cpu_side=system.toL2Bus.master[0]
> mem_side=system.membus.slave[0]
455c454,455
< port=system.l2c.mem_side system.system_port system.physmem.port[0]
---
> master=system.physmem.port[0]
> slave=system.l2c.mem_side system.system_port
458c458,459
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
459a461
> in_addr_map=true
465c467
< port=system.membus.port[2]
---
> port=system.membus.master[0]
475c477,478
< port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
---
> master=system.l2c.cpu_side
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side