| stats.txt (9797:9cd5f91e7a79) | stats.txt (9885:afd9ea6101d9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1256528 # Simulator instruction rate (inst/s) 8host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 162691956 # Simulator tick rate (ticks/s) 10host_mem_usage 1160656 # Number of bytes of host memory used 11host_seconds 0.54 # Real time elapsed on the host | 7host_inst_rate 170274 # Simulator instruction rate (inst/s) 8host_op_rate 170274 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22048637 # Simulator tick rate (ticks/s) 10host_mem_usage 246052 # Number of bytes of host memory used 11host_seconds 3.98 # Real time elapsed on the host |
| 12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 35 unchanged lines hidden (view full) --- 55system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 60system.membus.throughput 407903588 # Throughput (bytes/s) 61system.membus.data_through_bus 35776 # Total data (bytes) 62system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 35 unchanged lines hidden (view full) --- 55system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 60system.membus.throughput 407903588 # Throughput (bytes/s) 61system.membus.data_through_bus 35776 # Total data (bytes) 62system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 63system.l2c.tags.replacements 0 # number of replacements 64system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use 65system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 66system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 67system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 68system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 70system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 71system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 72system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 73system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 74system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 75system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 76system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 77system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor 78system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 79system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 80system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 81system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 82system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 83system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 84system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 85system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 86system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 87system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 88system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 89system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 90system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 91system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 92system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 93system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 94system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 95system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 96system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 97system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 98system.l2c.Writeback_hits::total 1 # number of Writeback hits 99system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 100system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 101system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 102system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 103system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 104system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 105system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 106system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 107system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 108system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 109system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 110system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 111system.l2c.overall_hits::cpu0.data 5 # number of overall hits 112system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 113system.l2c.overall_hits::cpu1.data 3 # number of overall hits 114system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 115system.l2c.overall_hits::cpu2.data 9 # number of overall hits 116system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 117system.l2c.overall_hits::cpu3.data 9 # number of overall hits 118system.l2c.overall_hits::total 1220 # number of overall hits 119system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 120system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 121system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 122system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 123system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 124system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 125system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 126system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 127system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 128system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 129system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 130system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 131system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 132system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses 133system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 134system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 135system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 136system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 137system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 138system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 139system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 140system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 141system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 142system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 143system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 144system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 145system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 146system.l2c.demand_misses::total 559 # number of demand (read+write) misses 147system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 148system.l2c.overall_misses::cpu0.data 165 # number of overall misses 149system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 150system.l2c.overall_misses::cpu1.data 20 # number of overall misses 151system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 152system.l2c.overall_misses::cpu2.data 13 # number of overall misses 153system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 154system.l2c.overall_misses::cpu3.data 13 # number of overall misses 155system.l2c.overall_misses::total 559 # number of overall misses 156system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 157system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 158system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 159system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 160system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 161system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 162system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 163system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 164system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 165system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 166system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 167system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 168system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 169system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 170system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 171system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) 172system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 173system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 174system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 175system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 176system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 177system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 178system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 179system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 180system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 181system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 182system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 183system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 184system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 185system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 186system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 187system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 188system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 189system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 190system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 191system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 192system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 193system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 194system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 195system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 196system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 197system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 198system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses 199system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 200system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses 201system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 202system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 203system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses 204system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 205system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 206system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 207system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 208system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses 209system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 210system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 211system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 212system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 213system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 214system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 215system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 216system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 217system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 218system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 219system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 220system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 221system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 222system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 223system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 224system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 225system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 226system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 227system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 228system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 229system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 230system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 231system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 232system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 233system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 234system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 235system.l2c.blocked::no_targets 0 # number of cycles access was blocked 236system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 237system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 238system.l2c.fast_writes 0 # number of fast writes performed 239system.l2c.cache_copies 0 # number of cache copies performed 240system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 63system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) 64system.toL2Bus.data_through_bus 166080 # Total data (bytes) 65system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 66system.cpu0.workload.num_syscalls 89 # Number of system calls 67system.cpu0.numCycles 175415 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 175326 # Number of instructions committed --- 10 unchanged lines hidden (view full) --- 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 82397 # number of memory refs 83system.cpu0.num_load_insts 54591 # Number of load instructions 84system.cpu0.num_store_insts 27806 # Number of store instructions 85system.cpu0.num_idle_cycles 0 # Number of idle cycles 86system.cpu0.num_busy_cycles 175415 # Number of busy cycles 87system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0 # Percentage of idle cycles | 241system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) 242system.toL2Bus.data_through_bus 166080 # Total data (bytes) 243system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 244system.cpu0.workload.num_syscalls 89 # Number of system calls 245system.cpu0.numCycles 175415 # number of cpu cycles simulated 246system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 247system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 248system.cpu0.committedInsts 175326 # Number of instructions committed --- 10 unchanged lines hidden (view full) --- 259system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 260system.cpu0.num_mem_refs 82397 # number of memory refs 261system.cpu0.num_load_insts 54591 # Number of load instructions 262system.cpu0.num_store_insts 27806 # Number of store instructions 263system.cpu0.num_idle_cycles 0 # Number of idle cycles 264system.cpu0.num_busy_cycles 175415 # Number of busy cycles 265system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 266system.cpu0.idle_fraction 0 # Percentage of idle cycles |
| 89system.cpu0.icache.tags.replacements 215 # number of replacements 90system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use 91system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 92system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 93system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 94system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 267system.cpu0.icache.tags.replacements 215 # number of replacements 268system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use 269system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 270system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 271system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 272system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 95system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor 96system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy | 273system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor 274system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy |
| 97system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy | 275system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy |
| 98system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 99system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 100system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 101system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 102system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 103system.cpu0.icache.overall_hits::total 174921 # number of overall hits 104system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 105system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 123system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 124system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 125system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 126system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 127system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128system.cpu0.icache.fast_writes 0 # number of fast writes performed 129system.cpu0.icache.cache_copies 0 # number of cache copies performed 130system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 276system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 277system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 278system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 279system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 280system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 281system.cpu0.icache.overall_hits::total 174921 # number of overall hits 282system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 283system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 301system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 302system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 303system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 304system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 305system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 306system.cpu0.icache.fast_writes 0 # number of fast writes performed 307system.cpu0.icache.cache_copies 0 # number of cache copies performed 308system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 131system.cpu0.dcache.tags.replacements 2 # number of replacements 132system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use 133system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. 134system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 135system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. 136system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 309system.cpu0.dcache.tags.replacements 2 # number of replacements 310system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use 311system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. 312system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 313system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. 314system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 137system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor 138system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy | 315system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor 316system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy |
| 139system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy | 317system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy |
| 140system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 141system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 142system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 143system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 144system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 145system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 146system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 147system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits --- 57 unchanged lines hidden (view full) --- 205system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 206system.cpu1.num_mem_refs 53394 # number of memory refs 207system.cpu1.num_load_insts 40652 # Number of load instructions 208system.cpu1.num_store_insts 12742 # Number of store instructions 209system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 210system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 211system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 212system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles | 318system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 319system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 320system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 321system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 322system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 323system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 324system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 325system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits --- 57 unchanged lines hidden (view full) --- 383system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 384system.cpu1.num_mem_refs 53394 # number of memory refs 385system.cpu1.num_load_insts 40652 # Number of load instructions 386system.cpu1.num_store_insts 12742 # Number of store instructions 387system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 388system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 389system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 390system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles |
| 213system.cpu1.icache.tags.replacements 278 # number of replacements 214system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use 215system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. 216system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 217system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. 218system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 391system.cpu1.icache.tags.replacements 278 # number of replacements 392system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use 393system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. 394system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 395system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. 396system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 219system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 220system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy | 397system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 398system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy |
| 221system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy | 399system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy |
| 222system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 223system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 224system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 225system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 226system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 227system.cpu1.icache.overall_hits::total 167072 # number of overall hits 228system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 229system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 247system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 248system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 249system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 250system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 251system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 252system.cpu1.icache.fast_writes 0 # number of fast writes performed 253system.cpu1.icache.cache_copies 0 # number of cache copies performed 254system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 400system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 401system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 402system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 403system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 404system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 405system.cpu1.icache.overall_hits::total 167072 # number of overall hits 406system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 407system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 425system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu1.icache.fast_writes 0 # number of fast writes performed 431system.cpu1.icache.cache_copies 0 # number of cache copies performed 432system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 255system.cpu1.dcache.tags.replacements 0 # number of replacements 256system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use 257system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. 258system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 259system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. 260system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 433system.cpu1.dcache.tags.replacements 0 # number of replacements 434system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use 435system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. 436system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 437system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. 438system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 261system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 262system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy | 439system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 440system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy |
| 263system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy | 441system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy |
| 264system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 265system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 266system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 267system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 268system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 269system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 270system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 271system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits --- 55 unchanged lines hidden (view full) --- 327system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 328system.cpu2.num_mem_refs 58537 # number of memory refs 329system.cpu2.num_load_insts 42362 # Number of load instructions 330system.cpu2.num_store_insts 16175 # Number of store instructions 331system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 332system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles 333system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 334system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles | 442system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 443system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 444system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 445system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 446system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 447system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 448system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 449system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits --- 55 unchanged lines hidden (view full) --- 505system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 506system.cpu2.num_mem_refs 58537 # number of memory refs 507system.cpu2.num_load_insts 42362 # Number of load instructions 508system.cpu2.num_store_insts 16175 # Number of store instructions 509system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 510system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles 511system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 512system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles |
| 335system.cpu2.icache.tags.replacements 278 # number of replacements 336system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use 337system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. 338system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 339system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. 340system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 513system.cpu2.icache.tags.replacements 278 # number of replacements 514system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use 515system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. 516system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 517system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. 518system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 341system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 342system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy | 519system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 520system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy |
| 343system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy | 521system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy |
| 344system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 345system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 346system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 347system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 348system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 349system.cpu2.icache.overall_hits::total 167008 # number of overall hits 350system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 351system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 369system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 370system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 371system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 372system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 373system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 374system.cpu2.icache.fast_writes 0 # number of fast writes performed 375system.cpu2.icache.cache_copies 0 # number of cache copies performed 376system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 522system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 523system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 524system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 525system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 526system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 527system.cpu2.icache.overall_hits::total 167008 # number of overall hits 528system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 529system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 547system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 552system.cpu2.icache.fast_writes 0 # number of fast writes performed 553system.cpu2.icache.cache_copies 0 # number of cache copies performed 554system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 377system.cpu2.dcache.tags.replacements 0 # number of replacements 378system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use 379system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. 380system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 381system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. 382system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 555system.cpu2.dcache.tags.replacements 0 # number of replacements 556system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use 557system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. 558system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 559system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. 560system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 383system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 384system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy | 561system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 562system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy |
| 385system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy | 563system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy |
| 386system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 387system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 388system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 389system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 390system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 391system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 392system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 393system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits --- 55 unchanged lines hidden (view full) --- 449system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 450system.cpu3.num_mem_refs 55900 # number of memory refs 451system.cpu3.num_load_insts 41466 # Number of load instructions 452system.cpu3.num_store_insts 14434 # Number of store instructions 453system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 454system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 455system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 456system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles | 564system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 565system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 566system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 567system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 568system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 569system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 570system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 571system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits --- 55 unchanged lines hidden (view full) --- 627system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 628system.cpu3.num_mem_refs 55900 # number of memory refs 629system.cpu3.num_load_insts 41466 # Number of load instructions 630system.cpu3.num_store_insts 14434 # Number of store instructions 631system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 632system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 633system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 634system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles |
| 457system.cpu3.icache.tags.replacements 279 # number of replacements 458system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use 459system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. 460system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 461system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. 462system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 635system.cpu3.icache.tags.replacements 279 # number of replacements 636system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use 637system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. 638system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 639system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. 640system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 463system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 464system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy | 641system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 642system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy |
| 465system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy | 643system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy |
| 466system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 467system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 468system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 469system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 470system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 471system.cpu3.icache.overall_hits::total 166942 # number of overall hits 472system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 473system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 491system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 492system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 493system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 494system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 495system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 496system.cpu3.icache.fast_writes 0 # number of fast writes performed 497system.cpu3.icache.cache_copies 0 # number of cache copies performed 498system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 644system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 645system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 646system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 647system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 648system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 649system.cpu3.icache.overall_hits::total 166942 # number of overall hits 650system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 651system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 669system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu3.icache.fast_writes 0 # number of fast writes performed 675system.cpu3.icache.cache_copies 0 # number of cache copies performed 676system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 499system.cpu3.dcache.tags.replacements 0 # number of replacements 500system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use 501system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. 502system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 503system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. 504system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 677system.cpu3.dcache.tags.replacements 0 # number of replacements 678system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use 679system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. 680system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 681system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. 682system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 505system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 506system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy | 683system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 684system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy |
| 507system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy | 685system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy |
| 508system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 509system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 510system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 511system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 512system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 513system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 514system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 515system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits --- 33 unchanged lines hidden (view full) --- 549system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 550system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 551system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 552system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 553system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 554system.cpu3.dcache.fast_writes 0 # number of fast writes performed 555system.cpu3.dcache.cache_copies 0 # number of cache copies performed 556system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 686system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 687system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 688system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 689system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 690system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 691system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 692system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 693system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits --- 33 unchanged lines hidden (view full) --- 727system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 728system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 729system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 730system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 731system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 732system.cpu3.dcache.fast_writes 0 # number of fast writes performed 733system.cpu3.dcache.cache_copies 0 # number of cache copies performed 734system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 557system.l2c.tags.replacements 0 # number of replacements 558system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use 559system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 560system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 561system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 562system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 564system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 565system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 566system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 567system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 568system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 569system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 570system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 571system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor 572system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 573system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 574system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 575system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 576system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 577system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 578system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 579system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 580system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 581system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 582system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 583system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 584system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 585system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 586system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 587system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 588system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 589system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 590system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 591system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 592system.l2c.Writeback_hits::total 1 # number of Writeback hits 593system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 594system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 595system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 596system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 597system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 598system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 599system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 600system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 601system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 602system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 603system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 604system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 605system.l2c.overall_hits::cpu0.data 5 # number of overall hits 606system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 607system.l2c.overall_hits::cpu1.data 3 # number of overall hits 608system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 609system.l2c.overall_hits::cpu2.data 9 # number of overall hits 610system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 611system.l2c.overall_hits::cpu3.data 9 # number of overall hits 612system.l2c.overall_hits::total 1220 # number of overall hits 613system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 614system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 615system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 616system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 617system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 618system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 619system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 620system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 621system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 622system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 623system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 624system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 625system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 626system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses 627system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 628system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 629system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 630system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 631system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 632system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 633system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 634system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 635system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 636system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 637system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 638system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 639system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 640system.l2c.demand_misses::total 559 # number of demand (read+write) misses 641system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 642system.l2c.overall_misses::cpu0.data 165 # number of overall misses 643system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 644system.l2c.overall_misses::cpu1.data 20 # number of overall misses 645system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 646system.l2c.overall_misses::cpu2.data 13 # number of overall misses 647system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 648system.l2c.overall_misses::cpu3.data 13 # number of overall misses 649system.l2c.overall_misses::total 559 # number of overall misses 650system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 651system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 652system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 653system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 654system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 655system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 656system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 657system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 658system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 659system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 660system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 661system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 662system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 663system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 664system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 665system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) 666system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 667system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 668system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 669system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 670system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 671system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 672system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 673system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 674system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 675system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 676system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 677system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 678system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 679system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 680system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 681system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 682system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 683system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 684system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 685system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 686system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 687system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 688system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 689system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 690system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 691system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 692system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses 693system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 694system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses 695system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 696system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 697system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses 698system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 699system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 700system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 701system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 702system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses 703system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 704system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 705system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 706system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 707system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 708system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 709system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 710system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 711system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 712system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 713system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 714system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 715system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 716system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 717system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 718system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 719system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 720system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 721system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 722system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 723system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 724system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 725system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 726system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 727system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 728system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 729system.l2c.blocked::no_targets 0 # number of cycles access was blocked 730system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 731system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 732system.l2c.fast_writes 0 # number of fast writes performed 733system.l2c.cache_copies 0 # number of cache copies performed 734system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 735 736---------- End Simulation Statistics ---------- | 735 736---------- End Simulation Statistics ---------- |