| stats.txt (9055:38f1926fb599) | stats.txt (9079:9a244ebdc3c9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1597903 # Simulator instruction rate (inst/s) 8host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 206906108 # Simulator tick rate (ticks/s) 10host_mem_usage 1149840 # Number of bytes of host memory used 11host_seconds 0.42 # Real time elapsed on the host | 7host_inst_rate 1588944 # Simulator instruction rate (inst/s) 8host_op_rate 1588869 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 205745598 # Simulator tick rate (ticks/s) 10host_mem_usage 1148436 # Number of bytes of host memory used 11host_seconds 0.43 # Real time elapsed on the host |
| 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 97 unchanged lines hidden (view full) --- 117system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 119system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 120system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.cpu0.icache.fast_writes 0 # number of fast writes performed 123system.cpu0.icache.cache_copies 0 # number of cache copies performed 124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 97 unchanged lines hidden (view full) --- 117system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 119system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 120system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.cpu0.icache.fast_writes 0 # number of fast writes performed 123system.cpu0.icache.cache_copies 0 # number of cache copies performed 124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 125system.cpu0.dcache.replacements 9 # number of replacements 126system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use 127system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. 128system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 129system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. | 125system.cpu0.dcache.replacements 2 # number of replacements 126system.cpu0.dcache.tagsinuse 150.735434 # Cycle average of tags in use 127system.cpu0.dcache.total_refs 81884 # Total number of references to valid blocks. 128system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. 129system.cpu0.dcache.avg_refs 490.323353 # Average number of references to valid blocks. |
| 130system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 130system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 131system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor 132system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy 133system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy | 131system.cpu0.dcache.occ_blocks::cpu0.data 150.735434 # Average occupied blocks per requestor 132system.cpu0.dcache.occ_percent::cpu0.data 0.294405 # Average percentage of cache occupancy 133system.cpu0.dcache.occ_percent::total 0.294405 # Average percentage of cache occupancy |
| 134system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits 135system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits 136system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 137system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 138system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 139system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 140system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits 141system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits --- 32 unchanged lines hidden (view full) --- 174system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu0.dcache.fast_writes 0 # number of fast writes performed 181system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 134system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits 135system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits 136system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 137system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 138system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 139system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 140system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits 141system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits --- 32 unchanged lines hidden (view full) --- 174system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu0.dcache.fast_writes 0 # number of fast writes performed 181system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 182system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 183system.cpu0.dcache.writebacks::total 6 # number of writebacks | 182system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 183system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 184system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 185system.cpu1.numCycles 173308 # number of cpu cycles simulated 186system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 187system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 188system.cpu1.committedInsts 167398 # Number of instructions committed 189system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 190system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 191system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 241system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 243system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 244system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 245system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 246system.cpu1.icache.fast_writes 0 # number of fast writes performed 247system.cpu1.icache.cache_copies 0 # number of cache copies performed 248system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 184system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 185system.cpu1.numCycles 173308 # number of cpu cycles simulated 186system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 187system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 188system.cpu1.committedInsts 167398 # Number of instructions committed 189system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 190system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 191system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 241system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 243system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 244system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 245system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 246system.cpu1.icache.fast_writes 0 # number of fast writes performed 247system.cpu1.icache.cache_copies 0 # number of cache copies performed 248system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 249system.cpu1.dcache.replacements 2 # number of replacements 250system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use 251system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. 252system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 253system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. | 249system.cpu1.dcache.replacements 0 # number of replacements 250system.cpu1.dcache.tagsinuse 30.314752 # Cycle average of tags in use 251system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. 252system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. 253system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. |
| 254system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 254system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 255system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor 256system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy 257system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy 258system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits 259system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits | 255system.cpu1.dcache.occ_blocks::cpu1.data 30.314752 # Average occupied blocks per requestor 256system.cpu1.dcache.occ_percent::cpu1.data 0.059208 # Average percentage of cache occupancy 257system.cpu1.dcache.occ_percent::total 0.059208 # Average percentage of cache occupancy 258system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 259system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits |
| 260system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 261system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 262system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 263system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits | 260system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 261system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 262system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 263system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits |
| 264system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits 265system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits 266system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits 267system.cpu1.dcache.overall_hits::total 53031 # number of overall hits 268system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses 269system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses | 264system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 265system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits 266system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits 267system.cpu1.dcache.overall_hits::total 53033 # number of overall hits 268system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses 269system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses |
| 270system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 271system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 272system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 273system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses | 270system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 271system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 272system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 273system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses |
| 274system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses 275system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses 276system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses 277system.cpu1.dcache.overall_misses::total 282 # number of overall misses | 274system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses 275system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses 276system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses 277system.cpu1.dcache.overall_misses::total 280 # number of overall misses |
| 278system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 279system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 280system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 281system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 282system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 283system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 284system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 285system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 286system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 287system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses | 278system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 279system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 280system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 281system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 282system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 283system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 284system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 285system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 286system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 287system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses |
| 288system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses 289system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses | 288system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses 289system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses |
| 290system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 291system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 292system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 293system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses | 290system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 291system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 292system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 293system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses |
| 294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses 295system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses 296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses 297system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses | 294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses 295system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses 296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses 297system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses |
| 298system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu1.dcache.fast_writes 0 # number of fast writes performed 305system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 298system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu1.dcache.fast_writes 0 # number of fast writes performed 305system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 306system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 307system.cpu1.dcache.writebacks::total 1 # number of writebacks | |
| 308system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 309system.cpu2.numCycles 173308 # number of cpu cycles simulated 310system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 311system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 312system.cpu2.committedInsts 167334 # Number of instructions committed 313system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 314system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 315system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 365system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 368system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 369system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 370system.cpu2.icache.fast_writes 0 # number of fast writes performed 371system.cpu2.icache.cache_copies 0 # number of cache copies performed 372system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 306system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 307system.cpu2.numCycles 173308 # number of cpu cycles simulated 308system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 309system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 310system.cpu2.committedInsts 167334 # Number of instructions committed 311system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 312system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 313system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 363system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu2.icache.fast_writes 0 # number of fast writes performed 369system.cpu2.icache.cache_copies 0 # number of cache copies performed 370system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 373system.cpu2.dcache.replacements 2 # number of replacements 374system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use 375system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. 376system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 377system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. | 371system.cpu2.dcache.replacements 0 # number of replacements 372system.cpu2.dcache.tagsinuse 29.603311 # Cycle average of tags in use 373system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. 374system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. 375system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. |
| 378system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 376system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 379system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor 380system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy 381system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy 382system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits 383system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits | 377system.cpu2.dcache.occ_blocks::cpu2.data 29.603311 # Average occupied blocks per requestor 378system.cpu2.dcache.occ_percent::cpu2.data 0.057819 # Average percentage of cache occupancy 379system.cpu2.dcache.occ_percent::total 0.057819 # Average percentage of cache occupancy 380system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 381system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits |
| 384system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 385system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 386system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 387system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits | 382system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 383system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 384system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 385system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits |
| 388system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits 389system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits 390system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits 391system.cpu2.dcache.overall_hits::total 58190 # number of overall hits 392system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses 393system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses | 386system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 387system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits 388system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits 389system.cpu2.dcache.overall_hits::total 58192 # number of overall hits 390system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses 391system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses |
| 394system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 395system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 396system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 397system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses | 392system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 393system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 394system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 395system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses |
| 398system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses 399system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses 400system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses 401system.cpu2.dcache.overall_misses::total 271 # number of overall misses | 396system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 397system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 398system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 399system.cpu2.dcache.overall_misses::total 269 # number of overall misses |
| 402system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 403system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 404system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 405system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 406system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 407system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 408system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 409system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 410system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 411system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses | 400system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 401system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 402system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 403system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 404system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 405system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 406system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 407system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 408system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 409system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses |
| 412system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses 413system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses | 410system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses 411system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses |
| 414system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 415system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 416system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 417system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses | 412system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 413system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 414system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 415system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses |
| 418system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses 419system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses 420system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses 421system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses | 416system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses 417system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses 418system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses 419system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses |
| 422system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu2.dcache.fast_writes 0 # number of fast writes performed 429system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 420system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu2.dcache.fast_writes 0 # number of fast writes performed 427system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 430system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 431system.cpu2.dcache.writebacks::total 1 # number of writebacks | |
| 432system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu3.numCycles 173307 # number of cpu cycles simulated 434system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 435system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 436system.cpu3.committedInsts 167269 # Number of instructions committed 437system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 438system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 439system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 489system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 490system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 491system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 492system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 493system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 494system.cpu3.icache.fast_writes 0 # number of fast writes performed 495system.cpu3.icache.cache_copies 0 # number of cache copies performed 496system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 428system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 429system.cpu3.numCycles 173307 # number of cpu cycles simulated 430system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 431system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 432system.cpu3.committedInsts 167269 # Number of instructions committed 433system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 434system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 435system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses --- 49 unchanged lines hidden (view full) --- 485system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 486system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 487system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 488system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 489system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 490system.cpu3.icache.fast_writes 0 # number of fast writes performed 491system.cpu3.icache.cache_copies 0 # number of cache copies performed 492system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 497system.cpu3.dcache.replacements 2 # number of replacements 498system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use 499system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. 500system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 501system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. | 493system.cpu3.dcache.replacements 0 # number of replacements 494system.cpu3.dcache.tagsinuse 28.793270 # Cycle average of tags in use 495system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. 496system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. 497system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. |
| 502system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 498system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 503system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor 504system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy 505system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy 506system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits 507system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits | 499system.cpu3.dcache.occ_blocks::cpu3.data 28.793270 # Average occupied blocks per requestor 500system.cpu3.dcache.occ_percent::cpu3.data 0.056237 # Average percentage of cache occupancy 501system.cpu3.dcache.occ_percent::total 0.056237 # Average percentage of cache occupancy 502system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 503system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits |
| 508system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 509system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 510system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 511system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits | 504system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 505system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 506system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 507system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits |
| 512system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits 513system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits 514system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits 515system.cpu3.dcache.overall_hits::total 55559 # number of overall hits 516system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses 517system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses | 508system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 509system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits 510system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits 511system.cpu3.dcache.overall_hits::total 55561 # number of overall hits 512system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 513system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses |
| 518system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 519system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 520system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 521system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses | 514system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 515system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 516system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 517system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses |
| 522system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses 523system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses 524system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses 525system.cpu3.dcache.overall_misses::total 261 # number of overall misses | 518system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses 519system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses 520system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses 521system.cpu3.dcache.overall_misses::total 259 # number of overall misses |
| 526system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 527system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 528system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 529system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 530system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 531system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 532system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 533system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 534system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 535system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses | 522system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 523system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 524system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 525system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 526system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 527system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 528system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 529system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 530system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 531system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses |
| 536system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses 537system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses | 532system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses 533system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses |
| 538system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 539system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 540system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 541system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses | 534system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 535system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 536system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 537system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses |
| 542system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses 543system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses 544system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses 545system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses | 538system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses 539system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses 540system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses 541system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses |
| 546system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 552system.cpu3.dcache.fast_writes 0 # number of fast writes performed 553system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 542system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 546system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 547system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 548system.cpu3.dcache.fast_writes 0 # number of fast writes performed 549system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 554system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 555system.cpu3.dcache.writebacks::total 1 # number of writebacks | |
| 556system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.l2c.replacements 0 # number of replacements | 550system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 551system.l2c.replacements 0 # number of replacements |
| 558system.l2c.tagsinuse 371.980910 # Cycle average of tags in use 559system.l2c.total_refs 1223 # Total number of references to valid blocks. 560system.l2c.sampled_refs 426 # Sample count of references to valid blocks. 561system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. | 552system.l2c.tagsinuse 366.557230 # Cycle average of tags in use 553system.l2c.total_refs 1220 # Total number of references to valid blocks. 554system.l2c.sampled_refs 421 # Sample count of references to valid blocks. 555system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. |
| 562system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 556system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 563system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor | 557system.l2c.occ_blocks::writebacks 0.966368 # Average occupied blocks per requestor |
| 564system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor 565system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor 566system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor 567system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor 568system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor 569system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor 570system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor 571system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor | 558system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor 559system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor 560system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor 561system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor 562system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor 563system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor 564system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor 565system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor |
| 572system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy | 566system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy |
| 573system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 574system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 575system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 576system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 577system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 578system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 579system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 580system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy | 567system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 568system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 569system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 570system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 571system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 572system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 573system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 574system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy |
| 581system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy | 575system.l2c.occ_percent::total 0.005593 # Average percentage of cache occupancy |
| 582system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 583system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 584system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits | 576system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 577system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 578system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits |
| 585system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits | 579system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits |
| 586system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits | 580system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits |
| 587system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits | 581system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits |
| 588system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits | 582system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits |
| 589system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 590system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits 591system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits 592system.l2c.Writeback_hits::total 9 # number of Writeback hits | 583system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 584system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 585system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 586system.l2c.Writeback_hits::total 1 # number of Writeback hits |
| 593system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 594system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 595system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 596system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 597system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits | 587system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 588system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 589system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 590system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 591system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits |
| 598system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits | 592system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits |
| 599system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits | 593system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits |
| 600system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits | 594system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits |
| 601system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits | 595system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits |
| 602system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 603system.l2c.demand_hits::total 1226 # number of demand (read+write) hits | 596system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 597system.l2c.demand_hits::total 1220 # number of demand (read+write) hits |
| 604system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 605system.l2c.overall_hits::cpu0.data 5 # number of overall hits 606system.l2c.overall_hits::cpu1.inst 296 # number of overall hits | 598system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 599system.l2c.overall_hits::cpu0.data 5 # number of overall hits 600system.l2c.overall_hits::cpu1.inst 296 # number of overall hits |
| 607system.l2c.overall_hits::cpu1.data 5 # number of overall hits | 601system.l2c.overall_hits::cpu1.data 3 # number of overall hits |
| 608system.l2c.overall_hits::cpu2.inst 356 # number of overall hits | 602system.l2c.overall_hits::cpu2.inst 356 # number of overall hits |
| 609system.l2c.overall_hits::cpu2.data 11 # number of overall hits | 603system.l2c.overall_hits::cpu2.data 9 # number of overall hits |
| 610system.l2c.overall_hits::cpu3.inst 357 # number of overall hits | 604system.l2c.overall_hits::cpu3.inst 357 # number of overall hits |
| 611system.l2c.overall_hits::cpu3.data 11 # number of overall hits 612system.l2c.overall_hits::total 1226 # number of overall hits | 605system.l2c.overall_hits::cpu3.data 9 # number of overall hits 606system.l2c.overall_hits::total 1220 # number of overall hits |
| 613system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 614system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 615system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 616system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 617system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 618system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 619system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 620system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 621system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 622system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses | 607system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 608system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 609system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 610system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 611system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 612system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 613system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 614system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 615system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 616system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses |
| 623system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 624system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses 625system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 626system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses | 617system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 618system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 619system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 620system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses |
| 627system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 628system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 629system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 630system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 631system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 632system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 633system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 634system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses --- 10 unchanged lines hidden (view full) --- 645system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 646system.l2c.overall_misses::cpu2.data 13 # number of overall misses 647system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 648system.l2c.overall_misses::cpu3.data 13 # number of overall misses 649system.l2c.overall_misses::total 559 # number of overall misses 650system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 651system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 652system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) | 621system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 622system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 623system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 624system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 625system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 626system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 627system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 628system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses --- 10 unchanged lines hidden (view full) --- 639system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 640system.l2c.overall_misses::cpu2.data 13 # number of overall misses 641system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 642system.l2c.overall_misses::cpu3.data 13 # number of overall misses 643system.l2c.overall_misses::total 559 # number of overall misses 644system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 645system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 646system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) |
| 653system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) | 647system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) |
| 654system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) | 648system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) |
| 655system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) | 649system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) |
| 656system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) | 650system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) |
| 657system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 658system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) 659system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) 660system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) | 651system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 652system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 653system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 654system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) |
| 661system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) | 655system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) |
| 662system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 663system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) 664system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 665system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) | 656system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 657system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 658system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 659system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) |
| 666system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 667system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 668system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 669system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 670system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 671system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 672system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 673system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses | 660system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 661system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 662system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 663system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 664system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 665system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 666system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 667system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses |
| 674system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses | 668system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses |
| 675system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses | 669system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses |
| 676system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses | 670system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses |
| 677system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses | 671system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses |
| 678system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 679system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses | 672system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 673system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses |
| 680system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 681system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 682system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses | 674system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 675system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 676system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses |
| 683system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses | 677system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses |
| 684system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses | 678system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses |
| 685system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses | 679system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses |
| 686system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses | 680system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses |
| 687system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 688system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses | 681system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 682system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses |
| 689system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 690system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 691system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses | 683system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 684system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 685system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses |
| 692system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses | 686system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses |
| 693system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses | 687system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses |
| 694system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses | 688system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses |
| 695system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses | 689system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses |
| 696system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 697system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses | 690system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 691system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses |
| 698system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 699system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 700system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 701system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 692system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 693system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 694system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 695system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 702system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses | 696system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses |
| 703system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 704system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 705system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 706system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 707system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 708system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 709system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 710system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses | 697system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 698system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 699system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 700system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 701system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 702system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 703system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 704system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses |
| 711system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses | 705system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses |
| 712system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses | 706system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses |
| 713system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses | 707system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses |
| 714system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses | 708system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses |
| 715system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 716system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses | 709system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 710system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses |
| 717system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 718system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 719system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses | 711system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 712system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 713system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses |
| 720system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses | 714system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses |
| 721system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses | 715system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses |
| 722system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses | 716system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses |
| 723system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses | 717system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses |
| 724system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 725system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses | 718system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 719system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses |
| 726system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 727system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 728system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 729system.l2c.blocked::no_targets 0 # number of cycles access was blocked 730system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 731system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 732system.l2c.fast_writes 0 # number of fast writes performed 733system.l2c.cache_copies 0 # number of cache copies performed 734system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 735 736---------- End Simulation Statistics ---------- | 720system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 723system.l2c.blocked::no_targets 0 # number of cycles access was blocked 724system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.l2c.fast_writes 0 # number of fast writes performed 727system.l2c.cache_copies 0 # number of cache copies performed 728system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 729 730---------- End Simulation Statistics ---------- |