| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 523852 # Simulator instruction rate (inst/s) 8host_op_rate 523839 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67834135 # Simulator tick rate (ticks/s) 10host_mem_usage 1149444 # Number of bytes of host memory used 11host_seconds 1.29 # Real time elapsed on the host | 7host_inst_rate 1597903 # Simulator instruction rate (inst/s) 8host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 206906108 # Simulator tick rate (ticks/s) 10host_mem_usage 1149840 # Number of bytes of host memory used 11host_seconds 0.42 # Real time elapsed on the host |
| 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated | 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 35776 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 559 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 205760801 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 120391958 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 45238190 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 14592965 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 1459296 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 9485427 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1459296 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 9485427 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 407873360 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 205760801 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 45238190 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 253917584 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 205760801 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 120391958 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 45238190 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 14592965 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 1459296 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 9485427 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1459296 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 9485427 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 407873360 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu0.workload.num_syscalls 89 # Number of system calls 24system.cpu0.numCycles 175428 # number of cpu cycles simulated 25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu0.committedInsts 175339 # Number of instructions committed 28system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed 29system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses 30system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 35 unchanged lines hidden (view full) --- 66system.cpu0.icache.overall_misses::total 467 # number of overall misses 67system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses) 68system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses) 69system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses 70system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses 71system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses 72system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses 73system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses | 60system.cpu0.workload.num_syscalls 89 # Number of system calls 61system.cpu0.numCycles 175428 # number of cpu cycles simulated 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu0.committedInsts 175339 # Number of instructions committed 65system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed 66system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses 67system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 35 unchanged lines hidden (view full) --- 103system.cpu0.icache.overall_misses::total 467 # number of overall misses 104system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses) 105system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses) 106system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses 107system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses 108system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses 109system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses 110system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses |
| 111system.cpu0.icache.ReadReq_miss_rate::total 0.002662 # miss rate for ReadReq accesses |
|
| 74system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses | 112system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses |
| 113system.cpu0.icache.demand_miss_rate::total 0.002662 # miss rate for demand accesses |
|
| 75system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses | 114system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses |
| 115system.cpu0.icache.overall_miss_rate::total 0.002662 # miss rate for overall accesses |
|
| 76system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 79system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 80system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 82system.cpu0.icache.fast_writes 0 # number of fast writes performed 83system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 117system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 118system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 119system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 120system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses 121system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses 122system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses 123system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses 124system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses | 116system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 119system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 120system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.cpu0.icache.fast_writes 0 # number of fast writes performed 123system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 157system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 158system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 159system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 160system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses 161system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses 162system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses 163system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses 164system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses |
| 165system.cpu0.dcache.ReadReq_miss_rate::total 0.002766 # miss rate for ReadReq accesses |
|
| 125system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses | 166system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses |
| 167system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses |
|
| 126system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses | 168system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses |
| 169system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses |
|
| 127system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses | 170system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses |
| 171system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses |
|
| 128system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses | 172system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses |
| 173system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses |
|
| 129system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 130system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 131system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 132system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 133system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 134system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 135system.cpu0.dcache.fast_writes 0 # number of fast writes performed 136system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 182system.cpu1.icache.overall_misses::total 358 # number of overall misses 183system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 184system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 185system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 186system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 187system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 188system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 189system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses | 174system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu0.dcache.fast_writes 0 # number of fast writes performed 181system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 227system.cpu1.icache.overall_misses::total 358 # number of overall misses 228system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 229system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 230system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 231system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 232system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 233system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 234system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses |
| 235system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses |
|
| 190system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses | 236system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses |
| 237system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses |
|
| 191system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses | 238system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses |
| 239system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses |
|
| 192system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 196system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 197system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 198system.cpu1.icache.fast_writes 0 # number of fast writes performed 199system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 233system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 234system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 235system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 236system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 237system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 238system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 239system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 240system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses | 240system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 241system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 243system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 244system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 245system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 246system.cpu1.icache.fast_writes 0 # number of fast writes performed 247system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 281system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 282system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 283system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 284system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 285system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 286system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 287system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 288system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses |
| 289system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses |
|
| 241system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses | 290system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses |
| 291system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses |
|
| 242system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses | 292system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses |
| 293system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses |
|
| 243system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses | 294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses |
| 295system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses |
|
| 244system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses | 296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses |
| 297system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses |
|
| 245system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251system.cpu1.dcache.fast_writes 0 # number of fast writes performed 252system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 298system.cpu2.icache.overall_misses::total 358 # number of overall misses 299system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 300system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 301system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 302system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 303system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 304system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 305system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses | 298system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu1.dcache.fast_writes 0 # number of fast writes performed 305system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 351system.cpu2.icache.overall_misses::total 358 # number of overall misses 352system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 353system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 354system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 355system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 356system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 357system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 358system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses |
| 359system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses |
|
| 306system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses | 360system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses |
| 361system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses |
|
| 307system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses | 362system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses |
| 363system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses |
|
| 308system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 309system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 310system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 311system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 312system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 313system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 314system.cpu2.icache.fast_writes 0 # number of fast writes performed 315system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 349system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 350system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 351system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 352system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 353system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 354system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 355system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 356system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses | 364system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 365system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 368system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 369system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 370system.cpu2.icache.fast_writes 0 # number of fast writes performed 371system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 405system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 406system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 407system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 408system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 409system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 410system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 411system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 412system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses |
| 413system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses |
|
| 357system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses | 414system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses |
| 415system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses |
|
| 358system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses | 416system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses |
| 417system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses |
|
| 359system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses | 418system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses |
| 419system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses |
|
| 360system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses | 420system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses |
| 421system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses |
|
| 361system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 365system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 366system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 367system.cpu2.dcache.fast_writes 0 # number of fast writes performed 368system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 414system.cpu3.icache.overall_misses::total 359 # number of overall misses 415system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 416system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 417system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 418system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 419system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 420system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 421system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses | 422system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu2.dcache.fast_writes 0 # number of fast writes performed 429system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 45 unchanged lines hidden (view full) --- 475system.cpu3.icache.overall_misses::total 359 # number of overall misses 476system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 477system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 478system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 479system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 480system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 481system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 482system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses |
| 483system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses |
|
| 422system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses | 484system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses |
| 485system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses |
|
| 423system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses | 486system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses |
| 487system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses |
|
| 424system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu3.icache.fast_writes 0 # number of fast writes performed 431system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 465system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 466system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 467system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 468system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 469system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 470system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 471system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 472system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses | 488system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 489system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 490system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 491system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 492system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 493system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 494system.cpu3.icache.fast_writes 0 # number of fast writes performed 495system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 33 unchanged lines hidden (view full) --- 529system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 530system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 531system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 532system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 533system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 534system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 535system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 536system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses |
| 537system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses |
|
| 473system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses | 538system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses |
| 539system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses |
|
| 474system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses | 540system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses |
| 541system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses |
|
| 475system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses | 542system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses |
| 543system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses |
|
| 476system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses | 544system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses |
| 545system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses |
|
| 477system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 478system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 479system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 480system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 481system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 482system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 483system.cpu3.dcache.fast_writes 0 # number of fast writes performed 484system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 135 unchanged lines hidden (view full) --- 620system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 621system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 622system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 623system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses 624system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 625system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses 626system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 627system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses | 546system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 552system.cpu3.dcache.fast_writes 0 # number of fast writes performed 553system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 135 unchanged lines hidden (view full) --- 689system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 690system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 691system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 692system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses 693system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 694system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses 695system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 696system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses |
| 697system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses |
|
| 628system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 629system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 630system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 631system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 698system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 699system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 700system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 701system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 702system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses |
|
| 632system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 633system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 634system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 635system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses | 703system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 704system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 705system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 706system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses |
| 707system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
|
| 636system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 637system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 638system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 639system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 640system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 641system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 642system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 643system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses | 708system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 709system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 710system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 711system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 712system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 713system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 714system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 715system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses |
| 716system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses |
|
| 644system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 645system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 646system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 647system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 648system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 649system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 650system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 651system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses | 717system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 718system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 719system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 720system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 721system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 722system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 723system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 724system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses |
| 725system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses |
|
| 652system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 655system.l2c.blocked::no_targets 0 # number of cycles access was blocked 656system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.l2c.fast_writes 0 # number of fast writes performed 659system.l2c.cache_copies 0 # number of cache copies performed 660system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 661 662---------- End Simulation Statistics ---------- | 726system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 727system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 728system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 729system.l2c.blocked::no_targets 0 # number of cycles access was blocked 730system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 731system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 732system.l2c.fast_writes 0 # number of fast writes performed 733system.l2c.cache_copies 0 # number of cache copies performed 734system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 735 736---------- End Simulation Statistics ---------- |