| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1664146 # Simulator instruction rate (inst/s) 8host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 215483439 # Simulator tick rate (ticks/s) 10host_mem_usage 1139232 # Number of bytes of host memory used 11host_seconds 0.41 # Real time elapsed on the host | 7host_inst_rate 523852 # Simulator instruction rate (inst/s) 8host_op_rate 523839 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67834135 # Simulator tick rate (ticks/s) 10host_mem_usage 1149444 # Number of bytes of host memory used 11host_seconds 1.29 # Real time elapsed on the host |
| 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 35776 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 559 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 52 unchanged lines hidden (view full) --- 72system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses 73system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses 74system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses 75system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses 76system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 79system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 35776 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 559 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 52 unchanged lines hidden (view full) --- 72system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses 73system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses 74system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses 75system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses 76system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 79system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 80system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 81system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 80system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 82system.cpu0.icache.fast_writes 0 # number of fast writes performed 83system.cpu0.icache.cache_copies 0 # number of cache copies performed 84system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 85system.cpu0.dcache.replacements 9 # number of replacements 86system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use 87system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. 88system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 89system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 125system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 126system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 127system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 128system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 129system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 130system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 131system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 132system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 82system.cpu0.icache.fast_writes 0 # number of fast writes performed 83system.cpu0.icache.cache_copies 0 # number of cache copies performed 84system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 85system.cpu0.dcache.replacements 9 # number of replacements 86system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use 87system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. 88system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 89system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 125system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 126system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 127system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 128system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 129system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 130system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 131system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 132system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 133system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 134system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 133system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 134system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 135system.cpu0.dcache.fast_writes 0 # number of fast writes performed 136system.cpu0.dcache.cache_copies 0 # number of cache copies performed 137system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 138system.cpu0.dcache.writebacks::total 6 # number of writebacks 139system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 140system.cpu1.numCycles 173308 # number of cpu cycles simulated 141system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 142system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 188system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 189system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 190system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 191system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 192system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 135system.cpu0.dcache.fast_writes 0 # number of fast writes performed 136system.cpu0.dcache.cache_copies 0 # number of cache copies performed 137system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 138system.cpu0.dcache.writebacks::total 6 # number of writebacks 139system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 140system.cpu1.numCycles 173308 # number of cpu cycles simulated 141system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 142system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 188system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 189system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 190system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 191system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 192system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 196system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 197system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 196system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 197system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 198system.cpu1.icache.fast_writes 0 # number of fast writes performed 199system.cpu1.icache.cache_copies 0 # number of cache copies performed 200system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 201system.cpu1.dcache.replacements 2 # number of replacements 202system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use 203system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. 204system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 205system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 241system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 242system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 243system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses 244system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses 245system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 198system.cpu1.icache.fast_writes 0 # number of fast writes performed 199system.cpu1.icache.cache_copies 0 # number of cache copies performed 200system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 201system.cpu1.dcache.replacements 2 # number of replacements 202system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use 203system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. 204system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 205system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 241system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 242system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 243system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses 244system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses 245system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 249system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 250system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 249system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 251system.cpu1.dcache.fast_writes 0 # number of fast writes performed 252system.cpu1.dcache.cache_copies 0 # number of cache copies performed 253system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 254system.cpu1.dcache.writebacks::total 1 # number of writebacks 255system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 256system.cpu2.numCycles 173308 # number of cpu cycles simulated 257system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 258system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 304system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 305system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 306system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 307system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 308system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 309system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 310system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 311system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked | 251system.cpu1.dcache.fast_writes 0 # number of fast writes performed 252system.cpu1.dcache.cache_copies 0 # number of cache copies performed 253system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 254system.cpu1.dcache.writebacks::total 1 # number of writebacks 255system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 256system.cpu2.numCycles 173308 # number of cpu cycles simulated 257system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 258system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 304system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 305system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 306system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 307system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 308system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 309system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 310system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 311system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 312system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 313system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 312system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 313system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 314system.cpu2.icache.fast_writes 0 # number of fast writes performed 315system.cpu2.icache.cache_copies 0 # number of cache copies performed 316system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 317system.cpu2.dcache.replacements 2 # number of replacements 318system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use 319system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. 320system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 321system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 357system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 358system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 359system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses 360system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses 361system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked | 314system.cpu2.icache.fast_writes 0 # number of fast writes performed 315system.cpu2.icache.cache_copies 0 # number of cache copies performed 316system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 317system.cpu2.dcache.replacements 2 # number of replacements 318system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use 319system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. 320system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 321system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 357system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 358system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 359system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses 360system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses 361system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 365system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 366system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 365system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 366system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 367system.cpu2.dcache.fast_writes 0 # number of fast writes performed 368system.cpu2.dcache.cache_copies 0 # number of cache copies performed 369system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 370system.cpu2.dcache.writebacks::total 1 # number of writebacks 371system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 372system.cpu3.numCycles 173307 # number of cpu cycles simulated 373system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 374system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 420system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 421system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 422system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 423system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 424system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked | 367system.cpu2.dcache.fast_writes 0 # number of fast writes performed 368system.cpu2.dcache.cache_copies 0 # number of cache copies performed 369system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 370system.cpu2.dcache.writebacks::total 1 # number of writebacks 371system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 372system.cpu3.numCycles 173307 # number of cpu cycles simulated 373system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 374system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed --- 45 unchanged lines hidden (view full) --- 420system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 421system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 422system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 423system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 424system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 428system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 429system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 428system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 430system.cpu3.icache.fast_writes 0 # number of fast writes performed 431system.cpu3.icache.cache_copies 0 # number of cache copies performed 432system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu3.dcache.replacements 2 # number of replacements 434system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use 435system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. 436system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 437system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 473system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 474system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 475system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses 476system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses 477system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 478system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 479system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 480system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked | 430system.cpu3.icache.fast_writes 0 # number of fast writes performed 431system.cpu3.icache.cache_copies 0 # number of cache copies performed 432system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu3.dcache.replacements 2 # number of replacements 434system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use 435system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. 436system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 437system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. --- 35 unchanged lines hidden (view full) --- 473system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 474system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 475system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses 476system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses 477system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 478system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 479system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 480system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 481system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 482system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 481system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 482system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 483system.cpu3.dcache.fast_writes 0 # number of fast writes performed 484system.cpu3.dcache.cache_copies 0 # number of cache copies performed 485system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 486system.cpu3.dcache.writebacks::total 1 # number of writebacks 487system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.l2c.replacements 0 # number of replacements 489system.l2c.tagsinuse 371.980910 # Cycle average of tags in use 490system.l2c.total_refs 1223 # Total number of references to valid blocks. --- 157 unchanged lines hidden (view full) --- 648system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 649system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 650system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 651system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 652system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 655system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 483system.cpu3.dcache.fast_writes 0 # number of fast writes performed 484system.cpu3.dcache.cache_copies 0 # number of cache copies performed 485system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 486system.cpu3.dcache.writebacks::total 1 # number of writebacks 487system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.l2c.replacements 0 # number of replacements 489system.l2c.tagsinuse 371.980910 # Cycle average of tags in use 490system.l2c.total_refs 1223 # Total number of references to valid blocks. --- 157 unchanged lines hidden (view full) --- 648system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 649system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 650system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 651system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 652system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 655system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 656system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 657system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 656system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 658system.l2c.fast_writes 0 # number of fast writes performed 659system.l2c.cache_copies 0 # number of cache copies performed 660system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 661 662---------- End Simulation Statistics ---------- | 658system.l2c.fast_writes 0 # number of fast writes performed 659system.l2c.cache_copies 0 # number of cache copies performed 660system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 661 662---------- End Simulation Statistics ---------- |