| stats.txt (11456:c0fb4435b80f) | stats.txt (11502:e273e86a873d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1039500 # Simulator instruction rate (inst/s) 8host_op_rate 1039462 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 134594380 # Simulator tick rate (ticks/s) 10host_mem_usage 262812 # Number of bytes of host memory used 11host_seconds 0.65 # Real time elapsed on the host 12sim_insts 677333 # Number of instructions simulated 13sim_ops 677333 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 62system.cpu_clk_domain.clock 500 # Clock period in ticks 63system.cpu0.workload.num_syscalls 89 # Number of system calls 64system.cpu0.numCycles 175415 # number of cpu cycles simulated 65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu0.committedInsts 175326 # Number of instructions committed 68system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 69system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 71system.cpu0.num_func_calls 390 # number of times a function call or return occured 72system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 73system.cpu0.num_int_insts 120376 # number of integer instructions 74system.cpu0.num_fp_insts 0 # number of float instructions 75system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 76system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 79system.cpu0.num_mem_refs 82397 # number of memory refs 80system.cpu0.num_load_insts 54591 # Number of load instructions 81system.cpu0.num_store_insts 27806 # Number of store instructions 82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 83system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles 84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 86system.cpu0.Branches 29689 # Number of branches fetched 87system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction 88system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction 89system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction 90system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction 91system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction 92system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction 93system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction 94system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction 95system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction 96system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction 97system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction 98system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction 99system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction 100system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction 101system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction 102system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction 103system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction 104system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction 105system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction 106system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction 107system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction 108system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction 109system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction 110system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction 111system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction 112system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction 113system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction 114system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction 115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 117system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 118system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 121system.cpu0.op_class::total 175388 # Class of executed instruction 122system.cpu0.dcache.tags.replacements 2 # number of replacements 123system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use 124system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. 125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 126system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. 127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 128system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor 129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 130system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 133system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 135system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses 136system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses 137system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 138system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 139system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 140system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 141system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 142system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 143system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 144system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 145system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 146system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 147system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 148system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 149system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 150system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 151system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 152system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 153system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 154system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 155system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 156system.cpu0.dcache.overall_misses::total 328 # number of overall misses 157system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 158system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 159system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 160system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 161system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 162system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 163system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 164system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 165system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 166system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 167system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 168system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 169system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 170system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 171system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 172system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 173system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 174system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 175system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 176system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 177system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 180system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 181system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 183system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 184system.cpu0.dcache.writebacks::total 1 # number of writebacks 185system.cpu0.icache.tags.replacements 215 # number of replacements 186system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use 187system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 188system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 189system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 190system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 191system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor 192system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 193system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 194system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 195system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 196system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 197system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 198system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 199system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 200system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 201system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 202system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 203system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 204system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 205system.cpu0.icache.overall_hits::total 174921 # number of overall hits 206system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 207system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 208system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 209system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 210system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 211system.cpu0.icache.overall_misses::total 467 # number of overall misses 212system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 213system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 214system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 215system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 216system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 217system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 218system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 219system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 220system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 221system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 222system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 223system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 224system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 225system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 226system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 227system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 228system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 229system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 230system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 231system.cpu0.icache.writebacks::total 215 # number of writebacks 232system.cpu1.numCycles 173297 # number of cpu cycles simulated 233system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 234system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 235system.cpu1.committedInsts 167400 # Number of instructions committed 236system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed 237system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses 238system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 239system.cpu1.num_func_calls 633 # number of times a function call or return occured 240system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls 241system.cpu1.num_int_insts 107326 # number of integer instructions 242system.cpu1.num_fp_insts 0 # number of float instructions 243system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read 244system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written 245system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 246system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 247system.cpu1.num_mem_refs 49494 # number of memory refs 248system.cpu1.num_load_insts 39345 # Number of load instructions 249system.cpu1.num_store_insts 10149 # Number of store instructions 250system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles 251system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles 252system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles 253system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles 254system.cpu1.Branches 35694 # Number of branches fetched 255system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction 256system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction 257system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 258system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 259system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 260system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 261system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 262system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 263system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 264system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 265system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 266system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 267system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 268system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 269system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 270system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 271system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 272system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 273system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 274system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 275system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 276system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 277system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 278system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 279system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 280system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 281system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 282system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 283system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 284system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 285system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction 286system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction 287system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 288system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 289system.cpu1.op_class::total 167432 # Class of executed instruction 290system.cpu1.dcache.tags.replacements 0 # number of replacements 291system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use 292system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. 293system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 294system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. 295system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 296system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor 297system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy 298system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy 299system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 300system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 301system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 302system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses 303system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses 304system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits 305system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits 306system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits 307system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits 308system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 309system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 310system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits 311system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits 312system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits 313system.cpu1.dcache.overall_hits::total 49120 # number of overall hits 314system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses 315system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses 316system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses 317system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses 318system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses 319system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses 320system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses 321system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses 322system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses 323system.cpu1.dcache.overall_misses::total 287 # number of overall misses 324system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) 325system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) 326system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) 327system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) 328system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) 329system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) 330system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses 331system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses 332system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses 333system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses 334system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses 335system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses 336system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses 337system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses 338system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses 339system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses 340system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses 341system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses 342system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses 343system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses 344system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 349system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 350system.cpu1.icache.tags.replacements 278 # number of replacements 351system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use 352system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. 353system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 354system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. 355system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor 357system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy 358system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy 359system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 360system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 361system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 362system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 363system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses 364system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 365system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits 366system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits 367system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits 368system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits 369system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits 370system.cpu1.icache.overall_hits::total 167074 # number of overall hits 371system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 372system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 373system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 374system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 375system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 376system.cpu1.icache.overall_misses::total 358 # number of overall misses 377system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) 378system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) 379system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses 380system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses 381system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses 382system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses 383system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 384system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 385system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 386system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 387system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 388system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 389system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu1.icache.writebacks::writebacks 278 # number of writebacks 396system.cpu1.icache.writebacks::total 278 # number of writebacks 397system.cpu2.numCycles 173296 # number of cpu cycles simulated 398system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 399system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 400system.cpu2.committedInsts 167335 # Number of instructions committed 401system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed 402system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses 403system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 404system.cpu2.num_func_calls 633 # number of times a function call or return occured 405system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls 406system.cpu2.num_int_insts 114196 # number of integer instructions 407system.cpu2.num_fp_insts 0 # number of float instructions 408system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read 409system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written 410system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 411system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 412system.cpu2.num_mem_refs 59830 # number of memory refs 413system.cpu2.num_load_insts 42793 # Number of load instructions 414system.cpu2.num_store_insts 17037 # Number of store instructions 415system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles 416system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles 417system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 418system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 419system.cpu2.Branches 32221 # Number of branches fetched 420system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction 421system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction 422system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 423system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 424system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 425system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 426system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 427system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 428system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 429system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 430system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 431system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 432system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 433system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 434system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 435system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 436system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 437system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 438system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 439system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 440system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 441system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 442system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 443system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 444system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 445system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 446system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 447system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 448system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 449system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 450system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction 451system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction 452system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 453system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 454system.cpu2.op_class::total 167367 # Class of executed instruction 455system.cpu2.dcache.tags.replacements 0 # number of replacements 456system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use 457system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. 458system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 459system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. 460system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 461system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor 462system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy 463system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy 464system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 465system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 466system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 467system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 468system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses 469system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses 470system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits 471system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits 472system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits 473system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits 474system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 475system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 476system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits 477system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits 478system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits 479system.cpu2.dcache.overall_hits::total 59499 # number of overall hits 480system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses 481system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses 482system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 483system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 484system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 485system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 486system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses 487system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses 488system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses 489system.cpu2.dcache.overall_misses::total 255 # number of overall misses 490system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) 491system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) 492system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) 493system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) 494system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 495system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 496system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses 497system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses 498system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses 499system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses 500system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses 501system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses 502system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses 503system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses 504system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses 505system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 506system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses 507system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses 508system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses 509system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses 510system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu2.icache.tags.replacements 278 # number of replacements 517system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use 518system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. 519system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 520system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. 521system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 522system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor 523system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy 524system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy 525system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 526system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 527system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 528system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 529system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses 530system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses 531system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits 532system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits 533system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits 534system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits 535system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits 536system.cpu2.icache.overall_hits::total 167009 # number of overall hits 537system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 538system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 539system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 540system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 541system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 542system.cpu2.icache.overall_misses::total 358 # number of overall misses 543system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) 544system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) 545system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses 546system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses 547system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses 548system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses 549system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 550system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 551system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 552system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 553system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 554system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 555system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu2.icache.writebacks::writebacks 278 # number of writebacks 562system.cpu2.icache.writebacks::total 278 # number of writebacks 563system.cpu3.numCycles 173297 # number of cpu cycles simulated 564system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 565system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 566system.cpu3.committedInsts 167272 # Number of instructions committed 567system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed 568system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses 569system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 570system.cpu3.num_func_calls 633 # number of times a function call or return occured 571system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls 572system.cpu3.num_int_insts 113295 # number of integer instructions 573system.cpu3.num_fp_insts 0 # number of float instructions 574system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read 575system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written 576system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 577system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 578system.cpu3.num_mem_refs 58510 # number of memory refs 579system.cpu3.num_load_insts 42344 # Number of load instructions 580system.cpu3.num_store_insts 16166 # Number of store instructions 581system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles 582system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles 583system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles 584system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles 585system.cpu3.Branches 32639 # Number of branches fetched 586system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction 587system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction 588system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 589system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 590system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 591system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 592system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 593system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 594system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 595system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction 596system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction 597system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction 598system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction 599system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction 600system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction 601system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction 602system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction 603system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction 604system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction 605system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction 606system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction 607system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction 608system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 609system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 610system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 611system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 612system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 613system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 614system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 615system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction 616system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction 617system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction 618system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 619system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 620system.cpu3.op_class::total 167304 # Class of executed instruction 621system.cpu3.dcache.tags.replacements 0 # number of replacements 622system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use 623system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. 624system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 625system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. 626system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 627system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor 628system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy 629system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy 630system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 631system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 632system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 633system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses 634system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses 635system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits 636system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits 637system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits 638system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits 639system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 640system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 641system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits 642system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits 643system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits 644system.cpu3.dcache.overall_hits::total 58176 # number of overall hits 645system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 646system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 647system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 648system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 649system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 650system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 651system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses 652system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses 653system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses 654system.cpu3.dcache.overall_misses::total 260 # number of overall misses 655system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) 656system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) 657system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) 658system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) 659system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 660system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 661system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses 662system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses 663system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses 664system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses 665system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses 666system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses 667system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses 668system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses 669system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 670system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 671system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses 672system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses 673system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses 674system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses 675system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu3.icache.tags.replacements 279 # number of replacements 682system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use 683system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. 684system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 685system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. 686system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 687system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor 688system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy 689system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy 690system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 691system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 692system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 693system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 694system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses 695system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses 696system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits 697system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits 698system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits 699system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits 700system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits 701system.cpu3.icache.overall_hits::total 166945 # number of overall hits 702system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 703system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 704system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 705system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 706system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 707system.cpu3.icache.overall_misses::total 359 # number of overall misses 708system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) 709system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) 710system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses 711system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses 712system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses 713system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses 714system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 715system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 716system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 717system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 718system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 719system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 720system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 723system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 724system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.cpu3.icache.writebacks::writebacks 279 # number of writebacks 727system.cpu3.icache.writebacks::total 279 # number of writebacks 728system.l2c.tags.replacements 0 # number of replacements 729system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use 730system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. 731system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. 732system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. 733system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 734system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 735system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 736system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor 737system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor 738system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor 739system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor 740system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor 741system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor 742system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor 743system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 744system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 745system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy 746system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 747system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 748system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy 749system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 750system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 751system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 752system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy 753system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id 754system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 755system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id 756system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id 757system.l2c.tags.tag_accesses 19424 # Number of tag accesses 758system.l2c.tags.data_accesses 19424 # Number of data accesses 759system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 760system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 761system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 762system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 763system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 764system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 765system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits 766system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits 767system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits 768system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits 769system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits 770system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 771system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits 772system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits 773system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 774system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 775system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 776system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 777system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 778system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 779system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits 780system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 781system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 782system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 783system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 784system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 785system.l2c.overall_hits::cpu0.data 5 # number of overall hits 786system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 787system.l2c.overall_hits::cpu1.data 3 # number of overall hits 788system.l2c.overall_hits::cpu2.inst 355 # number of overall hits 789system.l2c.overall_hits::cpu2.data 9 # number of overall hits 790system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 791system.l2c.overall_hits::cpu3.data 9 # number of overall hits 792system.l2c.overall_hits::total 1220 # number of overall hits 793system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 794system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 795system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 796system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 797system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses 798system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 799system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 800system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 801system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 802system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 803system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses 804system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses 805system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses 806system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses 807system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses 808system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 809system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 810system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 811system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 812system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses 813system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 814system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 815system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 816system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 817system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses 818system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 819system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses 820system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 821system.l2c.demand_misses::total 559 # number of demand (read+write) misses 822system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 823system.l2c.overall_misses::cpu0.data 165 # number of overall misses 824system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 825system.l2c.overall_misses::cpu1.data 20 # number of overall misses 826system.l2c.overall_misses::cpu2.inst 3 # number of overall misses 827system.l2c.overall_misses::cpu2.data 13 # number of overall misses 828system.l2c.overall_misses::cpu3.inst 1 # number of overall misses 829system.l2c.overall_misses::cpu3.data 13 # number of overall misses 830system.l2c.overall_misses::total 559 # number of overall misses 831system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 832system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 833system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 834system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 835system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 836system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 837system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 838system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 839system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 840system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 841system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 842system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 843system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 844system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 845system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 846system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) 847system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) 848system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) 849system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) 850system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 851system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) 852system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) 853system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) 854system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 855system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 856system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 857system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 858system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 859system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 860system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 861system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 862system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 863system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 864system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 865system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 866system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 867system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 868system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 869system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 870system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 871system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 872system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 873system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 874system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 875system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 876system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 877system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses 878system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 879system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 880system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 881system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 882system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 883system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses 884system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses 885system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses 886system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses 887system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses 888system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 889system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses 890system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses 891system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses 892system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses 893system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 894system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 895system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 896system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 897system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses 898system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 899system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses 900system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 901system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 902system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 903system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 904system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 905system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 906system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses 907system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 908system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses 909system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 910system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 911system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 914system.l2c.blocked::no_targets 0 # number of cycles access was blocked 915system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.membus.trans_dist::ReadResp 423 # Transaction distribution 918system.membus.trans_dist::UpgradeReq 273 # Transaction distribution 919system.membus.trans_dist::UpgradeResp 80 # Transaction distribution 920system.membus.trans_dist::ReadExReq 183 # Transaction distribution 921system.membus.trans_dist::ReadExResp 136 # Transaction distribution 922system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution 923system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) 924system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) 925system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) 926system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) 927system.membus.snoops 0 # Total snoops (count) 928system.membus.snoop_fanout::samples 879 # Request fanout histogram 929system.membus.snoop_fanout::mean 0 # Request fanout histogram 930system.membus.snoop_fanout::stdev 0 # Request fanout histogram 931system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 932system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram 933system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 934system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 935system.membus.snoop_fanout::min_value 0 # Request fanout histogram 936system.membus.snoop_fanout::max_value 0 # Request fanout histogram 937system.membus.snoop_fanout::total 879 # Request fanout histogram 938system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. 939system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 940system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 941system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 942system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 943system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 944system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution 945system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 946system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution 947system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 948system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 949system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 950system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution 951system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution 952system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution 953system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution 954system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 955system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) 956system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 957system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) 958system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 959system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) 960system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) 961system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) 962system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) 963system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 964system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 965system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 966system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) 967system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 968system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 969system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 970system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 971system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) 972system.toL2Bus.snoops 0 # Total snoops (count) 973system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram 974system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram 975system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram 976system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 977system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram 978system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram 979system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram 980system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram 981system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 982system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 983system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 984system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 985system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 986system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 987system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 988system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 989system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram 990 991---------- End Simulation Statistics ---------- | |