| stats.txt (10220:9eab5efc02e8) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1618143 # Simulator instruction rate (inst/s) 8host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 209518099 # Simulator tick rate (ticks/s) 10host_mem_usage 283888 # Number of bytes of host memory used 11host_seconds 0.42 # Real time elapsed on the host 12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated | 7host_inst_rate 1398636 # Simulator instruction rate (inst/s) 8host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 181097192 # Simulator tick rate (ticks/s) 10host_mem_usage 299844 # Number of bytes of host memory used 11host_seconds 0.48 # Real time elapsed on the host 12sim_insts 677333 # Number of instructions simulated 13sim_ops 677333 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory | 22system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory | 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory |
| 27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory | 27system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory |
| 29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory | 29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) |
| 43system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) | 43system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) | 45system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) |
| 50system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) | 50system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) |
| 52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) | 52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) |
| 57system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) | 57system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) |
| 58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) | 58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) |
| 59system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) | 59system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) |
| 60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) | 60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) |
| 62system.membus.throughput 407903588 # Throughput (bytes/s) 63system.membus.data_through_bus 35776 # Total data (bytes) 64system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 62system.membus.trans_dist::ReadReq 423 # Transaction distribution 63system.membus.trans_dist::ReadResp 423 # Transaction distribution 64system.membus.trans_dist::UpgradeReq 273 # Transaction distribution 65system.membus.trans_dist::UpgradeResp 80 # Transaction distribution 66system.membus.trans_dist::ReadExReq 412 # Transaction distribution 67system.membus.trans_dist::ReadExResp 136 # Transaction distribution 68system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) 69system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) 70system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) 71system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) 72system.membus.snoops 0 # Total snoops (count) 73system.membus.snoop_fanout::samples 1108 # Request fanout histogram 74system.membus.snoop_fanout::mean 0 # Request fanout histogram 75system.membus.snoop_fanout::stdev 0 # Request fanout histogram 76system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 77system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram 78system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 79system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 80system.membus.snoop_fanout::min_value 0 # Request fanout histogram 81system.membus.snoop_fanout::max_value 0 # Request fanout histogram 82system.membus.snoop_fanout::total 1108 # Request fanout histogram |
| 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.l2c.tags.replacements 0 # number of replacements | 83system.cpu_clk_domain.clock 500 # Clock period in ticks 84system.l2c.tags.replacements 0 # number of replacements |
| 67system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use | 85system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use |
| 68system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 69system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 70system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 71system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 72system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 73system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor | 86system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 87system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 88system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 89system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 90system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 91system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor |
| 74system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 75system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 76system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 77system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 78system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 79system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 80system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor | 92system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor 93system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor 94system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor 95system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor 96system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor 97system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor 98system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor |
| 81system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 82system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 83system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 84system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 85system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy | 99system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 100system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 101system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 102system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 103system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy |
| 86system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy | 104system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy |
| 87system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 88system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 89system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 90system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 91system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 92system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 93system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id 94system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id | 105system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 106system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 107system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 109system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 110system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 111system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id 112system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id |
| 95system.l2c.tags.tag_accesses 15488 # Number of tag accesses 96system.l2c.tags.data_accesses 15488 # Number of data accesses | 113system.l2c.tags.tag_accesses 15456 # Number of tag accesses 114system.l2c.tags.data_accesses 15456 # Number of data accesses |
| 97system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 98system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 99system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 100system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits | 115system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits |
| 101system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits | 119system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits |
| 102system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits | 120system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits |
| 103system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits | 121system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits |
| 104system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 105system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 106system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 107system.l2c.Writeback_hits::total 1 # number of Writeback hits 108system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 109system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 110system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 111system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 112system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 113system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits | 122system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 123system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 124system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 125system.l2c.Writeback_hits::total 1 # number of Writeback hits 126system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 127system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 128system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 129system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 130system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits |
| 114system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits | 132system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits |
| 115system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits | 133system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits |
| 116system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits | 134system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits |
| 117system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 118system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 119system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 120system.l2c.overall_hits::cpu0.data 5 # number of overall hits 121system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 122system.l2c.overall_hits::cpu1.data 3 # number of overall hits | 135system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 136system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 137system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 138system.l2c.overall_hits::cpu0.data 5 # number of overall hits 139system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 140system.l2c.overall_hits::cpu1.data 3 # number of overall hits |
| 123system.l2c.overall_hits::cpu2.inst 356 # number of overall hits | 141system.l2c.overall_hits::cpu2.inst 355 # number of overall hits |
| 124system.l2c.overall_hits::cpu2.data 9 # number of overall hits | 142system.l2c.overall_hits::cpu2.data 9 # number of overall hits |
| 125system.l2c.overall_hits::cpu3.inst 357 # number of overall hits | 143system.l2c.overall_hits::cpu3.inst 358 # number of overall hits |
| 126system.l2c.overall_hits::cpu3.data 9 # number of overall hits 127system.l2c.overall_hits::total 1220 # number of overall hits 128system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 129system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 130system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 131system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses | 144system.l2c.overall_hits::cpu3.data 9 # number of overall hits 145system.l2c.overall_hits::total 1220 # number of overall hits 146system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 147system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 148system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses |
| 132system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses | 150system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses |
| 133system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses | 151system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses |
| 134system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses | 152system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses |
| 135system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 136system.l2c.ReadReq_misses::total 423 # number of ReadReq misses | 153system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 154system.l2c.ReadReq_misses::total 423 # number of ReadReq misses |
| 137system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 138system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 139system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 140system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 141system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses | 155system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 156system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 159system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses |
| 142system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 143system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 144system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 145system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 146system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 147system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 148system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 149system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 150system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses | 160system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 161system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 162system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses |
| 151system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses | 169system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses |
| 152system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses | 170system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses |
| 153system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses | 171system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses |
| 154system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 155system.l2c.demand_misses::total 559 # number of demand (read+write) misses 156system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 157system.l2c.overall_misses::cpu0.data 165 # number of overall misses 158system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 159system.l2c.overall_misses::cpu1.data 20 # number of overall misses | 172system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 173system.l2c.demand_misses::total 559 # number of demand (read+write) misses 174system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 175system.l2c.overall_misses::cpu0.data 165 # number of overall misses 176system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 177system.l2c.overall_misses::cpu1.data 20 # number of overall misses |
| 160system.l2c.overall_misses::cpu2.inst 2 # number of overall misses | 178system.l2c.overall_misses::cpu2.inst 3 # number of overall misses |
| 161system.l2c.overall_misses::cpu2.data 13 # number of overall misses | 179system.l2c.overall_misses::cpu2.data 13 # number of overall misses |
| 162system.l2c.overall_misses::cpu3.inst 2 # number of overall misses | 180system.l2c.overall_misses::cpu3.inst 1 # number of overall misses |
| 163system.l2c.overall_misses::cpu3.data 13 # number of overall misses 164system.l2c.overall_misses::total 559 # number of overall misses 165system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 166system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 167system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 168system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 169system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 170system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 171system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 172system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 173system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 174system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 175system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) | 181system.l2c.overall_misses::cpu3.data 13 # number of overall misses 182system.l2c.overall_misses::total 559 # number of overall misses 183system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 184system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 185system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 186system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 187system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 188system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 189system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 190system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 191system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 192system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 193system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) |
| 176system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 177system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 178system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 179system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 180system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) | 194system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 195system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 196system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 197system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 198system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) |
| 181system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 182system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 183system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 184system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 185system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 186system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 187system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 188system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses --- 11 unchanged lines hidden (view full) --- 200system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 201system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 202system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 203system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 204system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 205system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 206system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses | 199system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 200system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 201system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 202system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 203system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 204system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 205system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 206system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses --- 11 unchanged lines hidden (view full) --- 218system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 219system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 220system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 221system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 222system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 223system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 224system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 225system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses |
| 208system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses | 226system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses |
| 209system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses | 227system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses |
| 210system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses | 228system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses |
| 211system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses | 229system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 230system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses |
| 213system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses | 231system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses |
| 214system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 216system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 232system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 233system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 234system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 217system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses | 235system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses |
| 218system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 220system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 221system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 222system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 223system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses | 236system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 237system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 238system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 239system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 240system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 241system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 242system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 243system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 244system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses |
| 227system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses | 245system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses |
| 228system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses | 246system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses |
| 229system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses | 247system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses |
| 230system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 231system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 232system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses | 248system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 249system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 250system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 251system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 252system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 253system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses |
| 236system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses | 254system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses |
| 237system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses | 255system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses |
| 238system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses | 256system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses |
| 239system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 240system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 241system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 242system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 244system.l2c.blocked::no_targets 0 # number of cycles access was blocked 245system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 246system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.l2c.fast_writes 0 # number of fast writes performed 248system.l2c.cache_copies 0 # number of cache copies performed 249system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 257system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 258system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 259system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 260system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 261system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 262system.l2c.blocked::no_targets 0 # number of cycles access was blocked 263system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 265system.l2c.fast_writes 0 # number of fast writes performed 266system.l2c.cache_copies 0 # number of cache copies performed 267system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 250system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) 251system.toL2Bus.data_through_bus 166080 # Total data (bytes) 252system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 268system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution 269system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution 270system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 271system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 272system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 273system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution 274system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution 275system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) 276system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes) 277system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) 278system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) 279system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) 280system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) 281system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes) 282system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) 283system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes) 284system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) 285system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 286system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) 287system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) 288system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) 289system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 290system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) 291system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 292system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) 293system.toL2Bus.snoops 0 # Total snoops (count) 294system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram 295system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 296system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 297system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 298system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 299system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 300system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 301system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 302system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 303system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 304system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 305system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram 306system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 307system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 308system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 309system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 310system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram |
| 253system.cpu0.workload.num_syscalls 89 # Number of system calls 254system.cpu0.numCycles 175415 # number of cpu cycles simulated 255system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 256system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 257system.cpu0.committedInsts 175326 # Number of instructions committed 258system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 259system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 260system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 44 unchanged lines hidden (view full) --- 305system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 306system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 307system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 308system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 309system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 310system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 311system.cpu0.op_class::total 175388 # Class of executed instruction 312system.cpu0.icache.tags.replacements 215 # number of replacements | 311system.cpu0.workload.num_syscalls 89 # Number of system calls 312system.cpu0.numCycles 175415 # number of cpu cycles simulated 313system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 314system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 315system.cpu0.committedInsts 175326 # Number of instructions committed 316system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 317system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 318system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses --- 44 unchanged lines hidden (view full) --- 363system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 364system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 365system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 366system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 367system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 368system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 369system.cpu0.op_class::total 175388 # Class of executed instruction 370system.cpu0.icache.tags.replacements 215 # number of replacements |
| 313system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use | 371system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use |
| 314system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 315system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 316system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 317system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 372system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 373system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 374system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 375system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 318system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor | 376system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor |
| 319system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 320system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 321system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 322system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 323system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 324system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 325system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 326system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses --- 26 unchanged lines hidden (view full) --- 353system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 354system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 355system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 356system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 357system.cpu0.icache.fast_writes 0 # number of fast writes performed 358system.cpu0.icache.cache_copies 0 # number of cache copies performed 359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 360system.cpu0.dcache.tags.replacements 2 # number of replacements | 377system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 378system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 379system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 380system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 381system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 382system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 383system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 384system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses --- 26 unchanged lines hidden (view full) --- 411system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu0.icache.fast_writes 0 # number of fast writes performed 416system.cpu0.icache.cache_copies 0 # number of cache copies performed 417system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 418system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 361system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use 362system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. | 419system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use 420system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. |
| 363system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. | 421system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. |
| 364system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. | 422system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. |
| 365system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 423system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 366system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor | 424system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor |
| 367system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 368system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 369system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 370system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 371system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 372system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id | 425system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 426system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 427system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 428system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 429system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 430system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id |
| 373system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses 374system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses | 431system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses 432system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses |
| 375system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 376system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 377system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 378system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 379system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 380system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 381system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 382system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits --- 35 unchanged lines hidden (view full) --- 418system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu0.dcache.fast_writes 0 # number of fast writes performed 422system.cpu0.dcache.cache_copies 0 # number of cache copies performed 423system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 424system.cpu0.dcache.writebacks::total 1 # number of writebacks 425system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 433system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 434system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 435system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 436system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 437system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 438system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 439system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 440system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits --- 35 unchanged lines hidden (view full) --- 476system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu0.dcache.fast_writes 0 # number of fast writes performed 480system.cpu0.dcache.cache_copies 0 # number of cache copies performed 481system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 482system.cpu0.dcache.writebacks::total 1 # number of writebacks 483system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 426system.cpu1.numCycles 173295 # number of cpu cycles simulated | 484system.cpu1.numCycles 173297 # number of cpu cycles simulated |
| 427system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 428system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 485system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 486system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 429system.cpu1.committedInsts 167398 # Number of instructions committed 430system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 431system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses | 487system.cpu1.committedInsts 167400 # Number of instructions committed 488system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed 489system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses |
| 432system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 433system.cpu1.num_func_calls 633 # number of times a function call or return occured | 490system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 491system.cpu1.num_func_calls 633 # number of times a function call or return occured |
| 434system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 435system.cpu1.num_int_insts 109926 # number of integer instructions | 492system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls 493system.cpu1.num_int_insts 107326 # number of integer instructions |
| 436system.cpu1.num_fp_insts 0 # number of float instructions | 494system.cpu1.num_fp_insts 0 # number of float instructions |
| 437system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 438system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written | 495system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read 496system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written |
| 439system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 440system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written | 497system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 498system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written |
| 441system.cpu1.num_mem_refs 53394 # number of memory refs 442system.cpu1.num_load_insts 40652 # Number of load instructions 443system.cpu1.num_store_insts 12742 # Number of store instructions 444system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 445system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 446system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 447system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles 448system.cpu1.Branches 34390 # Number of branches fetched 449system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction 450system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction | 499system.cpu1.num_mem_refs 49494 # number of memory refs 500system.cpu1.num_load_insts 39345 # Number of load instructions 501system.cpu1.num_store_insts 10149 # Number of store instructions 502system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles 503system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles 504system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles 505system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles 506system.cpu1.Branches 35694 # Number of branches fetched 507system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction 508system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction |
| 451system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 452system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 453system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 454system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 455system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 456system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 457system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 458system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 471system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 472system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 473system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 474system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 475system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 476system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 477system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 478system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction | 509system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 510system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 511system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 512system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 513system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 514system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 515system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 516system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 529system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 530system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 531system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 532system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 533system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 534system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 535system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 536system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction |
| 479system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction 480system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction | 537system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction 538system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction |
| 481system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 482system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 539system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 540system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 483system.cpu1.op_class::total 167430 # Class of executed instruction | 541system.cpu1.op_class::total 167432 # Class of executed instruction |
| 484system.cpu1.icache.tags.replacements 278 # number of replacements | 542system.cpu1.icache.tags.replacements 278 # number of replacements |
| 485system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use 486system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. | 543system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use 544system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. |
| 487system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. | 545system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. |
| 488system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. | 546system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. |
| 489system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 547system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 490system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 491system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy 492system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy | 548system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor 549system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy 550system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy |
| 493system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 494system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 495system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 496system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id | 551system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 552system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 553system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 554system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id |
| 497system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses 498system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses 499system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 500system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 501system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 502system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 503system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 504system.cpu1.icache.overall_hits::total 167072 # number of overall hits | 555system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses 556system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 557system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits 558system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits 559system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits 560system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits 561system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits 562system.cpu1.icache.overall_hits::total 167074 # number of overall hits |
| 505system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 506system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 507system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 508system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 509system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 510system.cpu1.icache.overall_misses::total 358 # number of overall misses | 563system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 564system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 565system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 566system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 567system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 568system.cpu1.icache.overall_misses::total 358 # number of overall misses |
| 511system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 512system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 513system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 514system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 515system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 516system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses | 569system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) 570system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) 571system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses 572system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses 573system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses 574system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses |
| 517system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 518system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 519system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 520system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 521system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 522system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 523system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu1.icache.fast_writes 0 # number of fast writes performed 530system.cpu1.icache.cache_copies 0 # number of cache copies performed 531system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu1.dcache.tags.replacements 0 # number of replacements | 575system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 576system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 577system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 578system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 579system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 580system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 581system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 587system.cpu1.icache.fast_writes 0 # number of fast writes performed 588system.cpu1.icache.cache_copies 0 # number of cache copies performed 589system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 590system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 533system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use 534system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. | 591system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use 592system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. |
| 535system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. | 593system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. |
| 536system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. | 594system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. |
| 537system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 595system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 539system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy 540system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy | 596system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor 597system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy 598system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy |
| 541system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 542system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 543system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id | 599system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 600system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 601system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id |
| 544system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses 545system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses 546system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 547system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 548system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 549system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 550system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 551system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 552system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 553system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits 554system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits 555system.cpu1.dcache.overall_hits::total 53033 # number of overall hits 556system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses 557system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses 558system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 559system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 560system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 561system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 562system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses 563system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses 564system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses 565system.cpu1.dcache.overall_misses::total 280 # number of overall misses 566system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 567system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 568system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 569system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 570system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 571system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 572system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 573system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 574system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 575system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 576system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses 577system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses 578system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 579system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 580system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 581system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 582system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses 583system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses 584system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses 585system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses | 602system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses 603system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses 604system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits 605system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits 606system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits 607system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits 608system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 609system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 610system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits 611system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits 612system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits 613system.cpu1.dcache.overall_hits::total 49120 # number of overall hits 614system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses 615system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses 616system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses 617system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses 618system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses 619system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses 620system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses 621system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses 622system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses 623system.cpu1.dcache.overall_misses::total 287 # number of overall misses 624system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) 625system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) 626system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) 627system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) 628system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) 629system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) 630system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses 631system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses 632system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses 633system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses 634system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses 635system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses 636system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses 637system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses 638system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses 639system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses 640system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses 641system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses 642system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses 643system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses |
| 586system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu1.dcache.fast_writes 0 # number of fast writes performed 593system.cpu1.dcache.cache_copies 0 # number of cache copies performed 594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 644system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu1.dcache.fast_writes 0 # number of fast writes performed 651system.cpu1.dcache.cache_copies 0 # number of cache copies performed 652system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 595system.cpu2.numCycles 173295 # number of cpu cycles simulated | 653system.cpu2.numCycles 173296 # number of cpu cycles simulated |
| 596system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 597system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 654system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 655system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 598system.cpu2.committedInsts 167334 # Number of instructions committed 599system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 600system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses | 656system.cpu2.committedInsts 167335 # Number of instructions committed 657system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed 658system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses |
| 601system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 602system.cpu2.num_func_calls 633 # number of times a function call or return occured | 659system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 660system.cpu2.num_func_calls 633 # number of times a function call or return occured |
| 603system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 604system.cpu2.num_int_insts 113333 # number of integer instructions | 661system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls 662system.cpu2.num_int_insts 114196 # number of integer instructions |
| 605system.cpu2.num_fp_insts 0 # number of float instructions | 663system.cpu2.num_fp_insts 0 # number of float instructions |
| 606system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 607system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written | 664system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read 665system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written |
| 608system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 609system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written | 666system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 667system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written |
| 610system.cpu2.num_mem_refs 58537 # number of memory refs 611system.cpu2.num_load_insts 42362 # Number of load instructions 612system.cpu2.num_store_insts 16175 # Number of store instructions 613system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 614system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles | 668system.cpu2.num_mem_refs 59830 # number of memory refs 669system.cpu2.num_load_insts 42793 # Number of load instructions 670system.cpu2.num_store_insts 17037 # Number of store instructions 671system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles 672system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles |
| 615system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 616system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles | 673system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 674system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles |
| 617system.cpu2.Branches 32652 # Number of branches fetched 618system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction 619system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction | 675system.cpu2.Branches 32221 # Number of branches fetched 676system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction 677system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction |
| 620system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 621system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 622system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 623system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 624system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 625system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 626system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 627system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 640system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 641system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 642system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 643system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 644system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 645system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 646system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 647system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction | 678system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 679system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 680system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 681system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 682system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 683system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 684system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 685system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 698system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 699system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 700system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 701system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 702system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 703system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 704system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 705system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction |
| 648system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction 649system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction | 706system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction 707system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction |
| 650system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 651system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 708system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 709system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 652system.cpu2.op_class::total 167366 # Class of executed instruction | 710system.cpu2.op_class::total 167367 # Class of executed instruction |
| 653system.cpu2.icache.tags.replacements 278 # number of replacements | 711system.cpu2.icache.tags.replacements 278 # number of replacements |
| 654system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use 655system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. | 712system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use 713system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. |
| 656system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. | 714system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. |
| 657system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. | 715system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. |
| 658system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 716system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 659system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 660system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy 661system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy | 717system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor 718system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy 719system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy |
| 662system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 663system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 664system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 665system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id | 720system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 721system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 722system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 723system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id |
| 666system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses 667system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses 668system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 669system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 670system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 671system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 672system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 673system.cpu2.icache.overall_hits::total 167008 # number of overall hits | 724system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses 725system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses 726system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits 727system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits 728system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits 729system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits 730system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits 731system.cpu2.icache.overall_hits::total 167009 # number of overall hits |
| 674system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 675system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 676system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 677system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 678system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 679system.cpu2.icache.overall_misses::total 358 # number of overall misses | 732system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 733system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 734system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 735system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 736system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 737system.cpu2.icache.overall_misses::total 358 # number of overall misses |
| 680system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 681system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 682system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 683system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 684system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 685system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses | 738system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) 739system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) 740system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses 741system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses 742system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses 743system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses |
| 686system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 687system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 688system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 689system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 690system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 691system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 692system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 693system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 694system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 695system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 696system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 697system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 698system.cpu2.icache.fast_writes 0 # number of fast writes performed 699system.cpu2.icache.cache_copies 0 # number of cache copies performed 700system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 701system.cpu2.dcache.tags.replacements 0 # number of replacements | 744system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 745system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 746system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 747system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 748system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 749system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 750system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu2.icache.fast_writes 0 # number of fast writes performed 757system.cpu2.icache.cache_copies 0 # number of cache copies performed 758system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 702system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use 703system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. 704system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 705system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. | 760system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use 761system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. 762system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 763system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. |
| 706system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 764system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 707system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 708system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy 709system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy 710system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id | 765system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor 766system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy 767system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy 768system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 769system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id |
| 711system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id | 770system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id |
| 712system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 713system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses 714system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses 715system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 716system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 717system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 718system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 719system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 720system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 721system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 722system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits 723system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits 724system.cpu2.dcache.overall_hits::total 58192 # number of overall hits 725system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses 726system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses 727system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 728system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 729system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 730system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 731system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 732system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 733system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 734system.cpu2.dcache.overall_misses::total 269 # number of overall misses 735system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 736system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 737system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 738system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) | 771system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 772system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses 773system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses 774system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits 775system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits 776system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits 777system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits 778system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 779system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 780system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits 781system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits 782system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits 783system.cpu2.dcache.overall_hits::total 59499 # number of overall hits 784system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses 785system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses 786system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 787system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 788system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 789system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 790system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses 791system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses 792system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses 793system.cpu2.dcache.overall_misses::total 255 # number of overall misses 794system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) 795system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) 796system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) 797system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) |
| 739system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 740system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) | 798system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 799system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) |
| 741system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 742system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 743system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 744system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 745system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses 746system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses 747system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 748system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 749system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 750system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 751system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses 752system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses 753system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses 754system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses | 800system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses 801system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses 802system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses 803system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses 804system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses 805system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses 806system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses 807system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses 808system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses 809system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 810system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses 811system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses 812system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses 813system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses |
| 755system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu2.dcache.fast_writes 0 # number of fast writes performed 762system.cpu2.dcache.cache_copies 0 # number of cache copies performed 763system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 814system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 815system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 816system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 817system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 818system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 819system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 820system.cpu2.dcache.fast_writes 0 # number of fast writes performed 821system.cpu2.dcache.cache_copies 0 # number of cache copies performed 822system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 764system.cpu3.numCycles 173294 # number of cpu cycles simulated | 823system.cpu3.numCycles 173297 # number of cpu cycles simulated |
| 765system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 766system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 824system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 825system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 767system.cpu3.committedInsts 167269 # Number of instructions committed 768system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 769system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses | 826system.cpu3.committedInsts 167272 # Number of instructions committed 827system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed 828system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses |
| 770system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 771system.cpu3.num_func_calls 633 # number of times a function call or return occured | 829system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 830system.cpu3.num_func_calls 633 # number of times a function call or return occured |
| 772system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 773system.cpu3.num_int_insts 111554 # number of integer instructions | 831system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls 832system.cpu3.num_int_insts 113295 # number of integer instructions |
| 774system.cpu3.num_fp_insts 0 # number of float instructions | 833system.cpu3.num_fp_insts 0 # number of float instructions |
| 775system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 776system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written | 834system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read 835system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written |
| 777system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 778system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written | 836system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 837system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written |
| 779system.cpu3.num_mem_refs 55900 # number of memory refs 780system.cpu3.num_load_insts 41466 # Number of load instructions 781system.cpu3.num_store_insts 14434 # Number of store instructions 782system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 783system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 784system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 785system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles 786system.cpu3.Branches 33511 # Number of branches fetched 787system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction 788system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction | 838system.cpu3.num_mem_refs 58510 # number of memory refs 839system.cpu3.num_load_insts 42344 # Number of load instructions 840system.cpu3.num_store_insts 16166 # Number of store instructions 841system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles 842system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles 843system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles 844system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles 845system.cpu3.Branches 32639 # Number of branches fetched 846system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction 847system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction |
| 789system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 790system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 791system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 792system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 793system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 794system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 795system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 796system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 809system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 810system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 811system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 812system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 813system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 814system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 815system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 816system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction | 848system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 849system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 850system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 851system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 852system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 853system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 854system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 855system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 868system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 869system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 870system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 871system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 872system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 873system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 874system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 875system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction |
| 817system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction 818system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction | 876system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction 877system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction |
| 819system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 820system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 878system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 879system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 821system.cpu3.op_class::total 167301 # Class of executed instruction | 880system.cpu3.op_class::total 167304 # Class of executed instruction |
| 822system.cpu3.icache.tags.replacements 279 # number of replacements | 881system.cpu3.icache.tags.replacements 279 # number of replacements |
| 823system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use 824system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. | 882system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use 883system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. |
| 825system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. | 884system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. |
| 826system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. | 885system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. |
| 827system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 886system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 828system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 829system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy 830system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy | 887system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor 888system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy 889system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy |
| 831system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 832system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 833system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 834system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id | 890system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 891system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 892system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 893system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id |
| 835system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses 836system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses 837system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 838system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 839system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 840system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 841system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 842system.cpu3.icache.overall_hits::total 166942 # number of overall hits | 894system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses 895system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses 896system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits 897system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits 898system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits 899system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits 900system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits 901system.cpu3.icache.overall_hits::total 166945 # number of overall hits |
| 843system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 844system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 845system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 846system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 847system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 848system.cpu3.icache.overall_misses::total 359 # number of overall misses | 902system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 903system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 904system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 905system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 906system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 907system.cpu3.icache.overall_misses::total 359 # number of overall misses |
| 849system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 850system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 851system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 852system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 853system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 854system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses | 908system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) 909system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) 910system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses 911system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses 912system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses 913system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses |
| 855system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 856system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 857system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 858system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 859system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 860system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 861system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 867system.cpu3.icache.fast_writes 0 # number of fast writes performed 868system.cpu3.icache.cache_copies 0 # number of cache copies performed 869system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 870system.cpu3.dcache.tags.replacements 0 # number of replacements | 914system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 915system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 916system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 917system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 918system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 919system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 920system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu3.icache.fast_writes 0 # number of fast writes performed 927system.cpu3.icache.cache_copies 0 # number of cache copies performed 928system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 929system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 871system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use 872system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. 873system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 874system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. | 930system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use 931system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. 932system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 933system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. |
| 875system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 934system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 876system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 877system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy 878system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy 879system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 880system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id | 935system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor 936system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy 937system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy 938system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id |
| 881system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id | 939system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id |
| 882system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 883system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses 884system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses 885system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 886system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 887system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 888system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 889system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 890system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 891system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 892system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits 893system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits 894system.cpu3.dcache.overall_hits::total 55561 # number of overall hits 895system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 896system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 897system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 898system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 899system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 900system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 901system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses 902system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses 903system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses 904system.cpu3.dcache.overall_misses::total 259 # number of overall misses 905system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 906system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 907system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 908system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 909system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 910system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 911system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 912system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 913system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 914system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 915system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses 916system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses 917system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 918system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 919system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 920system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 921system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses 922system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses 923system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses 924system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses | 940system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 941system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses 942system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses 943system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits 944system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits 945system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits 946system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits 947system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 948system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 949system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits 950system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits 951system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits 952system.cpu3.dcache.overall_hits::total 58176 # number of overall hits 953system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 954system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 955system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 956system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 957system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 958system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 959system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses 960system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses 961system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses 962system.cpu3.dcache.overall_misses::total 260 # number of overall misses 963system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) 964system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) 965system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) 966system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) 967system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 968system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 969system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses 970system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses 971system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses 972system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses 973system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses 974system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses 975system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses 976system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses 977system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 978system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 979system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses 980system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses 981system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses 982system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses |
| 925system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 926system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 927system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 928system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 929system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 930system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 931system.cpu3.dcache.fast_writes 0 # number of fast writes performed 932system.cpu3.dcache.cache_copies 0 # number of cache copies performed 933system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 934 935---------- End Simulation Statistics ---------- | 983system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 984system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 985system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 986system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 987system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 988system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 989system.cpu3.dcache.fast_writes 0 # number of fast writes performed 990system.cpu3.dcache.cache_copies 0 # number of cache copies performed 991system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 992 993---------- End Simulation Statistics ---------- |