7,11c7,11
< host_inst_rate 1256528 # Simulator instruction rate (inst/s)
< host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 162691956 # Simulator tick rate (ticks/s)
< host_mem_usage 1160656 # Number of bytes of host memory used
< host_seconds 0.54 # Real time elapsed on the host
---
> host_inst_rate 170274 # Simulator instruction rate (inst/s)
> host_op_rate 170274 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 22048637 # Simulator tick rate (ticks/s)
> host_mem_usage 246052 # Number of bytes of host memory used
> host_seconds 3.98 # Real time elapsed on the host
62a63,240
> system.l2c.tags.replacements 0 # number of replacements
> system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
> system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
> system.l2c.Writeback_hits::total 1 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
> system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
> system.l2c.overall_hits::cpu0.data 5 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
> system.l2c.overall_hits::cpu1.data 3 # number of overall hits
> system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
> system.l2c.overall_hits::cpu2.data 9 # number of overall hits
> system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
> system.l2c.overall_hits::cpu3.data 9 # number of overall hits
> system.l2c.overall_hits::total 1220 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
> system.l2c.demand_misses::total 559 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
> system.l2c.overall_misses::cpu0.data 165 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
> system.l2c.overall_misses::cpu1.data 20 # number of overall misses
> system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
> system.l2c.overall_misses::cpu2.data 13 # number of overall misses
> system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
> system.l2c.overall_misses::cpu3.data 13 # number of overall misses
> system.l2c.overall_misses::total 559 # number of overall misses
> system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
> system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
> system.l2c.blocked::no_targets 0 # number of cycles access was blocked
> system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.l2c.fast_writes 0 # number of fast writes performed
> system.l2c.cache_copies 0 # number of cache copies performed
> system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
89,94c267,272
< system.cpu0.icache.tags.replacements 215 # number of replacements
< system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu0.icache.tags.replacements 215 # number of replacements
> system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
97c275
< system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
131,136c309,314
< system.cpu0.dcache.tags.replacements 2 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu0.dcache.tags.replacements 2 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
139c317
< system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
213,218c391,396
< system.cpu1.icache.tags.replacements 278 # number of replacements
< system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu1.icache.tags.replacements 278 # number of replacements
> system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
221c399
< system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
255,260c433,438
< system.cpu1.dcache.tags.replacements 0 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu1.dcache.tags.replacements 0 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
263c441
< system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
335,340c513,518
< system.cpu2.icache.tags.replacements 278 # number of replacements
< system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
< system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
< system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
< system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu2.icache.tags.replacements 278 # number of replacements
> system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
> system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
> system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
> system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
343c521
< system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
377,382c555,560
< system.cpu2.dcache.tags.replacements 0 # number of replacements
< system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
< system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu2.dcache.tags.replacements 0 # number of replacements
> system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
> system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
385c563
< system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
---
> system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
457,462c635,640
< system.cpu3.icache.tags.replacements 279 # number of replacements
< system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
< system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
< system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
< system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu3.icache.tags.replacements 279 # number of replacements
> system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
> system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
> system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
> system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
465c643
< system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
499,504c677,682
< system.cpu3.dcache.tags.replacements 0 # number of replacements
< system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
< system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
< system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
< system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu3.dcache.tags.replacements 0 # number of replacements
> system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
> system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
> system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
> system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
507c685
< system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
557,734d734
< system.l2c.tags.replacements 0 # number of replacements
< system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
< system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
< system.l2c.Writeback_hits::total 1 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
< system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
< system.l2c.overall_hits::cpu0.data 5 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
< system.l2c.overall_hits::cpu1.data 3 # number of overall hits
< system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
< system.l2c.overall_hits::cpu2.data 9 # number of overall hits
< system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
< system.l2c.overall_hits::cpu3.data 9 # number of overall hits
< system.l2c.overall_hits::total 1220 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
< system.l2c.demand_misses::total 559 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
< system.l2c.overall_misses::cpu0.data 165 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
< system.l2c.overall_misses::cpu1.data 20 # number of overall misses
< system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
< system.l2c.overall_misses::cpu2.data 13 # number of overall misses
< system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
< system.l2c.overall_misses::cpu3.data 13 # number of overall misses
< system.l2c.overall_misses::total 559 # number of overall misses
< system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked::no_targets 0 # number of cycles access was blocked
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 1256528 # Simulator instruction rate (inst/s)
< host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 162691956 # Simulator tick rate (ticks/s)
< host_mem_usage 1160656 # Number of bytes of host memory used
< host_seconds 0.54 # Real time elapsed on the host
---
> host_inst_rate 170274 # Simulator instruction rate (inst/s)
> host_op_rate 170274 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 22048637 # Simulator tick rate (ticks/s)
> host_mem_usage 246052 # Number of bytes of host memory used
> host_seconds 3.98 # Real time elapsed on the host
62a63,240
> system.l2c.tags.replacements 0 # number of replacements
> system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
> system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
> system.l2c.Writeback_hits::total 1 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
> system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
> system.l2c.overall_hits::cpu0.data 5 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
> system.l2c.overall_hits::cpu1.data 3 # number of overall hits
> system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
> system.l2c.overall_hits::cpu2.data 9 # number of overall hits
> system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
> system.l2c.overall_hits::cpu3.data 9 # number of overall hits
> system.l2c.overall_hits::total 1220 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
> system.l2c.demand_misses::total 559 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
> system.l2c.overall_misses::cpu0.data 165 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
> system.l2c.overall_misses::cpu1.data 20 # number of overall misses
> system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
> system.l2c.overall_misses::cpu2.data 13 # number of overall misses
> system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
> system.l2c.overall_misses::cpu3.data 13 # number of overall misses
> system.l2c.overall_misses::total 559 # number of overall misses
> system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
> system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
> system.l2c.blocked::no_targets 0 # number of cycles access was blocked
> system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.l2c.fast_writes 0 # number of fast writes performed
> system.l2c.cache_copies 0 # number of cache copies performed
> system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
89,94c267,272
< system.cpu0.icache.tags.replacements 215 # number of replacements
< system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu0.icache.tags.replacements 215 # number of replacements
> system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
97c275
< system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
131,136c309,314
< system.cpu0.dcache.tags.replacements 2 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu0.dcache.tags.replacements 2 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
139c317
< system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
213,218c391,396
< system.cpu1.icache.tags.replacements 278 # number of replacements
< system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu1.icache.tags.replacements 278 # number of replacements
> system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
221c399
< system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
255,260c433,438
< system.cpu1.dcache.tags.replacements 0 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu1.dcache.tags.replacements 0 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
263c441
< system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
335,340c513,518
< system.cpu2.icache.tags.replacements 278 # number of replacements
< system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
< system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
< system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
< system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu2.icache.tags.replacements 278 # number of replacements
> system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
> system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
> system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
> system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
343c521
< system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
377,382c555,560
< system.cpu2.dcache.tags.replacements 0 # number of replacements
< system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
< system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu2.dcache.tags.replacements 0 # number of replacements
> system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
> system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
385c563
< system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
---
> system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
457,462c635,640
< system.cpu3.icache.tags.replacements 279 # number of replacements
< system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
< system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
< system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
< system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu3.icache.tags.replacements 279 # number of replacements
> system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
> system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
> system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
> system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
465c643
< system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
499,504c677,682
< system.cpu3.dcache.tags.replacements 0 # number of replacements
< system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
< system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
< system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
< system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
---
> system.cpu3.dcache.tags.replacements 0 # number of replacements
> system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
> system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
> system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
> system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
507c685
< system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
---
> system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
557,734d734
< system.l2c.tags.replacements 0 # number of replacements
< system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
< system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
< system.l2c.Writeback_hits::total 1 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
< system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
< system.l2c.overall_hits::cpu0.data 5 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
< system.l2c.overall_hits::cpu1.data 3 # number of overall hits
< system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
< system.l2c.overall_hits::cpu2.data 9 # number of overall hits
< system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
< system.l2c.overall_hits::cpu3.data 9 # number of overall hits
< system.l2c.overall_hits::total 1220 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
< system.l2c.demand_misses::total 559 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
< system.l2c.overall_misses::cpu0.data 165 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
< system.l2c.overall_misses::cpu1.data 20 # number of overall misses
< system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
< system.l2c.overall_misses::cpu2.data 13 # number of overall misses
< system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
< system.l2c.overall_misses::cpu3.data 13 # number of overall misses
< system.l2c.overall_misses::total 559 # number of overall misses
< system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked::no_targets 0 # number of cycles access was blocked
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate