7,13c7,13
< host_inst_rate 1618143 # Simulator instruction rate (inst/s)
< host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 209518099 # Simulator tick rate (ticks/s)
< host_mem_usage 283888 # Number of bytes of host memory used
< host_seconds 0.42 # Real time elapsed on the host
< sim_insts 677327 # Number of instructions simulated
< sim_ops 677327 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1398636 # Simulator instruction rate (inst/s)
> host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 181097192 # Simulator tick rate (ticks/s)
> host_mem_usage 299844 # Number of bytes of host memory used
> host_seconds 0.48 # Real time elapsed on the host
> sim_insts 677333 # Number of instructions simulated
> sim_ops 677333 # Number of ops (including micro ops) simulated
20c20
< system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
27,28c27,28
< system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
34c34
< system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
36c36
< system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
43c43
< system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
45c45
< system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
57c57
< system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
59c59
< system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
62,64c62,82
< system.membus.throughput 407903588 # Throughput (bytes/s)
< system.membus.data_through_bus 35776 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.trans_dist::ReadReq 423 # Transaction distribution
> system.membus.trans_dist::ReadResp 423 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
> system.membus.trans_dist::ReadExReq 412 # Transaction distribution
> system.membus.trans_dist::ReadExResp 136 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 1108 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 1108 # Request fanout histogram
67c85
< system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
74,80c92,98
< system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
86c104
< system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
95,96c113,114
< system.l2c.tags.tag_accesses 15488 # Number of tag accesses
< system.l2c.tags.data_accesses 15488 # Number of data accesses
---
> system.l2c.tags.tag_accesses 15456 # Number of tag accesses
> system.l2c.tags.data_accesses 15456 # Number of data accesses
101c119
< system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
103c121
< system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
114c132
< system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
116c134
< system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
123c141
< system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
---
> system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
125c143
< system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
---
> system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
132c150
< system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses
134c152
< system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses
137,141c155,159
< system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
151c169
< system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
153c171
< system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
160c178
< system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
---
> system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
162c180
< system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
---
> system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
176,180c194,198
< system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
208c226
< system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses
210c228
< system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses
213c231
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
217c235
< system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
227c245
< system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
229c247
< system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
236c254
< system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
238c256
< system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
250,252c268,310
< system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
< system.toL2Bus.data_through_bus 166080 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 0 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram
313c371
< system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
318c376
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
361,362c419,420
< system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
364c422
< system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
366c424
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
373,374c431,432
< system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses
---
> system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
426c484
< system.cpu1.numCycles 173295 # number of cpu cycles simulated
---
> system.cpu1.numCycles 173297 # number of cpu cycles simulated
429,431c487,489
< system.cpu1.committedInsts 167398 # Number of instructions committed
< system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
---
> system.cpu1.committedInsts 167400 # Number of instructions committed
> system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
434,435c492,493
< system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 109926 # number of integer instructions
---
> system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 107326 # number of integer instructions
437,438c495,496
< system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
441,450c499,508
< system.cpu1.num_mem_refs 53394 # number of memory refs
< system.cpu1.num_load_insts 40652 # Number of load instructions
< system.cpu1.num_store_insts 12742 # Number of store instructions
< system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
< system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
< system.cpu1.Branches 34390 # Number of branches fetched
< system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction
< system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction
---
> system.cpu1.num_mem_refs 49494 # number of memory refs
> system.cpu1.num_load_insts 39345 # Number of load instructions
> system.cpu1.num_store_insts 10149 # Number of store instructions
> system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
> system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
> system.cpu1.Branches 35694 # Number of branches fetched
> system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
> system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
479,480c537,538
< system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction
< system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
> system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
483c541
< system.cpu1.op_class::total 167430 # Class of executed instruction
---
> system.cpu1.op_class::total 167432 # Class of executed instruction
485,486c543,544
< system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
488c546
< system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
490,492c548,550
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
497,504c555,562
< system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
< system.cpu1.icache.overall_hits::total 167072 # number of overall hits
---
> system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
> system.cpu1.icache.overall_hits::total 167074 # number of overall hits
511,516c569,574
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
---
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
533,534c591,592
< system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
536c594
< system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
538,540c596,598
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
544,585c602,643
< system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
< system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
< system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
< system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
< system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
< system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
< system.cpu1.dcache.overall_misses::total 280 # number of overall misses
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
---
> system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
> system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
> system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
> system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
> system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
> system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
> system.cpu1.dcache.overall_misses::total 287 # number of overall misses
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
595c653
< system.cpu2.numCycles 173295 # number of cpu cycles simulated
---
> system.cpu2.numCycles 173296 # number of cpu cycles simulated
598,600c656,658
< system.cpu2.committedInsts 167334 # Number of instructions committed
< system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
< system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
---
> system.cpu2.committedInsts 167335 # Number of instructions committed
> system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
> system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
603,604c661,662
< system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
< system.cpu2.num_int_insts 113333 # number of integer instructions
---
> system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
> system.cpu2.num_int_insts 114196 # number of integer instructions
606,607c664,665
< system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
< system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
---
> system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
> system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
610,614c668,672
< system.cpu2.num_mem_refs 58537 # number of memory refs
< system.cpu2.num_load_insts 42362 # Number of load instructions
< system.cpu2.num_store_insts 16175 # Number of store instructions
< system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
< system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
---
> system.cpu2.num_mem_refs 59830 # number of memory refs
> system.cpu2.num_load_insts 42793 # Number of load instructions
> system.cpu2.num_store_insts 17037 # Number of store instructions
> system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
> system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
617,619c675,677
< system.cpu2.Branches 32652 # Number of branches fetched
< system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction
< system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction
---
> system.cpu2.Branches 32221 # Number of branches fetched
> system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
> system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
648,649c706,707
< system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction
< system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction
---
> system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
> system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
652c710
< system.cpu2.op_class::total 167366 # Class of executed instruction
---
> system.cpu2.op_class::total 167367 # Class of executed instruction
654,655c712,713
< system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
657c715
< system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
659,661c717,719
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
666,673c724,731
< system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
< system.cpu2.icache.overall_hits::total 167008 # number of overall hits
---
> system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
> system.cpu2.icache.overall_hits::total 167009 # number of overall hits
680,685c738,743
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
---
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
702,705c760,763
< system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
707,710c765,769
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
> system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
712,738c771,797
< system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
< system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
< system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
< system.cpu2.dcache.overall_misses::total 269 # number of overall misses
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
---
> system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
> system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
> system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
> system.cpu2.dcache.overall_misses::total 255 # number of overall misses
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
741,754c800,813
< system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
---
> system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
764c823
< system.cpu3.numCycles 173294 # number of cpu cycles simulated
---
> system.cpu3.numCycles 173297 # number of cpu cycles simulated
767,769c826,828
< system.cpu3.committedInsts 167269 # Number of instructions committed
< system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
< system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
---
> system.cpu3.committedInsts 167272 # Number of instructions committed
> system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
> system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
772,773c831,832
< system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
< system.cpu3.num_int_insts 111554 # number of integer instructions
---
> system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
> system.cpu3.num_int_insts 113295 # number of integer instructions
775,776c834,835
< system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
< system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
---
> system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
> system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
779,788c838,847
< system.cpu3.num_mem_refs 55900 # number of memory refs
< system.cpu3.num_load_insts 41466 # Number of load instructions
< system.cpu3.num_store_insts 14434 # Number of store instructions
< system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
< system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
< system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
< system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
< system.cpu3.Branches 33511 # Number of branches fetched
< system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction
< system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction
---
> system.cpu3.num_mem_refs 58510 # number of memory refs
> system.cpu3.num_load_insts 42344 # Number of load instructions
> system.cpu3.num_store_insts 16166 # Number of store instructions
> system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
> system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
> system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
> system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
> system.cpu3.Branches 32639 # Number of branches fetched
> system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
> system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
817,818c876,877
< system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction
< system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction
---
> system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
> system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
821c880
< system.cpu3.op_class::total 167301 # Class of executed instruction
---
> system.cpu3.op_class::total 167304 # Class of executed instruction
823,824c882,883
< system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
826c885
< system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
828,830c887,889
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
835,842c894,901
< system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
< system.cpu3.icache.overall_hits::total 166942 # number of overall hits
---
> system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
> system.cpu3.icache.overall_hits::total 166945 # number of overall hits
849,854c908,913
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
---
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
871,874c930,933
< system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
< system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
< system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
> system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
876,880c935,938
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
< system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
882,924c940,982
< system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
< system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
< system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
< system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
< system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
< system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
< system.cpu3.dcache.overall_misses::total 259 # number of overall misses
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
---
> system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
> system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
> system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
> system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
> system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
> system.cpu3.dcache.overall_misses::total 260 # number of overall misses
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
< host_inst_rate 1618143 # Simulator instruction rate (inst/s)
< host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 209518099 # Simulator tick rate (ticks/s)
< host_mem_usage 283888 # Number of bytes of host memory used
< host_seconds 0.42 # Real time elapsed on the host
< sim_insts 677327 # Number of instructions simulated
< sim_ops 677327 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1398636 # Simulator instruction rate (inst/s)
> host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 181097192 # Simulator tick rate (ticks/s)
> host_mem_usage 299844 # Number of bytes of host memory used
> host_seconds 0.48 # Real time elapsed on the host
> sim_insts 677333 # Number of instructions simulated
> sim_ops 677333 # Number of ops (including micro ops) simulated
20c20
< system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
27,28c27,28
< system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
34c34
< system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
36c36
< system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
43c43
< system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
45c45
< system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
57c57
< system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
59c59
< system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
62,64c62,82
< system.membus.throughput 407903588 # Throughput (bytes/s)
< system.membus.data_through_bus 35776 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.trans_dist::ReadReq 423 # Transaction distribution
> system.membus.trans_dist::ReadResp 423 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
> system.membus.trans_dist::ReadExReq 412 # Transaction distribution
> system.membus.trans_dist::ReadExResp 136 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 1108 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 1108 # Request fanout histogram
67c85
< system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
74,80c92,98
< system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
86c104
< system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
95,96c113,114
< system.l2c.tags.tag_accesses 15488 # Number of tag accesses
< system.l2c.tags.data_accesses 15488 # Number of data accesses
---
> system.l2c.tags.tag_accesses 15456 # Number of tag accesses
> system.l2c.tags.data_accesses 15456 # Number of data accesses
101c119
< system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
103c121
< system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
114c132
< system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
116c134
< system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
123c141
< system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
---
> system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
125c143
< system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
---
> system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
132c150
< system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses
134c152
< system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses
137,141c155,159
< system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
151c169
< system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
153c171
< system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
160c178
< system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
---
> system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
162c180
< system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
---
> system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
176,180c194,198
< system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
208c226
< system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses
210c228
< system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses
213c231
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
217c235
< system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
---
> system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
227c245
< system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
229c247
< system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
236c254
< system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
238c256
< system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
250,252c268,310
< system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
< system.toL2Bus.data_through_bus 166080 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 0 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram
313c371
< system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
---
> system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
318c376
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
361,362c419,420
< system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
364c422
< system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
366c424
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
373,374c431,432
< system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses
---
> system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
426c484
< system.cpu1.numCycles 173295 # number of cpu cycles simulated
---
> system.cpu1.numCycles 173297 # number of cpu cycles simulated
429,431c487,489
< system.cpu1.committedInsts 167398 # Number of instructions committed
< system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
---
> system.cpu1.committedInsts 167400 # Number of instructions committed
> system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
434,435c492,493
< system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 109926 # number of integer instructions
---
> system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 107326 # number of integer instructions
437,438c495,496
< system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
441,450c499,508
< system.cpu1.num_mem_refs 53394 # number of memory refs
< system.cpu1.num_load_insts 40652 # Number of load instructions
< system.cpu1.num_store_insts 12742 # Number of store instructions
< system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
< system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
< system.cpu1.Branches 34390 # Number of branches fetched
< system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction
< system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction
---
> system.cpu1.num_mem_refs 49494 # number of memory refs
> system.cpu1.num_load_insts 39345 # Number of load instructions
> system.cpu1.num_store_insts 10149 # Number of store instructions
> system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
> system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
> system.cpu1.Branches 35694 # Number of branches fetched
> system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
> system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
479,480c537,538
< system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction
< system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
> system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
483c541
< system.cpu1.op_class::total 167430 # Class of executed instruction
---
> system.cpu1.op_class::total 167432 # Class of executed instruction
485,486c543,544
< system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
488c546
< system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
490,492c548,550
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
497,504c555,562
< system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
< system.cpu1.icache.overall_hits::total 167072 # number of overall hits
---
> system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
> system.cpu1.icache.overall_hits::total 167074 # number of overall hits
511,516c569,574
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
---
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
533,534c591,592
< system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
536c594
< system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
538,540c596,598
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
544,585c602,643
< system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
< system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
< system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
< system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
< system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
< system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
< system.cpu1.dcache.overall_misses::total 280 # number of overall misses
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
---
> system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
> system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
> system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
> system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
> system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
> system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
> system.cpu1.dcache.overall_misses::total 287 # number of overall misses
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
> system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
595c653
< system.cpu2.numCycles 173295 # number of cpu cycles simulated
---
> system.cpu2.numCycles 173296 # number of cpu cycles simulated
598,600c656,658
< system.cpu2.committedInsts 167334 # Number of instructions committed
< system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
< system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
---
> system.cpu2.committedInsts 167335 # Number of instructions committed
> system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
> system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
603,604c661,662
< system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
< system.cpu2.num_int_insts 113333 # number of integer instructions
---
> system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
> system.cpu2.num_int_insts 114196 # number of integer instructions
606,607c664,665
< system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
< system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
---
> system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
> system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
610,614c668,672
< system.cpu2.num_mem_refs 58537 # number of memory refs
< system.cpu2.num_load_insts 42362 # Number of load instructions
< system.cpu2.num_store_insts 16175 # Number of store instructions
< system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
< system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
---
> system.cpu2.num_mem_refs 59830 # number of memory refs
> system.cpu2.num_load_insts 42793 # Number of load instructions
> system.cpu2.num_store_insts 17037 # Number of store instructions
> system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
> system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
617,619c675,677
< system.cpu2.Branches 32652 # Number of branches fetched
< system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction
< system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction
---
> system.cpu2.Branches 32221 # Number of branches fetched
> system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
> system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
648,649c706,707
< system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction
< system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction
---
> system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
> system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
652c710
< system.cpu2.op_class::total 167366 # Class of executed instruction
---
> system.cpu2.op_class::total 167367 # Class of executed instruction
654,655c712,713
< system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
< system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
---
> system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
> system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
657c715
< system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
---
> system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
659,661c717,719
< system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
< system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
< system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
---
> system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
> system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
> system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
666,673c724,731
< system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses
< system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses
< system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
< system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
< system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
< system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
< system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
< system.cpu2.icache.overall_hits::total 167008 # number of overall hits
---
> system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
> system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
> system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
> system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
> system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
> system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
> system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
> system.cpu2.icache.overall_hits::total 167009 # number of overall hits
680,685c738,743
< system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
< system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
< system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
< system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
< system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
---
> system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
> system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
> system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
> system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
> system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
702,705c760,763
< system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
< system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
< system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
< system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
---
> system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
> system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
> system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
> system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
707,710c765,769
< system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
< system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
< system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
---
> system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
> system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
> system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
> system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
712,738c771,797
< system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
< system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses
< system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses
< system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
< system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
< system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
< system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
< system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
< system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
< system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
< system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
< system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
< system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
< system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
< system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
< system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
< system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
< system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
< system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
< system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
< system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
< system.cpu2.dcache.overall_misses::total 269 # number of overall misses
< system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
< system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
---
> system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
> system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
> system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
> system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
> system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
> system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
> system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
> system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
> system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
> system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
> system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
> system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
> system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
> system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
> system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
> system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
> system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
> system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
> system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
> system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
> system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
> system.cpu2.dcache.overall_misses::total 255 # number of overall misses
> system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
> system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
741,754c800,813
< system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
< system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
< system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
< system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
< system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
< system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
< system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
< system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
< system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
< system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
< system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
< system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
---
> system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
> system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
> system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
> system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
> system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
> system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
> system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
> system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
> system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
> system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
> system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
> system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
764c823
< system.cpu3.numCycles 173294 # number of cpu cycles simulated
---
> system.cpu3.numCycles 173297 # number of cpu cycles simulated
767,769c826,828
< system.cpu3.committedInsts 167269 # Number of instructions committed
< system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
< system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
---
> system.cpu3.committedInsts 167272 # Number of instructions committed
> system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
> system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
772,773c831,832
< system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
< system.cpu3.num_int_insts 111554 # number of integer instructions
---
> system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
> system.cpu3.num_int_insts 113295 # number of integer instructions
775,776c834,835
< system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
< system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
---
> system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
> system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
779,788c838,847
< system.cpu3.num_mem_refs 55900 # number of memory refs
< system.cpu3.num_load_insts 41466 # Number of load instructions
< system.cpu3.num_store_insts 14434 # Number of store instructions
< system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
< system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
< system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
< system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
< system.cpu3.Branches 33511 # Number of branches fetched
< system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction
< system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction
---
> system.cpu3.num_mem_refs 58510 # number of memory refs
> system.cpu3.num_load_insts 42344 # Number of load instructions
> system.cpu3.num_store_insts 16166 # Number of store instructions
> system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
> system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
> system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
> system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
> system.cpu3.Branches 32639 # Number of branches fetched
> system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
> system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
817,818c876,877
< system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction
< system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction
---
> system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
> system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
821c880
< system.cpu3.op_class::total 167301 # Class of executed instruction
---
> system.cpu3.op_class::total 167304 # Class of executed instruction
823,824c882,883
< system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
< system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
---
> system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
> system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
826c885
< system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
---
> system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
828,830c887,889
< system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
< system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
< system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
---
> system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
> system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
> system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
835,842c894,901
< system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses
< system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses
< system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
< system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
< system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
< system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
< system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
< system.cpu3.icache.overall_hits::total 166942 # number of overall hits
---
> system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
> system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
> system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
> system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
> system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
> system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
> system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
> system.cpu3.icache.overall_hits::total 166945 # number of overall hits
849,854c908,913
< system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
< system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
< system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
< system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
< system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
---
> system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
> system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
> system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
> system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
> system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
871,874c930,933
< system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
< system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
< system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
< system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
---
> system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
> system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
> system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
> system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
876,880c935,938
< system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
< system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
< system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
< system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
---
> system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
> system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
> system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
882,924c940,982
< system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
< system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses
< system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses
< system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
< system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
< system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
< system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
< system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
< system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
< system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
< system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
< system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
< system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
< system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
< system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
< system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
< system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
< system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
< system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
< system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
< system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
< system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
< system.cpu3.dcache.overall_misses::total 259 # number of overall misses
< system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
< system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
< system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
< system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
< system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
< system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
< system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
< system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
< system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
< system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
< system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
< system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
< system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
---
> system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
> system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
> system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
> system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
> system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
> system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
> system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
> system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
> system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
> system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
> system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
> system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
> system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
> system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
> system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
> system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
> system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
> system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
> system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
> system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
> system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
> system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
> system.cpu3.dcache.overall_misses::total 260 # number of overall misses
> system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
> system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
> system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
> system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
> system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
> system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
> system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
> system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
> system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
> system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
> system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
> system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
> system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses