Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

stats.txt (11687:b3d5f0e9e258)	stats.txt (11754:c209cb86278a)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1262575 # Simulator instruction rate (inst/s) 8host_op_rate 1262551 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 163483418 # Simulator tick rate (ticks/s) 10host_mem_usage 263368 # Number of bytes of host memory used 11host_seconds 0.54 # Real time elapsed on the host	7host_inst_rate 1154171 # Simulator instruction rate (inst/s) 8host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 149440007 # Simulator tick rate (ticks/s) 10host_mem_usage 264052 # Number of bytes of host memory used 11host_seconds 0.59 # Real time elapsed on the host
12sim_insts 677333 # Number of instructions simulated 13sim_ops 677333 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 25system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 31system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 40system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 63system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls 66system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 67system.cpu0.numCycles 175415 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 175326 # Number of instructions committed 71system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured 75system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 76system.cpu0.num_int_insts 120376 # number of integer instructions 77system.cpu0.num_fp_insts 0 # number of float instructions 78system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 79system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 82397 # number of memory refs 83system.cpu0.num_load_insts 54591 # Number of load instructions 84system.cpu0.num_store_insts 27806 # Number of store instructions 85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 86system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles 87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 89system.cpu0.Branches 29689 # Number of branches fetched 90system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction 91system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction 92system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction 93system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction 94system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction 95system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction 96system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction 97system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction 98system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction 99system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction 100system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction 101system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction 102system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction 103system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction 104system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction 105system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction 106system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction 107system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction 108system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction 109system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction 110system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction 111system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction 112system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction 113system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction 114system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction 115system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction 116system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction 117system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction 119system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction 120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 122system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 123system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 128system.cpu0.op_class::total 175388 # Class of executed instruction 129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 130system.cpu0.dcache.tags.replacements 2 # number of replacements 131system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use 132system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. 133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 134system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. 135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor 137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 138system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 141system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 143system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses 144system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses 145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 146system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 147system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 148system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 149system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 150system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 151system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 152system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 153system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 154system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 155system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 156system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 157system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 158system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 159system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 160system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 161system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 162system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 163system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 164system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 165system.cpu0.dcache.overall_misses::total 328 # number of overall misses 166system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 167system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 171system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 173system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 174system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 175system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 176system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 177system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 178system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 180system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 181system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 182system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 183system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 184system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 185system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 186system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 189system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 190system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 191system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 192system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 193system.cpu0.dcache.writebacks::total 1 # number of writebacks 194system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 195system.cpu0.icache.tags.replacements 215 # number of replacements 196system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use 197system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 198system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 199system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 200system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 201system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor 202system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 203system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 204system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 205system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 206system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 207system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 208system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 209system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 210system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 211system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 212system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 213system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 214system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 215system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 216system.cpu0.icache.overall_hits::total 174921 # number of overall hits 217system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 218system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 219system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 220system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 221system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 222system.cpu0.icache.overall_misses::total 467 # number of overall misses 223system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 224system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 225system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 226system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 227system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 228system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 229system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 230system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 231system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 232system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 233system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 234system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 235system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 236system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 237system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 238system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 239system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 240system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 241system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 242system.cpu0.icache.writebacks::total 215 # number of writebacks 243system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 244system.cpu1.numCycles 173297 # number of cpu cycles simulated 245system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu1.committedInsts 167400 # Number of instructions committed 248system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed 249system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses 250system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 251system.cpu1.num_func_calls 633 # number of times a function call or return occured 252system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls 253system.cpu1.num_int_insts 107326 # number of integer instructions 254system.cpu1.num_fp_insts 0 # number of float instructions 255system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read 256system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written 257system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 258system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 259system.cpu1.num_mem_refs 49494 # number of memory refs 260system.cpu1.num_load_insts 39345 # Number of load instructions 261system.cpu1.num_store_insts 10149 # Number of store instructions 262system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles 263system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles 264system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles 265system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles 266system.cpu1.Branches 35694 # Number of branches fetched 267system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction 268system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction 269system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 270system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 271system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 272system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 273system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 274system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 275system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction 276system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 277system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction 278system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 279system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 280system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 281system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 282system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 283system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 284system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 285system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 286system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 287system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 288system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 289system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 290system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 291system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 292system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 293system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 294system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 295system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 296system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 297system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 298system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 299system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction 300system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction 301system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 302system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 303system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 305system.cpu1.op_class::total 167432 # Class of executed instruction 306system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 307system.cpu1.dcache.tags.replacements 0 # number of replacements 308system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use 309system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. 310system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 311system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. 312system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 313system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor 314system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy 315system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy 316system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 317system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 318system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 319system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses 320system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses 321system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 322system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits 323system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits 324system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits 325system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits 326system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 327system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 328system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits 329system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits 330system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits 331system.cpu1.dcache.overall_hits::total 49120 # number of overall hits 332system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses 333system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses 334system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses 335system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses 336system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses 337system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses 338system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses 339system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses 340system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses 341system.cpu1.dcache.overall_misses::total 287 # number of overall misses 342system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) 343system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) 344system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) 345system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) 346system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) 347system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) 348system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses 349system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses 350system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses 351system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses 352system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses 353system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses 354system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses 355system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses 356system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses 357system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses 358system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses 359system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses 360system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses 361system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses 362system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 369system.cpu1.icache.tags.replacements 278 # number of replacements 370system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use 371system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. 372system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 373system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. 374system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 375system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor 376system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy 377system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy 378system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 379system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 380system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 381system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 382system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses 383system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 384system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 385system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits 386system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits 387system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits 388system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits 389system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits 390system.cpu1.icache.overall_hits::total 167074 # number of overall hits 391system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 392system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 393system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 394system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 395system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 396system.cpu1.icache.overall_misses::total 358 # number of overall misses 397system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) 398system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) 399system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses 400system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses 401system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses 402system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses 403system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 404system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 405system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 406system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 407system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 408system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 409system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu1.icache.writebacks::writebacks 278 # number of writebacks 416system.cpu1.icache.writebacks::total 278 # number of writebacks 417system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 418system.cpu2.numCycles 173296 # number of cpu cycles simulated 419system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu2.committedInsts 167335 # Number of instructions committed 422system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed 423system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses 424system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 425system.cpu2.num_func_calls 633 # number of times a function call or return occured 426system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls 427system.cpu2.num_int_insts 114196 # number of integer instructions 428system.cpu2.num_fp_insts 0 # number of float instructions 429system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read 430system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written 431system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 432system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 433system.cpu2.num_mem_refs 59830 # number of memory refs 434system.cpu2.num_load_insts 42793 # Number of load instructions 435system.cpu2.num_store_insts 17037 # Number of store instructions 436system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles 437system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles 438system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 439system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 440system.cpu2.Branches 32221 # Number of branches fetched 441system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction 442system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction 443system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 444system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 445system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 446system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 447system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 448system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 449system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction 450system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 451system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction 452system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 453system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 454system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 455system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 456system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 457system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 458system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 459system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 460system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 461system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 462system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 463system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 464system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 465system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 466system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 467system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 468system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 469system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 470system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 471system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 472system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 473system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction 474system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction 475system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 476system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 477system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 478system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 479system.cpu2.op_class::total 167367 # Class of executed instruction 480system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 481system.cpu2.dcache.tags.replacements 0 # number of replacements 482system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use 483system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. 484system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 485system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. 486system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 487system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor 488system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy 489system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy 490system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 491system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 492system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 493system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 494system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses 495system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses 496system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 497system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits 498system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits 499system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits 500system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits 501system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 502system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 503system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits 504system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits 505system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits 506system.cpu2.dcache.overall_hits::total 59499 # number of overall hits 507system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses 508system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses 509system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 510system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 511system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 512system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 513system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses 514system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses 515system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses 516system.cpu2.dcache.overall_misses::total 255 # number of overall misses 517system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) 518system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) 519system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) 520system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) 521system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 522system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 523system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses 524system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses 525system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses 526system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses 527system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses 528system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses 529system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses 530system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses 531system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses 532system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 533system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses 534system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses 535system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses 536system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses 537system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 538system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 539system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 540system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 541system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 542system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 543system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 544system.cpu2.icache.tags.replacements 278 # number of replacements 545system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use 546system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. 547system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 548system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. 549system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 550system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor 551system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy 552system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy 553system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 554system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 555system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 556system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 557system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses 558system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses 559system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 560system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits 561system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits 562system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits 563system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits 564system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits 565system.cpu2.icache.overall_hits::total 167009 # number of overall hits 566system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 567system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 568system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 569system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 570system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 571system.cpu2.icache.overall_misses::total 358 # number of overall misses 572system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) 573system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) 574system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses 575system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses 576system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses 577system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses 578system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 579system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 580system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 581system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 582system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 583system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 584system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 585system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 587system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 589system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 590system.cpu2.icache.writebacks::writebacks 278 # number of writebacks 591system.cpu2.icache.writebacks::total 278 # number of writebacks 592system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 593system.cpu3.numCycles 173297 # number of cpu cycles simulated 594system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 595system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 596system.cpu3.committedInsts 167272 # Number of instructions committed 597system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed 598system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses 599system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 600system.cpu3.num_func_calls 633 # number of times a function call or return occured 601system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls 602system.cpu3.num_int_insts 113295 # number of integer instructions 603system.cpu3.num_fp_insts 0 # number of float instructions 604system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read 605system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written 606system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 607system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 608system.cpu3.num_mem_refs 58510 # number of memory refs 609system.cpu3.num_load_insts 42344 # Number of load instructions 610system.cpu3.num_store_insts 16166 # Number of store instructions 611system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles 612system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles 613system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles 614system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles 615system.cpu3.Branches 32639 # Number of branches fetched 616system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction 617system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction 618system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 619system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 620system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 621system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 622system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 623system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 624system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction 625system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 626system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction 627system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction 628system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction 629system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction 630system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction 631system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction 632system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction 633system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction 634system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction 635system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction 636system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction 637system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction 638system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction 639system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction 640system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 641system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 642system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 643system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 644system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 645system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 646system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 647system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction 648system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction 649system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction 650system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 651system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 652system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 653system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 654system.cpu3.op_class::total 167304 # Class of executed instruction 655system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 656system.cpu3.dcache.tags.replacements 0 # number of replacements 657system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use 658system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. 659system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 660system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. 661system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 662system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor 663system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy 664system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy 665system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 666system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 667system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 668system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses 669system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses 670system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 671system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits 672system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits 673system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits 674system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits 675system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 676system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 677system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits 678system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits 679system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits 680system.cpu3.dcache.overall_hits::total 58176 # number of overall hits 681system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 682system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 683system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 684system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 685system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 686system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 687system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses 688system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses 689system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses 690system.cpu3.dcache.overall_misses::total 260 # number of overall misses 691system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) 692system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) 693system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) 694system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) 695system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 696system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 697system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses 698system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses 699system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses 700system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses 701system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses 702system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses 703system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses 704system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses 705system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 706system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 707system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses 708system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses 709system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses 710system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses 711system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 718system.cpu3.icache.tags.replacements 279 # number of replacements 719system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use 720system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. 721system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 722system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. 723system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 724system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor 725system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy 726system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy 727system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 728system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 729system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 730system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 731system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses 732system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses 733system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 734system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits 735system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits 736system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits 737system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits 738system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits 739system.cpu3.icache.overall_hits::total 166945 # number of overall hits 740system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 741system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 742system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 743system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 744system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 745system.cpu3.icache.overall_misses::total 359 # number of overall misses 746system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) 747system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) 748system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses 749system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses 750system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses 751system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses 752system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 753system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 754system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 755system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 756system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 757system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 758system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 759system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 760system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 761system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 762system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 763system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 764system.cpu3.icache.writebacks::writebacks 279 # number of writebacks 765system.cpu3.icache.writebacks::total 279 # number of writebacks 766system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 767system.l2c.tags.replacements 0 # number of replacements 768system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use 769system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. 770system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. 771system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. 772system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 773system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 774system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor 775system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor 776system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor 777system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor 778system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor 779system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor 780system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor 781system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 782system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy 783system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 784system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy 785system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy 786system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy 787system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 788system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy 789system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy 790system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id 791system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 792system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id 793system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id 794system.l2c.tags.tag_accesses 19423 # Number of tag accesses 795system.l2c.tags.data_accesses 19423 # Number of data accesses 796system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 797system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 798system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 799system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 800system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 801system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits 802system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits 803system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits 804system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits 805system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits 806system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits 807system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits 808system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits 809system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits 810system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits 811system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 812system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits 813system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits 814system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 815system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 816system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 817system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 818system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 819system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 820system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits 821system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 822system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 823system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 824system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 825system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 826system.l2c.overall_hits::cpu0.data 5 # number of overall hits 827system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 828system.l2c.overall_hits::cpu1.data 3 # number of overall hits 829system.l2c.overall_hits::cpu2.inst 355 # number of overall hits 830system.l2c.overall_hits::cpu2.data 9 # number of overall hits 831system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 832system.l2c.overall_hits::cpu3.data 9 # number of overall hits 833system.l2c.overall_hits::total 1220 # number of overall hits 834system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 835system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 836system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 837system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 838system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 839system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses 840system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses 841system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses 842system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses 843system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses 844system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 845system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 846system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 847system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 848system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses 849system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 850system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 851system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 852system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 853system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses 854system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 855system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses 856system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 857system.l2c.demand_misses::total 559 # number of demand (read+write) misses 858system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 859system.l2c.overall_misses::cpu0.data 165 # number of overall misses 860system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 861system.l2c.overall_misses::cpu1.data 20 # number of overall misses 862system.l2c.overall_misses::cpu2.inst 3 # number of overall misses 863system.l2c.overall_misses::cpu2.data 13 # number of overall misses 864system.l2c.overall_misses::cpu3.inst 1 # number of overall misses 865system.l2c.overall_misses::cpu3.data 13 # number of overall misses 866system.l2c.overall_misses::total 559 # number of overall misses 867system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 868system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 869system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 870system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 871system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 872system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 873system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 874system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 875system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 876system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 877system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 878system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 879system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 880system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 881system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 882system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) 883system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) 884system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) 885system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) 886system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 887system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) 888system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) 889system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) 890system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 891system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 892system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 893system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 894system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 895system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 896system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 897system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 898system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 899system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 900system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 901system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 902system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 903system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 904system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 905system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 906system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 907system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 908system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 909system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 910system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 911system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 912system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 913system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 914system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses 915system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses 916system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses 917system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses 918system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses 919system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 920system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses 921system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses 922system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses 923system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses 924system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 925system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 926system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 927system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 928system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses 929system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 930system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses 931system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 932system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 933system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 934system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 935system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 936system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 937system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses 938system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 939system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses 940system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 941system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 942system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 945system.l2c.blocked::no_targets 0 # number of cycles access was blocked 946system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. 949system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. 950system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 951system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 952system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 953system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 954system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 955system.membus.trans_dist::ReadResp 423 # Transaction distribution 956system.membus.trans_dist::UpgradeReq 193 # Transaction distribution 957system.membus.trans_dist::ReadExReq 183 # Transaction distribution 958system.membus.trans_dist::ReadExResp 136 # Transaction distribution 959system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution 960system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) 961system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) 962system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) 963system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) 964system.membus.snoops 0 # Total snoops (count) 965system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 966system.membus.snoop_fanout::samples 799 # Request fanout histogram 967system.membus.snoop_fanout::mean 0 # Request fanout histogram 968system.membus.snoop_fanout::stdev 0 # Request fanout histogram 969system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 970system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram 971system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 972system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 973system.membus.snoop_fanout::min_value 0 # Request fanout histogram 974system.membus.snoop_fanout::max_value 0 # Request fanout histogram 975system.membus.snoop_fanout::total 799 # Request fanout histogram 976system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.	12sim_insts 677333 # Number of instructions simulated 13sim_ops 677333 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 25system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 31system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 40system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 63system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 64system.cpu_clk_domain.clock 500 # Clock period in ticks 65system.cpu0.workload.num_syscalls 89 # Number of system calls 66system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 67system.cpu0.numCycles 175415 # number of cpu cycles simulated 68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu0.committedInsts 175326 # Number of instructions committed 71system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 72system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 74system.cpu0.num_func_calls 390 # number of times a function call or return occured 75system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 76system.cpu0.num_int_insts 120376 # number of integer instructions 77system.cpu0.num_fp_insts 0 # number of float instructions 78system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 79system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu0.num_mem_refs 82397 # number of memory refs 83system.cpu0.num_load_insts 54591 # Number of load instructions 84system.cpu0.num_store_insts 27806 # Number of store instructions 85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 86system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles 87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 89system.cpu0.Branches 29689 # Number of branches fetched 90system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction 91system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction 92system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction 93system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction 94system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction 95system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction 96system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction 97system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction 98system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction 99system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction 100system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction 101system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction 102system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction 103system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction 104system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction 105system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction 106system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction 107system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction 108system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction 109system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction 110system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction 111system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction 112system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction 113system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction 114system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction 115system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction 116system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction 117system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction 118system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction 119system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction 120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 122system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 123system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 128system.cpu0.op_class::total 175388 # Class of executed instruction 129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 130system.cpu0.dcache.tags.replacements 2 # number of replacements 131system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use 132system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. 133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 134system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. 135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor 137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 138system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 141system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 143system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses 144system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses 145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 146system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 147system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 148system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 149system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 150system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 151system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 152system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 153system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 154system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 155system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 156system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 157system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 158system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 159system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 160system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 161system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 162system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 163system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 164system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 165system.cpu0.dcache.overall_misses::total 328 # number of overall misses 166system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 167system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 168system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 169system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 170system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 171system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 172system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 173system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 174system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 175system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 176system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 177system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 178system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 179system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 180system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 181system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 182system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 183system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 184system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 185system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 186system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 189system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 190system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 191system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 192system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 193system.cpu0.dcache.writebacks::total 1 # number of writebacks 194system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 195system.cpu0.icache.tags.replacements 215 # number of replacements 196system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use 197system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 198system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 199system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 200system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 201system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor 202system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 203system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 204system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 205system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 206system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 207system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 208system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 209system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 210system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 211system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 212system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 213system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 214system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 215system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 216system.cpu0.icache.overall_hits::total 174921 # number of overall hits 217system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 218system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 219system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 220system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 221system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 222system.cpu0.icache.overall_misses::total 467 # number of overall misses 223system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 224system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 225system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 226system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 227system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 228system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 229system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 230system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 231system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 232system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 233system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 234system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 235system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 236system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 237system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 238system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 239system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 240system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 241system.cpu0.icache.writebacks::writebacks 215 # number of writebacks 242system.cpu0.icache.writebacks::total 215 # number of writebacks 243system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 244system.cpu1.numCycles 173297 # number of cpu cycles simulated 245system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu1.committedInsts 167400 # Number of instructions committed 248system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed 249system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses 250system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 251system.cpu1.num_func_calls 633 # number of times a function call or return occured 252system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls 253system.cpu1.num_int_insts 107326 # number of integer instructions 254system.cpu1.num_fp_insts 0 # number of float instructions 255system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read 256system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written 257system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 258system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 259system.cpu1.num_mem_refs 49494 # number of memory refs 260system.cpu1.num_load_insts 39345 # Number of load instructions 261system.cpu1.num_store_insts 10149 # Number of store instructions 262system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles 263system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles 264system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles 265system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles 266system.cpu1.Branches 35694 # Number of branches fetched 267system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction 268system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction 269system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 270system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 271system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 272system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 273system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 274system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 275system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction 276system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 277system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction 278system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 279system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 280system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 281system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 282system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 283system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 284system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 285system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 286system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 287system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 288system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 289system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 290system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 291system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 292system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 293system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 294system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 295system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 296system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 297system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 298system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 299system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction 300system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction 301system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 302system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 303system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 305system.cpu1.op_class::total 167432 # Class of executed instruction 306system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 307system.cpu1.dcache.tags.replacements 0 # number of replacements 308system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use 309system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. 310system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 311system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. 312system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 313system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor 314system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy 315system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy 316system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 317system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 318system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 319system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses 320system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses 321system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 322system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits 323system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits 324system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits 325system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits 326system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 327system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 328system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits 329system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits 330system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits 331system.cpu1.dcache.overall_hits::total 49120 # number of overall hits 332system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses 333system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses 334system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses 335system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses 336system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses 337system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses 338system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses 339system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses 340system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses 341system.cpu1.dcache.overall_misses::total 287 # number of overall misses 342system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) 343system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) 344system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) 345system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) 346system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) 347system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) 348system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses 349system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses 350system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses 351system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses 352system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses 353system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses 354system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses 355system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses 356system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses 357system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses 358system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses 359system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses 360system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses 361system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses 362system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 369system.cpu1.icache.tags.replacements 278 # number of replacements 370system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use 371system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. 372system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 373system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. 374system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 375system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor 376system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy 377system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy 378system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 379system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 380system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 381system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 382system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses 383system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 384system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 385system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits 386system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits 387system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits 388system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits 389system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits 390system.cpu1.icache.overall_hits::total 167074 # number of overall hits 391system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 392system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 393system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 394system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 395system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 396system.cpu1.icache.overall_misses::total 358 # number of overall misses 397system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) 398system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) 399system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses 400system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses 401system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses 402system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses 403system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 404system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 405system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 406system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 407system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 408system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 409system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu1.icache.writebacks::writebacks 278 # number of writebacks 416system.cpu1.icache.writebacks::total 278 # number of writebacks 417system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 418system.cpu2.numCycles 173296 # number of cpu cycles simulated 419system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu2.committedInsts 167335 # Number of instructions committed 422system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed 423system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses 424system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 425system.cpu2.num_func_calls 633 # number of times a function call or return occured 426system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls 427system.cpu2.num_int_insts 114196 # number of integer instructions 428system.cpu2.num_fp_insts 0 # number of float instructions 429system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read 430system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written 431system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 432system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 433system.cpu2.num_mem_refs 59830 # number of memory refs 434system.cpu2.num_load_insts 42793 # Number of load instructions 435system.cpu2.num_store_insts 17037 # Number of store instructions 436system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles 437system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles 438system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 439system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 440system.cpu2.Branches 32221 # Number of branches fetched 441system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction 442system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction 443system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 444system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 445system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 446system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 447system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 448system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 449system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction 450system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 451system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction 452system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 453system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 454system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 455system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 456system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 457system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 458system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 459system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 460system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 461system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 462system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 463system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 464system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 465system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 466system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 467system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 468system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 469system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 470system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 471system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 472system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 473system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction 474system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction 475system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 476system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 477system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 478system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 479system.cpu2.op_class::total 167367 # Class of executed instruction 480system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 481system.cpu2.dcache.tags.replacements 0 # number of replacements 482system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use 483system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. 484system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 485system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. 486system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 487system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor 488system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy 489system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy 490system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 491system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 492system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 493system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 494system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses 495system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses 496system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 497system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits 498system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits 499system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits 500system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits 501system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 502system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 503system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits 504system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits 505system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits 506system.cpu2.dcache.overall_hits::total 59499 # number of overall hits 507system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses 508system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses 509system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 510system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 511system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 512system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 513system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses 514system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses 515system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses 516system.cpu2.dcache.overall_misses::total 255 # number of overall misses 517system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) 518system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) 519system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) 520system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) 521system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 522system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 523system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses 524system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses 525system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses 526system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses 527system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses 528system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses 529system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses 530system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses 531system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses 532system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 533system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses 534system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses 535system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses 536system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses 537system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 538system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 539system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 540system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 541system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 542system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 543system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 544system.cpu2.icache.tags.replacements 278 # number of replacements 545system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use 546system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. 547system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 548system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. 549system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 550system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor 551system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy 552system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy 553system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 554system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 555system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 556system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 557system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses 558system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses 559system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 560system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits 561system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits 562system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits 563system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits 564system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits 565system.cpu2.icache.overall_hits::total 167009 # number of overall hits 566system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 567system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 568system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 569system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 570system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 571system.cpu2.icache.overall_misses::total 358 # number of overall misses 572system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) 573system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) 574system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses 575system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses 576system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses 577system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses 578system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 579system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 580system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 581system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 582system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 583system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 584system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 585system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 587system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 589system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 590system.cpu2.icache.writebacks::writebacks 278 # number of writebacks 591system.cpu2.icache.writebacks::total 278 # number of writebacks 592system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states 593system.cpu3.numCycles 173297 # number of cpu cycles simulated 594system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 595system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 596system.cpu3.committedInsts 167272 # Number of instructions committed 597system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed 598system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses 599system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 600system.cpu3.num_func_calls 633 # number of times a function call or return occured 601system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls 602system.cpu3.num_int_insts 113295 # number of integer instructions 603system.cpu3.num_fp_insts 0 # number of float instructions 604system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read 605system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written 606system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 607system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 608system.cpu3.num_mem_refs 58510 # number of memory refs 609system.cpu3.num_load_insts 42344 # Number of load instructions 610system.cpu3.num_store_insts 16166 # Number of store instructions 611system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles 612system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles 613system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles 614system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles 615system.cpu3.Branches 32639 # Number of branches fetched 616system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction 617system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction 618system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 619system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 620system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 621system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 622system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 623system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 624system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction 625system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 626system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction 627system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction 628system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction 629system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction 630system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction 631system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction 632system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction 633system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction 634system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction 635system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction 636system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction 637system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction 638system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction 639system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction 640system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 641system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 642system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 643system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 644system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 645system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 646system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 647system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction 648system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction 649system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction 650system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 651system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 652system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 653system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 654system.cpu3.op_class::total 167304 # Class of executed instruction 655system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 656system.cpu3.dcache.tags.replacements 0 # number of replacements 657system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use 658system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. 659system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 660system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. 661system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 662system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor 663system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy 664system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy 665system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 666system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 667system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 668system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses 669system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses 670system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 671system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits 672system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits 673system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits 674system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits 675system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 676system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 677system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits 678system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits 679system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits 680system.cpu3.dcache.overall_hits::total 58176 # number of overall hits 681system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 682system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 683system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 684system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 685system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 686system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 687system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses 688system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses 689system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses 690system.cpu3.dcache.overall_misses::total 260 # number of overall misses 691system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) 692system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) 693system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) 694system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) 695system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 696system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 697system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses 698system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses 699system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses 700system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses 701system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses 702system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses 703system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses 704system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses 705system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 706system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 707system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses 708system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses 709system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses 710system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses 711system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 718system.cpu3.icache.tags.replacements 279 # number of replacements 719system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use 720system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. 721system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 722system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. 723system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 724system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor 725system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy 726system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy 727system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 728system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 729system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 730system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 731system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses 732system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses 733system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 734system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits 735system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits 736system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits 737system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits 738system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits 739system.cpu3.icache.overall_hits::total 166945 # number of overall hits 740system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 741system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 742system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 743system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 744system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 745system.cpu3.icache.overall_misses::total 359 # number of overall misses 746system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) 747system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) 748system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses 749system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses 750system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses 751system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses 752system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 753system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 754system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 755system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 756system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 757system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 758system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 759system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 760system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 761system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 762system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 763system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 764system.cpu3.icache.writebacks::writebacks 279 # number of writebacks 765system.cpu3.icache.writebacks::total 279 # number of writebacks 766system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 767system.l2c.tags.replacements 0 # number of replacements 768system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use 769system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. 770system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. 771system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. 772system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 773system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 774system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor 775system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor 776system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor 777system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor 778system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor 779system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor 780system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor 781system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 782system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy 783system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 784system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy 785system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy 786system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy 787system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 788system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy 789system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy 790system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id 791system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 792system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id 793system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id 794system.l2c.tags.tag_accesses 19423 # Number of tag accesses 795system.l2c.tags.data_accesses 19423 # Number of data accesses 796system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 797system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 798system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 799system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 800system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 801system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits 802system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits 803system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits 804system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits 805system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits 806system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits 807system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits 808system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits 809system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits 810system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits 811system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 812system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits 813system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits 814system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 815system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 816system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 817system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 818system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 819system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 820system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits 821system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 822system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 823system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 824system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 825system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 826system.l2c.overall_hits::cpu0.data 5 # number of overall hits 827system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 828system.l2c.overall_hits::cpu1.data 3 # number of overall hits 829system.l2c.overall_hits::cpu2.inst 355 # number of overall hits 830system.l2c.overall_hits::cpu2.data 9 # number of overall hits 831system.l2c.overall_hits::cpu3.inst 358 # number of overall hits 832system.l2c.overall_hits::cpu3.data 9 # number of overall hits 833system.l2c.overall_hits::total 1220 # number of overall hits 834system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 835system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 836system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 837system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 838system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 839system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses 840system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses 841system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses 842system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses 843system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses 844system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 845system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 846system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 847system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 848system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses 849system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 850system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 851system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 852system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 853system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses 854system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 855system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses 856system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 857system.l2c.demand_misses::total 559 # number of demand (read+write) misses 858system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 859system.l2c.overall_misses::cpu0.data 165 # number of overall misses 860system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 861system.l2c.overall_misses::cpu1.data 20 # number of overall misses 862system.l2c.overall_misses::cpu2.inst 3 # number of overall misses 863system.l2c.overall_misses::cpu2.data 13 # number of overall misses 864system.l2c.overall_misses::cpu3.inst 1 # number of overall misses 865system.l2c.overall_misses::cpu3.data 13 # number of overall misses 866system.l2c.overall_misses::total 559 # number of overall misses 867system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 868system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 869system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 870system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 871system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 872system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 873system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 874system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 875system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 876system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 877system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 878system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 879system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 880system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 881system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 882system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) 883system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) 884system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) 885system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) 886system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 887system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) 888system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) 889system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) 890system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 891system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 892system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 893system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 894system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 895system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 896system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 897system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 898system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 899system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 900system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 901system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 902system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 903system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 904system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 905system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 906system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 907system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 908system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 909system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 910system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 911system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 912system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 913system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 914system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses 915system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses 916system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses 917system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses 918system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses 919system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 920system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses 921system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses 922system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses 923system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses 924system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 925system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 926system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 927system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 928system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses 929system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 930system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses 931system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 932system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 933system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 934system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 935system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 936system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 937system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses 938system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 939system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses 940system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 941system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 942system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 945system.l2c.blocked::no_targets 0 # number of cycles access was blocked 946system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. 949system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. 950system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 951system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 952system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 953system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 954system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 955system.membus.trans_dist::ReadResp 423 # Transaction distribution 956system.membus.trans_dist::UpgradeReq 193 # Transaction distribution 957system.membus.trans_dist::ReadExReq 183 # Transaction distribution 958system.membus.trans_dist::ReadExResp 136 # Transaction distribution 959system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution 960system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) 961system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) 962system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) 963system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) 964system.membus.snoops 0 # Total snoops (count) 965system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 966system.membus.snoop_fanout::samples 799 # Request fanout histogram 967system.membus.snoop_fanout::mean 0 # Request fanout histogram 968system.membus.snoop_fanout::stdev 0 # Request fanout histogram 969system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 970system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram 971system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 972system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 973system.membus.snoop_fanout::min_value 0 # Request fanout histogram 974system.membus.snoop_fanout::max_value 0 # Request fanout histogram 975system.membus.snoop_fanout::total 799 # Request fanout histogram 976system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
977system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 978system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.	977system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data. 978system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
979system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 980system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 981system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 982system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 983system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution 984system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 985system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution 986system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 987system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 988system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 989system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution 990system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution 991system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution 992system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution 993system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 994system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) 995system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 996system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) 997system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 998system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) 999system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) 1000system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) 1001system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) 1002system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 1003system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 1004system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 1005system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) 1006system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 1007system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 1008system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 1009system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 1010system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) 1011system.toL2Bus.snoops 0 # Total snoops (count) 1012system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 1013system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram	979system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 980system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 981system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 982system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states 983system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution 984system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 985system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution 986system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 987system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 988system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 989system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution 990system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution 991system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution 992system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution 993system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 994system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) 995system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 996system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) 997system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 998system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) 999system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) 1000system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) 1001system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) 1002system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 1003system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 1004system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 1005system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) 1006system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 1007system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 1008system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 1009system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 1010system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) 1011system.toL2Bus.snoops 0 # Total snoops (count) 1012system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 1013system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
1014system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram 1015system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram	1014system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram 1015system.toL2Bus.snoop_fanout::stdev 1.218885 # Request fanout histogram
1016system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1017system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram	1016system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1017system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram
1018system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram 1019system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram 1020system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram	1018system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% # Request fanout histogram 1019system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% # Request fanout histogram 1020system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% # Request fanout histogram
1021system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1022system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1023system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1024system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1025system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1026system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1027system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1028system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1029system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram 1030 1031---------- End Simulation Statistics ----------	1021system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1022system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 1023system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 1024system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 1025system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 1026system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1027system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1028system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1029system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram 1030 1031---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000088 # Number of seconds simulated
4sim_ticks 87707000 # Number of ticks simulated
5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1262575 # Simulator instruction rate (inst/s)
8host_op_rate 1262551 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 163483418 # Simulator tick rate (ticks/s)
10host_mem_usage 263368 # Number of bytes of host memory used
11host_seconds 0.54 # Real time elapsed on the host

7host_inst_rate 1154171 # Simulator instruction rate (inst/s)
8host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 149440007 # Simulator tick rate (ticks/s)
10host_mem_usage 264052 # Number of bytes of host memory used
11host_seconds 0.59 # Real time elapsed on the host

12sim_insts 677333 # Number of instructions simulated
13sim_ops 677333 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
25system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
39system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
63system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
64system.cpu_clk_domain.clock 500 # Clock period in ticks
65system.cpu0.workload.num_syscalls 89 # Number of system calls
66system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
67system.cpu0.numCycles 175415 # number of cpu cycles simulated
68system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu0.committedInsts 175326 # Number of instructions committed
71system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
72system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
73system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
74system.cpu0.num_func_calls 390 # number of times a function call or return occured
75system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
76system.cpu0.num_int_insts 120376 # number of integer instructions
77system.cpu0.num_fp_insts 0 # number of float instructions
78system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
79system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
80system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
81system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
82system.cpu0.num_mem_refs 82397 # number of memory refs
83system.cpu0.num_load_insts 54591 # Number of load instructions
84system.cpu0.num_store_insts 27806 # Number of store instructions
85system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
86system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles
87system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
88system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
89system.cpu0.Branches 29689 # Number of branches fetched
90system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
91system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction
92system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction
93system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction
94system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction
95system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction
96system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction
97system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction
98system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction
99system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction
100system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction
101system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction
102system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction
103system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction
104system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction
105system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction
106system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction
107system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction
108system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction
109system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction
110system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction
111system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction
112system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction
113system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction
114system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction
115system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction
116system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction
117system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction
118system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction
119system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction
120system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction
121system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction
122system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction
123system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction
124system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
125system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
126system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
127system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
128system.cpu0.op_class::total 175388 # Class of executed instruction
129system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
130system.cpu0.dcache.tags.replacements 2 # number of replacements
131system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
132system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
133system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
134system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
135system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
137system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
138system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
139system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
140system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
141system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
142system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
143system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
144system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
145system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
146system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
147system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
148system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
149system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
150system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
151system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
152system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
153system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
154system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
155system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
156system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
157system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
158system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
159system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
160system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
161system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
162system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
163system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
164system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
165system.cpu0.dcache.overall_misses::total 328 # number of overall misses
166system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
167system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
168system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
169system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
170system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
171system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
172system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
173system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
174system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
175system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
176system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
177system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
178system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
179system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
180system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
181system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
182system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
183system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
184system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
185system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
186system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
187system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
188system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
189system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
190system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
191system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
192system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
193system.cpu0.dcache.writebacks::total 1 # number of writebacks
194system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
195system.cpu0.icache.tags.replacements 215 # number of replacements
196system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
197system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
198system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
199system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
200system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
201system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
202system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
203system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
204system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
205system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
206system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
207system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
208system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
209system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
210system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
211system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
212system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
213system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
214system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
215system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
216system.cpu0.icache.overall_hits::total 174921 # number of overall hits
217system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
218system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
219system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
220system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
221system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
222system.cpu0.icache.overall_misses::total 467 # number of overall misses
223system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
224system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
225system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
226system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
227system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
228system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
229system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
230system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
231system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
232system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
233system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
234system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
235system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
236system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
237system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
238system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
239system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
240system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
241system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
242system.cpu0.icache.writebacks::total 215 # number of writebacks
243system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
244system.cpu1.numCycles 173297 # number of cpu cycles simulated
245system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
246system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
247system.cpu1.committedInsts 167400 # Number of instructions committed
248system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
249system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
250system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
251system.cpu1.num_func_calls 633 # number of times a function call or return occured
252system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
253system.cpu1.num_int_insts 107326 # number of integer instructions
254system.cpu1.num_fp_insts 0 # number of float instructions
255system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
256system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
257system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
258system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
259system.cpu1.num_mem_refs 49494 # number of memory refs
260system.cpu1.num_load_insts 39345 # Number of load instructions
261system.cpu1.num_store_insts 10149 # Number of store instructions
262system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
263system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
264system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
265system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
266system.cpu1.Branches 35694 # Number of branches fetched
267system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
268system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
269system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
270system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
271system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
272system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
273system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
274system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
275system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction
276system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
277system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction
278system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
279system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
280system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
281system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
282system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
283system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
284system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
285system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
286system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
287system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
288system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
289system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
290system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
291system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
292system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
293system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
294system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
295system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
296system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
297system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
298system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
299system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
300system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
301system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
302system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
303system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
304system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
305system.cpu1.op_class::total 167432 # Class of executed instruction
306system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
307system.cpu1.dcache.tags.replacements 0 # number of replacements
308system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
309system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
310system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
311system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
312system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
313system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
314system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
315system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
316system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
317system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
318system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
319system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
320system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
321system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
322system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
323system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
324system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
325system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
326system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
327system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
328system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
329system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
330system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
331system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
332system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
333system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
334system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
335system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
336system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
337system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
338system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
339system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
340system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
341system.cpu1.dcache.overall_misses::total 287 # number of overall misses
342system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
343system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
344system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
345system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
346system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
347system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
348system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
349system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
350system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
351system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
352system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
353system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
354system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
355system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
356system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
357system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
358system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
359system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
360system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
361system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
362system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
363system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
364system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
365system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
366system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
367system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
368system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
369system.cpu1.icache.tags.replacements 278 # number of replacements
370system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
371system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
372system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
373system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
374system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
375system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
376system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
377system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
378system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
379system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
380system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
381system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
382system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
383system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
384system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
385system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
386system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
387system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
388system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
389system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
390system.cpu1.icache.overall_hits::total 167074 # number of overall hits
391system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
392system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
393system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
394system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
395system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
396system.cpu1.icache.overall_misses::total 358 # number of overall misses
397system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
398system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
399system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
400system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
401system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
402system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
403system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
404system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
405system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
406system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
407system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
408system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
409system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
410system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
411system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
412system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
413system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
414system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
415system.cpu1.icache.writebacks::writebacks 278 # number of writebacks
416system.cpu1.icache.writebacks::total 278 # number of writebacks
417system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
418system.cpu2.numCycles 173296 # number of cpu cycles simulated
419system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
420system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
421system.cpu2.committedInsts 167335 # Number of instructions committed
422system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
423system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
424system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
425system.cpu2.num_func_calls 633 # number of times a function call or return occured
426system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
427system.cpu2.num_int_insts 114196 # number of integer instructions
428system.cpu2.num_fp_insts 0 # number of float instructions
429system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
430system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
431system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
432system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
433system.cpu2.num_mem_refs 59830 # number of memory refs
434system.cpu2.num_load_insts 42793 # Number of load instructions
435system.cpu2.num_store_insts 17037 # Number of store instructions
436system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
437system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
438system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
439system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
440system.cpu2.Branches 32221 # Number of branches fetched
441system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
442system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
443system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
444system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
445system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
446system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
447system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
448system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
449system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction
450system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
451system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction
452system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
453system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
454system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
455system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
456system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
457system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
458system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
459system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
460system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
461system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
462system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
463system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
464system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
465system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
466system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
467system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
468system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
469system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
470system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
471system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
472system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
473system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
474system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
475system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
476system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
477system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
478system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
479system.cpu2.op_class::total 167367 # Class of executed instruction
480system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
481system.cpu2.dcache.tags.replacements 0 # number of replacements
482system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
483system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
484system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
485system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
486system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
487system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
488system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
489system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
490system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
491system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
492system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
493system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
494system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
495system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
496system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
497system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
498system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
499system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
500system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
501system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
502system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
503system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
504system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
505system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
506system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
507system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
508system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
509system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
510system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
511system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
512system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
513system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
514system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
515system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
516system.cpu2.dcache.overall_misses::total 255 # number of overall misses
517system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
518system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
519system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
520system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
521system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
522system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
523system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
524system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
525system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
526system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
527system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
528system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
529system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
530system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
531system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
532system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
533system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
534system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
535system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
536system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
537system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
538system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
539system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
540system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
541system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
542system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
543system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
544system.cpu2.icache.tags.replacements 278 # number of replacements
545system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
546system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
547system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
548system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
549system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
550system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
551system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
552system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
553system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
554system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
555system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
556system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
557system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
558system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
559system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
560system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
561system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
562system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
563system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
564system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
565system.cpu2.icache.overall_hits::total 167009 # number of overall hits
566system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
567system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
568system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
569system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
570system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
571system.cpu2.icache.overall_misses::total 358 # number of overall misses
572system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
573system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
574system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
575system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
576system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
577system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
578system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
579system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
580system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
581system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
582system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
583system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
584system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
585system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
586system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
587system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
588system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
589system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
590system.cpu2.icache.writebacks::writebacks 278 # number of writebacks
591system.cpu2.icache.writebacks::total 278 # number of writebacks
592system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
593system.cpu3.numCycles 173297 # number of cpu cycles simulated
594system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
595system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
596system.cpu3.committedInsts 167272 # Number of instructions committed
597system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
598system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
599system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
600system.cpu3.num_func_calls 633 # number of times a function call or return occured
601system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
602system.cpu3.num_int_insts 113295 # number of integer instructions
603system.cpu3.num_fp_insts 0 # number of float instructions
604system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
605system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
606system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
607system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
608system.cpu3.num_mem_refs 58510 # number of memory refs
609system.cpu3.num_load_insts 42344 # Number of load instructions
610system.cpu3.num_store_insts 16166 # Number of store instructions
611system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
612system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
613system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
614system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
615system.cpu3.Branches 32639 # Number of branches fetched
616system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
617system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
618system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
619system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
620system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
621system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction
622system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction
623system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction
624system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction
625system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction
626system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction
627system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction
628system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction
629system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction
630system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction
631system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction
632system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction
633system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction
634system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction
635system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction
636system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction
637system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction
638system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction
639system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction
640system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction
641system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction
642system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction
643system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction
644system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction
645system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
646system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
647system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
648system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
649system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
650system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
651system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
652system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
653system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
654system.cpu3.op_class::total 167304 # Class of executed instruction
655system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
656system.cpu3.dcache.tags.replacements 0 # number of replacements
657system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
658system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
659system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
660system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
661system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
662system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
663system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
664system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
665system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
666system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
667system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
668system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
669system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
670system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
671system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
672system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
673system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
674system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
675system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
676system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
677system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
678system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
679system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
680system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
681system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
682system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
683system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
684system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
685system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
686system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
687system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
688system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
689system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
690system.cpu3.dcache.overall_misses::total 260 # number of overall misses
691system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
692system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
693system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
694system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
695system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
696system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
697system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
698system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
699system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
700system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
701system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
702system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
703system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
704system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
705system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
706system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
707system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
708system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
709system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
710system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
711system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
712system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
713system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
714system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
715system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
716system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
717system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
718system.cpu3.icache.tags.replacements 279 # number of replacements
719system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
720system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
721system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
722system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
723system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
724system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
725system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
726system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
727system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
728system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
729system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
730system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
731system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
732system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
733system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
734system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
735system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
736system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
737system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
738system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
739system.cpu3.icache.overall_hits::total 166945 # number of overall hits
740system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
741system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
742system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
743system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
744system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
745system.cpu3.icache.overall_misses::total 359 # number of overall misses
746system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
747system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
748system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
749system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
750system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
751system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
752system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
753system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
754system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
755system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
756system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
757system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
758system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
759system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
760system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
761system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
762system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
763system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
764system.cpu3.icache.writebacks::writebacks 279 # number of writebacks
765system.cpu3.icache.writebacks::total 279 # number of writebacks
766system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
767system.l2c.tags.replacements 0 # number of replacements
768system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use
769system.l2c.tags.total_refs 1799 # Total number of references to valid blocks.
770system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks.
771system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks.
772system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
773system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
774system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor
775system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
776system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor
777system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
778system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor
779system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
780system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor
781system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
782system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy
783system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
784system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy
785system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
786system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy
787system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
788system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy
789system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy
790system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id
791system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
792system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id
793system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id
794system.l2c.tags.tag_accesses 19423 # Number of tag accesses
795system.l2c.tags.data_accesses 19423 # Number of data accesses
796system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
797system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
798system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
799system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
800system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
801system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits
802system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
803system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits
804system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits
805system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits
806system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
807system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits
808system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits
809system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
810system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
811system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
812system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits
813system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
814system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
815system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
816system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
817system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
818system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
819system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
820system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
821system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
822system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
823system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
824system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
825system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
826system.l2c.overall_hits::cpu0.data 5 # number of overall hits
827system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
828system.l2c.overall_hits::cpu1.data 3 # number of overall hits
829system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
830system.l2c.overall_hits::cpu2.data 9 # number of overall hits
831system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
832system.l2c.overall_hits::cpu3.data 9 # number of overall hits
833system.l2c.overall_hits::total 1220 # number of overall hits
834system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
835system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
836system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
837system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
838system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
839system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses
840system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses
841system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses
842system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses
843system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses
844system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
845system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
846system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
847system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
848system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
849system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
850system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
851system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
852system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
853system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
854system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
855system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
856system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
857system.l2c.demand_misses::total 559 # number of demand (read+write) misses
858system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
859system.l2c.overall_misses::cpu0.data 165 # number of overall misses
860system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
861system.l2c.overall_misses::cpu1.data 20 # number of overall misses
862system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
863system.l2c.overall_misses::cpu2.data 13 # number of overall misses
864system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
865system.l2c.overall_misses::cpu3.data 13 # number of overall misses
866system.l2c.overall_misses::total 559 # number of overall misses
867system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
868system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
869system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
870system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
871system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
872system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
873system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
874system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
875system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
876system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
877system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
878system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
879system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
880system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
881system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
882system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses)
883system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses)
884system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses)
885system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses)
886system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
887system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses)
888system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses)
889system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses)
890system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
891system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
892system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
893system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
894system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
895system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
896system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
897system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
898system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
899system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
900system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
901system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
902system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
903system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
904system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
905system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
906system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
907system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
908system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
909system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
910system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
911system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
912system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
913system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
914system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses
915system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses
916system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses
917system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses
918system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses
919system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
920system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses
921system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses
922system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses
923system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses
924system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
925system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
926system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
927system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
928system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
929system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
930system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
931system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
932system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
933system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
934system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
935system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
936system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
937system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
938system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
939system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
940system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
941system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
942system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
943system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
944system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
945system.l2c.blocked::no_targets 0 # number of cycles access was blocked
946system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
947system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
948system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter.
949system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data.
950system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
951system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
952system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
953system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
954system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
955system.membus.trans_dist::ReadResp 423 # Transaction distribution
956system.membus.trans_dist::UpgradeReq 193 # Transaction distribution
957system.membus.trans_dist::ReadExReq 183 # Transaction distribution
958system.membus.trans_dist::ReadExResp 136 # Transaction distribution
959system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
960system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes)
961system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes)
962system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
963system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
964system.membus.snoops 0 # Total snoops (count)
965system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
966system.membus.snoop_fanout::samples 799 # Request fanout histogram
967system.membus.snoop_fanout::mean 0 # Request fanout histogram
968system.membus.snoop_fanout::stdev 0 # Request fanout histogram
969system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
970system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram
971system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
972system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
973system.membus.snoop_fanout::min_value 0 # Request fanout histogram
974system.membus.snoop_fanout::max_value 0 # Request fanout histogram
975system.membus.snoop_fanout::total 799 # Request fanout histogram
976system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.

977system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
978system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

977system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data.
978system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

979system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
980system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
981system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
982system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
983system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
984system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
985system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution
986system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
987system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
988system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
989system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
990system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
991system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
992system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution
993system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
994system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)
995system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
996system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
997system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
998system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
999system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)
1000system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
1001system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)
1002system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
1003system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
1004system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
1005system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
1006system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
1007system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
1008system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
1009system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
1010system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes)
1011system.toL2Bus.snoops 0 # Total snoops (count)
1012system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
1013system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram

1014system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
1015system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram

1014system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram
1015system.toL2Bus.snoop_fanout::stdev 1.218885 # Request fanout histogram

1016system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1017system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram

1018system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram
1019system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram
1020system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram

1018system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% # Request fanout histogram
1019system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% # Request fanout histogram
1020system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% # Request fanout histogram