Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000088 # Number of seconds simulated
4sim_ticks 87707000 # Number of ticks simulated
5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1750110 # Simulator instruction rate (inst/s)
8host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 226603798 # Simulator tick rate (ticks/s)
10host_mem_usage 303668 # Number of bytes of host memory used

7host_inst_rate 1726221 # Simulator instruction rate (inst/s)
8host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 223510854 # Simulator tick rate (ticks/s)
10host_mem_usage 306324 # Number of bytes of host memory used

11host_seconds 0.39 # Real time elapsed on the host
12sim_insts 677333 # Number of instructions simulated
13sim_ops 677333 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
62system.cpu_clk_domain.clock 500 # Clock period in ticks
63system.cpu0.workload.num_syscalls 89 # Number of system calls
64system.cpu0.numCycles 175415 # number of cpu cycles simulated
65system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
66system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
67system.cpu0.committedInsts 175326 # Number of instructions committed
68system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
69system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
70system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
71system.cpu0.num_func_calls 390 # number of times a function call or return occured
72system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
73system.cpu0.num_int_insts 120376 # number of integer instructions
74system.cpu0.num_fp_insts 0 # number of float instructions
75system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
76system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
77system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
78system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
79system.cpu0.num_mem_refs 82397 # number of memory refs
80system.cpu0.num_load_insts 54591 # Number of load instructions
81system.cpu0.num_store_insts 27806 # Number of store instructions
82system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
83system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles
84system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
85system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
86system.cpu0.Branches 29689 # Number of branches fetched
87system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
88system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction
89system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction
90system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction
91system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction
92system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction
93system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction
94system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction
95system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction
96system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction
97system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction
98system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction
99system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction
100system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction
101system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction
102system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction
103system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction
104system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction
105system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction
106system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction
107system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction
108system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction
109system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction
110system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction
111system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction
112system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction
113system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction
114system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction
115system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction
116system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction
117system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction
118system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction
119system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
120system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
121system.cpu0.op_class::total 175388 # Class of executed instruction
122system.cpu0.dcache.tags.replacements 2 # number of replacements
123system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
124system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
125system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
126system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
127system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
128system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
129system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
130system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
131system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
132system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
133system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
134system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
135system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
136system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
137system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
138system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
139system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
140system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
141system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
142system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
143system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
144system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
145system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
146system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
147system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
148system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
149system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
150system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
151system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
152system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
153system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
154system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
155system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
156system.cpu0.dcache.overall_misses::total 328 # number of overall misses
157system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
158system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
159system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
160system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
161system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
162system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
163system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
164system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
165system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
166system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
167system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
168system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
169system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
170system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
171system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
172system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
173system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
174system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
175system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
176system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
177system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
179system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
180system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
181system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
182system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
183system.cpu0.dcache.fast_writes 0 # number of fast writes performed
184system.cpu0.dcache.cache_copies 0 # number of cache copies performed
185system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
186system.cpu0.dcache.writebacks::total 1 # number of writebacks
187system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
188system.cpu0.icache.tags.replacements 215 # number of replacements
189system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
190system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
191system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
192system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
193system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
194system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
195system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
196system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
197system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
198system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
199system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
200system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
201system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
202system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
203system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
204system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
205system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
206system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
207system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
208system.cpu0.icache.overall_hits::total 174921 # number of overall hits
209system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
210system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
211system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
212system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
213system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
214system.cpu0.icache.overall_misses::total 467 # number of overall misses
215system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
216system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
217system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
218system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
219system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
220system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
221system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
222system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
223system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
224system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
225system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
226system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
227system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
228system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
229system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
230system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
231system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
232system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
233system.cpu0.icache.fast_writes 0 # number of fast writes performed
234system.cpu0.icache.cache_copies 0 # number of cache copies performed
235system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
236system.cpu1.numCycles 173297 # number of cpu cycles simulated
237system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
238system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
239system.cpu1.committedInsts 167400 # Number of instructions committed
240system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
241system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
242system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
243system.cpu1.num_func_calls 633 # number of times a function call or return occured
244system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
245system.cpu1.num_int_insts 107326 # number of integer instructions
246system.cpu1.num_fp_insts 0 # number of float instructions
247system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
248system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
249system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
250system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
251system.cpu1.num_mem_refs 49494 # number of memory refs
252system.cpu1.num_load_insts 39345 # Number of load instructions
253system.cpu1.num_store_insts 10149 # Number of store instructions
254system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
255system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
256system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
257system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
258system.cpu1.Branches 35694 # Number of branches fetched
259system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
260system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
261system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
262system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
263system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
264system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
265system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
266system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
267system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
268system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
269system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
270system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
271system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
272system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
273system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
274system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
275system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
276system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
277system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
278system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
279system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
280system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
281system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
282system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
283system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
284system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
285system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
286system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
287system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
288system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
289system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
290system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
291system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
292system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
293system.cpu1.op_class::total 167432 # Class of executed instruction
294system.cpu1.dcache.tags.replacements 0 # number of replacements
295system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
296system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
297system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
298system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
299system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
300system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
301system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
302system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
303system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
304system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
305system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
306system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
307system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
308system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
309system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
310system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
311system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
312system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
313system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
314system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
315system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
316system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
317system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
318system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
319system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
320system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
321system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
322system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
323system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
324system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
325system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
326system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
327system.cpu1.dcache.overall_misses::total 287 # number of overall misses
328system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
329system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
330system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
331system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
332system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
333system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
334system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
335system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
336system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
337system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
338system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
339system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
340system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
341system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
342system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
343system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
344system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
345system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
346system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
347system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
348system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
349system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
350system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
351system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
352system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
353system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
354system.cpu1.dcache.fast_writes 0 # number of fast writes performed
355system.cpu1.dcache.cache_copies 0 # number of cache copies performed
356system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
357system.cpu1.icache.tags.replacements 278 # number of replacements
358system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
359system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
360system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
361system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
362system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
363system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
364system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
365system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
366system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
367system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
368system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
369system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
370system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
371system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
372system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
373system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
374system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
375system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
376system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
377system.cpu1.icache.overall_hits::total 167074 # number of overall hits
378system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
379system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
380system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
381system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
382system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
383system.cpu1.icache.overall_misses::total 358 # number of overall misses
384system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
385system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
386system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
387system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
388system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
389system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
390system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
391system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
392system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
393system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
394system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
395system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
396system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
397system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
398system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
399system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
400system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
401system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
402system.cpu1.icache.fast_writes 0 # number of fast writes performed
403system.cpu1.icache.cache_copies 0 # number of cache copies performed
404system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
405system.cpu2.numCycles 173296 # number of cpu cycles simulated
406system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
407system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
408system.cpu2.committedInsts 167335 # Number of instructions committed
409system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
410system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
411system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
412system.cpu2.num_func_calls 633 # number of times a function call or return occured
413system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
414system.cpu2.num_int_insts 114196 # number of integer instructions
415system.cpu2.num_fp_insts 0 # number of float instructions
416system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
417system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
418system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
419system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
420system.cpu2.num_mem_refs 59830 # number of memory refs
421system.cpu2.num_load_insts 42793 # Number of load instructions
422system.cpu2.num_store_insts 17037 # Number of store instructions
423system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
424system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
425system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
426system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
427system.cpu2.Branches 32221 # Number of branches fetched
428system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
429system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
430system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
431system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
432system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
433system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
434system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
435system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
436system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
437system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
438system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
439system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
440system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
441system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
442system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
443system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
444system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
445system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
446system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
447system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
448system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
449system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
450system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
451system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
452system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
453system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
454system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
455system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
456system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
457system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
458system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
459system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
460system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
461system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
462system.cpu2.op_class::total 167367 # Class of executed instruction
463system.cpu2.dcache.tags.replacements 0 # number of replacements
464system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
465system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
466system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
467system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
468system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
469system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
470system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
471system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
472system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
473system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
474system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
475system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
476system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
477system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
478system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
479system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
480system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
481system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
482system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
483system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
484system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
485system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
486system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
487system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
488system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
489system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
490system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
491system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
492system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
493system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
494system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
495system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
496system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
497system.cpu2.dcache.overall_misses::total 255 # number of overall misses
498system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
499system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
500system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
501system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
502system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
503system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
504system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
505system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
506system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
507system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
508system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
509system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
510system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
511system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
512system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
513system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
514system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
515system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
516system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
517system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
518system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
519system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
520system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
521system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
522system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
523system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
524system.cpu2.dcache.fast_writes 0 # number of fast writes performed
525system.cpu2.dcache.cache_copies 0 # number of cache copies performed
526system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
527system.cpu2.icache.tags.replacements 278 # number of replacements
528system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
529system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
530system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
531system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
532system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
533system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
534system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
535system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
536system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
537system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
538system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
539system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
540system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
541system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
542system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
543system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
544system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
545system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
546system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
547system.cpu2.icache.overall_hits::total 167009 # number of overall hits
548system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
549system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
550system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
551system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
552system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
553system.cpu2.icache.overall_misses::total 358 # number of overall misses
554system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
555system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
556system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
557system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
558system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
559system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
560system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
561system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
562system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
563system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
564system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
565system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
566system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
567system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
568system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
569system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
570system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
571system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
572system.cpu2.icache.fast_writes 0 # number of fast writes performed
573system.cpu2.icache.cache_copies 0 # number of cache copies performed
574system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
575system.cpu3.numCycles 173297 # number of cpu cycles simulated
576system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
577system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
578system.cpu3.committedInsts 167272 # Number of instructions committed
579system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
580system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
581system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
582system.cpu3.num_func_calls 633 # number of times a function call or return occured
583system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
584system.cpu3.num_int_insts 113295 # number of integer instructions
585system.cpu3.num_fp_insts 0 # number of float instructions
586system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
587system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
588system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
589system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
590system.cpu3.num_mem_refs 58510 # number of memory refs
591system.cpu3.num_load_insts 42344 # Number of load instructions
592system.cpu3.num_store_insts 16166 # Number of store instructions
593system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
594system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
595system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
596system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
597system.cpu3.Branches 32639 # Number of branches fetched
598system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
599system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
600system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
601system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
602system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
603system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction
604system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction
605system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction
606system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction
607system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction
608system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction
609system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction
610system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction
611system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction
612system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction
613system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction
614system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction
615system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction
616system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction
617system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction
618system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction
619system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction
620system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction
621system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction
622system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction
623system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction
624system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction
625system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
626system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
627system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
628system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
629system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
630system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
631system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
632system.cpu3.op_class::total 167304 # Class of executed instruction
633system.cpu3.dcache.tags.replacements 0 # number of replacements
634system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
635system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
636system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
637system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
638system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
639system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
640system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
641system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
642system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
643system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
644system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
645system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
646system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
647system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
648system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
649system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
650system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
651system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
652system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
653system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
654system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
655system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
656system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
657system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
658system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
659system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
660system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
661system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
662system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
663system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
664system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
665system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
666system.cpu3.dcache.overall_misses::total 260 # number of overall misses
667system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
668system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
669system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
670system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
671system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
672system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
673system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
674system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
675system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
676system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
677system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
678system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
679system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
680system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
681system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
682system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
683system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
684system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
685system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
686system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
687system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
688system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
689system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
690system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
691system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
692system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
693system.cpu3.dcache.fast_writes 0 # number of fast writes performed
694system.cpu3.dcache.cache_copies 0 # number of cache copies performed
695system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
696system.cpu3.icache.tags.replacements 279 # number of replacements
697system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
698system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
699system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
700system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
701system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
702system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
703system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
704system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
705system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
706system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
707system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
708system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
709system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
710system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
711system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
712system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
713system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
714system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
715system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
716system.cpu3.icache.overall_hits::total 166945 # number of overall hits
717system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
718system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
719system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
720system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
721system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
722system.cpu3.icache.overall_misses::total 359 # number of overall misses
723system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
724system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
725system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
726system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
727system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
728system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
729system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
730system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
731system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
732system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
733system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
734system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
735system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
736system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
738system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
739system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
740system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741system.cpu3.icache.fast_writes 0 # number of fast writes performed
742system.cpu3.icache.cache_copies 0 # number of cache copies performed
743system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
744system.l2c.tags.replacements 0 # number of replacements
745system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use

746system.l2c.tags.total_refs 2271 # Total number of references to valid blocks.

746system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.

747system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.

748system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks.

748system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks.

749system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
750system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
751system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
752system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor
753system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
754system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
755system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
756system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
757system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
758system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
759system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
760system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
761system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
762system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
763system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
764system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
765system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
766system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
767system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
768system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
769system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
770system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
771system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
772system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id

773system.l2c.tags.tag_accesses 23864 # Number of tag accesses
774system.l2c.tags.data_accesses 23864 # Number of data accesses

773system.l2c.tags.tag_accesses 19424 # Number of tag accesses
774system.l2c.tags.data_accesses 19424 # Number of data accesses

775system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
776system.l2c.Writeback_hits::total 1 # number of Writeback hits
777system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
778system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
779system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
780system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits
781system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits
782system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
783system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
784system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
785system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits
786system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
787system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
788system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
789system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
790system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
791system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
792system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
793system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
794system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
795system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
796system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
797system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
798system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
799system.l2c.overall_hits::cpu0.data 5 # number of overall hits
800system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
801system.l2c.overall_hits::cpu1.data 3 # number of overall hits
802system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
803system.l2c.overall_hits::cpu2.data 9 # number of overall hits
804system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
805system.l2c.overall_hits::cpu3.data 9 # number of overall hits
806system.l2c.overall_hits::total 1220 # number of overall hits
807system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
808system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
809system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
810system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
811system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
812system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
813system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
814system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
815system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
816system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
817system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses
818system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses
819system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses
820system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses
821system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses
822system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
823system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
824system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
825system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
826system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
827system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
828system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
829system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
830system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
831system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
832system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
833system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
834system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
835system.l2c.demand_misses::total 559 # number of demand (read+write) misses
836system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
837system.l2c.overall_misses::cpu0.data 165 # number of overall misses
838system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
839system.l2c.overall_misses::cpu1.data 20 # number of overall misses
840system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
841system.l2c.overall_misses::cpu2.data 13 # number of overall misses
842system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
843system.l2c.overall_misses::cpu3.data 13 # number of overall misses
844system.l2c.overall_misses::total 559 # number of overall misses
845system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
846system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
847system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
848system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
849system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
850system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
851system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
852system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
853system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
854system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
855system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
856system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
857system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
858system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses)
859system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses)
860system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses)
861system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses)
862system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
863system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses)
864system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses)
865system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses)
866system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
867system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
868system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
869system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
870system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
871system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
872system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
873system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
874system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
875system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
876system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
877system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
878system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
879system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
880system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
881system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
882system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
883system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
884system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
885system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
886system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
887system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
888system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
889system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
890system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
891system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
892system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
893system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
894system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
895system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses
896system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses
897system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses
898system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses
899system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses
900system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
901system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses
902system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses
903system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses
904system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses
905system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
906system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
907system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
908system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
909system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
910system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
911system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
912system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
913system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
914system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
915system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
916system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
917system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
918system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
919system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
920system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
921system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
922system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
923system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
924system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
925system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
926system.l2c.blocked::no_targets 0 # number of cycles access was blocked
927system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
928system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
929system.l2c.fast_writes 0 # number of fast writes performed
930system.l2c.cache_copies 0 # number of cache copies performed
931system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
932system.membus.trans_dist::ReadResp 423 # Transaction distribution
933system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
934system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
935system.membus.trans_dist::ReadExReq 412 # Transaction distribution
936system.membus.trans_dist::ReadExResp 136 # Transaction distribution
937system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
938system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes)
939system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes)
940system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
941system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
942system.membus.snoops 0 # Total snoops (count)
943system.membus.snoop_fanout::samples 1108 # Request fanout histogram
944system.membus.snoop_fanout::mean 0 # Request fanout histogram
945system.membus.snoop_fanout::stdev 0 # Request fanout histogram
946system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
947system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram
948system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
949system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
950system.membus.snoop_fanout::min_value 0 # Request fanout histogram
951system.membus.snoop_fanout::max_value 0 # Request fanout histogram
952system.membus.snoop_fanout::total 1108 # Request fanout histogram

953system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
954system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
955system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
956system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
957system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
958system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

953system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
954system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution

959system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
960system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution

955system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution

961system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution

956system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
957system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
958system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
959system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
960system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
961system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution

962system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
963system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
964system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
965system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
966system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
967system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution

962system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)

968system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)

963system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)

969system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)

964system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)

970system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes)

965system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)

971system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)

966system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)

972system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes)

967system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)

973system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)

968system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)

974system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes)

969system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)

975system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)

970system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)

976system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes)

971system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
972system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
973system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
974system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
975system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
976system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
977system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
978system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
979system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
980system.toL2Bus.snoops 0 # Total snoops (count)
981system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram

977system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
978system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
979system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
980system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
981system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
982system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
983system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes)
984system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
985system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
986system.toL2Bus.snoops 0 # Total snoops (count)
987system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram

982system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
983system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram

988system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
989system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram

984system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

990system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

985system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
986system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
987system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
988system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
989system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
990system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
991system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
992system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram

991system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram
992system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram
993system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram
994system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram
995system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
996system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
997system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
998system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram

993system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
994system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

999system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
1000system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

995system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
996system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram

1001system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1002system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram