Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

Deleted Added

sdiff udiff text old ( 10063:9595c7a1d837 ) new ( 10220:9eab5efc02e8 )

full compact

stats.txt (10063:9595c7a1d837)	stats.txt (10220:9eab5efc02e8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87707000 # Number of ticks simulated 5final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 202617 # Simulator instruction rate (inst/s) 8host_op_rate 202616 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26236566 # Simulator tick rate (ticks/s) 10host_mem_usage 297428 # Number of bytes of host memory used 11host_seconds 3.34 # Real time elapsed on the host	7host_inst_rate 1618143 # Simulator instruction rate (inst/s) 8host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 209518099 # Simulator tick rate (ticks/s) 10host_mem_usage 283888 # Number of bytes of host memory used 11host_seconds 0.42 # Real time elapsed on the host
12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 62system.membus.throughput 407903588 # Throughput (bytes/s) 63system.membus.data_through_bus 35776 # Total data (bytes) 64system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.l2c.tags.replacements 0 # number of replacements 67system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use 68system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 69system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 70system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 71system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 72system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 73system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 74system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 75system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 76system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 77system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 78system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 79system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 80system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor 81system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 82system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 83system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 84system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 85system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 86system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 87system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 88system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 89system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 90system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 91system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 92system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 93system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id 94system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id 95system.l2c.tags.tag_accesses 15488 # Number of tag accesses 96system.l2c.tags.data_accesses 15488 # Number of data accesses 97system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 98system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 99system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 100system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 101system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 102system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 103system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 104system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 105system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 106system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 107system.l2c.Writeback_hits::total 1 # number of Writeback hits 108system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 109system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 110system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 111system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 112system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 113system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 114system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 115system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 116system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 117system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 118system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 119system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 120system.l2c.overall_hits::cpu0.data 5 # number of overall hits 121system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 122system.l2c.overall_hits::cpu1.data 3 # number of overall hits 123system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 124system.l2c.overall_hits::cpu2.data 9 # number of overall hits 125system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 126system.l2c.overall_hits::cpu3.data 9 # number of overall hits 127system.l2c.overall_hits::total 1220 # number of overall hits 128system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 129system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 130system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 131system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 132system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 133system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 134system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 135system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 136system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 137system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 138system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 139system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 140system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 141system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses 142system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 143system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 144system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 145system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 146system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 147system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 148system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 149system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 150system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 151system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 152system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 153system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 154system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 155system.l2c.demand_misses::total 559 # number of demand (read+write) misses 156system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 157system.l2c.overall_misses::cpu0.data 165 # number of overall misses 158system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 159system.l2c.overall_misses::cpu1.data 20 # number of overall misses 160system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 161system.l2c.overall_misses::cpu2.data 13 # number of overall misses 162system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 163system.l2c.overall_misses::cpu3.data 13 # number of overall misses 164system.l2c.overall_misses::total 559 # number of overall misses 165system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 166system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 167system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 168system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 169system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 170system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 171system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 172system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 173system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 174system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 175system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 176system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 177system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 178system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 179system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 180system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) 181system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 182system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 183system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 184system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 185system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 186system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 187system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 188system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 189system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 190system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 191system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 192system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 193system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 194system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 195system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 196system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 197system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 198system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 199system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 200system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 201system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 202system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 203system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 204system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 205system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 206system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses 208system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 209system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses 210system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 211system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses 213system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 214system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 216system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 217system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses 218system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 220system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 221system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 222system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 223system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 227system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 228system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 229system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 230system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 231system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 232system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 236system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 237system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 238system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 239system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 240system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 241system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 242system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 244system.l2c.blocked::no_targets 0 # number of cycles access was blocked 245system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 246system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.l2c.fast_writes 0 # number of fast writes performed 248system.l2c.cache_copies 0 # number of cache copies performed 249system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 250system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) 251system.toL2Bus.data_through_bus 166080 # Total data (bytes) 252system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 253system.cpu0.workload.num_syscalls 89 # Number of system calls 254system.cpu0.numCycles 175415 # number of cpu cycles simulated 255system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 256system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 257system.cpu0.committedInsts 175326 # Number of instructions committed 258system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 259system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 260system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 261system.cpu0.num_func_calls 390 # number of times a function call or return occured 262system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 263system.cpu0.num_int_insts 120376 # number of integer instructions 264system.cpu0.num_fp_insts 0 # number of float instructions 265system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 266system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 267system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 268system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 269system.cpu0.num_mem_refs 82397 # number of memory refs 270system.cpu0.num_load_insts 54591 # Number of load instructions 271system.cpu0.num_store_insts 27806 # Number of store instructions 272system.cpu0.num_idle_cycles 0 # Number of idle cycles 273system.cpu0.num_busy_cycles 175415 # Number of busy cycles 274system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 275system.cpu0.idle_fraction 0 # Percentage of idle cycles 276system.cpu0.Branches 29689 # Number of branches fetched	12sim_insts 677327 # Number of instructions simulated 13sim_ops 677327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 35776 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 559 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 62system.membus.throughput 407903588 # Throughput (bytes/s) 63system.membus.data_through_bus 35776 # Total data (bytes) 64system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.l2c.tags.replacements 0 # number of replacements 67system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use 68system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. 69system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. 70system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. 71system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 72system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 73system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 74system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor 75system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor 76system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor 77system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor 78system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor 79system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor 80system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor 81system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 82system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 83system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 84system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 85system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 86system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 87system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 88system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 89system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 90system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy 91system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 92system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 93system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id 94system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id 95system.l2c.tags.tag_accesses 15488 # Number of tag accesses 96system.l2c.tags.data_accesses 15488 # Number of data accesses 97system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 98system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 99system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 100system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits 101system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 102system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits 103system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 104system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits 105system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits 106system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 107system.l2c.Writeback_hits::total 1 # number of Writeback hits 108system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 109system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 110system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 111system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 112system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 113system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 114system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 115system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 116system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 117system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 118system.l2c.demand_hits::total 1220 # number of demand (read+write) hits 119system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 120system.l2c.overall_hits::cpu0.data 5 # number of overall hits 121system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 122system.l2c.overall_hits::cpu1.data 3 # number of overall hits 123system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 124system.l2c.overall_hits::cpu2.data 9 # number of overall hits 125system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 126system.l2c.overall_hits::cpu3.data 9 # number of overall hits 127system.l2c.overall_hits::total 1220 # number of overall hits 128system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 129system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 130system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 131system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 132system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 133system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 134system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 135system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 136system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 137system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 138system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 139system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses 140system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 141system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses 142system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 143system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 144system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 145system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 146system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 147system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 148system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 149system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 150system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 151system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 152system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 153system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 154system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 155system.l2c.demand_misses::total 559 # number of demand (read+write) misses 156system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 157system.l2c.overall_misses::cpu0.data 165 # number of overall misses 158system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 159system.l2c.overall_misses::cpu1.data 20 # number of overall misses 160system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 161system.l2c.overall_misses::cpu2.data 13 # number of overall misses 162system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 163system.l2c.overall_misses::cpu3.data 13 # number of overall misses 164system.l2c.overall_misses::total 559 # number of overall misses 165system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 166system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 167system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 168system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) 169system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 170system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) 171system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 172system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) 173system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) 174system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 175system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 176system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 177system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 178system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) 179system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 180system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) 181system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 182system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 183system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 184system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 185system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 186system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 187system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 188system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 189system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 190system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 191system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 192system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 193system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 194system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 195system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 196system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 197system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 198system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 199system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 200system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 201system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 202system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 203system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 204system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 205system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 206system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses 208system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 209system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses 210system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 211system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses 213system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 214system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 216system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 217system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses 218system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 220system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 221system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 222system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 223system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 227system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 228system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 229system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 230system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 231system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 232system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 236system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 237system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 238system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 239system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 240system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 241system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 242system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 244system.l2c.blocked::no_targets 0 # number of cycles access was blocked 245system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 246system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.l2c.fast_writes 0 # number of fast writes performed 248system.l2c.cache_copies 0 # number of cache copies performed 249system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 250system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) 251system.toL2Bus.data_through_bus 166080 # Total data (bytes) 252system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 253system.cpu0.workload.num_syscalls 89 # Number of system calls 254system.cpu0.numCycles 175415 # number of cpu cycles simulated 255system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 256system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 257system.cpu0.committedInsts 175326 # Number of instructions committed 258system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 259system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 260system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 261system.cpu0.num_func_calls 390 # number of times a function call or return occured 262system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 263system.cpu0.num_int_insts 120376 # number of integer instructions 264system.cpu0.num_fp_insts 0 # number of float instructions 265system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 266system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 267system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 268system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 269system.cpu0.num_mem_refs 82397 # number of memory refs 270system.cpu0.num_load_insts 54591 # Number of load instructions 271system.cpu0.num_store_insts 27806 # Number of store instructions 272system.cpu0.num_idle_cycles 0 # Number of idle cycles 273system.cpu0.num_busy_cycles 175415 # Number of busy cycles 274system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 275system.cpu0.idle_fraction 0 # Percentage of idle cycles 276system.cpu0.Branches 29689 # Number of branches fetched
	277system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction 278system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction 279system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction 280system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction 281system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction 282system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction 283system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction 284system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction 285system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction 286system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction 287system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction 288system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction 289system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction 290system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction 291system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction 292system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction 293system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction 294system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction 295system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction 296system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction 297system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction 298system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction 299system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction 300system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction 301system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction 302system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction 303system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction 304system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction 305system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 306system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 307system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 308system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 309system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 310system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 311system.cpu0.op_class::total 175388 # Class of executed instruction
277system.cpu0.icache.tags.replacements 215 # number of replacements 278system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use 279system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 280system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 281system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 282system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 283system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor 284system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 285system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 286system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 287system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 288system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 289system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 290system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 291system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 292system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 293system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 294system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 295system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 296system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 297system.cpu0.icache.overall_hits::total 174921 # number of overall hits 298system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 299system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 300system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 301system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 302system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 303system.cpu0.icache.overall_misses::total 467 # number of overall misses 304system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 305system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 306system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 307system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 308system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 309system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 310system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 311system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 312system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 313system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 314system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 315system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 316system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 317system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 318system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 319system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 320system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 321system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 322system.cpu0.icache.fast_writes 0 # number of fast writes performed 323system.cpu0.icache.cache_copies 0 # number of cache copies performed 324system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.cpu0.dcache.tags.replacements 2 # number of replacements 326system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use 327system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. 328system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 329system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. 330system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 331system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor 332system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 333system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 334system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 335system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 336system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 337system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 338system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses 339system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses 340system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 341system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 342system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 343system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 344system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 345system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 346system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 347system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 348system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 349system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 350system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 351system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 352system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 353system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 354system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 355system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 356system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 357system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 358system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 359system.cpu0.dcache.overall_misses::total 328 # number of overall misses 360system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 361system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 362system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 363system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 364system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 365system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 366system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 374system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 375system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 376system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 377system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 378system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 379system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 380system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 381system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 382system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 383system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 384system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 385system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.cpu0.dcache.fast_writes 0 # number of fast writes performed 387system.cpu0.dcache.cache_copies 0 # number of cache copies performed 388system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 389system.cpu0.dcache.writebacks::total 1 # number of writebacks 390system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 391system.cpu1.numCycles 173295 # number of cpu cycles simulated 392system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu1.committedInsts 167398 # Number of instructions committed 395system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 396system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 397system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 398system.cpu1.num_func_calls 633 # number of times a function call or return occured 399system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 400system.cpu1.num_int_insts 109926 # number of integer instructions 401system.cpu1.num_fp_insts 0 # number of float instructions 402system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 403system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written 404system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 405system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 406system.cpu1.num_mem_refs 53394 # number of memory refs 407system.cpu1.num_load_insts 40652 # Number of load instructions 408system.cpu1.num_store_insts 12742 # Number of store instructions 409system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 410system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 411system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 412system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles 413system.cpu1.Branches 34390 # Number of branches fetched	312system.cpu0.icache.tags.replacements 215 # number of replacements 313system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use 314system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 315system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 316system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 317system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 318system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor 319system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 320system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 321system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 322system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 323system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 324system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 325system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 326system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 327system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 328system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 329system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 330system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 331system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 332system.cpu0.icache.overall_hits::total 174921 # number of overall hits 333system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 334system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 335system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 336system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 337system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 338system.cpu0.icache.overall_misses::total 467 # number of overall misses 339system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 340system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 341system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 342system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 343system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 344system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 345system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 346system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 347system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 348system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 349system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 350system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 351system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 352system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 353system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 354system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 355system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 356system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 357system.cpu0.icache.fast_writes 0 # number of fast writes performed 358system.cpu0.icache.cache_copies 0 # number of cache copies performed 359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 360system.cpu0.dcache.tags.replacements 2 # number of replacements 361system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use 362system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. 363system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 364system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. 365system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 366system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor 367system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 368system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 369system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 370system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 371system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 372system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 373system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses 374system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses 375system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 376system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 377system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 378system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 379system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 380system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 381system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 382system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 383system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 384system.cpu0.dcache.overall_hits::total 82008 # number of overall hits 385system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 386system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 387system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 388system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 389system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 390system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 391system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 392system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 393system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 394system.cpu0.dcache.overall_misses::total 328 # number of overall misses 395system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 396system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 397system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 398system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 399system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 400system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 401system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 402system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 403system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 404system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 405system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 406system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 407system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 408system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 409system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 410system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 411system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 412system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 413system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 414system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 415system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu0.dcache.fast_writes 0 # number of fast writes performed 422system.cpu0.dcache.cache_copies 0 # number of cache copies performed 423system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 424system.cpu0.dcache.writebacks::total 1 # number of writebacks 425system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 426system.cpu1.numCycles 173295 # number of cpu cycles simulated 427system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 428system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 429system.cpu1.committedInsts 167398 # Number of instructions committed 430system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 431system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 432system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 433system.cpu1.num_func_calls 633 # number of times a function call or return occured 434system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 435system.cpu1.num_int_insts 109926 # number of integer instructions 436system.cpu1.num_fp_insts 0 # number of float instructions 437system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 438system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written 439system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 440system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 441system.cpu1.num_mem_refs 53394 # number of memory refs 442system.cpu1.num_load_insts 40652 # Number of load instructions 443system.cpu1.num_store_insts 12742 # Number of store instructions 444system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles 445system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles 446system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles 447system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles 448system.cpu1.Branches 34390 # Number of branches fetched
	449system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction 450system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction 451system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 452system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 453system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 454system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 455system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 456system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 457system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 458system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 459system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 460system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 461system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 462system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 463system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 464system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 465system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 466system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 467system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 468system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 469system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 470system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 471system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 472system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 473system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 474system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 475system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 476system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 477system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 478system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 479system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction 480system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction 481system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 482system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 483system.cpu1.op_class::total 167430 # Class of executed instruction
414system.cpu1.icache.tags.replacements 278 # number of replacements 415system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use 416system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. 417system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 418system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. 419system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 420system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 421system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy 422system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy 423system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 424system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 425system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 426system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 427system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses 428system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses 429system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 430system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 431system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 432system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 433system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 434system.cpu1.icache.overall_hits::total 167072 # number of overall hits 435system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 436system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 437system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 438system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 439system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 440system.cpu1.icache.overall_misses::total 358 # number of overall misses 441system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 442system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 443system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 444system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 445system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 446system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 447system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 448system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 449system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 450system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 451system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 452system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 453system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu1.icache.fast_writes 0 # number of fast writes performed 460system.cpu1.icache.cache_copies 0 # number of cache copies performed 461system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 462system.cpu1.dcache.tags.replacements 0 # number of replacements 463system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use 464system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. 465system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 466system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. 467system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 468system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 469system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy 470system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy 471system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 472system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 473system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 474system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses 475system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses 476system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 477system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 478system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 479system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 480system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 481system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 482system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 483system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits 484system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits 485system.cpu1.dcache.overall_hits::total 53033 # number of overall hits 486system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses 487system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses 488system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 489system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 490system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 491system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 492system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses 493system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses 494system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses 495system.cpu1.dcache.overall_misses::total 280 # number of overall misses 496system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 497system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 498system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 499system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 500system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 501system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 502system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 503system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 504system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 505system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 506system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses 507system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses 508system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 509system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 510system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 511system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 512system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses 513system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses 514system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses 515system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses 516system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 517system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 518system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 519system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 520system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 521system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.cpu1.dcache.fast_writes 0 # number of fast writes performed 523system.cpu1.dcache.cache_copies 0 # number of cache copies performed 524system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 525system.cpu2.numCycles 173295 # number of cpu cycles simulated 526system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 528system.cpu2.committedInsts 167334 # Number of instructions committed 529system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 530system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 531system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 532system.cpu2.num_func_calls 633 # number of times a function call or return occured 533system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 534system.cpu2.num_int_insts 113333 # number of integer instructions 535system.cpu2.num_fp_insts 0 # number of float instructions 536system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 537system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written 538system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 539system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 540system.cpu2.num_mem_refs 58537 # number of memory refs 541system.cpu2.num_load_insts 42362 # Number of load instructions 542system.cpu2.num_store_insts 16175 # Number of store instructions 543system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 544system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles 545system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 546system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 547system.cpu2.Branches 32652 # Number of branches fetched	484system.cpu1.icache.tags.replacements 278 # number of replacements 485system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use 486system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. 487system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 488system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. 489system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 490system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor 491system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy 492system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy 493system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 494system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 495system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 496system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 497system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses 498system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses 499system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 500system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 501system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 502system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 503system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 504system.cpu1.icache.overall_hits::total 167072 # number of overall hits 505system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 506system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 507system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 508system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 509system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 510system.cpu1.icache.overall_misses::total 358 # number of overall misses 511system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 512system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 513system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 514system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 515system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 516system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 517system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 518system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 519system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 520system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 521system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 522system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 523system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu1.icache.fast_writes 0 # number of fast writes performed 530system.cpu1.icache.cache_copies 0 # number of cache copies performed 531system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu1.dcache.tags.replacements 0 # number of replacements 533system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use 534system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. 535system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 536system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. 537system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 538system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor 539system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy 540system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy 541system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 542system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 543system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 544system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses 545system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses 546system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits 547system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits 548system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 549system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 550system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 551system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 552system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits 553system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits 554system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits 555system.cpu1.dcache.overall_hits::total 53033 # number of overall hits 556system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses 557system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses 558system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 559system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 560system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 561system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 562system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses 563system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses 564system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses 565system.cpu1.dcache.overall_misses::total 280 # number of overall misses 566system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 567system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 568system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 569system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 570system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 571system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 572system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 573system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 574system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 575system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 576system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses 577system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses 578system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 579system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses 580system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 581system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 582system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses 583system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses 584system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses 585system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses 586system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu1.dcache.fast_writes 0 # number of fast writes performed 593system.cpu1.dcache.cache_copies 0 # number of cache copies performed 594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu2.numCycles 173295 # number of cpu cycles simulated 596system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 597system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 598system.cpu2.committedInsts 167334 # Number of instructions committed 599system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 600system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 601system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 602system.cpu2.num_func_calls 633 # number of times a function call or return occured 603system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 604system.cpu2.num_int_insts 113333 # number of integer instructions 605system.cpu2.num_fp_insts 0 # number of float instructions 606system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 607system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written 608system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 609system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 610system.cpu2.num_mem_refs 58537 # number of memory refs 611system.cpu2.num_load_insts 42362 # Number of load instructions 612system.cpu2.num_store_insts 16175 # Number of store instructions 613system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles 614system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles 615system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 616system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 617system.cpu2.Branches 32652 # Number of branches fetched
	618system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction 619system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction 620system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 621system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 622system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 623system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 624system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 625system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 626system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 627system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 628system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 629system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 630system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 631system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 632system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 633system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 634system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 635system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 636system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 637system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 638system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 639system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 640system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 641system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 642system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 643system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 644system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 645system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 646system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 647system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 648system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction 649system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction 650system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 651system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 652system.cpu2.op_class::total 167366 # Class of executed instruction
548system.cpu2.icache.tags.replacements 278 # number of replacements 549system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use 550system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. 551system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 552system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. 553system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 554system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 555system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy 556system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy 557system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 558system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 559system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 560system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 561system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses 562system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses 563system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 564system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 565system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 566system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 567system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 568system.cpu2.icache.overall_hits::total 167008 # number of overall hits 569system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 570system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 571system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 572system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 573system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 574system.cpu2.icache.overall_misses::total 358 # number of overall misses 575system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 576system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 577system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 578system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 579system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 580system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 581system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 582system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 583system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 584system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 585system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 586system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 587system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 593system.cpu2.icache.fast_writes 0 # number of fast writes performed 594system.cpu2.icache.cache_copies 0 # number of cache copies performed 595system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 596system.cpu2.dcache.tags.replacements 0 # number of replacements 597system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use 598system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. 599system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 600system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. 601system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 602system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 603system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy 604system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy 605system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 606system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 607system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 608system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses 609system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses 610system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 611system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 612system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 613system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 614system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 615system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 616system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 617system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits 618system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits 619system.cpu2.dcache.overall_hits::total 58192 # number of overall hits 620system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses 621system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses 622system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 623system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 624system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 625system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 626system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 627system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 628system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 629system.cpu2.dcache.overall_misses::total 269 # number of overall misses 630system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 631system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 632system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 633system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 634system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 635system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 636system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 637system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 638system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 639system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 640system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses 641system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses 642system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 643system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 644system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 645system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 646system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses 647system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses 648system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses 649system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses 650system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu2.dcache.fast_writes 0 # number of fast writes performed 657system.cpu2.dcache.cache_copies 0 # number of cache copies performed 658system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu3.numCycles 173294 # number of cpu cycles simulated 660system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 661system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 662system.cpu3.committedInsts 167269 # Number of instructions committed 663system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 664system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 665system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 666system.cpu3.num_func_calls 633 # number of times a function call or return occured 667system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 668system.cpu3.num_int_insts 111554 # number of integer instructions 669system.cpu3.num_fp_insts 0 # number of float instructions 670system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 671system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written 672system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 673system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 674system.cpu3.num_mem_refs 55900 # number of memory refs 675system.cpu3.num_load_insts 41466 # Number of load instructions 676system.cpu3.num_store_insts 14434 # Number of store instructions 677system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 678system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 679system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 680system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles 681system.cpu3.Branches 33511 # Number of branches fetched	653system.cpu2.icache.tags.replacements 278 # number of replacements 654system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use 655system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. 656system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 657system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. 658system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 659system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor 660system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy 661system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy 662system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 663system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 664system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 665system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 666system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses 667system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses 668system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 669system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 670system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 671system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 672system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 673system.cpu2.icache.overall_hits::total 167008 # number of overall hits 674system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 675system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 676system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 677system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 678system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 679system.cpu2.icache.overall_misses::total 358 # number of overall misses 680system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 681system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 682system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 683system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 684system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 685system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 686system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 687system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 688system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 689system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 690system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 691system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 692system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 693system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 694system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 695system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 696system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 697system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 698system.cpu2.icache.fast_writes 0 # number of fast writes performed 699system.cpu2.icache.cache_copies 0 # number of cache copies performed 700system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 701system.cpu2.dcache.tags.replacements 0 # number of replacements 702system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use 703system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. 704system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 705system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. 706system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 707system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor 708system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy 709system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy 710system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 711system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 712system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 713system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses 714system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses 715system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits 716system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits 717system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 718system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 719system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 720system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 721system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits 722system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits 723system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits 724system.cpu2.dcache.overall_hits::total 58192 # number of overall hits 725system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses 726system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses 727system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 728system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 729system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 730system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 731system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses 732system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses 733system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses 734system.cpu2.dcache.overall_misses::total 269 # number of overall misses 735system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 736system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 737system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 738system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 739system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 740system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 741system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 742system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 743system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 744system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 745system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses 746system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses 747system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 748system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses 749system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 750system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses 751system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses 752system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses 753system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses 754system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses 755system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu2.dcache.fast_writes 0 # number of fast writes performed 762system.cpu2.dcache.cache_copies 0 # number of cache copies performed 763system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 764system.cpu3.numCycles 173294 # number of cpu cycles simulated 765system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 766system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 767system.cpu3.committedInsts 167269 # Number of instructions committed 768system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 769system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 770system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 771system.cpu3.num_func_calls 633 # number of times a function call or return occured 772system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 773system.cpu3.num_int_insts 111554 # number of integer instructions 774system.cpu3.num_fp_insts 0 # number of float instructions 775system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 776system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written 777system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 778system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 779system.cpu3.num_mem_refs 55900 # number of memory refs 780system.cpu3.num_load_insts 41466 # Number of load instructions 781system.cpu3.num_store_insts 14434 # Number of store instructions 782system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles 783system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles 784system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles 785system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles 786system.cpu3.Branches 33511 # Number of branches fetched
	787system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction 788system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction 789system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 790system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 791system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 792system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 793system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 794system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 795system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 796system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction 797system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction 798system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction 799system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction 800system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction 801system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction 802system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction 803system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction 804system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction 805system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction 806system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction 807system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction 808system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction 809system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 810system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 811system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 812system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 813system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 814system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 815system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 816system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction 817system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction 818system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction 819system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 820system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 821system.cpu3.op_class::total 167301 # Class of executed instruction
682system.cpu3.icache.tags.replacements 279 # number of replacements 683system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use 684system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. 685system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 686system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. 687system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 688system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 689system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy 690system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy 691system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 692system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 693system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 694system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 695system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses 696system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses 697system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 698system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 699system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 700system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 701system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 702system.cpu3.icache.overall_hits::total 166942 # number of overall hits 703system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 704system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 705system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 706system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 707system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 708system.cpu3.icache.overall_misses::total 359 # number of overall misses 709system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 710system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 711system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 712system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 713system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 714system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 715system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 716system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 717system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 718system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 719system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 720system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 721system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 725system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu3.icache.fast_writes 0 # number of fast writes performed 728system.cpu3.icache.cache_copies 0 # number of cache copies performed 729system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 730system.cpu3.dcache.tags.replacements 0 # number of replacements 731system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use 732system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. 733system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 734system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. 735system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 736system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 737system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy 738system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy 739system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 740system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 741system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 742system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 743system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses 744system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses 745system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 746system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 747system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 748system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 749system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 750system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 751system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 752system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits 753system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits 754system.cpu3.dcache.overall_hits::total 55561 # number of overall hits 755system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 756system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 757system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 758system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 759system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 760system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 761system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses 762system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses 763system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses 764system.cpu3.dcache.overall_misses::total 259 # number of overall misses 765system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 766system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 767system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 768system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 769system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 770system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 771system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 772system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 773system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 774system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 775system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses 776system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses 777system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 778system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 779system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 780system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 781system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses 782system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses 783system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses 784system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses 785system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 786system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 787system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 788system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 789system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 790system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 791system.cpu3.dcache.fast_writes 0 # number of fast writes performed 792system.cpu3.dcache.cache_copies 0 # number of cache copies performed 793system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 794 795---------- End Simulation Statistics ----------	822system.cpu3.icache.tags.replacements 279 # number of replacements 823system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use 824system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. 825system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 826system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. 827system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 828system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor 829system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy 830system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy 831system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 832system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 833system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 834system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 835system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses 836system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses 837system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 838system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 839system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 840system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 841system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 842system.cpu3.icache.overall_hits::total 166942 # number of overall hits 843system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 844system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 845system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 846system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 847system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 848system.cpu3.icache.overall_misses::total 359 # number of overall misses 849system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 850system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 851system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 852system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 853system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 854system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 855system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 856system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 857system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 858system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 859system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 860system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 861system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 867system.cpu3.icache.fast_writes 0 # number of fast writes performed 868system.cpu3.icache.cache_copies 0 # number of cache copies performed 869system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 870system.cpu3.dcache.tags.replacements 0 # number of replacements 871system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use 872system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. 873system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 874system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. 875system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 876system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor 877system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy 878system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy 879system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 880system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 881system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 882system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 883system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses 884system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses 885system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits 886system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits 887system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 888system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 889system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 890system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 891system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits 892system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits 893system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits 894system.cpu3.dcache.overall_hits::total 55561 # number of overall hits 895system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses 896system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses 897system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 898system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 899system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 900system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 901system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses 902system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses 903system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses 904system.cpu3.dcache.overall_misses::total 259 # number of overall misses 905system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 906system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 907system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 908system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 909system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 910system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 911system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 912system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 913system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 914system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 915system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses 916system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses 917system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 918system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses 919system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 920system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 921system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses 922system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses 923system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses 924system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses 925system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 926system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 927system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 928system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 929system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 930system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 931system.cpu3.dcache.fast_writes 0 # number of fast writes performed 932system.cpu3.dcache.cache_copies 0 # number of cache copies performed 933system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 934 935---------- End Simulation Statistics ----------