19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[2]
---
> system_port=system.membus.slave[1]
41a41
> fastmem=false
65c65
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
86c86
< mem_side=system.toL2Bus.port[2]
---
> mem_side=system.toL2Bus.slave[1]
94c94
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
115c115
< mem_side=system.toL2Bus.port[1]
---
> mem_side=system.toL2Bus.slave[0]
156a157
> fastmem=false
180c181
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
201c202
< mem_side=system.toL2Bus.port[4]
---
> mem_side=system.toL2Bus.slave[3]
209c210
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
230c231
< mem_side=system.toL2Bus.port[3]
---
> mem_side=system.toL2Bus.slave[2]
252a254
> fastmem=false
276c278
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
297c299
< mem_side=system.toL2Bus.port[6]
---
> mem_side=system.toL2Bus.slave[5]
305c307
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
326c328
< mem_side=system.toL2Bus.port[5]
---
> mem_side=system.toL2Bus.slave[4]
348a351
> fastmem=false
372c375
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
393c396
< mem_side=system.toL2Bus.port[8]
---
> mem_side=system.toL2Bus.slave[7]
401c404
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
422c425
< mem_side=system.toL2Bus.port[7]
---
> mem_side=system.toL2Bus.slave[6]
436c439
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
456,457c459,460
< cpu_side=system.toL2Bus.port[0]
< mem_side=system.membus.port[0]
---
> cpu_side=system.toL2Bus.master[0]
> mem_side=system.membus.slave[0]
467c470,471
< port=system.l2c.mem_side system.physmem.port[0] system.system_port
---
> master=system.physmem.port[0]
> slave=system.l2c.mem_side system.system_port
470c474,475
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
471a477
> in_addr_map=true
477c483
< port=system.membus.port[1]
---
> port=system.membus.master[0]
487c493,494
< port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
---
> master=system.l2c.cpu_side
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side