| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 111025500 # Number of ticks simulated 5final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 111025500 # Number of ticks simulated 5final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 119782 # Simulator instruction rate (inst/s) 8host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12747983 # Simulator tick rate (ticks/s) 10host_mem_usage 275656 # Number of bytes of host memory used 11host_seconds 8.71 # Real time elapsed on the host | 7host_inst_rate 77886 # Simulator instruction rate (inst/s) 8host_op_rate 77886 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8289137 # Simulator tick rate (ticks/s) 10host_mem_usage 295244 # Number of bytes of host memory used 11host_seconds 13.39 # Real time elapsed on the host |
| 12sim_insts 1043212 # Number of instructions simulated 13sim_ops 1043212 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 179 unchanged lines hidden (view full) --- 199system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation | 12sim_insts 1043212 # Number of instructions simulated 13sim_ops 1043212 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 179 unchanged lines hidden (view full) --- 199system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation |
| 207system.physmem.totQLat 4010250 # Total ticks spent queuing 208system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM | 207system.physmem.totQLat 4008250 # Total ticks spent queuing 208system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM |
| 209system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers 210system.physmem.totBankLat 10848750 # Total ticks spent accessing banks | 209system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers 210system.physmem.totBankLat 10848750 # Total ticks spent accessing banks |
| 211system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst | 211system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst |
| 212system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst 213system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 212system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst 213system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 214system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst | 214system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst |
| 215system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s 216system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 217system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s 218system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 219system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 220system.physmem.busUtil 2.97 # Data bus utilization in percentage 221system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 222system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 14 unchanged lines hidden (view full) --- 237system.membus.trans_dist::ReadExReq 164 # Transaction distribution 238system.membus.trans_dist::ReadExResp 131 # Transaction distribution 239system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) 240system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) 241system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 242system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 243system.membus.data_through_bus 42176 # Total data (bytes) 244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 215system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s 216system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 217system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s 218system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 219system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 220system.physmem.busUtil 2.97 # Data bus utilization in percentage 221system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 222system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 14 unchanged lines hidden (view full) --- 237system.membus.trans_dist::ReadExReq 164 # Transaction distribution 238system.membus.trans_dist::ReadExResp 131 # Transaction distribution 239system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) 240system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) 241system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 242system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 243system.membus.data_through_bus 42176 # Total data (bytes) 244system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 245system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) | 245system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks) |
| 246system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) | 246system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 247system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) | 247system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) |
| 248system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 249system.l2c.tags.replacements 0 # number of replacements | 248system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 249system.l2c.tags.replacements 0 # number of replacements |
| 250system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use | 250system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use |
| 251system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. 252system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 253system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. 254system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 255system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor | 251system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. 252system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 253system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. 254system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 255system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor |
| 256system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor 257system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor | 256system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor 257system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor |
| 258system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor 259system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor 260system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor 261system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor 262system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor 263system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor 264system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 265system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy --- 68 unchanged lines hidden (view full) --- 334system.l2c.overall_misses::cpu0.data 168 # number of overall misses 335system.l2c.overall_misses::cpu1.inst 16 # number of overall misses 336system.l2c.overall_misses::cpu1.data 13 # number of overall misses 337system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 338system.l2c.overall_misses::cpu2.data 20 # number of overall misses 339system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 340system.l2c.overall_misses::cpu3.data 13 # number of overall misses 341system.l2c.overall_misses::total 674 # number of overall misses | 258system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor 259system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor 260system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor 261system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor 262system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor 263system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor 264system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 265system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy --- 68 unchanged lines hidden (view full) --- 334system.l2c.overall_misses::cpu0.data 168 # number of overall misses 335system.l2c.overall_misses::cpu1.inst 16 # number of overall misses 336system.l2c.overall_misses::cpu1.data 13 # number of overall misses 337system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 338system.l2c.overall_misses::cpu2.data 20 # number of overall misses 339system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 340system.l2c.overall_misses::cpu3.data 13 # number of overall misses 341system.l2c.overall_misses::total 674 # number of overall misses |
| 342system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles | 342system.l2c.ReadReq_miss_latency::cpu0.inst 24802000 # number of ReadReq miss cycles |
| 343system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles 344system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles 345system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles 346system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles 347system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles | 343system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles 344system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles 345system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles 346system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles 347system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles |
| 348system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles | 348system.l2c.ReadReq_miss_latency::cpu3.inst 583750 # number of ReadReq miss cycles |
| 349system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles 350system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles 351system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles 352system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles | 349system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles 350system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles 351system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles 352system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles |
| 354system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles 356system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles | 354system.l2c.ReadExReq_miss_latency::cpu3.data 957750 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 9622000 # number of ReadExReq miss cycles 356system.l2c.demand_miss_latency::cpu0.inst 24802000 # number of demand (read+write) miss cycles |
| 357system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles 360system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles 361system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles | 357system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles 360system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles 361system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles |
| 362system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles 364system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles 365system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles | 362system.l2c.demand_miss_latency::cpu3.inst 583750 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::cpu3.data 1032250 # number of demand (read+write) miss cycles 364system.l2c.demand_miss_latency::total 47788000 # number of demand (read+write) miss cycles 365system.l2c.overall_miss_latency::cpu0.inst 24802000 # number of overall miss cycles |
| 366system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles 368system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles 369system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles | 366system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles 368system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles 369system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles |
| 371system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles 372system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles 373system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles | 371system.l2c.overall_miss_latency::cpu3.inst 583750 # number of overall miss cycles 372system.l2c.overall_miss_latency::cpu3.data 1032250 # number of overall miss cycles 373system.l2c.overall_miss_latency::total 47788000 # number of overall miss cycles |
| 374system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) 381system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 442system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 443system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses 444system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 445system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 446system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 447system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses 448system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 449system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses | 374system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) 381system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 442system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 443system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses 444system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 445system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 446system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 447system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses 448system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 449system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses |
| 450system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency | 450system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975 # average ReadReq miss latency |
| 451system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency 452system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency 453system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency 454system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency 455system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency | 451system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency 452system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency 453system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency 454system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency 455system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency |
| 456system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency | 456system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111 # average ReadReq miss latency |
| 457system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency 458system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency 460system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency 461system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency | 457system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency 458system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency 460system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency 461system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency |
| 462system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency 463system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency 464system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency | 462system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000 # average ReadExReq miss latency 463system.l2c.ReadExReq_avg_miss_latency::total 73450.381679 # average ReadExReq miss latency 464system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency |
| 465system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency 467system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency 468system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency 469system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency | 465system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency 467system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency 468system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency 469system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency |
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| 644system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency 646system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency 647system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 648system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency 649system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency | 644system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency 646system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency 647system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 648system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency 649system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency |
| 650system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency 651system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency 652system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency | 650system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency 651system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency 652system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency |
| 653system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 654system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) 655system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution 656system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution 657system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 658system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution 659system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution 660system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution --- 44 unchanged lines hidden (view full) --- 705system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 706system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage 707system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 708system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 709system.cpu0.workload.num_syscalls 89 # Number of system calls 710system.cpu0.numCycles 222052 # number of cpu cycles simulated 711system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 712system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 653system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 654system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) 655system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution 656system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution 657system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 658system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution 659system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution 660system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution --- 44 unchanged lines hidden (view full) --- 705system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 706system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage 707system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 708system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 709system.cpu0.workload.num_syscalls 89 # Number of system calls 710system.cpu0.numCycles 222052 # number of cpu cycles simulated 711system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 712system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 713system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss | 713system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss |
| 714system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed 715system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered 716system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken 717system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked 718system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing 719system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked 720system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 721system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 722system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched | 714system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed 715system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered 716system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken 717system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked 718system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing 719system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked 720system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 721system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 722system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched |
| 723system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed 724system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) 725system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) 726system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) | 723system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed 724system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total) 725system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total) 726system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total) |
| 727system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 727system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 728system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) | 728system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total) |
| 729system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) 730system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) 731system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) 732system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) 733system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) 734system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 729system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) 730system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) 731system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) 732system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) 733system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) 734system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 740system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) | 740system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total) |
| 741system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle 742system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle | 741system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle 742system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle |
| 743system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle | 743system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle |
| 744system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked 745system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running 746system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking 747system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing 748system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode 749system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing | 744system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked 745system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running 746system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking 747system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing 748system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode 749system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing |
| 750system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle | 750system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle |
| 751system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking 752system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst 753system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running 754system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking 755system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename 756system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 757system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full 758system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed --- 5 unchanged lines hidden (view full) --- 764system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed 765system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer 766system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. 767system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. 768system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. 769system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. 770system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) 771system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ | 751system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking 752system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst 753system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running 754system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking 755system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename 756system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 757system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full 758system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed --- 5 unchanged lines hidden (view full) --- 764system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed 765system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer 766system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. 767system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. 768system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. 769system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. 770system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) 771system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ |
| 772system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued 773system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued | 772system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued 773system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued |
| 774system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling | 774system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 775system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph | 775system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph |
| 776system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed | 776system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed |
| 777system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle 778system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle 779system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle | 777system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle 778system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle 779system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle |
| 780system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 780system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 781system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle | 781system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle |
| 782system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle 783system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle | 782system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle 783system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle |
| 784system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle 785system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle | 784system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle 785system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle |
| 786system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle 787system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle 788system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 789system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 790system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 791system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 792system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 786system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle 787system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle 788system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 789system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 790system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 791system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 792system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 793system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle | 793system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle |
| 794system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 795system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available 796system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available 797system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available 798system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available 799system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available 800system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available 801system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available --- 48 unchanged lines hidden (view full) --- 850system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued 851system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued 852system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued 853system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued | 794system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 795system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available 796system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available 797system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available 798system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available 799system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available 800system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available 801system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available --- 48 unchanged lines hidden (view full) --- 850system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued 851system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued 852system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued 853system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued |
| 858system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued | 858system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued |
| 859system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued 860system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 861system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 859system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued 860system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 861system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 862system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued 863system.cpu0.iq.rate 1.824118 # Inst issue rate | 862system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued 863system.cpu0.iq.rate 1.824095 # Inst issue rate |
| 864system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested 865system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) | 864system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested 865system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) |
| 866system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads | 866system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads |
| 867system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes | 867system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes |
| 868system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses | 868system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses |
| 869system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 870system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 871system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 869system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 870system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 871system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 872system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses | 872system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses |
| 873system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 874system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores 875system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 876system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed 877system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 878system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 879system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 880system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 893system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall 894system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 895system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations 896system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly 897system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly 898system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute 899system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions 900system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed | 873system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 874system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores 875system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 876system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed 877system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 878system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 879system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 880system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 893system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall 894system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 895system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations 896system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly 897system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly 898system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute 899system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions 900system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed |
| 901system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute | 901system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute |
| 902system.cpu0.iew.exec_swp 0 # number of swp insts executed 903system.cpu0.iew.exec_nop 76577 # number of nop insts executed 904system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed 905system.cpu0.iew.exec_branches 80250 # Number of branches executed 906system.cpu0.iew.exec_stores 78134 # Number of stores executed 907system.cpu0.iew.exec_rate 1.819295 # Inst execution rate | 902system.cpu0.iew.exec_swp 0 # number of swp insts executed 903system.cpu0.iew.exec_nop 76577 # number of nop insts executed 904system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed 905system.cpu0.iew.exec_branches 80250 # Number of branches executed 906system.cpu0.iew.exec_stores 78134 # Number of stores executed 907system.cpu0.iew.exec_rate 1.819295 # Inst execution rate |
| 908system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit 909system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back 910system.cpu0.iew.wb_producers 238895 # num instructions producing a value 911system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value | 908system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit 909system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back 910system.cpu0.iew.wb_producers 238890 # num instructions producing a value 911system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value |
| 912system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 912system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 913system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle | 913system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle |
| 914system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back 915system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 916system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit 917system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 918system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted | 914system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back 915system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 916system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit 917system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 918system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted |
| 919system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle 920system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle 921system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle | 919system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle 920system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle 921system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle |
| 922system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 922system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 923system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle | 923system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle |
| 924system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle 925system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle 926system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle 927system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle 928system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle 929system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle 930system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle 931system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle 932system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 933system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 934system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 924system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle 925system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle 926system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle 927system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle 928system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle 929system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle 930system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle 931system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle 932system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 933system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 934system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 935system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle | 935system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle |
| 936system.cpu0.commit.committedInsts 472968 # Number of instructions committed 937system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed 938system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 939system.cpu0.commit.refs 231199 # Number of memory references committed 940system.cpu0.commit.loads 153795 # Number of loads committed 941system.cpu0.commit.membars 84 # Number of memory barriers committed 942system.cpu0.commit.branches 79291 # Number of branches committed 943system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 944system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. 945system.cpu0.commit.function_calls 223 # Number of function calls committed. 946system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached 947system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 936system.cpu0.commit.committedInsts 472968 # Number of instructions committed 937system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed 938system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 939system.cpu0.commit.refs 231199 # Number of memory references committed 940system.cpu0.commit.loads 153795 # Number of loads committed 941system.cpu0.commit.membars 84 # Number of memory barriers committed 942system.cpu0.commit.branches 79291 # Number of branches committed 943system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 944system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. 945system.cpu0.commit.function_calls 223 # Number of function calls committed. 946system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached 947system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 948system.cpu0.rob.rob_reads 678234 # The number of ROB reads | 948system.cpu0.rob.rob_reads 678235 # The number of ROB reads |
| 949system.cpu0.rob.rob_writes 972657 # The number of ROB writes 950system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself | 949system.cpu0.rob.rob_writes 972657 # The number of ROB writes 950system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 951system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling | 951system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 952system.cpu0.committedInsts 396861 # Number of Instructions Simulated 953system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated 954system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated 955system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction 956system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads 957system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle 958system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads 959system.cpu0.int_regfile_reads 722661 # number of integer regfile reads | 952system.cpu0.committedInsts 396861 # Number of Instructions Simulated 953system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated 954system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated 955system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction 956system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads 957system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle 958system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads 959system.cpu0.int_regfile_reads 722661 # number of integer regfile reads |
| 960system.cpu0.int_regfile_writes 325773 # number of integer regfile writes | 960system.cpu0.int_regfile_writes 325753 # number of integer regfile writes |
| 961system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 962system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads 963system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 964system.cpu0.icache.tags.replacements 297 # number of replacements | 961system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 962system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads 963system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 964system.cpu0.icache.tags.replacements 297 # number of replacements |
| 965system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use | 965system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use |
| 966system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. 967system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 968system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. 969system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 966system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. 967system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 968system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. 969system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 970system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor 971system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy 972system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy | 970system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor 971system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy 972system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy |
| 973system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits 974system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits 975system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits 976system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits 977system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits 978system.cpu0.icache.overall_hits::total 5113 # number of overall hits 979system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 980system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 981system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 982system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 983system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 984system.cpu0.icache.overall_misses::total 756 # number of overall misses | 973system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits 974system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits 975system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits 976system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits 977system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits 978system.cpu0.icache.overall_hits::total 5113 # number of overall hits 979system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 980system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 981system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 982system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 983system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 984system.cpu0.icache.overall_misses::total 756 # number of overall misses |
| 985system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles 986system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles 987system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles 988system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles 989system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles 990system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles | 985system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles 986system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles 987system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles 988system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles 989system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles 990system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles |
| 991system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) 992system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) 993system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses 994system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses 995system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses 996system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses 997system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses 998system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses 999system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses 1000system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses 1001system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses 1002system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses | 991system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) 992system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) 993system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses 994system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses 995system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses 996system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses 997system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses 998system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses 999system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses 1000system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses 1001system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses 1002system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses |
| 1003system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency 1004system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency 1005system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency 1006system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency 1007system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency 1008system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency | 1003system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency 1004system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency 1005system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency 1006system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency 1007system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency 1008system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency |
| 1009system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1010system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1011system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1012system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1013system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1014system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1015system.cpu0.icache.fast_writes 0 # number of fast writes performed 1016system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1021system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1022system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1023system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1024system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1025system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1026system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1027system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1028system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses | 1009system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1010system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1011system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1012system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1013system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1014system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1015system.cpu0.icache.fast_writes 0 # number of fast writes performed 1016system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1021system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1022system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1023system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1024system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1025system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1026system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1027system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1028system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses |
| 1029system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles 1030system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles 1031system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles 1032system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles 1033system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles 1034system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles | 1029system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles 1030system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles 1031system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles 1032system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles 1033system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles 1034system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles |
| 1035system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses 1036system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses 1037system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses 1038system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses 1039system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses 1040system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses | 1035system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses 1036system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses 1037system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses 1038system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses 1039system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses 1040system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses |
| 1041system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency 1042system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency 1043system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency 1044system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency 1045system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency 1046system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency | 1041system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency 1042system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency 1043system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency 1044system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency 1045system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency 1046system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency |
| 1047system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1048system.cpu0.dcache.tags.replacements 2 # number of replacements | 1047system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1048system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 1049system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use | 1049system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use |
| 1050system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. 1051system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 1052system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. 1053system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1050system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. 1051system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 1052system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. 1053system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1054system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor 1055system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy 1056system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy | 1054system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor 1055system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy 1056system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy |
| 1057system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits 1058system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits 1059system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits 1060system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits 1061system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1062system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1063system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits 1064system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits --- 175 unchanged lines hidden (view full) --- 1240system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed 1241system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer 1242system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. 1243system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. 1244system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. 1245system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. 1246system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) 1247system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ | 1057system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits 1058system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits 1059system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits 1060system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits 1061system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1062system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1063system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits 1064system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits --- 175 unchanged lines hidden (view full) --- 1240system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed 1241system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer 1242system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. 1243system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. 1244system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. 1245system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. 1246system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) 1247system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ |
| 1248system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued 1249system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued | 1248system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued 1249system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued |
| 1250system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling | 1250system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 1251system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph | 1251system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph |
| 1252system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1253system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle | 1252system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1253system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle |
| 1254system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle 1255system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle | 1254system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle 1255system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle |
| 1256system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1257system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle 1258system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle 1259system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle | 1256system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1257system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle 1258system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle 1259system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle |
| 1260system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle 1261system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle | 1260system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle 1261system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle |
| 1262system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle 1263system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle 1264system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle 1265system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1266system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1267system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1268system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1269system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 1326system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued 1327system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued 1328system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued 1329system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued 1330system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued 1331system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued 1332system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued 1333system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued | 1262system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle 1263system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle 1264system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle 1265system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1266system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1267system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1268system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1269system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 1326system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued 1327system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued 1328system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued 1329system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued 1330system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued 1331system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued 1332system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued 1333system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued |
| 1334system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued | 1334system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued |
| 1335system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued 1336system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1337system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1335system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued 1336system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1337system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1338system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued 1339system.cpu1.iq.rate 1.191033 # Inst issue rate | 1338system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued 1339system.cpu1.iq.rate 1.190965 # Inst issue rate |
| 1340system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1341system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) | 1340system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1341system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) |
| 1342system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads | 1342system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads |
| 1343system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes | 1343system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes |
| 1344system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses | 1344system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses |
| 1345system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1346system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1347system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1345system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1346system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1347system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1348system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses | 1348system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses |
| 1349system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1350system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores 1351system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1352system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed 1353system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1354system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 1355system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed 1356system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 1369system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 1370system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1371system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations 1372system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly 1373system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 1374system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute 1375system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions 1376system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed | 1349system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1350system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores 1351system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1352system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed 1353system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1354system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 1355system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed 1356system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 1369system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 1370system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1371system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations 1372system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly 1373system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 1374system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute 1375system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions 1376system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed |
| 1377system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute | 1377system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute |
| 1378system.cpu1.iew.exec_swp 0 # number of swp insts executed 1379system.cpu1.iew.exec_nop 34927 # number of nop insts executed 1380system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed 1381system.cpu1.iew.exec_branches 44131 # Number of branches executed 1382system.cpu1.iew.exec_stores 31196 # Number of stores executed 1383system.cpu1.iew.exec_rate 1.184317 # Inst execution rate | 1378system.cpu1.iew.exec_swp 0 # number of swp insts executed 1379system.cpu1.iew.exec_nop 34927 # number of nop insts executed 1380system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed 1381system.cpu1.iew.exec_branches 44131 # Number of branches executed 1382system.cpu1.iew.exec_stores 31196 # Number of stores executed 1383system.cpu1.iew.exec_rate 1.184317 # Inst execution rate |
| 1384system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit 1385system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back 1386system.cpu1.iew.wb_producers 116723 # num instructions producing a value 1387system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value | 1384system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit 1385system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back 1386system.cpu1.iew.wb_producers 116711 # num instructions producing a value 1387system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value |
| 1388system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1388system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1389system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle 1390system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back | 1389system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle 1390system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back |
| 1391system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1392system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit 1393system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards 1394system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted 1395system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle 1396system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle 1397system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle 1398system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 1429system.cpu1.committedInsts 197745 # Number of Instructions Simulated 1430system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated 1431system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated 1432system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction 1433system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads 1434system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle 1435system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads 1436system.cpu1.int_regfile_reads 358439 # number of integer regfile reads | 1391system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1392system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit 1393system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards 1394system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted 1395system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle 1396system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle 1397system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle 1398system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 1429system.cpu1.committedInsts 197745 # Number of Instructions Simulated 1430system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated 1431system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated 1432system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction 1433system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads 1434system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle 1435system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads 1436system.cpu1.int_regfile_reads 358439 # number of integer regfile reads |
| 1437system.cpu1.int_regfile_writes 167816 # number of integer regfile writes | 1437system.cpu1.int_regfile_writes 167768 # number of integer regfile writes |
| 1438system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1439system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads 1440system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1441system.cpu1.icache.tags.replacements 318 # number of replacements | 1438system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1439system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads 1440system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1441system.cpu1.icache.tags.replacements 318 # number of replacements |
| 1442system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use | 1442system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use |
| 1443system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. 1444system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1445system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. 1446system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1443system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. 1444system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1445system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. 1446system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor | 1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor |
| 1448system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy 1449system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy 1450system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits 1451system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits 1452system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits 1453system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits 1454system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits 1455system.cpu1.icache.overall_hits::total 22903 # number of overall hits 1456system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses 1457system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses 1458system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses 1459system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses 1460system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses 1461system.cpu1.icache.overall_misses::total 476 # number of overall misses | 1448system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy 1449system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy 1450system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits 1451system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits 1452system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits 1453system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits 1454system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits 1455system.cpu1.icache.overall_hits::total 22903 # number of overall hits 1456system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses 1457system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses 1458system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses 1459system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses 1460system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses 1461system.cpu1.icache.overall_misses::total 476 # number of overall misses |
| 1462system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles 1463system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles 1464system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles 1465system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles 1466system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles 1467system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles | 1462system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles 1463system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles 1464system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles 1465system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles 1466system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles 1467system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles |
| 1468system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) 1469system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) 1470system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses 1471system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses 1472system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses 1473system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses 1474system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses 1475system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses 1476system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses 1477system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses 1478system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses 1479system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses | 1468system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) 1469system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) 1470system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses 1471system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses 1472system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses 1473system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses 1474system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses 1475system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses 1476system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses 1477system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses 1478system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses 1479system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses |
| 1480system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency 1481system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency 1482system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency 1483system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency 1484system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency 1485system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency | 1480system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency 1481system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency 1482system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency 1483system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency 1484system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency 1485system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency |
| 1486system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1487system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1488system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1489system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1490system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1491system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1492system.cpu1.icache.fast_writes 0 # number of fast writes performed 1493system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1498system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits 1499system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1500system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1501system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1502system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1503system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1504system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1505system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses | 1486system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1487system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1488system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1489system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1490system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1491system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1492system.cpu1.icache.fast_writes 0 # number of fast writes performed 1493system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1498system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits 1499system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1500system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1501system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1502system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1503system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1504system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1505system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses |
| 1506system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles 1507system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles 1508system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles 1509system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles 1510system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles 1511system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles | 1506system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles 1507system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles 1508system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles 1509system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles 1510system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles 1511system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles |
| 1512system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses 1513system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses 1514system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses 1515system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses 1516system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses 1517system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses | 1512system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses 1513system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses 1514system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses 1515system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses 1516system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses 1517system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses |
| 1518system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency 1519system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency 1520system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency 1521system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency 1522system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency 1523system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency | 1518system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency 1519system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency 1520system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency 1521system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency 1522system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency 1523system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency |
| 1524system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1525system.cpu1.dcache.tags.replacements 0 # number of replacements 1526system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use 1527system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. 1528system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1529system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. 1530system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1531system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor --- 111 unchanged lines hidden (view full) --- 1643system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency 1644system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency 1645system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency 1646system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1647system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1648system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1649system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1650system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1524system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1525system.cpu1.dcache.tags.replacements 0 # number of replacements 1526system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use 1527system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. 1528system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1529system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. 1530system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1531system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor --- 111 unchanged lines hidden (view full) --- 1643system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency 1644system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency 1645system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency 1646system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1647system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1648system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1649system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1650system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1651system.cpu2.branchPred.lookups 51290 # Number of BP lookups | 1651system.cpu2.branchPred.lookups 51289 # Number of BP lookups |
| 1652system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted 1653system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect | 1652system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted 1653system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect |
| 1654system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups | 1654system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups |
| 1655system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits 1656system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1655system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits 1656system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1657system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage | 1657system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage |
| 1658system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. 1659system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1660system.cpu2.numCycles 177568 # number of cpu cycles simulated 1661system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1662system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1658system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. 1659system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1660system.cpu2.numCycles 177568 # number of cpu cycles simulated 1661system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1662system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1663system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss 1664system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed 1665system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered | 1663system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss 1664system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed 1665system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered |
| 1666system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken | 1666system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken |
| 1667system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked | 1667system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked |
| 1668system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing | 1668system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing |
| 1669system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked | 1669system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked |
| 1670system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1671system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from 1672system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps | 1670system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1671system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from 1672system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps |
| 1673system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched 1674system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed | 1673system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched 1674system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed |
| 1675system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) | 1675system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) |
| 1676system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) 1677system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) | 1676system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total) 1677system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total) |
| 1678system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1678system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1679system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) 1680system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) | 1679system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total) 1680system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total) |
| 1681system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) 1682system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) 1683system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) 1684system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) 1685system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) 1686system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) | 1681system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) 1682system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) 1683system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) 1684system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) 1685system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) 1686system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) |
| 1687system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) | 1687system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 1688system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1689system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1690system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1691system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) | 1688system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1689system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1690system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1691system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) |
| 1692system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle 1693system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle | 1692system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle 1693system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle |
| 1694system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle | 1694system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle |
| 1695system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked 1696system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running | 1695system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked 1696system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running |
| 1697system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking 1698system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing | 1697system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking 1698system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing |
| 1699system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode | 1699system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode |
| 1700system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing 1701system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle 1702system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking | 1700system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing 1701system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle 1702system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking |
| 1703system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst 1704system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running | 1703system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst 1704system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running |
| 1705system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking | 1705system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking |
| 1706system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename | 1706system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename |
| 1707system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full 1708system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed | 1707system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full 1708system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed |
| 1709system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made 1710system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups | 1709system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made 1710system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups |
| 1711system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed 1712system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing 1713system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed 1714system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed 1715system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer 1716system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. 1717system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. 1718system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. 1719system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. 1720system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) 1721system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ | 1711system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed 1712system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing 1713system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed 1714system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed 1715system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer 1716system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. 1717system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. 1718system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. 1719system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. 1720system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) 1721system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ |
| 1722system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued 1723system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued | 1722system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued 1723system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued |
| 1724system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling | 1724system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 1725system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph | 1725system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph |
| 1726system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1727system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle | 1726system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1727system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle |
| 1728system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle 1729system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle | 1728system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle 1729system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle |
| 1730system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1731system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle 1732system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle 1733system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle | 1730system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1731system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle 1732system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle 1733system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle |
| 1734system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle 1735system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle | 1734system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle 1735system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle |
| 1736system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle 1737system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle 1738system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle 1739system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1740system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1741system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1742system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1743system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 1800system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued 1801system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued 1802system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued 1803system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued 1804system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued 1805system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued 1806system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued 1807system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued | 1736system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle 1737system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle 1738system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle 1739system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1740system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1741system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1742system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1743system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 1800system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued 1801system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued 1802system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued 1803system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued 1804system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued 1805system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued 1806system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued 1807system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued |
| 1808system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued | 1808system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued |
| 1809system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued 1810system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1811system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1809system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued 1810system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1811system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1812system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued 1813system.cpu2.iq.rate 1.322924 # Inst issue rate | 1812system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued 1813system.cpu2.iq.rate 1.322873 # Inst issue rate |
| 1814system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested 1815system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) | 1814system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested 1815system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) |
| 1816system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads | 1816system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads |
| 1817system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes | 1817system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes |
| 1818system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses | 1818system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses |
| 1819system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1820system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1821system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1819system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1820system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1821system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1822system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses | 1822system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses |
| 1823system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1824system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores 1825system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1826system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed 1827system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1828system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 1829system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed 1830system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 1843system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall 1844system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1845system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations 1846system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly 1847system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly 1848system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute 1849system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions 1850system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed | 1823system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1824system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores 1825system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1826system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed 1827system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1828system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 1829system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed 1830system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 1843system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall 1844system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1845system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations 1846system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly 1847system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly 1848system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute 1849system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions 1850system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed |
| 1851system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute | 1851system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute |
| 1852system.cpu2.iew.exec_swp 0 # number of swp insts executed 1853system.cpu2.iew.exec_nop 38771 # number of nop insts executed 1854system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed 1855system.cpu2.iew.exec_branches 48001 # Number of branches executed 1856system.cpu2.iew.exec_stores 36873 # Number of stores executed 1857system.cpu2.iew.exec_rate 1.316482 # Inst execution rate | 1852system.cpu2.iew.exec_swp 0 # number of swp insts executed 1853system.cpu2.iew.exec_nop 38771 # number of nop insts executed 1854system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed 1855system.cpu2.iew.exec_branches 48001 # Number of branches executed 1856system.cpu2.iew.exec_stores 36873 # Number of stores executed 1857system.cpu2.iew.exec_rate 1.316482 # Inst execution rate |
| 1858system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit 1859system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back 1860system.cpu2.iew.wb_producers 131942 # num instructions producing a value 1861system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value | 1858system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit 1859system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back 1860system.cpu2.iew.wb_producers 131933 # num instructions producing a value 1861system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value |
| 1862system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1862system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1863system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle 1864system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back | 1863system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle 1864system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back |
| 1865system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1866system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit 1867system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards 1868system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted 1869system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle 1870system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle 1871system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle 1872system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 1903system.cpu2.committedInsts 222382 # Number of Instructions Simulated 1904system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated 1905system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated 1906system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction 1907system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads 1908system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle 1909system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads 1910system.cpu2.int_regfile_reads 404230 # number of integer regfile reads | 1865system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1866system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit 1867system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards 1868system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted 1869system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle 1870system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle 1871system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle 1872system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 1903system.cpu2.committedInsts 222382 # Number of Instructions Simulated 1904system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated 1905system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated 1906system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction 1907system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads 1908system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle 1909system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads 1910system.cpu2.int_regfile_reads 404230 # number of integer regfile reads |
| 1911system.cpu2.int_regfile_writes 188808 # number of integer regfile writes | 1911system.cpu2.int_regfile_writes 188772 # number of integer regfile writes |
| 1912system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1913system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads 1914system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1915system.cpu2.icache.tags.replacements 317 # number of replacements | 1912system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1913system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads 1914system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1915system.cpu2.icache.tags.replacements 317 # number of replacements |
| 1916system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use 1917system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. | 1916system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use 1917system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks. |
| 1918system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. | 1918system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. |
| 1919system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. | 1919system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks. |
| 1920system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1920system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1921system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor | 1921system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor |
| 1922system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy 1923system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy | 1922system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy 1923system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy |
| 1924system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits 1925system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits 1926system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits 1927system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits 1928system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits 1929system.cpu2.icache.overall_hits::total 19259 # number of overall hits | 1924system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits 1925system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits 1926system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits 1927system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits 1928system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits 1929system.cpu2.icache.overall_hits::total 19258 # number of overall hits |
| 1930system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1931system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses 1932system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses 1933system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses 1934system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses 1935system.cpu2.icache.overall_misses::total 493 # number of overall misses | 1930system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1931system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses 1932system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses 1933system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses 1934system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses 1935system.cpu2.icache.overall_misses::total 493 # number of overall misses |
| 1936system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles 1937system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles 1938system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles 1939system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles 1940system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles 1941system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles 1942system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) 1943system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) 1944system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses 1945system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses 1946system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses 1947system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses 1948system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses 1949system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses 1950system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses 1951system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses 1952system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses 1953system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses 1954system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency 1955system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency 1956system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency 1957system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency 1958system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency 1959system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency | 1936system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles 1937system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles 1938system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles 1939system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles 1940system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles 1941system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles 1942system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses) 1943system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses) 1944system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses 1945system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses 1946system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses 1947system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses 1948system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses 1949system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses 1950system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses 1951system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses 1952system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses 1953system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses 1954system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency 1955system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency 1956system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency 1957system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency 1958system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency 1959system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency |
| 1960system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 1961system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1962system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1963system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1964system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 1965system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1966system.cpu2.icache.fast_writes 0 # number of fast writes performed 1967system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1972system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits 1973system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 1974system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 1975system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1976system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 1977system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1978system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 1979system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses | 1960system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 1961system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1962system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1963system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1964system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 1965system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1966system.cpu2.icache.fast_writes 0 # number of fast writes performed 1967system.cpu2.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1972system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits 1973system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 1974system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 1975system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1976system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 1977system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1978system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 1979system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses |
| 1980system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles 1981system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles 1982system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles 1983system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles 1984system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles 1985system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles 1986system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses 1987system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses 1988system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses 1989system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses 1990system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses 1991system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses 1992system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency 1993system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency 1994system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency 1995system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency 1996system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency 1997system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency | 1980system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles 1981system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles 1982system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles 1983system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles 1984system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles 1985system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles 1986system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses 1987system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses 1988system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses 1989system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses 1990system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses 1991system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses 1992system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency 1993system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency 1994system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency 1995system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency 1996system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency 1997system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency |
| 1998system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1999system.cpu2.dcache.tags.replacements 0 # number of replacements | 1998system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1999system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 2000system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use | 2000system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use |
| 2001system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. 2002system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2003system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. 2004system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2001system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. 2002system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2003system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. 2004system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2005system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor | 2005system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor |
| 2006system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy 2007system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy 2008system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits 2009system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits 2010system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits 2011system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits 2012system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 2013system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 2020system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses 2021system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2022system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses 2023system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2024system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses 2025system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses 2026system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses 2027system.cpu2.dcache.overall_misses::total 485 # number of overall misses | 2006system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy 2007system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy 2008system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits 2009system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits 2010system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits 2011system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits 2012system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 2013system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 2020system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses 2021system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2022system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses 2023system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2024system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses 2025system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses 2026system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses 2027system.cpu2.dcache.overall_misses::total 485 # number of overall misses |
| 2028system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles 2029system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles | 2028system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles 2029system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles |
| 2030system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles 2031system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles 2032system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles 2033system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles | 2030system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles 2031system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles 2032system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles 2033system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles |
| 2034system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles 2035system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles 2036system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles 2037system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles | 2034system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles 2035system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles 2036system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles 2037system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles |
| 2038system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) 2039system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) 2040system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) 2041system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) 2042system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) 2043system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2044system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses 2045system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 2050system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses 2051system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses 2052system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses 2053system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 2054system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses 2055system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses 2056system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses 2057system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses | 2038system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) 2039system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) 2040system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) 2041system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) 2042system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) 2043system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2044system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses 2045system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 2050system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses 2051system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses 2052system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses 2053system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 2054system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses 2055system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses 2056system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses 2057system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses |
| 2058system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency 2059system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency | 2058system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency 2059system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency |
| 2060system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency 2061system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency 2062system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency 2063system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency | 2060system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency 2061system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency 2062system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency 2063system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency |
| 2064system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency 2065system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency 2066system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency 2067system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency | 2064system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency 2065system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency 2066system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency 2067system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency |
| 2068system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2069system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2070system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2071system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2072system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2073system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2074system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2075system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 53 unchanged lines hidden (view full) --- 2129system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits 2130system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2131system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage 2132system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. 2133system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 2134system.cpu3.numCycles 177222 # number of cpu cycles simulated 2135system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2136system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 2068system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2069system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2070system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2071system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2072system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2073system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2074system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2075system.cpu2.dcache.cache_copies 0 # number of cache copies performed --- 53 unchanged lines hidden (view full) --- 2129system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits 2130system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2131system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage 2132system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. 2133system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 2134system.cpu3.numCycles 177222 # number of cpu cycles simulated 2135system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2136system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2137system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss | 2137system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss |
| 2138system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed 2139system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered 2140system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken 2141system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked 2142system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing | 2138system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed 2139system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered 2140system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken 2141system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked 2142system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing |
| 2143system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked | 2143system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked |
| 2144system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2145system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from 2146system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps 2147system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched 2148system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed 2149system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) 2150system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) 2151system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) --- 8 unchanged lines hidden (view full) --- 2160system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) 2161system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) 2162system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2163system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2164system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2165system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) 2166system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle 2167system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle | 2144system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2145system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from 2146system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps 2147system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched 2148system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed 2149system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) 2150system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) 2151system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) --- 8 unchanged lines hidden (view full) --- 2160system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) 2161system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) 2162system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2163system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2164system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2165system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) 2166system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle 2167system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle |
| 2168system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle 2169system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked | 2168system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle 2169system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked |
| 2170system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running 2171system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking 2172system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing 2173system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode 2174system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing | 2170system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running 2171system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking 2172system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing 2173system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode 2174system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing |
| 2175system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle | 2175system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle |
| 2176system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking | 2176system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking |
| 2177system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst | 2177system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst |
| 2178system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running 2179system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking 2180system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename 2181system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2182system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full 2183system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed 2184system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made 2185system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups 2186system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed 2187system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing 2188system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2189system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed 2190system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer 2191system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. 2192system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. 2193system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. 2194system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. 2195system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) 2196system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ | 2178system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running 2179system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking 2180system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename 2181system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2182system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full 2183system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed 2184system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made 2185system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups 2186system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed 2187system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing 2188system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2189system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed 2190system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer 2191system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. 2192system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. 2193system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. 2194system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. 2195system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) 2196system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ |
| 2197system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued 2198system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued | 2197system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued 2198system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued |
| 2199system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling | 2199system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 2200system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph | 2200system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph |
| 2201system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed 2202system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle | 2201system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed 2202system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle |
| 2203system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle 2204system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle | 2203system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle 2204system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle |
| 2205system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2206system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle 2207system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle 2208system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle | 2205system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2206system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle 2207system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle 2208system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle |
| 2209system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle 2210system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle | 2209system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle 2210system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle |
| 2211system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle 2212system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle 2213system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 2214system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2215system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2216system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2217system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2218system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 2275system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued 2276system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued 2277system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued 2278system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued 2279system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued 2280system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued 2281system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued 2282system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued | 2211system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle 2212system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle 2213system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 2214system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2215system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2216system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2217system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2218system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle --- 56 unchanged lines hidden (view full) --- 2275system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued 2276system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued 2277system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued 2278system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued 2279system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued 2280system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued 2281system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued 2282system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued |
| 2283system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued | 2283system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued |
| 2284system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued 2285system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2286system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2284system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued 2285system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2286system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2287system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued 2288system.cpu3.iq.rate 1.348602 # Inst issue rate | 2287system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued 2288system.cpu3.iq.rate 1.348535 # Inst issue rate |
| 2289system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested 2290system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) | 2289system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested 2290system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) |
| 2291system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads | 2291system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads |
| 2292system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes | 2292system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes |
| 2293system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses | 2293system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses |
| 2294system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2295system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2296system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 2294system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2295system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2296system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 2297system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses | 2297system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses |
| 2298system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2299system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores 2300system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2301system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed 2302system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2303system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 2304system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed 2305system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 2318system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 2319system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2320system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations 2321system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly 2322system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly 2323system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 2324system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions 2325system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed | 2298system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2299system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores 2300system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2301system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed 2302system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2303system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 2304system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed 2305system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 12 unchanged lines hidden (view full) --- 2318system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 2319system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2320system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations 2321system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly 2322system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly 2323system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 2324system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions 2325system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed |
| 2326system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute | 2326system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute |
| 2327system.cpu3.iew.exec_swp 0 # number of swp insts executed 2328system.cpu3.iew.exec_nop 39788 # number of nop insts executed 2329system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed 2330system.cpu3.iew.exec_branches 49028 # Number of branches executed 2331system.cpu3.iew.exec_stores 37424 # Number of stores executed 2332system.cpu3.iew.exec_rate 1.342091 # Inst execution rate | 2327system.cpu3.iew.exec_swp 0 # number of swp insts executed 2328system.cpu3.iew.exec_nop 39788 # number of nop insts executed 2329system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed 2330system.cpu3.iew.exec_branches 49028 # Number of branches executed 2331system.cpu3.iew.exec_stores 37424 # Number of stores executed 2332system.cpu3.iew.exec_rate 1.342091 # Inst execution rate |
| 2333system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit 2334system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back 2335system.cpu3.iew.wb_producers 134044 # num instructions producing a value 2336system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value | 2333system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit 2334system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back 2335system.cpu3.iew.wb_producers 134032 # num instructions producing a value 2336system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value |
| 2337system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2337system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2338system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle 2339system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back | 2338system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle 2339system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back |
| 2340system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2341system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit 2342system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards 2343system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted 2344system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle 2345system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle 2346system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle 2347system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 2378system.cpu3.committedInsts 226224 # Number of Instructions Simulated 2379system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated 2380system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated 2381system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction 2382system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads 2383system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle 2384system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads 2385system.cpu3.int_regfile_reads 410473 # number of integer regfile reads | 2340system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2341system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit 2342system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards 2343system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted 2344system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle 2345system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle 2346system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle 2347system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle --- 30 unchanged lines hidden (view full) --- 2378system.cpu3.committedInsts 226224 # Number of Instructions Simulated 2379system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated 2380system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated 2381system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction 2382system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads 2383system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle 2384system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads 2385system.cpu3.int_regfile_reads 410473 # number of integer regfile reads |
| 2386system.cpu3.int_regfile_writes 191401 # number of integer regfile writes | 2386system.cpu3.int_regfile_writes 191353 # number of integer regfile writes |
| 2387system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2388system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads 2389system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2390system.cpu3.icache.tags.replacements 319 # number of replacements | 2387system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2388system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads 2389system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2390system.cpu3.icache.tags.replacements 319 # number of replacements |
| 2391system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use | 2391system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use |
| 2392system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. 2393system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. 2394system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. 2395system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2392system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. 2393system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. 2394system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. 2395system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2396system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor | 2396system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor |
| 2397system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy 2398system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy 2399system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits 2400system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits 2401system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits 2402system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits 2403system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits 2404system.cpu3.icache.overall_hits::total 20090 # number of overall hits 2405system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2406system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2407system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2408system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2409system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2410system.cpu3.icache.overall_misses::total 475 # number of overall misses | 2397system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy 2398system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy 2399system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits 2400system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits 2401system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits 2402system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits 2403system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits 2404system.cpu3.icache.overall_hits::total 20090 # number of overall hits 2405system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2406system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2407system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2408system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2409system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2410system.cpu3.icache.overall_misses::total 475 # number of overall misses |
| 2411system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles 2412system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles 2413system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles 2414system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles 2415system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles 2416system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles | 2411system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles 2412system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles 2413system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles 2414system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles 2415system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles 2416system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles |
| 2417system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) 2418system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) 2419system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses 2420system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses 2421system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses 2422system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses 2423system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses 2424system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses 2425system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses 2426system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses 2427system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses 2428system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses | 2417system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) 2418system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) 2419system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses 2420system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses 2421system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses 2422system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses 2423system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses 2424system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses 2425system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses 2426system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses 2427system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses 2428system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses |
| 2429system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency 2430system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency 2431system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency 2432system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency 2433system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency 2434system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency | 2429system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency 2430system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency 2431system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency 2432system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency 2433system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency 2434system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency |
| 2435system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2436system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2437system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2438system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2439system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2440system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2441system.cpu3.icache.fast_writes 0 # number of fast writes performed 2442system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 2447system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 2448system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 2449system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 2450system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 2451system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 2452system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 2453system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 2454system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses | 2435system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2436system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2437system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2438system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2439system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2440system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2441system.cpu3.icache.fast_writes 0 # number of fast writes performed 2442system.cpu3.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 2447system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 2448system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 2449system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 2450system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 2451system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 2452system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 2453system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 2454system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses |
| 2455system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles 2456system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles 2457system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles 2458system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles 2459system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles 2460system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles | 2455system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles 2456system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles 2457system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles 2458system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles 2459system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles 2460system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles |
| 2461system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses 2462system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses 2463system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses 2464system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses 2465system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses 2466system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses | 2461system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses 2462system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses 2463system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses 2464system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses 2465system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses 2466system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses |
| 2467system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency 2468system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency 2469system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency 2470system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency 2471system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency 2472system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency | 2467system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency 2468system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency 2469system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency 2470system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency 2471system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency 2472system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency |
| 2473system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2474system.cpu3.dcache.tags.replacements 0 # number of replacements | 2473system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2474system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 2475system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use | 2475system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use |
| 2476system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. 2477system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2478system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. 2479system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2476system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. 2477system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2478system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. 2479system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2480system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor | 2480system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor |
| 2481system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy 2482system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy 2483system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits 2484system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits 2485system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits 2486system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits 2487system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 2488system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 2495system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses 2496system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses 2497system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 2498system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 2499system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses 2500system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses 2501system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses 2502system.cpu3.dcache.overall_misses::total 464 # number of overall misses | 2481system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy 2482system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy 2483system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits 2484system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits 2485system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits 2486system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits 2487system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 2488system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits --- 6 unchanged lines hidden (view full) --- 2495system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses 2496system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses 2497system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 2498system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 2499system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses 2500system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses 2501system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses 2502system.cpu3.dcache.overall_misses::total 464 # number of overall misses |
| 2503system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles 2504system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles 2505system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles 2506system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles | 2503system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4248100 # number of ReadReq miss cycles 2504system.cpu3.dcache.ReadReq_miss_latency::total 4248100 # number of ReadReq miss cycles 2505system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3351512 # number of WriteReq miss cycles 2506system.cpu3.dcache.WriteReq_miss_latency::total 3351512 # number of WriteReq miss cycles |
| 2507system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles 2508system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles | 2507system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles 2508system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles |
| 2509system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles 2510system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles 2511system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles 2512system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles | 2509system.cpu3.dcache.demand_miss_latency::cpu3.data 7599612 # number of demand (read+write) miss cycles 2510system.cpu3.dcache.demand_miss_latency::total 7599612 # number of demand (read+write) miss cycles 2511system.cpu3.dcache.overall_miss_latency::cpu3.data 7599612 # number of overall miss cycles 2512system.cpu3.dcache.overall_miss_latency::total 7599612 # number of overall miss cycles |
| 2513system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) 2514system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) 2515system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) 2516system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) 2517system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) 2518system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 2519system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses 2520system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 2525system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses 2526system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses 2527system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses 2528system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses 2529system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses 2530system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses 2531system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses 2532system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses | 2513system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) 2514system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) 2515system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) 2516system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) 2517system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) 2518system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 2519system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses 2520system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses --- 4 unchanged lines hidden (view full) --- 2525system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses 2526system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses 2527system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses 2528system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses 2529system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses 2530system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses 2531system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses 2532system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses |
| 2533system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency 2534system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency 2535system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency 2536system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency | 2533system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency 2534system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency 2535system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency 2536system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency |
| 2537system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency 2538system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency | 2537system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency 2538system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency |
| 2539system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency 2540system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency 2541system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency 2542system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency | 2539system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency 2540system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency 2541system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency 2542system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency |
| 2543system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2544system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2545system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2546system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2547system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2548system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2549system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2550system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 2563system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 2564system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 2565system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses 2566system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2567system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses 2568system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses 2569system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles 2570system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles | 2543system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2544system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2545system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2546system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2547system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2548system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2549system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2550system.cpu3.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 2563system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 2564system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 2565system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses 2566system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2567system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses 2568system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses 2569system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles 2570system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles |
| 2571system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles 2572system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles | 2571system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408238 # number of WriteReq MSHR miss cycles 2572system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408238 # number of WriteReq MSHR miss cycles |
| 2573system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles 2574system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles | 2573system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles 2574system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles |
| 2575system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles 2576system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles 2577system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles 2578system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles | 2575system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles 2576system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles 2577system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles 2578system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles |
| 2579system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses 2580system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses 2581system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses 2582system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses 2583system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses 2584system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses 2585system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses 2586system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses 2587system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses 2588system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses 2589system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency 2590system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency | 2579system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses 2580system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses 2581system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses 2582system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses 2583system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses 2584system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses 2585system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses 2586system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses 2587system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses 2588system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses 2589system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency 2590system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency |
| 2591system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency 2592system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency | 2591system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency 2592system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency |
| 2593system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency 2594system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency | 2593system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency 2594system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency |
| 2595system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency 2596system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency 2597system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency 2598system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency | 2595system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency 2596system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency 2597system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency 2598system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency |
| 2599system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2600 2601---------- End Simulation Statistics ---------- | 2599system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2600 2601---------- End Simulation Statistics ---------- |