| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 110804500 # Number of ticks simulated 5final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 110804500 # Number of ticks simulated 5final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 110530 # Simulator instruction rate (inst/s) 8host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11745373 # Simulator tick rate (ticks/s) 10host_mem_usage 249508 # Number of bytes of host memory used 11host_seconds 9.43 # Real time elapsed on the host | 7host_inst_rate 170931 # Simulator instruction rate (inst/s) 8host_op_rate 170931 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18163832 # Simulator tick rate (ticks/s) 10host_mem_usage 247816 # Number of bytes of host memory used 11host_seconds 6.10 # Real time elapsed on the host |
| 12sim_insts 1042724 # Number of instructions simulated 13sim_ops 1042724 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 32 unchanged lines hidden (view full) --- 52system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 1042724 # Number of instructions simulated 13sim_ops 1042724 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory --- 32 unchanged lines hidden (view full) --- 52system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) |
| 60system.physmem.readReqs 660 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady | 60system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller 61system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 62system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 63system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 63system.physmem.bytesRead 42176 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() | 64system.physmem.bytesRead 42176 # Total number of bytes read from memory 65system.physmem.bytesWritten 0 # Total number of bytes written to memory 66system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() 67system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 68system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q |
| 68system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis --- 148 unchanged lines hidden (view full) --- 224system.physmem.avgGap 167843.18 # Average gap between requests 225system.membus.throughput 380634361 # Throughput (bytes/s) 226system.membus.trans_dist::ReadReq 529 # Transaction distribution 227system.membus.trans_dist::ReadResp 528 # Transaction distribution 228system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 229system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 230system.membus.trans_dist::ReadExReq 163 # Transaction distribution 231system.membus.trans_dist::ReadExResp 131 # Transaction distribution | 69system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed 70system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis --- 148 unchanged lines hidden (view full) --- 225system.physmem.avgGap 167843.18 # Average gap between requests 226system.membus.throughput 380634361 # Throughput (bytes/s) 227system.membus.trans_dist::ReadReq 529 # Transaction distribution 228system.membus.trans_dist::ReadResp 528 # Transaction distribution 229system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 230system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 231system.membus.trans_dist::ReadExReq 163 # Transaction distribution 232system.membus.trans_dist::ReadExResp 131 # Transaction distribution |
| 232system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) | 233system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) 235system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 236system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) |
| 236system.membus.data_through_bus 42176 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 238system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) 239system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 240system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 5.7 # Layer utilization (%) | 237system.membus.data_through_bus 42176 # Total data (bytes) 238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 239system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) 240system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 241system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) 242system.membus.respLayer1.utilization 5.7 # Layer utilization (%) |
| 243system.l2c.tags.replacements 0 # number of replacements 244system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use 245system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 246system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 247system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 248system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 249system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor 250system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor 251system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor 252system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor 253system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor 254system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor 255system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor 256system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor 257system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor 258system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 259system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy 260system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 261system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy 262system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 263system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy 264system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 265system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy 266system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 267system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 278system.l2c.Writeback_hits::total 1 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 281system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits 282system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 283system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits 284system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 285system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits 286system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 287system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits 288system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 289system.l2c.demand_hits::total 1443 # number of demand (read+write) hits 290system.l2c.overall_hits::cpu0.inst 229 # number of overall hits 291system.l2c.overall_hits::cpu0.data 5 # number of overall hits 292system.l2c.overall_hits::cpu1.inst 412 # number of overall hits 293system.l2c.overall_hits::cpu1.data 11 # number of overall hits 294system.l2c.overall_hits::cpu2.inst 349 # number of overall hits 295system.l2c.overall_hits::cpu2.data 5 # number of overall hits 296system.l2c.overall_hits::cpu3.inst 421 # number of overall hits 297system.l2c.overall_hits::cpu3.data 11 # number of overall hits 298system.l2c.overall_hits::total 1443 # number of overall hits 299system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses 300system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 301system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses 302system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 303system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses 304system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 305system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 306system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 307system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 308system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 309system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 310system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses 311system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 312system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 313system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 314system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 315system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 316system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 317system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 318system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses 319system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 320system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses 321system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 322system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses 323system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 324system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 325system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 326system.l2c.demand_misses::total 674 # number of demand (read+write) misses 327system.l2c.overall_misses::cpu0.inst 359 # number of overall misses 328system.l2c.overall_misses::cpu0.data 168 # number of overall misses 329system.l2c.overall_misses::cpu1.inst 16 # number of overall misses 330system.l2c.overall_misses::cpu1.data 13 # number of overall misses 331system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 332system.l2c.overall_misses::cpu2.data 20 # number of overall misses 333system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 334system.l2c.overall_misses::cpu3.data 13 # number of overall misses 335system.l2c.overall_misses::total 674 # number of overall misses 336system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles 337system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles 338system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles 339system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles 340system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles 342system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles 343system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles 344system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles 345system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles 346system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles 347system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles 348system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles 349system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles 350system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles 351system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles 352system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles 353system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles 354system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles 355system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles 356system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles 359system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles 360system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles 361system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles 362system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles 363system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles 364system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles 367system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles 368system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 369system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 370system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 371system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 372system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) 377system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 378system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 379system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 380system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 381system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) 382system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 383system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 384system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 385system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 386system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 387system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 388system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 389system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses 390system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 391system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses 392system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 397system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses 398system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses 399system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 400system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses 401system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 406system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses 407system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses 408system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 409system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses 410system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses 416system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses 417system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 418system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 419system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 420system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses 421system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 422system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 423system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 424system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 425system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 426system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses 427system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu1.inst 0.037383 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses 433system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 434system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses 435system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses 442system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 443system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses 444system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # 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number of demand (read+write) MSHR hits 494system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 495system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 496system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits 497system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits 498system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 499system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses 500system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses 501system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses 502system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses 503system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses 504system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 505system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses 506system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 507system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses 508system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses 509system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses 510system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses 511system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 512system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses 513system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 514system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 515system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 516system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 517system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 518system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses 519system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses 520system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses 521system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 522system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses 523system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 524system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses 525system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 526system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 527system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses 528system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 529system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses 530system.l2c.overall_mshr_misses::cpu1.data 13 # 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number of ReadReq MSHR miss cycles 543system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles 544system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles 545system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles 546system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles 547system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles 548system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles 549system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles 550system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles 551system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles 552system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles 553system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles 554system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles 555system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles 556system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles 557system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles 559system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles 560system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles 561system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles 562system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles 563system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles 564system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles 565system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles 566system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles 567system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles 568system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles 569system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles 570system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles 571system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles 572system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles 573system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses 574system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 575system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses 576system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 577system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses 578system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 579system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses 580system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 581system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses 582system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses 583system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 584system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 585system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 586system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses 587system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 588system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 589system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 590system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 591system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 592system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 593system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 594system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses 595system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 596system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses 597system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 598system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses 599system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 600system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses 601system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 602system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 603system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses 604system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 605system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses 606system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 607system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses 608system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 609system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses 610system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency 611system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency 612system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency 613system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency 615system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency 619system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 620system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency 624system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency 625system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency 626system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency 629system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 636system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 637system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 641system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 642system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 643system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 644system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 646system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 647system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 242system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) 243system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 244system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 245system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 246system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 247system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 248system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution 249system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution | 648system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) 649system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 650system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 651system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 652system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 653system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 654system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution 655system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution |
| 250system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) 251system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) 252system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) 253system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) 254system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) 255system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) 256system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) 257system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) 258system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) 259system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) 260system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) 261system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) 262system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 263system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) 264system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) 265system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) 266system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 267system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) | 656system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) 657system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) 658system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) 659system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 660system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) 661system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) 662system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) 663system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) 664system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) 665system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) 666system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 667system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) 668system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 669system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) 670system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 671system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) 672system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 673system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) |
| 268system.toL2Bus.data_through_bus 135488 # Total data (bytes) 269system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) 270system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) 271system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 272system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) 273system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 274system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) 275system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) --- 267 unchanged lines hidden (view full) --- 543system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads 544system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle 545system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads 546system.cpu0.int_regfile_reads 721592 # number of integer regfile reads 547system.cpu0.int_regfile_writes 325227 # number of integer regfile writes 548system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 549system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads 550system.cpu0.misc_regfile_writes 564 # number of misc regfile writes | 674system.toL2Bus.data_through_bus 135488 # Total data (bytes) 675system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) 676system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) 677system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 678system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) 679system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 680system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) 681system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) --- 267 unchanged lines hidden (view full) --- 949system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads 950system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle 951system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads 952system.cpu0.int_regfile_reads 721592 # number of integer regfile reads 953system.cpu0.int_regfile_writes 325227 # number of integer regfile writes 954system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 955system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads 956system.cpu0.misc_regfile_writes 564 # number of misc regfile writes |
| 551system.cpu0.icache.tags.replacements 297 # number of replacements 552system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use 553system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 554system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 555system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 556system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 957system.cpu0.icache.tags.replacements 297 # number of replacements 958system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use 959system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 960system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 961system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 962system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 557system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor 558system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy | 963system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor 964system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy |
| 559system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy | 965system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy |
| 560system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 561system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 562system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 563system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 564system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 565system.cpu0.icache.overall_hits::total 5079 # number of overall hits 566system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 567system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 627system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 628system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency 629system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency 630system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 631system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 632system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 633system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 634system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 966system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 967system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 968system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 969system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 970system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 971system.cpu0.icache.overall_hits::total 5079 # number of overall hits 972system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 973system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 1033system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 1034system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency 1035system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency 1036system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 1037system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 1038system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 1039system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 1040system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 635system.cpu0.dcache.tags.replacements 2 # number of replacements 636system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use 637system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. 638system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 639system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. 640system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1041system.cpu0.dcache.tags.replacements 2 # number of replacements 1042system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use 1043system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. 1044system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 1045system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. 1046system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 641system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor 642system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy | 1047system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor 1048system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy |
| 643system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy | 1049system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy |
| 644system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits 645system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits 646system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits 647system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits 648system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 649system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 650system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits --- 368 unchanged lines hidden (view full) --- 1020system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads 1021system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle 1022system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads 1023system.cpu1.int_regfile_reads 315718 # number of integer regfile reads 1024system.cpu1.int_regfile_writes 148477 # number of integer regfile writes 1025system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1026system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads 1027system.cpu1.misc_regfile_writes 648 # number of misc regfile writes | 1050system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits 1051system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits 1052system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits 1053system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits 1054system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1055system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1056system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits 1057system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits --- 368 unchanged lines hidden (view full) --- 1426system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads 1427system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle 1428system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads 1429system.cpu1.int_regfile_reads 315718 # number of integer regfile reads 1430system.cpu1.int_regfile_writes 148477 # number of integer regfile writes 1431system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1432system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads 1433system.cpu1.misc_regfile_writes 648 # number of misc regfile writes |
| 1028system.cpu1.icache.tags.replacements 318 # number of replacements 1029system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use 1030system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. 1031system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1032system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. 1033system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1434system.cpu1.icache.tags.replacements 318 # number of replacements 1435system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use 1436system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. 1437system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1438system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. 1439system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1034system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor 1035system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy | 1440system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor 1441system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy |
| 1036system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy | 1442system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy |
| 1037system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits 1038system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits 1039system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits 1040system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits 1041system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits 1042system.cpu1.icache.overall_hits::total 25178 # number of overall hits 1043system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses 1044system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 1104system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses 1105system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency 1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency 1107system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1108system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1109system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1110system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1111system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1443system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits 1444system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits 1445system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits 1446system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits 1447system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits 1448system.cpu1.icache.overall_hits::total 25178 # number of overall hits 1449system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses 1450system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 1510system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses 1511system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency 1512system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency 1513system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1514system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1515system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1516system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1517system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1112system.cpu1.dcache.tags.replacements 0 # number of replacements 1113system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use 1114system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. 1115system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1116system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. 1117system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1518system.cpu1.dcache.tags.replacements 0 # number of replacements 1519system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use 1520system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. 1521system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1522system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. 1523system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1118system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor 1119system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy | 1524system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor 1525system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy |
| 1120system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy | 1526system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy |
| 1121system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits 1122system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits 1123system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits 1124system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits 1125system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 1126system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1127system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits 1128system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits --- 366 unchanged lines hidden (view full) --- 1495system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads 1496system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle 1497system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads 1498system.cpu2.int_regfile_reads 403571 # number of integer regfile reads 1499system.cpu2.int_regfile_writes 188531 # number of integer regfile writes 1500system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1501system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads 1502system.cpu2.misc_regfile_writes 648 # number of misc regfile writes | 1527system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits 1528system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits 1529system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits 1530system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits 1531system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 1532system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1533system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits 1534system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits --- 366 unchanged lines hidden (view full) --- 1901system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads 1902system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle 1903system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads 1904system.cpu2.int_regfile_reads 403571 # number of integer regfile reads 1905system.cpu2.int_regfile_writes 188531 # number of integer regfile writes 1906system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1907system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads 1908system.cpu2.misc_regfile_writes 648 # number of misc regfile writes |
| 1503system.cpu2.icache.tags.replacements 317 # number of replacements 1504system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use 1505system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. 1506system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 1507system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. 1508system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1909system.cpu2.icache.tags.replacements 317 # number of replacements 1910system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use 1911system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. 1912system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 1913system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. 1914system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1509system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor 1510system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy | 1915system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor 1916system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy |
| 1511system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy | 1917system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy |
| 1512system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits 1513system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits 1514system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits 1515system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits 1516system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits 1517system.cpu2.icache.overall_hits::total 19274 # number of overall hits 1518system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1519system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 1579system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses 1580system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency 1581system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency 1582system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1583system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1584system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1585system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1586system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1918system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits 1919system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits 1920system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits 1921system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits 1922system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits 1923system.cpu2.icache.overall_hits::total 19274 # number of overall hits 1924system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1925system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 1985system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses 1986system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency 1987system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency 1988system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1989system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1990system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1991system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1992system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1587system.cpu2.dcache.tags.replacements 0 # number of replacements 1588system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use 1589system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. 1590system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1591system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. 1592system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1993system.cpu2.dcache.tags.replacements 0 # number of replacements 1994system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use 1995system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. 1996system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1997system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. 1998system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1593system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor 1594system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy | 1999system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor 2000system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy |
| 1595system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy | 2001system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy |
| 1596system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits 1597system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits 1598system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits 1599system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits 1600system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 1601system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1602system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits 1603system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits --- 366 unchanged lines hidden (view full) --- 1970system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads 1971system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle 1972system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads 1973system.cpu3.int_regfile_reads 453881 # number of integer regfile reads 1974system.cpu3.int_regfile_writes 211087 # number of integer regfile writes 1975system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 1976system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads 1977system.cpu3.misc_regfile_writes 648 # number of misc regfile writes | 2002system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits 2003system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits 2004system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits 2005system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits 2006system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 2007system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2008system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits 2009system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits --- 366 unchanged lines hidden (view full) --- 2376system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads 2377system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle 2378system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads 2379system.cpu3.int_regfile_reads 453881 # number of integer regfile reads 2380system.cpu3.int_regfile_writes 211087 # number of integer regfile writes 2381system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2382system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads 2383system.cpu3.misc_regfile_writes 648 # number of misc regfile writes |
| 1978system.cpu3.icache.tags.replacements 319 # number of replacements 1979system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use 1980system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. 1981system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. 1982system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. 1983system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2384system.cpu3.icache.tags.replacements 319 # number of replacements 2385system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use 2386system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. 2387system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. 2388system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. 2389system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1984system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor 1985system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy | 2390system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor 2391system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy |
| 1986system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy | 2392system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy |
| 1987system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits 1988system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits 1989system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits 1990system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits 1991system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits 1992system.cpu3.icache.overall_hits::total 17724 # number of overall hits 1993system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 1994system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 2054system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses 2055system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency 2056system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency 2057system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2058system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2059system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2060system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2061system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2393system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits 2394system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits 2395system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits 2396system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits 2397system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits 2398system.cpu3.icache.overall_hits::total 17724 # number of overall hits 2399system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2400system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 2460system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses 2461system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency 2462system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency 2463system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2464system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2465system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2466system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2467system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2062system.cpu3.dcache.tags.replacements 0 # number of replacements 2063system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use 2064system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. 2065system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2066system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. 2067system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2468system.cpu3.dcache.tags.replacements 0 # number of replacements 2469system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use 2470system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. 2471system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2472system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. 2473system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2068system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor 2069system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy | 2474system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor 2475system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy |
| 2070system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy | 2476system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy |
| 2071system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits 2072system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits 2073system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits 2074system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits 2075system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2076system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2077system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits 2078system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits --- 101 unchanged lines hidden (view full) --- 2180system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency 2181system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency 2182system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency 2183system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2184system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2185system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2186system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2187system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2477system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits 2478system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits 2479system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits 2480system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits 2481system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2482system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2483system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits 2484system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits --- 101 unchanged lines hidden (view full) --- 2586system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency 2587system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency 2588system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency 2589system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2590system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2591system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2592system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2593system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2188system.l2c.tags.replacements 0 # number of replacements 2189system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use 2190system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 2191system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 2192system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 2193system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2194system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor 2195system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor 2196system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor 2197system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor 2198system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor 2199system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor 2200system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor 2201system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor 2202system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor 2203system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2204system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy 2205system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 2206system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy 2207system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 2208system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy 2209system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 2210system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy 2211system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2212system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy 2213system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 2214system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2215system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits 2216system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 2217system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits 2218system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 2219system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits 2220system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 2221system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits 2222system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2223system.l2c.Writeback_hits::total 1 # number of Writeback hits 2224system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2225system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2226system.l2c.demand_hits::cpu0.inst 229 # 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number of UpgradeReq misses 2256system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 2257system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 2258system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2259system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 2260system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 2261system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2262system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2263system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses 2264system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2265system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses 2266system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 2267system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses 2268system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 2269system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 2270system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2271system.l2c.demand_misses::total 674 # number of demand (read+write) misses 2272system.l2c.overall_misses::cpu0.inst 359 # number of overall misses 2273system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2274system.l2c.overall_misses::cpu1.inst 16 # number of overall misses 2275system.l2c.overall_misses::cpu1.data 13 # number of overall misses 2276system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 2277system.l2c.overall_misses::cpu2.data 20 # number of overall misses 2278system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 2279system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2280system.l2c.overall_misses::total 674 # number of overall misses 2281system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles 2282system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # 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number of ReadExReq miss cycles 2295system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles 2296system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles 2297system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles 2298system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles 2299system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles 2300system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles 2301system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles 2302system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles 2303system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles 2304system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles 2305system.l2c.overall_miss_latency::cpu0.data 12997500 # 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number of ReadReq accesses(hits+misses) 2318system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 2319system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) 2320system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 2321system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) 2322system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2323system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2324system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 2325system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 2326system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) 2327system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 2328system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 2329system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2330system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 2331system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 2332system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2333system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2334system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses 2335system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2336system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses 2337system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 2338system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses 2339system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 2340system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses 2341system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2342system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses 2343system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses 2344system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2345system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses 2346system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses 2347system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses 2348system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 2349system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses 2350system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2351system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses 2352system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses 2353system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # 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number of ReadExReq MSHR misses 2461system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2462system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2463system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses 2464system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses 2465system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses 2466system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 2467system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses 2468system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 2469system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses 2470system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2471system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 2472system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses 2473system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 2474system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses 2475system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses 2476system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses 2477system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 2478system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses 2479system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2480system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses 2481system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles 2482system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles 2483system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles 2484system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles 2485system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles 2486system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles 2487system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles 2488system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles 2489system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles 2490system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles 2491system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles 2492system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles 2493system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles 2494system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles 2495system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles 2496system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles 2497system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles 2498system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles 2499system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles 2500system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles 2501system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles 2502system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles 2503system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles 2504system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles 2505system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles 2506system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles 2507system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles 2508system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles 2509system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles 2510system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles 2511system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles 2512system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles 2513system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles 2514system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles 2515system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles 2516system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles 2517system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles 2518system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses 2519system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2520system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses 2521system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 2522system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses 2523system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 2524system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses 2525system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 2526system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses 2527system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses 2528system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2529system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2530system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2531system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses 2532system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2533system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2534system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2535system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2536system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2537system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 2538system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2539system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses 2540system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 2541system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses 2542system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 2543system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses 2544system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2545system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses 2546system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 2547system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2548system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses 2549system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 2550system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses 2551system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 2552system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses 2553system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2554system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses 2555system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency 2556system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency 2557system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency 2558system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency 2559system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency 2560system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency 2561system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency 2562system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency 2563system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency 2564system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 2565system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency 2566system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 2567system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 2568system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency 2569system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency 2570system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency 2571system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency 2572system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency 2573system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency 2574system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 2575system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 2576system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 2577system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 2578system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 2579system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 2580system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 2581system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 2582system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 2583system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 2584system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 2585system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 2586system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 2587system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 2588system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 2589system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 2590system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 2591system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 2592system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2593 2594---------- End Simulation Statistics ---------- | 2594 2595---------- End Simulation Statistics ---------- |