| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105945500 # Number of ticks simulated 5final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000110 # Number of seconds simulated 4sim_ticks 110344500 # Number of ticks simulated 5final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 48441 # Simulator instruction rate (inst/s) 8host_op_rate 48441 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4953275 # Simulator tick rate (ticks/s) 10host_mem_usage 291288 # Number of bytes of host memory used 11host_seconds 21.39 # Real time elapsed on the host 12sim_insts 1036095 # Number of instructions simulated 13sim_ops 1036095 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory | 7host_inst_rate 97195 # Simulator instruction rate (inst/s) 8host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10306929 # Simulator tick rate (ticks/s) 10host_mem_usage 249456 # Number of bytes of host memory used 11host_seconds 10.71 # Real time elapsed on the host 12sim_insts 1040548 # Number of instructions simulated 13sim_ops 1040548 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 42240 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory | 22system.physmem.bytes_read::total 42176 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::total 660 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 661 # Total number of read requests seen | 36system.physmem.num_reads::total 659 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 660 # Total number of read requests seen |
| 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady | 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady |
| 63system.physmem.bytesRead 42240 # Total number of bytes read from memory | 63system.physmem.bytesRead 42176 # Total number of bytes read from memory |
| 64system.physmem.bytesWritten 0 # Total number of bytes written to memory | 64system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 65system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() | 65system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() |
| 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q |
| 68system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis | 68system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis |
| 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis | 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis |
| 71system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis | 71system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis |
| 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 103system.physmem.totGap 105917500 # Total gap between requests | 103system.physmem.totGap 110316500 # Total gap between requests |
| 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes | 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 110system.physmem.readPktSize::6 661 # Categorize read packet sizes | 110system.physmem.readPktSize::6 660 # Categorize read packet sizes |
| 111system.physmem.writePktSize::0 0 # Categorize write packet sizes 112system.physmem.writePktSize::1 0 # Categorize write packet sizes 113system.physmem.writePktSize::2 0 # Categorize write packet sizes 114system.physmem.writePktSize::3 0 # Categorize write packet sizes 115system.physmem.writePktSize::4 0 # Categorize write packet sizes 116system.physmem.writePktSize::5 0 # Categorize write packet sizes 117system.physmem.writePktSize::6 0 # Categorize write packet sizes | 111system.physmem.writePktSize::0 0 # Categorize write packet sizes 112system.physmem.writePktSize::1 0 # Categorize write packet sizes 113system.physmem.writePktSize::2 0 # Categorize write packet sizes 114system.physmem.writePktSize::3 0 # Categorize write packet sizes 115system.physmem.writePktSize::4 0 # Categorize write packet sizes 116system.physmem.writePktSize::5 0 # Categorize write packet sizes 117system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 118system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 118system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 123system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 182system.physmem.totQLat 4080500 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests 184system.physmem.totBusLat 3305000 # Total cycles spent in databus access 185system.physmem.totBankLat 13310000 # Total cycles spent in bank access 186system.physmem.avgQLat 6173.22 # Average queueing delay per request 187system.physmem.avgBankLat 20136.16 # Average bank access latency per request | 182system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation 183system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation 184system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation 185system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation 204system.physmem.totQLat 3607500 # Total cycles spent in queuing delays 205system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests 206system.physmem.totBusLat 3300000 # Total cycles spent in databus access 207system.physmem.totBankLat 11013750 # Total cycles spent in bank access 208system.physmem.avgQLat 5465.91 # Average queueing delay per request 209system.physmem.avgBankLat 16687.50 # Average bank access latency per request |
| 188system.physmem.avgBusLat 5000.00 # Average bus latency per request | 210system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 189system.physmem.avgMemAccLat 31309.38 # Average memory access latency 190system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s | 211system.physmem.avgMemAccLat 27153.41 # Average memory access latency 212system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s |
| 191system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 213system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 192system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s | 214system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s |
| 193system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 215system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 216system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 195system.physmem.busUtil 3.11 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.19 # Average read queue length over time | 217system.physmem.busUtil 2.99 # Data bus utilization in percentage 218system.physmem.avgRdQLen 0.16 # Average read queue length over time |
| 197system.physmem.avgWrQLen 0.00 # Average write queue length over time | 219system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 198system.physmem.readRowHits 465 # Number of row buffer hits during reads | 220system.physmem.readRowHits 532 # Number of row buffer hits during reads |
| 199system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 200system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads |
| 201system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 202system.physmem.avgGap 160238.28 # Average gap between requests 203system.cpu0.branchPred.lookups 82343 # Number of BP lookups 204system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted 205system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect 206system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups 207system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits | 224system.physmem.avgGap 167146.21 # Average gap between requests 225system.membus.throughput 382221135 # Throughput (bytes/s) 226system.membus.trans_dist::ReadReq 529 # Transaction distribution 227system.membus.trans_dist::ReadResp 528 # Transaction distribution 228system.membus.trans_dist::UpgradeReq 284 # Transaction distribution 229system.membus.trans_dist::UpgradeResp 75 # Transaction distribution 230system.membus.trans_dist::ReadExReq 164 # Transaction distribution 231system.membus.trans_dist::ReadExResp 131 # Transaction distribution 232system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 42176 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 238system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) 239system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 240system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) 241system.membus.respLayer0.utilization 5.7 # Layer utilization (%) 242system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) 243system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution 244system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution 245system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 246system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution 247system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution 248system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution 249system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution 250system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) 251system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) 252system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) 253system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) 254system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) 255system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) 256system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) 257system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) 258system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) 259system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) 260system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) 261system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) 262system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) 263system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) 264system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 265system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) 266system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 267system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) 268system.toL2Bus.data_through_bus 135488 # Total data (bytes) 269system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) 270system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) 271system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 272system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) 273system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 274system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) 275system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 276system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) 277system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 278system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) 279system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) 280system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) 281system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) 282system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) 283system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) 284system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) 285system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) 286system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) 287system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) 288system.cpu0.branchPred.lookups 82851 # Number of BP lookups 289system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted 290system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect 291system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups 292system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits |
| 208system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 293system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 209system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage 210system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. | 294system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage 295system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. |
| 211system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 212system.cpu0.workload.num_syscalls 89 # Number of system calls | 296system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 297system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 213system.cpu0.numCycles 211892 # number of cpu cycles simulated | 298system.cpu0.numCycles 220690 # number of cpu cycles simulated |
| 214system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 299system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 216system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss 217system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed 218system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered 219system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken 220system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked 221system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing 222system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked | 301system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss 302system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed 303system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered 304system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken 305system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked 306system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing 307system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked |
| 223system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 308system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 224system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps 225system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched 226system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed 227system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total) 228system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total) 229system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total) | 309system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps 310system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched 311system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed 312system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) |
| 230system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 315system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 231system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total) 232system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total) 233system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) 234system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total) 235system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) 236system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total) 237system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total) 238system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total) 239system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total) | 316system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) 322system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) |
| 240system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 241system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 242system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 325system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 327system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 243system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total) 244system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle 245system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle 246system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle 247system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked 248system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running 249system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking 250system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing 251system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode 252system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing 253system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle 254system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking 255system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst 256system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running 257system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking 258system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename 259system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 260system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full 261system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed 262system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made 263system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups 264system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed 265system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing 266system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed 267system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed 268system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer 269system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit. 270system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit. 271system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads. 272system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores. 273system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec) 274system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ 275system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued 276system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued 277system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling 278system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph 279system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed 280system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle 281system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle 282system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle | 328system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) 329system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle 330system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle 331system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle 332system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked 333system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running 334system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking 335system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing 336system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode 337system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing 338system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle 339system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking 340system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst 341system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running 342system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking 343system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename 344system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full 345system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed 346system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made 347system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups 348system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed 349system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing 350system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed 351system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed 352system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer 353system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. 354system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. 355system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. 356system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. 357system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) 358system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ 359system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued 360system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued 361system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling 362system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph 363system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed 364system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle |
| 283system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 367system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 284system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle 285system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle 286system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle 287system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle 288system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle 289system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle 290system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle 291system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle | 368system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle 374system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle 375system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle |
| 292system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle 293system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 294system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 295system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 376system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 379system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 296system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle | 380system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle |
| 297system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 381system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 298system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available 299system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available 300system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available 301system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available 302system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available 303system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available 304system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available 305system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available 306system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available 307system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available 308system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available 309system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available 310system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available 311system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available 312system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available 313system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available 314system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available 315system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available 316system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available 317system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available 318system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available 319system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available 320system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available 321system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available 322system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available 323system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available 324system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available 325system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available 326system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available 327system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available 328system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available | 382system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available 383system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available 384system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available 388system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available 389system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available 390system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available 410system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available 411system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available 412system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available |
| 329system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 330system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 331system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 413system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 415system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 332system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued 333system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued 334system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued 335system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued 336system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued 337system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued 338system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued 339system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued 340system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued 341system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued 342system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued 343system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued 344system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued 345system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued 346system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued 347system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued 348system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued 349system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued 350system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued 351system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued 352system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued 353system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued 354system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued 355system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued 356system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued 357system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued 358system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued 359system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued 360system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued 361system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued 362system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued | 416system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued 417system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued 418system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued 422system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued 423system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued 424system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued 444system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued 445system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued 446system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued |
| 363system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 364system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 447system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 448system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 365system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued 366system.cpu0.iq.rate 1.891860 # Inst issue rate 367system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested 368system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) 369system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads 370system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes 371system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses | 449system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued 450system.cpu0.iq.rate 1.829381 # Inst issue rate 451system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested 452system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) 453system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads 454system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes 455system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses |
| 372system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 373system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 374system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 456system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 457system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 458system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 375system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses | 459system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses |
| 376system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 460system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 377system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores | 461system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores |
| 378system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 462system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 379system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed 380system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 381system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations 382system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed | 463system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed 464system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 465system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 466system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed |
| 383system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 384system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 385system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 467system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 468system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 469system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 386system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked | 470system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked |
| 387system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 471system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 388system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing 389system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking 390system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 391system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ 392system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch 393system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions 394system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions 395system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions 396system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall | 472system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing 473system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking 474system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking 475system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ 476system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch 477system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions 478system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions 479system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions 480system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall |
| 397system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 481system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 398system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations 399system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly 400system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly 401system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute 402system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions 403system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed 404system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute | 482system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 483system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly 484system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 485system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute 486system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions 487system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed 488system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute |
| 405system.cpu0.iew.exec_swp 0 # number of swp insts executed | 489system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 406system.cpu0.iew.exec_nop 75778 # number of nop insts executed 407system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed 408system.cpu0.iew.exec_branches 79388 # Number of branches executed 409system.cpu0.iew.exec_stores 77294 # Number of stores executed 410system.cpu0.iew.exec_rate 1.886744 # Inst execution rate 411system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit 412system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back 413system.cpu0.iew.wb_producers 236486 # num instructions producing a value 414system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value | 490system.cpu0.iew.exec_nop 76372 # number of nop insts executed 491system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed 492system.cpu0.iew.exec_branches 79993 # Number of branches executed 493system.cpu0.iew.exec_stores 77893 # Number of stores executed 494system.cpu0.iew.exec_rate 1.824559 # Inst execution rate 495system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit 496system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back 497system.cpu0.iew.wb_producers 238133 # num instructions producing a value 498system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value |
| 415system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 499system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 416system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle 417system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back | 500system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle 501system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back |
| 418system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 502system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 419system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit | 503system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit |
| 420system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards | 504system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards |
| 421system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted 422system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle 423system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle 424system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle | 505system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 506system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle |
| 425system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 509system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 426system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle 427system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle 428system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle 429system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle 430system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle 431system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle 432system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle 433system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle 434system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle | 510system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle 517system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle |
| 435system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 436system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 437system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 519system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 520system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 521system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 438system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle 439system.cpu0.commit.committedInsts 467838 # Number of instructions committed 440system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed | 522system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle 523system.cpu0.commit.committedInsts 471462 # Number of instructions committed 524system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed |
| 441system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 525system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 442system.cpu0.commit.refs 228634 # Number of memory references committed 443system.cpu0.commit.loads 152085 # Number of loads committed | 526system.cpu0.commit.refs 230446 # Number of memory references committed 527system.cpu0.commit.loads 153293 # Number of loads committed |
| 444system.cpu0.commit.membars 84 # Number of memory barriers committed | 528system.cpu0.commit.membars 84 # Number of memory barriers committed |
| 445system.cpu0.commit.branches 78436 # Number of branches committed | 529system.cpu0.commit.branches 79040 # Number of branches committed |
| 446system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 530system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
| 447system.cpu0.commit.int_insts 315322 # Number of committed integer instructions. | 531system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. |
| 448system.cpu0.commit.function_calls 223 # Number of function calls committed. | 532system.cpu0.commit.function_calls 223 # Number of function calls committed. |
| 449system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached | 533system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached |
| 450system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 534system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 451system.cpu0.rob.rob_reads 670698 # The number of ROB reads 452system.cpu0.rob.rob_writes 963274 # The number of ROB writes 453system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself 454system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling 455system.cpu0.committedInsts 392586 # Number of Instructions Simulated 456system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated 457system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated 458system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction 459system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads 460system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle 461system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads 462system.cpu0.int_regfile_reads 715161 # number of integer regfile reads 463system.cpu0.int_regfile_writes 322387 # number of integer regfile writes | 535system.cpu0.rob.rob_reads 676185 # The number of ROB reads 536system.cpu0.rob.rob_writes 969800 # The number of ROB writes 537system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself 538system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling 539system.cpu0.committedInsts 395606 # Number of Instructions Simulated 540system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated 541system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated 542system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction 543system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads 544system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle 545system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads 546system.cpu0.int_regfile_reads 720352 # number of integer regfile reads 547system.cpu0.int_regfile_writes 324661 # number of integer regfile writes |
| 464system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 548system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
| 465system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads | 549system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads |
| 466system.cpu0.misc_regfile_writes 564 # number of misc regfile writes | 550system.cpu0.misc_regfile_writes 564 # number of misc regfile writes |
| 467system.cpu0.icache.replacements 298 # number of replacements 468system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use 469system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks. 470system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. 471system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks. | 551system.cpu0.icache.replacements 297 # number of replacements 552system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use 553system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. 554system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. 555system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. |
| 472system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 556system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 473system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor 474system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy 475system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy 476system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits 477system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits 478system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits 479system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits 480system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits 481system.cpu0.icache.overall_hits::total 5155 # number of overall hits 482system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses 483system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses 484system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses 485system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses 486system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses 487system.cpu0.icache.overall_misses::total 746 # number of overall misses 488system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles 489system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles 490system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles 491system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles 492system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles 493system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles 494system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses) 495system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses) 496system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses 497system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses 498system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses 499system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses 500system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses 501system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses 502system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses 503system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses 504system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses 505system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses 506system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency 507system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency 508system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency 509system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency 510system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency 511system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency | 557system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor 558system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy 559system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy 560system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits 561system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits 562system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits 563system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits 564system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits 565system.cpu0.icache.overall_hits::total 5081 # number of overall hits 566system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses 567system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses 568system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses 569system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses 570system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses 571system.cpu0.icache.overall_misses::total 754 # number of overall misses 572system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles 573system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles 574system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles 575system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles 576system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles 577system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles 578system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 579system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 580system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 581system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 582system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 583system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 584system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses 585system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses 586system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses 587system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses 588system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # miss rate for overall accesses 589system.cpu0.icache.overall_miss_rate::total 0.129220 # miss rate for overall accesses 590system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45945.623342 # average ReadReq miss latency 591system.cpu0.icache.ReadReq_avg_miss_latency::total 45945.623342 # average ReadReq miss latency 592system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency 593system.cpu0.icache.demand_avg_miss_latency::total 45945.623342 # average overall miss latency 594system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency 595system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency |
| 512system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu0.icache.fast_writes 0 # number of fast writes performed 519system.cpu0.icache.cache_copies 0 # number of cache copies performed | 596system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu0.icache.fast_writes 0 # number of fast writes performed 603system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 520system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 156 # number of ReadReq MSHR hits 521system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits 522system.cpu0.icache.demand_mshr_hits::cpu0.inst 156 # number of demand (read+write) MSHR hits 523system.cpu0.icache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits 524system.cpu0.icache.overall_mshr_hits::cpu0.inst 156 # number of overall MSHR hits 525system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits 526system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses 527system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses 528system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses 529system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses 530system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses 531system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses 532system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21166500 # number of ReadReq MSHR miss cycles 533system.cpu0.icache.ReadReq_mshr_miss_latency::total 21166500 # number of ReadReq MSHR miss cycles 534system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21166500 # number of demand (read+write) MSHR miss cycles 535system.cpu0.icache.demand_mshr_miss_latency::total 21166500 # number of demand (read+write) MSHR miss cycles 536system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21166500 # number of overall MSHR miss cycles 537system.cpu0.icache.overall_mshr_miss_latency::total 21166500 # number of overall MSHR miss cycles 538system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for ReadReq accesses 539system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099983 # mshr miss rate for ReadReq accesses 540system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for demand accesses 541system.cpu0.icache.demand_mshr_miss_rate::total 0.099983 # mshr miss rate for demand accesses 542system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for overall accesses 543system.cpu0.icache.overall_mshr_miss_rate::total 0.099983 # mshr miss rate for overall accesses 544system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average ReadReq mshr miss latency 545system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35875.423729 # average ReadReq mshr miss latency 546system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency 547system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency 548system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency 549system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency | 604system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 166 # number of ReadReq MSHR hits 605system.cpu0.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits 606system.cpu0.icache.demand_mshr_hits::cpu0.inst 166 # number of demand (read+write) MSHR hits 607system.cpu0.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits 608system.cpu0.icache.overall_mshr_hits::cpu0.inst 166 # number of overall MSHR hits 609system.cpu0.icache.overall_mshr_hits::total 166 # number of overall MSHR hits 610system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 611system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 612system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 613system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 614system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 615system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 616system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27004002 # number of ReadReq MSHR miss cycles 617system.cpu0.icache.ReadReq_mshr_miss_latency::total 27004002 # number of ReadReq MSHR miss cycles 618system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27004002 # number of demand (read+write) MSHR miss cycles 619system.cpu0.icache.demand_mshr_miss_latency::total 27004002 # number of demand (read+write) MSHR miss cycles 620system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27004002 # number of overall MSHR miss cycles 621system.cpu0.icache.overall_mshr_miss_latency::total 27004002 # number of overall MSHR miss cycles 622system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 623system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 624system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 625system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 626system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 627system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 628system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average ReadReq mshr miss latency 629system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45925.173469 # average ReadReq mshr miss latency 630system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency 631system.cpu0.icache.demand_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency 632system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency 633system.cpu0.icache.overall_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency |
| 550system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 551system.cpu0.dcache.replacements 2 # number of replacements | 634system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 635system.cpu0.dcache.replacements 2 # number of replacements |
| 552system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use 553system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks. | 636system.cpu0.dcache.tagsinuse 141.846177 # Cycle average of tags in use 637system.cpu0.dcache.total_refs 155338 # Total number of references to valid blocks. |
| 554system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. | 638system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. |
| 555system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks. | 639system.cpu0.dcache.avg_refs 913.752941 # Average number of references to valid blocks. |
| 556system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 640system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 557system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor 558system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy 559system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy 560system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits 561system.cpu0.dcache.ReadReq_hits::total 78219 # number of ReadReq hits 562system.cpu0.dcache.WriteReq_hits::cpu0.data 75963 # number of WriteReq hits 563system.cpu0.dcache.WriteReq_hits::total 75963 # number of WriteReq hits | 641system.cpu0.dcache.occ_blocks::cpu0.data 141.846177 # Average occupied blocks per requestor 642system.cpu0.dcache.occ_percent::cpu0.data 0.277043 # Average percentage of cache occupancy 643system.cpu0.dcache.occ_percent::total 0.277043 # Average percentage of cache occupancy 644system.cpu0.dcache.ReadReq_hits::cpu0.data 78856 # number of ReadReq hits 645system.cpu0.dcache.ReadReq_hits::total 78856 # number of ReadReq hits 646system.cpu0.dcache.WriteReq_hits::cpu0.data 76566 # number of WriteReq hits 647system.cpu0.dcache.WriteReq_hits::total 76566 # number of WriteReq hits |
| 564system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 565system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits | 648system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 649system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits |
| 566system.cpu0.dcache.demand_hits::cpu0.data 154182 # number of demand (read+write) hits 567system.cpu0.dcache.demand_hits::total 154182 # number of demand (read+write) hits 568system.cpu0.dcache.overall_hits::cpu0.data 154182 # number of overall hits 569system.cpu0.dcache.overall_hits::total 154182 # number of overall hits 570system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses 571system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses 572system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses 573system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses | 650system.cpu0.dcache.demand_hits::cpu0.data 155422 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 155422 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 155422 # number of overall hits 653system.cpu0.dcache.overall_hits::total 155422 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::cpu0.data 406 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 406 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses |
| 574system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 575system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses | 658system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 659system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses |
| 576system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses 577system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses 578system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses 579system.cpu0.dcache.overall_misses::total 1019 # number of overall misses 580system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles 581system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles 582system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles 583system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles 584system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles 585system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles 586system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles 587system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles 588system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles 589system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles 590system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses) 591system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses) 592system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses) 593system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses) | 660system.cpu0.dcache.demand_misses::cpu0.data 951 # number of demand (read+write) misses 661system.cpu0.dcache.demand_misses::total 951 # number of demand (read+write) misses 662system.cpu0.dcache.overall_misses::cpu0.data 951 # number of overall misses 663system.cpu0.dcache.overall_misses::total 951 # number of overall misses 664system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12750500 # number of ReadReq miss cycles 665system.cpu0.dcache.ReadReq_miss_latency::total 12750500 # number of ReadReq miss cycles 666system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35495482 # number of WriteReq miss cycles 667system.cpu0.dcache.WriteReq_miss_latency::total 35495482 # number of WriteReq miss cycles 668system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 416500 # number of SwapReq miss cycles 669system.cpu0.dcache.SwapReq_miss_latency::total 416500 # number of SwapReq miss cycles 670system.cpu0.dcache.demand_miss_latency::cpu0.data 48245982 # number of demand (read+write) miss cycles 671system.cpu0.dcache.demand_miss_latency::total 48245982 # number of demand (read+write) miss cycles 672system.cpu0.dcache.overall_miss_latency::cpu0.data 48245982 # number of overall miss cycles 673system.cpu0.dcache.overall_miss_latency::total 48245982 # number of overall miss cycles 674system.cpu0.dcache.ReadReq_accesses::cpu0.data 79262 # number of ReadReq accesses(hits+misses) 675system.cpu0.dcache.ReadReq_accesses::total 79262 # number of ReadReq accesses(hits+misses) 676system.cpu0.dcache.WriteReq_accesses::cpu0.data 77111 # number of WriteReq accesses(hits+misses) 677system.cpu0.dcache.WriteReq_accesses::total 77111 # number of WriteReq accesses(hits+misses) |
| 594system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 595system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 678system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 679system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 596system.cpu0.dcache.demand_accesses::cpu0.data 155201 # number of demand (read+write) accesses 597system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses 598system.cpu0.dcache.overall_accesses::cpu0.data 155201 # number of overall (read+write) accesses 599system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses 600system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses 601system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses 602system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses 603system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses | 680system.cpu0.dcache.demand_accesses::cpu0.data 156373 # number of demand (read+write) accesses 681system.cpu0.dcache.demand_accesses::total 156373 # number of demand (read+write) accesses 682system.cpu0.dcache.overall_accesses::cpu0.data 156373 # number of overall (read+write) accesses 683system.cpu0.dcache.overall_accesses::total 156373 # number of overall (read+write) accesses 684system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005122 # miss rate for ReadReq accesses 685system.cpu0.dcache.ReadReq_miss_rate::total 0.005122 # miss rate for ReadReq accesses 686system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007068 # miss rate for WriteReq accesses 687system.cpu0.dcache.WriteReq_miss_rate::total 0.007068 # miss rate for WriteReq accesses |
| 604system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 605system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses | 688system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 689system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses |
| 606system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses 607system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses 608system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses 609system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses 610system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency 611system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency 612system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency 613system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency 614system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency 615system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency 616system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency 617system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency 618system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency 619system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency 620system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked | 690system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses 691system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses 692system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses 693system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses 694system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency 695system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency 696system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency 697system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency 698system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency 699system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency 700system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency 701system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency 702system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency 703system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency 704system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked |
| 621system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 705system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 622system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked | 706system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked |
| 623system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 707system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 624system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked | 708system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked |
| 625system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu0.dcache.fast_writes 0 # number of fast writes performed 627system.cpu0.dcache.cache_copies 0 # number of cache copies performed 628system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 629system.cpu0.dcache.writebacks::total 1 # number of writebacks | 709system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.cpu0.dcache.fast_writes 0 # number of fast writes performed 711system.cpu0.dcache.cache_copies 0 # number of cache copies performed 712system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 713system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 630system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits 631system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits 632system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits 633system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits 634system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits 635system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits 636system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits 637system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits 638system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses 639system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses 640system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses 641system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses | 714system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits 715system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits 716system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 717system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits 718system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits 719system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits 720system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits 721system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits 722system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses 723system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses 724system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 725system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses |
| 642system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 643system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses | 726system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 727system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses |
| 644system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 645system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 646system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 647system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses 648system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles 649system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles 650system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles 651system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles 652system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles 653system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles 654system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles 655system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles 656system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles 657system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles 658system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses 659system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses 660system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses 661system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses | 728system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses 729system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 730system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses 731system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses 732system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles 733system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles 734system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles 735system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles 736system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles 737system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles 738system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles 739system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles 740system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles 741system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles 742system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses 743system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses 744system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses 745system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses |
| 662system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 663system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses | 746system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 747system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses |
| 664system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses 665system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses 666system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses 667system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses 668system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency 669system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency 670system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency 671system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency 672system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency 673system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency 674system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency 675system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency 676system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency 677system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency | 748system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses 749system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses 750system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses 751system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses 752system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency 753system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency 754system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency 755system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency 756system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency 757system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency 758system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency 759system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency 760system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency 761system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency |
| 678system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 762system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 679system.cpu1.branchPred.lookups 56473 # Number of BP lookups 680system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted 681system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect 682system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups 683system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits | 763system.cpu1.branchPred.lookups 58259 # Number of BP lookups 764system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted 765system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect 766system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups 767system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits |
| 684system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 768system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 685system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage 686system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target. | 769system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage 770system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. |
| 687system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 771system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 688system.cpu1.numCycles 175078 # number of cpu cycles simulated | 772system.cpu1.numCycles 176870 # number of cpu cycles simulated |
| 689system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 690system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 773system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 774system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 691system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss 692system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed 693system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered 694system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken 695system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked 696system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing 697system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked | 775system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss 776system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed 777system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered 778system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken 779system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked 780system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing 781system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked |
| 698system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 782system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 699system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from 700system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps 701system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched 702system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 703system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total) 704system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total) 705system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total) | 783system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from 784system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps 785system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched 786system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed 787system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) 788system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) 789system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) |
| 706system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 790system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 707system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total) 708system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total) 709system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total) 710system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total) 711system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total) 712system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total) 713system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total) 714system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total) 715system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total) | 791system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) 792system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) 793system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) 794system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) 795system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) 796system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) 797system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) 798system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) 799system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 716system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 717system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 718system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 800system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 801system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 802system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 719system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total) 720system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle 721system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle 722system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle 723system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked 724system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running 725system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking 726system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing 727system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode 728system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing 729system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle 730system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking 731system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst 732system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running 733system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking 734system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename 735system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 736system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full 737system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed 738system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made 739system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups 740system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed 741system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing 742system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed 743system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed 744system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer 745system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit. 746system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit. 747system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads. 748system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores. 749system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec) 750system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ 751system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued 752system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued 753system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling 754system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph 755system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed 756system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle 757system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle 758system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle | 803system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) 804system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle 805system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle 806system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle 807system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked 808system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running 809system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking 810system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing 811system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode 812system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing 813system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle 814system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking 815system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst 816system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running 817system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking 818system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename 819system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full 820system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed 821system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made 822system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups 823system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed 824system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing 825system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed 826system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed 827system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer 828system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. 829system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. 830system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. 831system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. 832system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) 833system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ 834system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued 835system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued 836system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling 837system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph 838system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed 839system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle 840system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle 841system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle |
| 759system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 842system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 760system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle 761system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle 762system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle 763system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle 764system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle 765system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle 766system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle 767system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle | 843system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle 844system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle 845system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle 846system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle 847system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle 848system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle 849system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle 850system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle |
| 768system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 769system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 770system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 771system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 851system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 852system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 853system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 854system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 772system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle | 855system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle |
| 773system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 856system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 774system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available 775system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available 776system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available 777system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available 778system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available 779system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available 780system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available 781system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available 782system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available 783system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available 784system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available 785system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available 786system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available 787system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available 788system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available 789system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available 790system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available 791system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available 792system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available 793system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available 794system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available 795system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available 796system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available 797system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available 798system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available 799system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available 800system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available 801system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available 802system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available 803system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available 804system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available | 857system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available 858system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available 859system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available 860system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available 861system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available 862system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available 863system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available 864system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available 865system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available 866system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available 867system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available 868system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available 869system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available 870system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available 871system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available 872system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available 873system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available 874system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available 875system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available 876system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available 877system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available 878system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available 879system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available 880system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available 881system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available 882system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available 883system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available 884system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available 885system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available 886system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available 887system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available |
| 805system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 806system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 807system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 888system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 889system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 890system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 808system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued 809system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued 810system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued 811system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued 812system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued 813system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued 814system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued 815system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued 816system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued 817system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued 818system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued 819system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued 820system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued 821system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued 822system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued 823system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued 824system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued 825system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued 826system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued 827system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued 828system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued 829system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued 830system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued 831system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued 832system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued 833system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued 834system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued 835system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued 836system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued 837system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued 838system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued | 891system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued 892system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued 893system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued 894system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued 895system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued 896system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued 897system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued 898system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued 899system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued 900system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued 901system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued 902system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued 903system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued 904system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued 905system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued 906system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued 907system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued 908system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued 909system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued 910system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued 911system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued 912system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued 913system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued 914system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued 915system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued 916system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued 917system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued 918system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued 919system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued 920system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued 921system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued |
| 839system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 840system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 922system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 923system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 841system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued 842system.cpu1.iq.rate 1.510424 # Inst issue rate 843system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested 844system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst) 845system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads 846system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes 847system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses | 924system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued 925system.cpu1.iq.rate 1.550964 # Inst issue rate 926system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested 927system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) 928system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads 929system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes 930system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses |
| 848system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 849system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 850system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 931system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 932system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 933system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 851system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses | 934system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses |
| 852system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 935system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 853system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores | 936system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores |
| 854system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 937system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 855system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed | 938system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed |
| 856system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 939system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 857system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 858system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed | 940system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 941system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed |
| 859system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 860system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 861system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 862system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 863system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 942system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 943system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 944system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 945system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 946system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 864system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing 865system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking 866system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking 867system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ 868system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch 869system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions 870system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions 871system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions 872system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall | 947system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing 948system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking 949system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking 950system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ 951system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch 952system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions 953system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions 954system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions 955system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall |
| 873system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 956system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 874system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations 875system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 876system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly 877system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute 878system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions 879system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed 880system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute | 957system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations 958system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly 959system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly 960system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute 961system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions 962system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed 963system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute |
| 881system.cpu1.iew.exec_swp 0 # number of swp insts executed | 964system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 882system.cpu1.iew.exec_nop 44011 # number of nop insts executed 883system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed 884system.cpu1.iew.exec_branches 53318 # Number of branches executed 885system.cpu1.iew.exec_stores 43665 # Number of stores executed 886system.cpu1.iew.exec_rate 1.503964 # Inst execution rate 887system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit 888system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back 889system.cpu1.iew.wb_producers 150856 # num instructions producing a value 890system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value | 965system.cpu1.iew.exec_nop 45766 # number of nop insts executed 966system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed 967system.cpu1.iew.exec_branches 55097 # Number of branches executed 968system.cpu1.iew.exec_stores 45923 # Number of stores executed 969system.cpu1.iew.exec_rate 1.544264 # Inst execution rate 970system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit 971system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back 972system.cpu1.iew.wb_producers 157153 # num instructions producing a value 973system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value |
| 891system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 974system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 892system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle 893system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back | 975system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle 976system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back |
| 894system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 977system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 895system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit 896system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards 897system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted 898system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle 899system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle 900system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle | 978system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit 979system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards 980system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted 981system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle 982system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle 983system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle |
| 901system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 984system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 902system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle 903system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle 904system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle 905system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle 906system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle 907system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle 908system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle 909system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle 910system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle | 985system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle 986system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle 987system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle 988system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle 989system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle 990system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle 991system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle 992system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle 993system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle |
| 911system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 912system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 913system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 994system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 995system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 996system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 914system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle 915system.cpu1.commit.committedInsts 300197 # Number of instructions committed 916system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed | 997system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle 998system.cpu1.commit.committedInsts 311949 # Number of instructions committed 999system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed |
| 917system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1000system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 918system.cpu1.commit.refs 131930 # Number of memory references committed 919system.cpu1.commit.loads 88970 # Number of loads committed 920system.cpu1.commit.membars 3544 # Number of memory barriers committed 921system.cpu1.commit.branches 52469 # Number of branches committed | 1001system.cpu1.commit.refs 138308 # Number of memory references committed 1002system.cpu1.commit.loads 93049 # Number of loads committed 1003system.cpu1.commit.membars 3038 # Number of memory barriers committed 1004system.cpu1.commit.branches 54264 # Number of branches committed |
| 922system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 1005system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
| 923system.cpu1.commit.int_insts 206526 # Number of committed integer instructions. | 1006system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. |
| 924system.cpu1.commit.function_calls 322 # Number of function calls committed. | 1007system.cpu1.commit.function_calls 322 # Number of function calls committed. |
| 925system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached | 1008system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached |
| 926system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1009system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 927system.cpu1.rob.rob_reads 472949 # The number of ROB reads 928system.cpu1.rob.rob_writes 627337 # The number of ROB writes 929system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 930system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling 931system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 932system.cpu1.committedInsts 253388 # Number of Instructions Simulated 933system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated 934system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated 935system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction 936system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads 937system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle 938system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads 939system.cpu1.int_regfile_reads 460976 # number of integer regfile reads 940system.cpu1.int_regfile_writes 214498 # number of integer regfile writes | 1010system.cpu1.rob.rob_reads 484071 # The number of ROB reads 1011system.cpu1.rob.rob_writes 650455 # The number of ROB writes 1012system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself 1013system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling 1014system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1015system.cpu1.committedInsts 263856 # Number of Instructions Simulated 1016system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated 1017system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated 1018system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction 1019system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads 1020system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle 1021system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads 1022system.cpu1.int_regfile_reads 479823 # number of integer regfile reads 1023system.cpu1.int_regfile_writes 223101 # number of integer regfile writes |
| 941system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 1024system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
| 942system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads | 1025system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads |
| 943system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 944system.cpu1.icache.replacements 317 # number of replacements | 1026system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1027system.cpu1.icache.replacements 317 # number of replacements |
| 945system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use 946system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks. | 1028system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use 1029system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. |
| 947system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. | 1030system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. |
| 948system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks. | 1031system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. |
| 949system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1032system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 950system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor 951system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy 952system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy 953system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits 954system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits 955system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits 956system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits 957system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits 958system.cpu1.icache.overall_hits::total 16176 # number of overall hits 959system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses 960system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses 961system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses 962system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses 963system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses 964system.cpu1.icache.overall_misses::total 484 # number of overall misses 965system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles 966system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles 967system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles 968system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles 969system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles 970system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles 971system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses) 972system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses) 973system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses 974system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses 975system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses 976system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses 977system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses 978system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses 979system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses 980system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses 981system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses 982system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses 983system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency 984system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency 985system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency 986system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency 987system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency 988system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency 989system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked | 1033system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor 1034system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy 1035system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy 1036system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits 1037system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits 1038system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits 1039system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits 1040system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits 1041system.cpu1.icache.overall_hits::total 15036 # number of overall hits 1042system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses 1043system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses 1044system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses 1045system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses 1046system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses 1047system.cpu1.icache.overall_misses::total 487 # number of overall misses 1048system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles 1049system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles 1050system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles 1051system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles 1052system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles 1053system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles 1054system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) 1055system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) 1056system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses 1057system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses 1058system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses 1059system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses 1060system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses 1061system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses 1062system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses 1063system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses 1064system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses 1065system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses 1066system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency 1067system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency 1068system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency 1069system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency 1070system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency 1071system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency 1072system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked |
| 990system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 991system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 992system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1073system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1074system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1075system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 993system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked | 1076system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked |
| 994system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 995system.cpu1.icache.fast_writes 0 # number of fast writes performed 996system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1077system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1078system.cpu1.icache.fast_writes 0 # number of fast writes performed 1079system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 997system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits 998system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 999system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits 1000system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits 1001system.cpu1.icache.overall_mshr_hits::cpu1.inst 59 # number of overall MSHR hits 1002system.cpu1.icache.overall_mshr_hits::total 59 # number of overall MSHR hits | 1080system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits 1081system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 1082system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits 1083system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 1084system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits 1085system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits |
| 1003system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1004system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1005system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1006system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1007system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1008system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses | 1086system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1087system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1088system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1089system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1090system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1091system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses |
| 1009system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8244000 # number of ReadReq MSHR miss cycles 1010system.cpu1.icache.ReadReq_mshr_miss_latency::total 8244000 # number of ReadReq MSHR miss cycles 1011system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8244000 # number of demand (read+write) MSHR miss cycles 1012system.cpu1.icache.demand_mshr_miss_latency::total 8244000 # number of demand (read+write) MSHR miss cycles 1013system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8244000 # number of overall MSHR miss cycles 1014system.cpu1.icache.overall_mshr_miss_latency::total 8244000 # number of overall MSHR miss cycles 1015system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for ReadReq accesses 1016system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025510 # mshr miss rate for ReadReq accesses 1017system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for demand accesses 1018system.cpu1.icache.demand_mshr_miss_rate::total 0.025510 # mshr miss rate for demand accesses 1019system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for overall accesses 1020system.cpu1.icache.overall_mshr_miss_rate::total 0.025510 # mshr miss rate for overall accesses 1021system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average ReadReq mshr miss latency 1022system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19397.647059 # average ReadReq mshr miss latency 1023system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency 1024system.cpu1.icache.demand_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency 1025system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency 1026system.cpu1.icache.overall_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency | 1092system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles 1093system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles 1094system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles 1095system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles 1096system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles 1097system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles 1098system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses 1099system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses 1100system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses 1101system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses 1102system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses 1103system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses 1104system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency 1105system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency 1106system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency 1107system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency 1108system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency 1109system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency |
| 1027system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1028system.cpu1.dcache.replacements 0 # number of replacements | 1110system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1111system.cpu1.dcache.replacements 0 # number of replacements |
| 1029system.cpu1.dcache.tagsinuse 27.077196 # Cycle average of tags in use 1030system.cpu1.dcache.total_refs 49103 # Total number of references to valid blocks. 1031system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. 1032system.cpu1.dcache.avg_refs 1693.206897 # Average number of references to valid blocks. | 1112system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use 1113system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks. 1114system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1115system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks. |
| 1033system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1116system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1034system.cpu1.dcache.occ_blocks::cpu1.data 27.077196 # Average occupied blocks per requestor 1035system.cpu1.dcache.occ_percent::cpu1.data 0.052885 # Average percentage of cache occupancy 1036system.cpu1.dcache.occ_percent::total 0.052885 # Average percentage of cache occupancy 1037system.cpu1.dcache.ReadReq_hits::cpu1.data 50842 # number of ReadReq hits 1038system.cpu1.dcache.ReadReq_hits::total 50842 # number of ReadReq hits 1039system.cpu1.dcache.WriteReq_hits::cpu1.data 42756 # number of WriteReq hits 1040system.cpu1.dcache.WriteReq_hits::total 42756 # number of WriteReq hits 1041system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits 1042system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1043system.cpu1.dcache.demand_hits::cpu1.data 93598 # number of demand (read+write) hits 1044system.cpu1.dcache.demand_hits::total 93598 # number of demand (read+write) hits 1045system.cpu1.dcache.overall_hits::cpu1.data 93598 # number of overall hits 1046system.cpu1.dcache.overall_hits::total 93598 # number of overall hits 1047system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses 1048system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses | 1117system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor 1118system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy 1119system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy 1120system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits 1121system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits 1122system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits 1123system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits 1124system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 1125system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 1126system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits 1127system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits 1128system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits 1129system.cpu1.dcache.overall_hits::total 97736 # number of overall hits 1130system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses 1131system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses |
| 1049system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses 1050system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses | 1132system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses 1133system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses |
| 1051system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses 1052system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses 1053system.cpu1.dcache.demand_misses::cpu1.data 557 # number of demand (read+write) misses 1054system.cpu1.dcache.demand_misses::total 557 # number of demand (read+write) misses 1055system.cpu1.dcache.overall_misses::cpu1.data 557 # number of overall misses 1056system.cpu1.dcache.overall_misses::total 557 # number of overall misses 1057system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8012000 # number of ReadReq miss cycles 1058system.cpu1.dcache.ReadReq_miss_latency::total 8012000 # number of ReadReq miss cycles 1059system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3190500 # number of WriteReq miss cycles 1060system.cpu1.dcache.WriteReq_miss_latency::total 3190500 # number of WriteReq miss cycles 1061system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 514000 # number of SwapReq miss cycles 1062system.cpu1.dcache.SwapReq_miss_latency::total 514000 # number of SwapReq miss cycles 1063system.cpu1.dcache.demand_miss_latency::cpu1.data 11202500 # number of demand (read+write) miss cycles 1064system.cpu1.dcache.demand_miss_latency::total 11202500 # number of demand (read+write) miss cycles 1065system.cpu1.dcache.overall_miss_latency::cpu1.data 11202500 # number of overall miss cycles 1066system.cpu1.dcache.overall_miss_latency::total 11202500 # number of overall miss cycles 1067system.cpu1.dcache.ReadReq_accesses::cpu1.data 51257 # number of ReadReq accesses(hits+misses) 1068system.cpu1.dcache.ReadReq_accesses::total 51257 # number of ReadReq accesses(hits+misses) 1069system.cpu1.dcache.WriteReq_accesses::cpu1.data 42898 # number of WriteReq accesses(hits+misses) 1070system.cpu1.dcache.WriteReq_accesses::total 42898 # number of WriteReq accesses(hits+misses) 1071system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) 1072system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) 1073system.cpu1.dcache.demand_accesses::cpu1.data 94155 # number of demand (read+write) accesses 1074system.cpu1.dcache.demand_accesses::total 94155 # number of demand (read+write) accesses 1075system.cpu1.dcache.overall_accesses::cpu1.data 94155 # number of overall (read+write) accesses 1076system.cpu1.dcache.overall_accesses::total 94155 # number of overall (read+write) accesses 1077system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008096 # miss rate for ReadReq accesses 1078system.cpu1.dcache.ReadReq_miss_rate::total 0.008096 # miss rate for ReadReq accesses 1079system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003310 # miss rate for WriteReq accesses 1080system.cpu1.dcache.WriteReq_miss_rate::total 0.003310 # miss rate for WriteReq accesses 1081system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses 1082system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses 1083system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005916 # miss rate for demand accesses 1084system.cpu1.dcache.demand_miss_rate::total 0.005916 # miss rate for demand accesses 1085system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005916 # miss rate for overall accesses 1086system.cpu1.dcache.overall_miss_rate::total 0.005916 # miss rate for overall accesses 1087system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19306.024096 # average ReadReq miss latency 1088system.cpu1.dcache.ReadReq_avg_miss_latency::total 19306.024096 # average ReadReq miss latency 1089system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22468.309859 # average WriteReq miss latency 1090system.cpu1.dcache.WriteReq_avg_miss_latency::total 22468.309859 # average WriteReq miss latency 1091system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10280 # average SwapReq miss latency 1092system.cpu1.dcache.SwapReq_avg_miss_latency::total 10280 # average SwapReq miss latency 1093system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency 1094system.cpu1.dcache.demand_avg_miss_latency::total 20112.208259 # average overall miss latency 1095system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency 1096system.cpu1.dcache.overall_avg_miss_latency::total 20112.208259 # average overall miss latency | 1134system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 1135system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1136system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses 1137system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses 1138system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses 1139system.cpu1.dcache.overall_misses::total 482 # number of overall misses 1140system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles 1141system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles 1142system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles 1143system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles 1144system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles 1145system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles 1146system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles 1147system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles 1148system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles 1149system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles 1150system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) 1151system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) 1152system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) 1153system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) 1154system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) 1155system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 1156system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses 1157system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses 1158system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses 1159system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses 1160system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses 1161system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses 1162system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses 1163system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses 1164system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses 1165system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses 1166system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses 1167system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses 1168system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses 1169system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses 1170system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency 1171system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency 1172system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency 1174system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency 1175system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency 1176system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency 1177system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency 1178system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency 1179system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency |
| 1097system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1098system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1099system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1100system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1101system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1102system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1103system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1104system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1180system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1187system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1105system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 264 # number of ReadReq MSHR hits 1106system.cpu1.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits | 1188system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits 1189system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits |
| 1107system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 1108system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits | 1190system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 1191system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits |
| 1109system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits 1110system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits 1111system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits 1112system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits 1113system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses 1114system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses | 1192system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits 1193system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits 1194system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits 1195system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits 1196system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses 1197system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses |
| 1115system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses 1116system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses | 1198system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses 1199system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses |
| 1117system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses 1118system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses 1119system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses 1120system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 1121system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses 1122system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 1123system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles 1124system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles 1125system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles 1126system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles 1127system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles 1128system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles 1129system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles 1130system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles 1131system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles 1132system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles 1133system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses 1134system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses 1135system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses 1136system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses 1137system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses 1138system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses 1139system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses 1140system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses 1141system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses 1142system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses 1143system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency 1144system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency 1145system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency 1146system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency 1147system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency 1148system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency 1149system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency 1150system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency 1151system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency 1152system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency | 1200system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 1201system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1202system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 1203system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 1204system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 1205system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 1206system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles 1207system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles 1208system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles 1209system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles 1210system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles 1211system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles 1212system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles 1213system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles 1214system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles 1215system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles 1216system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses 1217system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses 1218system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses 1219system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses 1220system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses 1221system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses 1222system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses 1223system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses 1224system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses 1225system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses 1226system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency 1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency 1228system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency 1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency 1230system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency 1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency 1232system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency 1233system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency 1234system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency 1235system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency |
| 1153system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1236system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1154system.cpu2.branchPred.lookups 48435 # Number of BP lookups 1155system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted 1156system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect 1157system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups 1158system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits | 1237system.cpu2.branchPred.lookups 40256 # Number of BP lookups 1238system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted 1239system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect 1240system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups 1241system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits |
| 1159system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1242system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1160system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage 1161system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. | 1243system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage 1244system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. |
| 1162system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1245system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1163system.cpu2.numCycles 174747 # number of cpu cycles simulated | 1246system.cpu2.numCycles 176505 # number of cpu cycles simulated |
| 1164system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1165system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1247system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1248system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1166system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss 1167system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed 1168system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered 1169system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken 1170system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked 1171system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing 1172system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked 1173system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1174system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from 1175system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps 1176system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched 1177system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed 1178system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total) 1179system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total) 1180system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total) | 1249system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss 1250system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed 1251system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered 1252system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken 1253system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked 1254system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing 1255system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked 1256system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1257system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from 1258system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps 1259system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched 1260system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed 1261system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) 1262system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) 1263system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) |
| 1181system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1264system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1182system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total) 1183system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total) 1184system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total) 1185system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total) 1186system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total) 1187system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total) 1188system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total) 1189system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total) 1190system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total) | 1265system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) 1266system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) 1267system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) 1268system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) 1269system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) 1270system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) 1271system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) 1272system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) 1273system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) |
| 1191system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1192system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1193system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1274system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1275system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1276system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1194system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total) 1195system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle 1196system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle 1197system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle 1198system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked 1199system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running 1200system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking 1201system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing 1202system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode 1203system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing 1204system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle 1205system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking 1206system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst 1207system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running 1208system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking 1209system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename | 1277system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) 1278system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle 1279system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle 1280system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle 1281system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked 1282system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running 1283system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking 1284system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing 1285system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode 1286system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing 1287system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle 1288system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking 1289system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst 1290system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running 1291system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking 1292system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename |
| 1210system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full | 1293system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full |
| 1211system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full 1212system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed 1213system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made 1214system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups 1215system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed 1216system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing 1217system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed 1218system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed 1219system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer 1220system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit. 1221system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit. 1222system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads. 1223system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores. 1224system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec) 1225system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ 1226system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued 1227system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued 1228system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling 1229system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph 1230system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed 1231system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle 1232system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle 1233system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle | 1294system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full 1295system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed 1296system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made 1297system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups 1298system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed 1299system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing 1300system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed 1301system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed 1302system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer 1303system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. 1304system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. 1305system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. 1306system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. 1307system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) 1308system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ 1309system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued 1310system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued 1311system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling 1312system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph 1313system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed 1314system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle 1315system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle 1316system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle |
| 1234system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1317system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1235system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle 1236system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle 1237system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle 1238system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle 1239system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle 1240system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle 1241system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle 1242system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle 1243system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle | 1318system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle 1319system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle 1320system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle 1321system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle 1322system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle 1323system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle 1324system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle 1325system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 1326system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle |
| 1244system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1245system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1246system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1327system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1328system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1329system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1247system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle | 1330system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle |
| 1248system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1331system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1249system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available 1250system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available 1251system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available 1252system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available 1253system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available 1254system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available 1255system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available 1256system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available 1257system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available 1258system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available 1259system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available 1260system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available 1261system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available 1262system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available 1263system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available 1264system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available 1265system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available 1266system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available 1267system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available 1268system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available 1269system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available 1270system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available 1271system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available 1272system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available 1273system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available 1274system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available 1275system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available 1276system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available 1277system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available 1278system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available 1279system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available | 1332system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available 1333system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available 1334system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available 1335system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available 1336system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available 1337system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available 1338system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available 1339system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available 1340system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available 1341system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available 1342system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available 1343system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available 1344system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available 1345system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available 1346system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available 1347system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available 1348system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available 1349system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available 1350system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available 1351system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available 1352system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available 1353system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available 1354system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available 1355system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available 1356system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available 1357system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available 1358system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available 1359system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available 1360system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available 1361system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available 1362system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available |
| 1280system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1281system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1282system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1363system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1364system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1365system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1283system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued 1284system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued 1285system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued 1286system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued 1287system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued 1288system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued 1289system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued 1290system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued 1291system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued 1292system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued 1293system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued 1294system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued 1295system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued 1296system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued 1297system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued 1298system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued 1299system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued 1300system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued 1301system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued 1302system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued 1303system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued 1304system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued 1305system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued 1306system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued 1307system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued 1308system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued 1309system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued 1310system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued 1311system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued 1312system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued 1313system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued | 1366system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued 1367system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued 1368system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued 1369system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued 1370system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued 1371system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued 1372system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued 1373system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued 1374system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued 1375system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued 1376system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued 1377system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued 1378system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued 1379system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued 1380system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued 1381system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued 1382system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued 1383system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued 1384system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued 1385system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued 1386system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued 1387system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued 1388system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued 1389system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued 1390system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued 1391system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued 1392system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued 1393system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued 1394system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued 1395system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued 1396system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued |
| 1314system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1315system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1397system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1398system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1316system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued 1317system.cpu2.iq.rate 1.246190 # Inst issue rate 1318system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested 1319system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) 1320system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads 1321system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes 1322system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses | 1399system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued 1400system.cpu2.iq.rate 0.975530 # Inst issue rate 1401system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested 1402system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) 1403system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads 1404system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes 1405system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses |
| 1323system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1324system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1325system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1406system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1407system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1408system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1326system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses | 1409system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses |
| 1327system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1410system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1328system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores | 1411system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores |
| 1329system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1412system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1330system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed | 1413system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed |
| 1331system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1332system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations | 1414system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1415system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations |
| 1333system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed | 1416system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed |
| 1334system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1335system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1336system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1337system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1338system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1417system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1418system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1419system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1420system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1421system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1339system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing 1340system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking 1341system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking 1342system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ 1343system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch 1344system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions 1345system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions 1346system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions 1347system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall | 1422system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing 1423system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking 1424system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking 1425system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ 1426system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch 1427system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions 1428system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions 1429system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions 1430system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall |
| 1348system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1349system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations | 1431system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1432system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations |
| 1350system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1351system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly 1352system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute 1353system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions 1354system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed 1355system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute | 1433system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly 1434system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly 1435system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute 1436system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions 1437system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed 1438system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute |
| 1356system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1439system.cpu2.iew.exec_swp 0 # number of swp insts executed |
| 1357system.cpu2.iew.exec_nop 35937 # number of nop insts executed 1358system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed 1359system.cpu2.iew.exec_branches 45106 # Number of branches executed 1360system.cpu2.iew.exec_stores 32695 # Number of stores executed 1361system.cpu2.iew.exec_rate 1.239535 # Inst execution rate 1362system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit 1363system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back 1364system.cpu2.iew.wb_producers 120625 # num instructions producing a value 1365system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value | 1440system.cpu2.iew.exec_nop 27820 # number of nop insts executed 1441system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed 1442system.cpu2.iew.exec_branches 36982 # Number of branches executed 1443system.cpu2.iew.exec_stores 22143 # Number of stores executed 1444system.cpu2.iew.exec_rate 0.969321 # Inst execution rate 1445system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit 1446system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back 1447system.cpu2.iew.wb_producers 91387 # num instructions producing a value 1448system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value |
| 1366system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1449system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1367system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle 1368system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back | 1450system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle 1451system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back |
| 1369system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1452system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1370system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit 1371system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards 1372system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted 1373system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle 1374system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle 1375system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle | 1453system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit 1454system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards 1455system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted 1456system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle 1457system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle 1458system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle |
| 1376system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1459system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1377system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle 1378system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle 1379system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle 1380system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle 1381system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle 1382system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle 1383system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle 1384system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle 1385system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle | 1460system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle 1461system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle 1462system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle 1463system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle 1464system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle 1465system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle 1466system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle 1467system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle 1468system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle |
| 1386system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1387system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1388system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1469system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1470system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1471system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1389system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle 1390system.cpu2.commit.committedInsts 245558 # Number of instructions committed 1391system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed | 1472system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle 1473system.cpu2.commit.committedInsts 192088 # Number of instructions committed 1474system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed |
| 1392system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 1475system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
| 1393system.cpu2.commit.refs 101851 # Number of memory references committed 1394system.cpu2.commit.loads 69824 # Number of loads committed 1395system.cpu2.commit.membars 6301 # Number of memory barriers committed 1396system.cpu2.commit.branches 44289 # Number of branches committed | 1476system.cpu2.commit.refs 72624 # Number of memory references committed 1477system.cpu2.commit.loads 51171 # Number of loads committed 1478system.cpu2.commit.membars 8798 # Number of memory barriers committed 1479system.cpu2.commit.branches 36206 # Number of branches committed |
| 1397system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 1480system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1398system.cpu2.commit.int_insts 168258 # Number of committed integer instructions. | 1481system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. |
| 1399system.cpu2.commit.function_calls 322 # Number of function calls committed. | 1482system.cpu2.commit.function_calls 322 # Number of function calls committed. |
| 1400system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached | 1483system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached |
| 1401system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits | 1484system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1402system.cpu2.rob.rob_reads 421045 # The number of ROB reads 1403system.cpu2.rob.rob_writes 518771 # The number of ROB writes 1404system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself 1405system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling 1406system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1407system.cpu2.committedInsts 204183 # Number of Instructions Simulated 1408system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated 1409system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated 1410system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction 1411system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads 1412system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle 1413system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads 1414system.cpu2.int_regfile_reads 370277 # number of integer regfile reads 1415system.cpu2.int_regfile_writes 173276 # number of integer regfile writes | 1485system.cpu2.rob.rob_reads 367870 # The number of ROB reads 1486system.cpu2.rob.rob_writes 411061 # The number of ROB writes 1487system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 1488system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling 1489system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1490system.cpu2.committedInsts 156297 # Number of Instructions Simulated 1491system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated 1492system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated 1493system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction 1494system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads 1495system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle 1496system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads 1497system.cpu2.int_regfile_reads 282509 # number of integer regfile reads 1498system.cpu2.int_regfile_writes 133289 # number of integer regfile writes |
| 1416system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 1499system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
| 1417system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads | 1500system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads |
| 1418system.cpu2.misc_regfile_writes 648 # number of misc regfile writes | 1501system.cpu2.misc_regfile_writes 648 # number of misc regfile writes |
| 1419system.cpu2.icache.replacements 319 # number of replacements 1420system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use 1421system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks. 1422system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. 1423system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks. | 1502system.cpu2.icache.replacements 318 # number of replacements 1503system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use 1504system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. 1505system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. 1506system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. |
| 1424system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1507system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1425system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor 1426system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy 1427system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy 1428system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits 1429system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits 1430system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits 1431system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits 1432system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits 1433system.cpu2.icache.overall_hits::total 21789 # number of overall hits 1434system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses 1435system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses 1436system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses 1437system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses 1438system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses 1439system.cpu2.icache.overall_misses::total 478 # number of overall misses 1440system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles 1441system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles 1442system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles 1443system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles 1444system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles 1445system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles 1446system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses) 1447system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses) 1448system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses 1449system.cpu2.icache.demand_accesses::total 22267 # number of demand (read+write) accesses 1450system.cpu2.icache.overall_accesses::cpu2.inst 22267 # number of overall (read+write) accesses 1451system.cpu2.icache.overall_accesses::total 22267 # number of overall (read+write) accesses 1452system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021467 # miss rate for ReadReq accesses 1453system.cpu2.icache.ReadReq_miss_rate::total 0.021467 # miss rate for ReadReq accesses 1454system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021467 # miss rate for demand accesses 1455system.cpu2.icache.demand_miss_rate::total 0.021467 # miss rate for demand accesses 1456system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021467 # miss rate for overall accesses 1457system.cpu2.icache.overall_miss_rate::total 0.021467 # miss rate for overall accesses 1458system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14296.025105 # average ReadReq miss latency 1459system.cpu2.icache.ReadReq_avg_miss_latency::total 14296.025105 # average ReadReq miss latency 1460system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency 1461system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency 1462system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency 1463system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency 1464system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1508system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor 1509system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy 1510system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy 1511system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits 1512system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits 1513system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits 1514system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits 1515system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits 1516system.cpu2.icache.overall_hits::total 26999 # number of overall hits 1517system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses 1518system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses 1519system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses 1520system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses 1521system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses 1522system.cpu2.icache.overall_misses::total 474 # number of overall misses 1523system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles 1524system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles 1525system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles 1526system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles 1527system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles 1528system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles 1529system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses) 1530system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses) 1531system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses 1532system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses 1533system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses 1534system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses 1535system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses 1536system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses 1537system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses 1538system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses 1539system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses 1540system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses 1541system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency 1542system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency 1543system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency 1544system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency 1545system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency 1546system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency 1547system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked |
| 1465system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1548system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1466system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 1549system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 1467system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked | 1550system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1468system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1551system.cpu2.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked |
| 1469system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1470system.cpu2.icache.fast_writes 0 # number of fast writes performed 1471system.cpu2.icache.cache_copies 0 # number of cache copies performed | 1552system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1553system.cpu2.icache.fast_writes 0 # number of fast writes performed 1554system.cpu2.icache.cache_copies 0 # number of cache copies performed |
| 1472system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits 1473system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1474system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits 1475system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1476system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits 1477system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1478system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses 1479system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1480system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses 1481system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 1482system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses 1483system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 1484system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5518500 # number of ReadReq MSHR miss cycles 1485system.cpu2.icache.ReadReq_mshr_miss_latency::total 5518500 # number of ReadReq MSHR miss cycles 1486system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5518500 # number of demand (read+write) MSHR miss cycles 1487system.cpu2.icache.demand_mshr_miss_latency::total 5518500 # number of demand (read+write) MSHR miss cycles 1488system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5518500 # number of overall MSHR miss cycles 1489system.cpu2.icache.overall_mshr_miss_latency::total 5518500 # number of overall MSHR miss cycles 1490system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for ReadReq accesses 1491system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses 1492system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for demand accesses 1493system.cpu2.icache.demand_mshr_miss_rate::total 0.019311 # mshr miss rate for demand accesses 1494system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for overall accesses 1495system.cpu2.icache.overall_mshr_miss_rate::total 0.019311 # mshr miss rate for overall accesses 1496system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average ReadReq mshr miss latency 1497system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12833.720930 # average ReadReq mshr miss latency 1498system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency 1499system.cpu2.icache.demand_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency 1500system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency 1501system.cpu2.icache.overall_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency | 1555system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits 1556system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1557system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits 1558system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1559system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits 1560system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1561system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 428 # number of ReadReq MSHR misses 1562system.cpu2.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1563system.cpu2.icache.demand_mshr_misses::cpu2.inst 428 # number of demand (read+write) MSHR misses 1564system.cpu2.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1565system.cpu2.icache.overall_mshr_misses::cpu2.inst 428 # number of overall MSHR misses 1566system.cpu2.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1567system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5331008 # number of ReadReq MSHR miss cycles 1568system.cpu2.icache.ReadReq_mshr_miss_latency::total 5331008 # number of ReadReq MSHR miss cycles 1569system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5331008 # number of demand (read+write) MSHR miss cycles 1570system.cpu2.icache.demand_mshr_miss_latency::total 5331008 # number of demand (read+write) MSHR miss cycles 1571system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5331008 # number of overall MSHR miss cycles 1572system.cpu2.icache.overall_mshr_miss_latency::total 5331008 # number of overall MSHR miss cycles 1573system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for ReadReq accesses 1574system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.015579 # mshr miss rate for ReadReq accesses 1575system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for demand accesses 1576system.cpu2.icache.demand_mshr_miss_rate::total 0.015579 # mshr miss rate for demand accesses 1577system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for overall accesses 1578system.cpu2.icache.overall_mshr_miss_rate::total 0.015579 # mshr miss rate for overall accesses 1579system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average ReadReq mshr miss latency 1580system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12455.626168 # average ReadReq mshr miss latency 1581system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency 1582system.cpu2.icache.demand_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency 1583system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency 1584system.cpu2.icache.overall_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency |
| 1502system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1503system.cpu2.dcache.replacements 0 # number of replacements | 1585system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1586system.cpu2.dcache.replacements 0 # number of replacements |
| 1504system.cpu2.dcache.tagsinuse 25.660288 # Cycle average of tags in use 1505system.cpu2.dcache.total_refs 38032 # Total number of references to valid blocks. 1506system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1507system.cpu2.dcache.avg_refs 1358.285714 # Average number of references to valid blocks. | 1587system.cpu2.dcache.tagsinuse 23.628047 # Cycle average of tags in use 1588system.cpu2.dcache.total_refs 27574 # Total number of references to valid blocks. 1589system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. 1590system.cpu2.dcache.avg_refs 950.827586 # Average number of references to valid blocks. |
| 1508system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1591system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1509system.cpu2.dcache.occ_blocks::cpu2.data 25.660288 # Average occupied blocks per requestor 1510system.cpu2.dcache.occ_percent::cpu2.data 0.050118 # Average percentage of cache occupancy 1511system.cpu2.dcache.occ_percent::total 0.050118 # Average percentage of cache occupancy 1512system.cpu2.dcache.ReadReq_hits::cpu2.data 42624 # number of ReadReq hits 1513system.cpu2.dcache.ReadReq_hits::total 42624 # number of ReadReq hits 1514system.cpu2.dcache.WriteReq_hits::cpu2.data 31820 # number of WriteReq hits 1515system.cpu2.dcache.WriteReq_hits::total 31820 # number of WriteReq hits 1516system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits 1517system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 1518system.cpu2.dcache.demand_hits::cpu2.data 74444 # number of demand (read+write) hits 1519system.cpu2.dcache.demand_hits::total 74444 # number of demand (read+write) hits 1520system.cpu2.dcache.overall_hits::cpu2.data 74444 # number of overall hits 1521system.cpu2.dcache.overall_hits::total 74444 # number of overall hits 1522system.cpu2.dcache.ReadReq_misses::cpu2.data 407 # number of ReadReq misses 1523system.cpu2.dcache.ReadReq_misses::total 407 # number of ReadReq misses | 1592system.cpu2.dcache.occ_blocks::cpu2.data 23.628047 # Average occupied blocks per requestor 1593system.cpu2.dcache.occ_percent::cpu2.data 0.046149 # Average percentage of cache occupancy 1594system.cpu2.dcache.occ_percent::total 0.046149 # Average percentage of cache occupancy 1595system.cpu2.dcache.ReadReq_hits::cpu2.data 34611 # number of ReadReq hits 1596system.cpu2.dcache.ReadReq_hits::total 34611 # number of ReadReq hits 1597system.cpu2.dcache.WriteReq_hits::cpu2.data 21248 # number of WriteReq hits 1598system.cpu2.dcache.WriteReq_hits::total 21248 # number of WriteReq hits 1599system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits 1600system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits 1601system.cpu2.dcache.demand_hits::cpu2.data 55859 # number of demand (read+write) hits 1602system.cpu2.dcache.demand_hits::total 55859 # number of demand (read+write) hits 1603system.cpu2.dcache.overall_hits::cpu2.data 55859 # number of overall hits 1604system.cpu2.dcache.overall_hits::total 55859 # number of overall hits 1605system.cpu2.dcache.ReadReq_misses::cpu2.data 317 # number of ReadReq misses 1606system.cpu2.dcache.ReadReq_misses::total 317 # number of ReadReq misses |
| 1524system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses 1525system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses | 1607system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses 1608system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses |
| 1526system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses 1527system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses 1528system.cpu2.dcache.demand_misses::cpu2.data 541 # number of demand (read+write) misses 1529system.cpu2.dcache.demand_misses::total 541 # number of demand (read+write) misses 1530system.cpu2.dcache.overall_misses::cpu2.data 541 # number of overall misses 1531system.cpu2.dcache.overall_misses::total 541 # number of overall misses 1532system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5612500 # number of ReadReq miss cycles 1533system.cpu2.dcache.ReadReq_miss_latency::total 5612500 # number of ReadReq miss cycles 1534system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2750000 # number of WriteReq miss cycles 1535system.cpu2.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles 1536system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 572000 # number of SwapReq miss cycles 1537system.cpu2.dcache.SwapReq_miss_latency::total 572000 # number of SwapReq miss cycles 1538system.cpu2.dcache.demand_miss_latency::cpu2.data 8362500 # number of demand (read+write) miss cycles 1539system.cpu2.dcache.demand_miss_latency::total 8362500 # number of demand (read+write) miss cycles 1540system.cpu2.dcache.overall_miss_latency::cpu2.data 8362500 # number of overall miss cycles 1541system.cpu2.dcache.overall_miss_latency::total 8362500 # number of overall miss cycles 1542system.cpu2.dcache.ReadReq_accesses::cpu2.data 43031 # number of ReadReq accesses(hits+misses) 1543system.cpu2.dcache.ReadReq_accesses::total 43031 # number of ReadReq accesses(hits+misses) 1544system.cpu2.dcache.WriteReq_accesses::cpu2.data 31954 # number of WriteReq accesses(hits+misses) 1545system.cpu2.dcache.WriteReq_accesses::total 31954 # number of WriteReq accesses(hits+misses) 1546system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) 1547system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) 1548system.cpu2.dcache.demand_accesses::cpu2.data 74985 # number of demand (read+write) accesses 1549system.cpu2.dcache.demand_accesses::total 74985 # number of demand (read+write) accesses 1550system.cpu2.dcache.overall_accesses::cpu2.data 74985 # number of overall (read+write) accesses 1551system.cpu2.dcache.overall_accesses::total 74985 # number of overall (read+write) accesses 1552system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009458 # miss rate for ReadReq accesses 1553system.cpu2.dcache.ReadReq_miss_rate::total 0.009458 # miss rate for ReadReq accesses 1554system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004194 # miss rate for WriteReq accesses 1555system.cpu2.dcache.WriteReq_miss_rate::total 0.004194 # miss rate for WriteReq accesses 1556system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses 1557system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses 1558system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007215 # miss rate for demand accesses 1559system.cpu2.dcache.demand_miss_rate::total 0.007215 # miss rate for demand accesses 1560system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007215 # miss rate for overall accesses 1561system.cpu2.dcache.overall_miss_rate::total 0.007215 # miss rate for overall accesses 1562system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13789.926290 # average ReadReq miss latency 1563system.cpu2.dcache.ReadReq_avg_miss_latency::total 13789.926290 # average ReadReq miss latency 1564system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20522.388060 # average WriteReq miss latency 1565system.cpu2.dcache.WriteReq_avg_miss_latency::total 20522.388060 # average WriteReq miss latency 1566system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9862.068966 # average SwapReq miss latency 1567system.cpu2.dcache.SwapReq_avg_miss_latency::total 9862.068966 # average SwapReq miss latency 1568system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency 1569system.cpu2.dcache.demand_avg_miss_latency::total 15457.486137 # average overall miss latency 1570system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency 1571system.cpu2.dcache.overall_avg_miss_latency::total 15457.486137 # average overall miss latency | 1609system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 1610system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 1611system.cpu2.dcache.demand_misses::cpu2.data 451 # number of demand (read+write) misses 1612system.cpu2.dcache.demand_misses::total 451 # number of demand (read+write) misses 1613system.cpu2.dcache.overall_misses::cpu2.data 451 # number of overall misses 1614system.cpu2.dcache.overall_misses::total 451 # number of overall misses 1615system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3712500 # number of ReadReq miss cycles 1616system.cpu2.dcache.ReadReq_miss_latency::total 3712500 # number of ReadReq miss cycles 1617system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2774500 # number of WriteReq miss cycles 1618system.cpu2.dcache.WriteReq_miss_latency::total 2774500 # number of WriteReq miss cycles 1619system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 533000 # number of SwapReq miss cycles 1620system.cpu2.dcache.SwapReq_miss_latency::total 533000 # number of SwapReq miss cycles 1621system.cpu2.dcache.demand_miss_latency::cpu2.data 6487000 # number of demand (read+write) miss cycles 1622system.cpu2.dcache.demand_miss_latency::total 6487000 # number of demand (read+write) miss cycles 1623system.cpu2.dcache.overall_miss_latency::cpu2.data 6487000 # number of overall miss cycles 1624system.cpu2.dcache.overall_miss_latency::total 6487000 # number of overall miss cycles 1625system.cpu2.dcache.ReadReq_accesses::cpu2.data 34928 # number of ReadReq accesses(hits+misses) 1626system.cpu2.dcache.ReadReq_accesses::total 34928 # number of ReadReq accesses(hits+misses) 1627system.cpu2.dcache.WriteReq_accesses::cpu2.data 21382 # number of WriteReq accesses(hits+misses) 1628system.cpu2.dcache.WriteReq_accesses::total 21382 # number of WriteReq accesses(hits+misses) 1629system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) 1630system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 1631system.cpu2.dcache.demand_accesses::cpu2.data 56310 # number of demand (read+write) accesses 1632system.cpu2.dcache.demand_accesses::total 56310 # number of demand (read+write) accesses 1633system.cpu2.dcache.overall_accesses::cpu2.data 56310 # number of overall (read+write) accesses 1634system.cpu2.dcache.overall_accesses::total 56310 # number of overall (read+write) accesses 1635system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009076 # miss rate for ReadReq accesses 1636system.cpu2.dcache.ReadReq_miss_rate::total 0.009076 # miss rate for ReadReq accesses 1637system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006267 # miss rate for WriteReq accesses 1638system.cpu2.dcache.WriteReq_miss_rate::total 0.006267 # miss rate for WriteReq accesses 1639system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.760563 # miss rate for SwapReq accesses 1640system.cpu2.dcache.SwapReq_miss_rate::total 0.760563 # miss rate for SwapReq accesses 1641system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008009 # miss rate for demand accesses 1642system.cpu2.dcache.demand_miss_rate::total 0.008009 # miss rate for demand accesses 1643system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008009 # miss rate for overall accesses 1644system.cpu2.dcache.overall_miss_rate::total 0.008009 # miss rate for overall accesses 1645system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 11711.356467 # average ReadReq miss latency 1646system.cpu2.dcache.ReadReq_avg_miss_latency::total 11711.356467 # average ReadReq miss latency 1647system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20705.223881 # average WriteReq miss latency 1648system.cpu2.dcache.WriteReq_avg_miss_latency::total 20705.223881 # average WriteReq miss latency 1649system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9870.370370 # average SwapReq miss latency 1650system.cpu2.dcache.SwapReq_avg_miss_latency::total 9870.370370 # average SwapReq miss latency 1651system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency 1652system.cpu2.dcache.demand_avg_miss_latency::total 14383.592018 # average overall miss latency 1653system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency 1654system.cpu2.dcache.overall_avg_miss_latency::total 14383.592018 # average overall miss latency |
| 1572system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1573system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1574system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1575system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1576system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1577system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1578system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1579system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 1655system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1656system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1657system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1658system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1659system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1660system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1661system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1662system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 1580system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits 1581system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits | 1663system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits 1664system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits |
| 1582system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 1583system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits | 1665system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 1666system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits |
| 1584system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits 1585system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits 1586system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits 1587system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits | 1667system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits 1668system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits 1669system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits 1670system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits |
| 1588system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 1589system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1590system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses 1591system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses | 1671system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 1672system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1673system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses 1674system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses |
| 1592system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses 1593system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses | 1675system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses 1676system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses |
| 1594system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1595system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1596system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1597system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses | 1677system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses 1678system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 1679system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses 1680system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses |
| 1598system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles 1599system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles 1600system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles 1601system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles 1602system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles 1603system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles 1604system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles 1605system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles 1606system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles 1607system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles 1608system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses 1609system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses 1610system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses 1611system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses 1612system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses 1613system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses 1614system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses 1615system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses 1616system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses 1617system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses 1618system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency 1619system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency 1620system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency 1621system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency 1622system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency 1623system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency 1624system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency 1625system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency 1626system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency 1627system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency | 1681system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles 1682system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles 1683system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles 1684system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles 1685system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles 1686system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles 1687system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles 1688system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles 1689system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles 1690system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles 1691system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses 1692system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses 1693system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses 1694system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses 1695system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses 1696system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses 1697system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses 1698system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses 1699system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses 1700system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses 1701system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency 1702system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency 1703system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency 1704system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency 1705system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency 1706system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency 1707system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency 1708system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency 1709system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency 1710system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency |
| 1628system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1711system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1629system.cpu3.branchPred.lookups 45379 # Number of BP lookups 1630system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted 1631system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect 1632system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups 1633system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits | 1712system.cpu3.branchPred.lookups 52069 # Number of BP lookups 1713system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted 1714system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect 1715system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups 1716system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits |
| 1634system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1717system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1635system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage 1636system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target. | 1718system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage 1719system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. |
| 1637system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1720system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1638system.cpu3.numCycles 174437 # number of cpu cycles simulated | 1721system.cpu3.numCycles 176161 # number of cpu cycles simulated |
| 1639system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1640system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 1722system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1723system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1641system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss 1642system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed 1643system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered 1644system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken 1645system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked 1646system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing 1647system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked | 1724system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss 1725system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed 1726system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered 1727system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken 1728system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked 1729system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing 1730system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked |
| 1648system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 1731system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1649system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from 1650system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps 1651system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched 1652system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed 1653system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total) 1654system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total) 1655system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total) | 1732system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from 1733system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps 1734system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched 1735system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed 1736system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) 1737system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) 1738system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) |
| 1656system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1739system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1657system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total) 1658system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total) 1659system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total) 1660system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total) 1661system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total) 1662system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total) 1663system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total) 1664system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total) 1665system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total) | 1740system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) 1741system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) 1742system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) 1743system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) 1744system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) 1745system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) 1746system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) 1747system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) 1748system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) |
| 1666system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1667system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1668system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1749system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1750system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1751system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1669system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total) 1670system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle 1671system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle 1672system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle 1673system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked 1674system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running 1675system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking 1676system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing 1677system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode 1678system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing 1679system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle 1680system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking 1681system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst 1682system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running 1683system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking 1684system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename 1685system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1686system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full 1687system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed 1688system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made 1689system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups 1690system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed 1691system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing 1692system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed 1693system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed 1694system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer 1695system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit. 1696system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit. 1697system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads. 1698system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores. 1699system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec) 1700system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ 1701system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued 1702system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued 1703system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling 1704system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph 1705system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed 1706system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle 1707system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle 1708system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle | 1752system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) 1753system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle 1754system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle 1755system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle 1756system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked 1757system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running 1758system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking 1759system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing 1760system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode 1761system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing 1762system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle 1763system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking 1764system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst 1765system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running 1766system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking 1767system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename 1768system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full 1769system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full 1770system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed 1771system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made 1772system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups 1773system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed 1774system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing 1775system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed 1776system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed 1777system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer 1778system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. 1779system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. 1780system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. 1781system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. 1782system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) 1783system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ 1784system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued 1785system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued 1786system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling 1787system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph 1788system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed 1789system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle 1790system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle 1791system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle |
| 1709system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1792system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1710system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle 1711system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle 1712system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle 1713system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle 1714system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle 1715system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle 1716system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle 1717system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle 1718system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle | 1793system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle 1794system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle 1795system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle 1796system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle 1797system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle 1798system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle 1799system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle 1800system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 1801system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle |
| 1719system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1720system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1721system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1802system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1803system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1804system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1722system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle | 1805system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle |
| 1723system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1806system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1724system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available 1725system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available 1726system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available 1727system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available 1728system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available 1729system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available 1730system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available 1731system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available 1732system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available 1733system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available 1734system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available 1735system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available 1736system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available 1737system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available 1738system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available 1739system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available 1740system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available 1741system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available 1742system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available 1743system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available 1744system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available 1745system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available 1746system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available 1747system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available 1748system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available 1749system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available 1750system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available 1751system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available 1752system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available 1753system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available 1754system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available | 1807system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available 1808system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available 1809system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available 1810system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available 1811system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available 1812system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available 1813system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available 1814system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available 1815system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available 1816system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available 1817system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available 1818system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available 1819system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available 1820system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available 1821system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available 1822system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available 1823system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available 1824system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available 1825system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available 1826system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available 1827system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available 1828system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available 1829system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available 1830system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available 1831system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available 1832system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available 1833system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available 1834system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available 1835system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available 1836system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available 1837system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available |
| 1755system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1756system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1757system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1838system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1839system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1840system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1758system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued 1759system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued 1760system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued 1761system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued 1762system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued 1763system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued 1764system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued 1765system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued 1766system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued 1767system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued 1768system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued 1769system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued 1770system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued 1771system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued 1772system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued 1773system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued 1774system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued 1775system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued 1776system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued 1777system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued 1778system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued 1779system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued 1780system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued 1781system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued 1782system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued 1783system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued 1784system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued 1785system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued 1786system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued 1787system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued 1788system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued | 1841system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued 1842system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued 1843system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued 1844system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued 1845system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued 1846system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued 1847system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued 1848system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued 1849system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued 1850system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued 1851system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued 1852system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued 1853system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued 1854system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued 1855system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued 1856system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued 1857system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued 1858system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued 1859system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued 1860system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued 1861system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued 1862system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued 1863system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued 1864system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued 1865system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued 1866system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued 1867system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued 1868system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued 1869system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued 1870system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued 1871system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued |
| 1789system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1790system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1872system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1873system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1791system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued 1792system.cpu3.iq.rate 1.148908 # Inst issue rate 1793system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested 1794system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst) 1795system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads 1796system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes 1797system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses | 1874system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued 1875system.cpu3.iq.rate 1.349169 # Inst issue rate 1876system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested 1877system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) 1878system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads 1879system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes 1880system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses |
| 1798system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1799system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1800system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1881system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1882system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1883system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1801system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses | 1884system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses |
| 1802system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1885system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1803system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores | 1886system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores |
| 1804system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1887system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1805system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed | 1888system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed |
| 1806system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1889system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 1807system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 1808system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed | 1890system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations 1891system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed |
| 1809system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1810system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1811system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1812system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1813system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1892system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1893system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1894system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1895system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1896system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1814system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing 1815system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking 1816system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking 1817system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ 1818system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch 1819system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions 1820system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions 1821system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions 1822system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall | 1897system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing 1898system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking 1899system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 1900system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ 1901system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch 1902system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions 1903system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions 1904system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions 1905system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall |
| 1823system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1906system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 1824system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations 1825system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly 1826system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly 1827system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute 1828system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions 1829system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed 1830system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute | 1907system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations 1908system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly 1909system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly 1910system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute 1911system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions 1912system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed 1913system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute |
| 1831system.cpu3.iew.exec_swp 0 # number of swp insts executed | 1914system.cpu3.iew.exec_swp 0 # number of swp insts executed |
| 1832system.cpu3.iew.exec_nop 32807 # number of nop insts executed 1833system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed 1834system.cpu3.iew.exec_branches 41971 # Number of branches executed 1835system.cpu3.iew.exec_stores 28736 # Number of stores executed 1836system.cpu3.iew.exec_rate 1.142235 # Inst execution rate 1837system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit 1838system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back 1839system.cpu3.iew.wb_producers 109565 # num instructions producing a value 1840system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value | 1915system.cpu3.iew.exec_nop 39523 # number of nop insts executed 1916system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed 1917system.cpu3.iew.exec_branches 48746 # Number of branches executed 1918system.cpu3.iew.exec_stores 37155 # Number of stores executed 1919system.cpu3.iew.exec_rate 1.342386 # Inst execution rate 1920system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit 1921system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back 1922system.cpu3.iew.wb_producers 133214 # num instructions producing a value 1923system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value |
| 1841system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1924system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1842system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle 1843system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back | 1925system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle 1926system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back |
| 1844system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1927system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1845system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit 1846system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards 1847system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted 1848system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle 1849system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle 1850system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle | 1928system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit 1929system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards 1930system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted 1931system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle 1932system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle 1933system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle |
| 1851system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1934system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1852system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle 1853system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle 1854system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle 1855system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle 1856system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle 1857system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle 1858system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle 1859system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle 1860system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle | 1935system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle 1936system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle 1937system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle 1938system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle 1939system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle 1940system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle 1941system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle 1942system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle 1943system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle |
| 1861system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1862system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1863system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1944system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1945system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1946system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1864system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle 1865system.cpu3.commit.committedInsts 225028 # Number of instructions committed 1866system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed | 1947system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle 1948system.cpu3.commit.committedInsts 268955 # Number of instructions committed 1949system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed |
| 1867system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 1950system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
| 1868system.cpu3.commit.refs 90734 # Number of memory references committed 1869system.cpu3.commit.loads 62697 # Number of loads committed 1870system.cpu3.commit.membars 7153 # Number of memory barriers committed 1871system.cpu3.commit.branches 41151 # Number of branches committed | 1951system.cpu3.commit.refs 114381 # Number of memory references committed 1952system.cpu3.commit.loads 77904 # Number of loads committed 1953system.cpu3.commit.membars 5468 # Number of memory barriers committed 1954system.cpu3.commit.branches 47910 # Number of branches committed |
| 1872system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 1955system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1873system.cpu3.commit.int_insts 154003 # Number of committed integer instructions. | 1956system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. |
| 1874system.cpu3.commit.function_calls 322 # Number of function calls committed. | 1957system.cpu3.commit.function_calls 322 # Number of function calls committed. |
| 1875system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached | 1958system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached |
| 1876system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits | 1959system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1877system.cpu3.rob.rob_reads 400338 # The number of ROB reads 1878system.cpu3.rob.rob_writes 477767 # The number of ROB writes 1879system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 1880system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling 1881system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1882system.cpu3.committedInsts 185938 # Number of Instructions Simulated 1883system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated 1884system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated 1885system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction 1886system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads 1887system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle 1888system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads 1889system.cpu3.int_regfile_reads 337021 # number of integer regfile reads 1890system.cpu3.int_regfile_writes 158120 # number of integer regfile writes | 1960system.cpu3.rob.rob_reads 445085 # The number of ROB reads 1961system.cpu3.rob.rob_writes 565364 # The number of ROB writes 1962system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 1963system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling 1964system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1965system.cpu3.committedInsts 224789 # Number of Instructions Simulated 1966system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated 1967system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated 1968system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction 1969system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads 1970system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle 1971system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads 1972system.cpu3.int_regfile_reads 408025 # number of integer regfile reads 1973system.cpu3.int_regfile_writes 190344 # number of integer regfile writes |
| 1891system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 1974system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
| 1892system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads | 1975system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads |
| 1893system.cpu3.misc_regfile_writes 648 # number of misc regfile writes | 1976system.cpu3.misc_regfile_writes 648 # number of misc regfile writes |
| 1894system.cpu3.icache.replacements 318 # number of replacements 1895system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use 1896system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks. 1897system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. 1898system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks. | 1977system.cpu3.icache.replacements 319 # number of replacements 1978system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use 1979system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. 1980system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. 1981system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. |
| 1899system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1982system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1900system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor 1901system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy 1902system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy 1903system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits 1904system.cpu3.icache.ReadReq_hits::total 23677 # number of ReadReq hits 1905system.cpu3.icache.demand_hits::cpu3.inst 23677 # number of demand (read+write) hits 1906system.cpu3.icache.demand_hits::total 23677 # number of demand (read+write) hits 1907system.cpu3.icache.overall_hits::cpu3.inst 23677 # number of overall hits 1908system.cpu3.icache.overall_hits::total 23677 # number of overall hits 1909system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 1910system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 1911system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 1912system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 1913system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 1914system.cpu3.icache.overall_misses::total 475 # number of overall misses 1915system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6195500 # number of ReadReq miss cycles 1916system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles 1917system.cpu3.icache.demand_miss_latency::cpu3.inst 6195500 # number of demand (read+write) miss cycles 1918system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles 1919system.cpu3.icache.overall_miss_latency::cpu3.inst 6195500 # number of overall miss cycles 1920system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles 1921system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses) 1922system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses) 1923system.cpu3.icache.demand_accesses::cpu3.inst 24152 # number of demand (read+write) accesses 1924system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses 1925system.cpu3.icache.overall_accesses::cpu3.inst 24152 # number of overall (read+write) accesses 1926system.cpu3.icache.overall_accesses::total 24152 # number of overall (read+write) accesses 1927system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.019667 # miss rate for ReadReq accesses 1928system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses 1929system.cpu3.icache.demand_miss_rate::cpu3.inst 0.019667 # miss rate for demand accesses 1930system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses 1931system.cpu3.icache.overall_miss_rate::cpu3.inst 0.019667 # miss rate for overall accesses 1932system.cpu3.icache.overall_miss_rate::total 0.019667 # miss rate for overall accesses 1933system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13043.157895 # average ReadReq miss latency 1934system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency 1935system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency 1936system.cpu3.icache.demand_avg_miss_latency::total 13043.157895 # average overall miss latency 1937system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency 1938system.cpu3.icache.overall_avg_miss_latency::total 13043.157895 # average overall miss latency | 1983system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor 1984system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy 1985system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy 1986system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits 1987system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits 1988system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits 1989system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits 1990system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits 1991system.cpu3.icache.overall_hits::total 20059 # number of overall hits 1992system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses 1993system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses 1994system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses 1995system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses 1996system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses 1997system.cpu3.icache.overall_misses::total 477 # number of overall misses 1998system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles 1999system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles 2000system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles 2001system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles 2002system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles 2003system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles 2004system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses) 2005system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses) 2006system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses 2007system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses 2008system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses 2009system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses 2010system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses 2011system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses 2012system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses 2013system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses 2014system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses 2015system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses 2016system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency 2017system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency 2018system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency 2019system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency 2020system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency 2021system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency |
| 1939system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1940system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1941system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1942system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1943system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1944system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1945system.cpu3.icache.fast_writes 0 # number of fast writes performed 1946system.cpu3.icache.cache_copies 0 # number of cache copies performed | 2022system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2023system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2024system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2025system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2026system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2027system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2028system.cpu3.icache.fast_writes 0 # number of fast writes performed 2029system.cpu3.icache.cache_copies 0 # number of cache copies performed |
| 1947system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits 1948system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1949system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits 1950system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1951system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 1952system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1953system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 1954system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 1955system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 1956system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 1957system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 1958system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 1959system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4977500 # number of ReadReq MSHR miss cycles 1960system.cpu3.icache.ReadReq_mshr_miss_latency::total 4977500 # number of ReadReq MSHR miss cycles 1961system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4977500 # number of demand (read+write) MSHR miss cycles 1962system.cpu3.icache.demand_mshr_miss_latency::total 4977500 # number of demand (read+write) MSHR miss cycles 1963system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4977500 # number of overall MSHR miss cycles 1964system.cpu3.icache.overall_mshr_miss_latency::total 4977500 # number of overall MSHR miss cycles 1965system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for ReadReq accesses 1966system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses 1967system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for demand accesses 1968system.cpu3.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses 1969system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for overall accesses 1970system.cpu3.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses 1971system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average ReadReq mshr miss latency 1972system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11602.564103 # average ReadReq mshr miss latency 1973system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency 1974system.cpu3.icache.demand_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency 1975system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency 1976system.cpu3.icache.overall_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency | 2030system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits 2031system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits 2032system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits 2033system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits 2034system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits 2035system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits 2036system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses 2037system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 2038system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses 2039system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 2040system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2041system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2042system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles 2043system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles 2044system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles 2045system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles 2046system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles 2047system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles 2048system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses 2049system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses 2050system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses 2051system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses 2052system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses 2053system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses 2054system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency 2055system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency 2056system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency 2057system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency 2058system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency 2059system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency |
| 1977system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1978system.cpu3.dcache.replacements 0 # number of replacements | 2060system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2061system.cpu3.dcache.replacements 0 # number of replacements |
| 1979system.cpu3.dcache.tagsinuse 24.570062 # Cycle average of tags in use 1980system.cpu3.dcache.total_refs 34044 # Total number of references to valid blocks. | 2062system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use 2063system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks. |
| 1981system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. | 2064system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. |
| 1982system.cpu3.dcache.avg_refs 1215.857143 # Average number of references to valid blocks. | 2065system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks. |
| 1983system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2066system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1984system.cpu3.dcache.occ_blocks::cpu3.data 24.570062 # Average occupied blocks per requestor 1985system.cpu3.dcache.occ_percent::cpu3.data 0.047988 # Average percentage of cache occupancy 1986system.cpu3.dcache.occ_percent::total 0.047988 # Average percentage of cache occupancy 1987system.cpu3.dcache.ReadReq_hits::cpu3.data 39468 # number of ReadReq hits 1988system.cpu3.dcache.ReadReq_hits::total 39468 # number of ReadReq hits 1989system.cpu3.dcache.WriteReq_hits::cpu3.data 27827 # number of WriteReq hits 1990system.cpu3.dcache.WriteReq_hits::total 27827 # number of WriteReq hits 1991system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 1992system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1993system.cpu3.dcache.demand_hits::cpu3.data 67295 # number of demand (read+write) hits 1994system.cpu3.dcache.demand_hits::total 67295 # number of demand (read+write) hits 1995system.cpu3.dcache.overall_hits::cpu3.data 67295 # number of overall hits 1996system.cpu3.dcache.overall_hits::total 67295 # number of overall hits 1997system.cpu3.dcache.ReadReq_misses::cpu3.data 421 # number of ReadReq misses 1998system.cpu3.dcache.ReadReq_misses::total 421 # number of ReadReq misses | 2067system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor 2068system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy 2069system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy 2070system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits 2071system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits 2072system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits 2073system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits 2074system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2075system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2076system.cpu3.dcache.demand_hits::cpu3.data 82604 # number of demand (read+write) hits 2077system.cpu3.dcache.demand_hits::total 82604 # number of demand (read+write) hits 2078system.cpu3.dcache.overall_hits::cpu3.data 82604 # number of overall hits 2079system.cpu3.dcache.overall_hits::total 82604 # number of overall hits 2080system.cpu3.dcache.ReadReq_misses::cpu3.data 340 # number of ReadReq misses 2081system.cpu3.dcache.ReadReq_misses::total 340 # number of ReadReq misses |
| 1999system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses 2000system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses 2001system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 2002system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses | 2082system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses 2083system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses 2084system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses 2085system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses |
| 2003system.cpu3.dcache.demand_misses::cpu3.data 559 # number of demand (read+write) misses 2004system.cpu3.dcache.demand_misses::total 559 # number of demand (read+write) misses 2005system.cpu3.dcache.overall_misses::cpu3.data 559 # number of overall misses 2006system.cpu3.dcache.overall_misses::total 559 # number of overall misses 2007system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5610000 # number of ReadReq miss cycles 2008system.cpu3.dcache.ReadReq_miss_latency::total 5610000 # number of ReadReq miss cycles 2009system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2578000 # number of WriteReq miss cycles 2010system.cpu3.dcache.WriteReq_miss_latency::total 2578000 # number of WriteReq miss cycles 2011system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 603500 # number of SwapReq miss cycles 2012system.cpu3.dcache.SwapReq_miss_latency::total 603500 # number of SwapReq miss cycles 2013system.cpu3.dcache.demand_miss_latency::cpu3.data 8188000 # number of demand (read+write) miss cycles 2014system.cpu3.dcache.demand_miss_latency::total 8188000 # number of demand (read+write) miss cycles 2015system.cpu3.dcache.overall_miss_latency::cpu3.data 8188000 # number of overall miss cycles 2016system.cpu3.dcache.overall_miss_latency::total 8188000 # number of overall miss cycles 2017system.cpu3.dcache.ReadReq_accesses::cpu3.data 39889 # number of ReadReq accesses(hits+misses) 2018system.cpu3.dcache.ReadReq_accesses::total 39889 # number of ReadReq accesses(hits+misses) 2019system.cpu3.dcache.WriteReq_accesses::cpu3.data 27965 # number of WriteReq accesses(hits+misses) 2020system.cpu3.dcache.WriteReq_accesses::total 27965 # number of WriteReq accesses(hits+misses) 2021system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) 2022system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) 2023system.cpu3.dcache.demand_accesses::cpu3.data 67854 # number of demand (read+write) accesses 2024system.cpu3.dcache.demand_accesses::total 67854 # number of demand (read+write) accesses 2025system.cpu3.dcache.overall_accesses::cpu3.data 67854 # number of overall (read+write) accesses 2026system.cpu3.dcache.overall_accesses::total 67854 # number of overall (read+write) accesses 2027system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010554 # miss rate for ReadReq accesses 2028system.cpu3.dcache.ReadReq_miss_rate::total 0.010554 # miss rate for ReadReq accesses 2029system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004935 # miss rate for WriteReq accesses 2030system.cpu3.dcache.WriteReq_miss_rate::total 0.004935 # miss rate for WriteReq accesses 2031system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses 2032system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses 2033system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008238 # miss rate for demand accesses 2034system.cpu3.dcache.demand_miss_rate::total 0.008238 # miss rate for demand accesses 2035system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008238 # miss rate for overall accesses 2036system.cpu3.dcache.overall_miss_rate::total 0.008238 # miss rate for overall accesses 2037system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13325.415677 # average ReadReq miss latency 2038system.cpu3.dcache.ReadReq_avg_miss_latency::total 13325.415677 # average ReadReq miss latency 2039system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18681.159420 # average WriteReq miss latency 2040system.cpu3.dcache.WriteReq_avg_miss_latency::total 18681.159420 # average WriteReq miss latency 2041system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10405.172414 # average SwapReq miss latency 2042system.cpu3.dcache.SwapReq_avg_miss_latency::total 10405.172414 # average SwapReq miss latency 2043system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14647.584973 # average overall miss latency 2044system.cpu3.dcache.demand_avg_miss_latency::total 14647.584973 # average overall miss latency 2045system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14647.584973 # average overall miss latency 2046system.cpu3.dcache.overall_avg_miss_latency::total 14647.584973 # average overall miss latency | 2086system.cpu3.dcache.demand_misses::cpu3.data 478 # number of demand (read+write) misses 2087system.cpu3.dcache.demand_misses::total 478 # number of demand (read+write) misses 2088system.cpu3.dcache.overall_misses::cpu3.data 478 # number of overall misses 2089system.cpu3.dcache.overall_misses::total 478 # number of overall misses 2090system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4247000 # number of ReadReq miss cycles 2091system.cpu3.dcache.ReadReq_miss_latency::total 4247000 # number of ReadReq miss cycles 2092system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2709000 # number of WriteReq miss cycles 2093system.cpu3.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles 2094system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 548500 # number of SwapReq miss cycles 2095system.cpu3.dcache.SwapReq_miss_latency::total 548500 # number of SwapReq miss cycles 2096system.cpu3.dcache.demand_miss_latency::cpu3.data 6956000 # number of demand (read+write) miss cycles 2097system.cpu3.dcache.demand_miss_latency::total 6956000 # number of demand (read+write) miss cycles 2098system.cpu3.dcache.overall_miss_latency::cpu3.data 6956000 # number of overall miss cycles 2099system.cpu3.dcache.overall_miss_latency::total 6956000 # number of overall miss cycles 2100system.cpu3.dcache.ReadReq_accesses::cpu3.data 46675 # number of ReadReq accesses(hits+misses) 2101system.cpu3.dcache.ReadReq_accesses::total 46675 # number of ReadReq accesses(hits+misses) 2102system.cpu3.dcache.WriteReq_accesses::cpu3.data 36407 # number of WriteReq accesses(hits+misses) 2103system.cpu3.dcache.WriteReq_accesses::total 36407 # number of WriteReq accesses(hits+misses) 2104system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 2105system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2106system.cpu3.dcache.demand_accesses::cpu3.data 83082 # number of demand (read+write) accesses 2107system.cpu3.dcache.demand_accesses::total 83082 # number of demand (read+write) accesses 2108system.cpu3.dcache.overall_accesses::cpu3.data 83082 # number of overall (read+write) accesses 2109system.cpu3.dcache.overall_accesses::total 83082 # number of overall (read+write) accesses 2110system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007284 # miss rate for ReadReq accesses 2111system.cpu3.dcache.ReadReq_miss_rate::total 0.007284 # miss rate for ReadReq accesses 2112system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003790 # miss rate for WriteReq accesses 2113system.cpu3.dcache.WriteReq_miss_rate::total 0.003790 # miss rate for WriteReq accesses 2114system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828571 # miss rate for SwapReq accesses 2115system.cpu3.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses 2116system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005753 # miss rate for demand accesses 2117system.cpu3.dcache.demand_miss_rate::total 0.005753 # miss rate for demand accesses 2118system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005753 # miss rate for overall accesses 2119system.cpu3.dcache.overall_miss_rate::total 0.005753 # miss rate for overall accesses 2120system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12491.176471 # average ReadReq miss latency 2121system.cpu3.dcache.ReadReq_avg_miss_latency::total 12491.176471 # average ReadReq miss latency 2122system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19630.434783 # average WriteReq miss latency 2123system.cpu3.dcache.WriteReq_avg_miss_latency::total 19630.434783 # average WriteReq miss latency 2124system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9456.896552 # average SwapReq miss latency 2125system.cpu3.dcache.SwapReq_avg_miss_latency::total 9456.896552 # average SwapReq miss latency 2126system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency 2127system.cpu3.dcache.demand_avg_miss_latency::total 14552.301255 # average overall miss latency 2128system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency 2129system.cpu3.dcache.overall_avg_miss_latency::total 14552.301255 # average overall miss latency |
| 2047system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2048system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2049system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2050system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2051system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2052system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2053system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2054system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 2130system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2131system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2132system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2133system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2134system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2135system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2136system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2137system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 2055system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 258 # number of ReadReq MSHR hits 2056system.cpu3.dcache.ReadReq_mshr_hits::total 258 # number of ReadReq MSHR hits 2057system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits 2058system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 2059system.cpu3.dcache.demand_mshr_hits::cpu3.data 290 # number of demand (read+write) MSHR hits 2060system.cpu3.dcache.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits 2061system.cpu3.dcache.overall_mshr_hits::cpu3.data 290 # number of overall MSHR hits 2062system.cpu3.dcache.overall_mshr_hits::total 290 # number of overall MSHR hits 2063system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses 2064system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 2065system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2066system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses | 2138system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits 2139system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits 2140system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2141system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2142system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits 2143system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 2144system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits 2145system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits 2146system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses 2147system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 2148system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 2149system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses |
| 2067system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 2068system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses | 2150system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses 2151system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses |
| 2069system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses 2070system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 2071system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses 2072system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 2073system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1447000 # number of ReadReq MSHR miss cycles 2074system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1447000 # number of ReadReq MSHR miss cycles 2075system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1250000 # number of WriteReq MSHR miss cycles 2076system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1250000 # number of WriteReq MSHR miss cycles 2077system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 487500 # number of SwapReq MSHR miss cycles 2078system.cpu3.dcache.SwapReq_mshr_miss_latency::total 487500 # number of SwapReq MSHR miss cycles 2079system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2697000 # number of demand (read+write) MSHR miss cycles 2080system.cpu3.dcache.demand_mshr_miss_latency::total 2697000 # number of demand (read+write) MSHR miss cycles 2081system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2697000 # number of overall MSHR miss cycles 2082system.cpu3.dcache.overall_mshr_miss_latency::total 2697000 # number of overall MSHR miss cycles 2083system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004086 # mshr miss rate for ReadReq accesses 2084system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004086 # mshr miss rate for ReadReq accesses 2085system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003790 # mshr miss rate for WriteReq accesses 2086system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003790 # mshr miss rate for WriteReq accesses 2087system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses 2088system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses 2089system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for demand accesses 2090system.cpu3.dcache.demand_mshr_miss_rate::total 0.003964 # mshr miss rate for demand accesses 2091system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for overall accesses 2092system.cpu3.dcache.overall_mshr_miss_rate::total 0.003964 # mshr miss rate for overall accesses 2093system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8877.300613 # average ReadReq mshr miss latency 2094system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8877.300613 # average ReadReq mshr miss latency 2095system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11792.452830 # average WriteReq mshr miss latency 2096system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11792.452830 # average WriteReq mshr miss latency 2097system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 8405.172414 # average SwapReq mshr miss latency 2098system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 8405.172414 # average SwapReq mshr miss latency 2099system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency 2100system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency 2101system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency 2102system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency | 2152system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses 2153system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 2154system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses 2155system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 2156system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1065020 # number of ReadReq MSHR miss cycles 2157system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1065020 # number of ReadReq MSHR miss cycles 2158system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1284501 # number of WriteReq MSHR miss cycles 2159system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1284501 # number of WriteReq MSHR miss cycles 2160system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles 2161system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles 2162system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles 2163system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles 2164system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles 2165system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles 2166system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses 2167system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses 2168system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses 2169system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses 2170system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses 2171system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses 2172system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses 2173system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses 2174system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses 2175system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses 2176system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency 2177system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency 2178system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency 2179system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency 2180system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency 2181system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency 2182system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency 2183system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency 2184system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency 2185system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency |
| 2103system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2104system.l2c.replacements 0 # number of replacements | 2186system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2187system.l2c.replacements 0 # number of replacements |
| 2105system.l2c.tagsinuse 425.302863 # Cycle average of tags in use 2106system.l2c.total_refs 1445 # Total number of references to valid blocks. 2107system.l2c.sampled_refs 527 # Sample count of references to valid blocks. 2108system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. | 2188system.l2c.tagsinuse 416.873465 # Cycle average of tags in use 2189system.l2c.total_refs 1443 # Total number of references to valid blocks. 2190system.l2c.sampled_refs 526 # Sample count of references to valid blocks. 2191system.l2c.avg_refs 2.743346 # Average number of references to valid blocks. |
| 2109system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2192system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2110system.l2c.occ_blocks::writebacks 0.824834 # Average occupied blocks per requestor 2111system.l2c.occ_blocks::cpu0.inst 289.870828 # Average occupied blocks per requestor 2112system.l2c.occ_blocks::cpu0.data 59.081037 # Average occupied blocks per requestor 2113system.l2c.occ_blocks::cpu1.inst 62.204312 # Average occupied blocks per requestor 2114system.l2c.occ_blocks::cpu1.data 5.605545 # Average occupied blocks per requestor 2115system.l2c.occ_blocks::cpu2.inst 4.564656 # Average occupied blocks per requestor 2116system.l2c.occ_blocks::cpu2.data 0.760691 # Average occupied blocks per requestor 2117system.l2c.occ_blocks::cpu3.inst 1.668516 # Average occupied blocks per requestor 2118system.l2c.occ_blocks::cpu3.data 0.722445 # Average occupied blocks per requestor 2119system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 2120system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy 2121system.l2c.occ_percent::cpu0.data 0.000902 # Average percentage of cache occupancy 2122system.l2c.occ_percent::cpu1.inst 0.000949 # Average percentage of cache occupancy 2123system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy 2124system.l2c.occ_percent::cpu2.inst 0.000070 # Average percentage of cache occupancy 2125system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy 2126system.l2c.occ_percent::cpu3.inst 0.000025 # Average percentage of cache occupancy | 2193system.l2c.occ_blocks::writebacks 0.799918 # Average occupied blocks per requestor 2194system.l2c.occ_blocks::cpu0.inst 284.792904 # Average occupied blocks per requestor 2195system.l2c.occ_blocks::cpu0.data 58.372123 # Average occupied blocks per requestor 2196system.l2c.occ_blocks::cpu1.inst 60.210015 # Average occupied blocks per requestor 2197system.l2c.occ_blocks::cpu1.data 5.411849 # Average occupied blocks per requestor 2198system.l2c.occ_blocks::cpu2.inst 2.383180 # Average occupied blocks per requestor 2199system.l2c.occ_blocks::cpu2.data 0.694731 # Average occupied blocks per requestor 2200system.l2c.occ_blocks::cpu3.inst 3.476542 # Average occupied blocks per requestor 2201system.l2c.occ_blocks::cpu3.data 0.732205 # Average occupied blocks per requestor 2202system.l2c.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2203system.l2c.occ_percent::cpu0.inst 0.004346 # Average percentage of cache occupancy 2204system.l2c.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 2205system.l2c.occ_percent::cpu1.inst 0.000919 # Average percentage of cache occupancy 2206system.l2c.occ_percent::cpu1.data 0.000083 # Average percentage of cache occupancy 2207system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy 2208system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy 2209system.l2c.occ_percent::cpu3.inst 0.000053 # Average percentage of cache occupancy |
| 2127system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy | 2210system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy |
| 2128system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy 2129system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits | 2211system.l2c.occ_percent::total 0.006361 # Average percentage of cache occupancy 2212system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits |
| 2130system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2131system.l2c.ReadReq_hits::cpu1.inst 343 # number of ReadReq hits 2132system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits | 2213system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2214system.l2c.ReadReq_hits::cpu1.inst 343 # number of ReadReq hits 2215system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits |
| 2133system.l2c.ReadReq_hits::cpu2.inst 416 # number of ReadReq hits | 2216system.l2c.ReadReq_hits::cpu2.inst 417 # number of ReadReq hits |
| 2134system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits | 2217system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits |
| 2135system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits | 2218system.l2c.ReadReq_hits::cpu3.inst 422 # number of ReadReq hits |
| 2136system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits | 2219system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits |
| 2137system.l2c.ReadReq_hits::total 1445 # number of ReadReq hits | 2220system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits |
| 2138system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2139system.l2c.Writeback_hits::total 1 # number of Writeback hits 2140system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2141system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits | 2221system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2222system.l2c.Writeback_hits::total 1 # number of Writeback hits 2223system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2224system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
| 2142system.l2c.demand_hits::cpu0.inst 230 # number of demand (read+write) hits | 2225system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits |
| 2143system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2144system.l2c.demand_hits::cpu1.inst 343 # number of demand (read+write) hits 2145system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits | 2226system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2227system.l2c.demand_hits::cpu1.inst 343 # number of demand (read+write) hits 2228system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits |
| 2146system.l2c.demand_hits::cpu2.inst 416 # number of demand (read+write) hits | 2229system.l2c.demand_hits::cpu2.inst 417 # number of demand (read+write) hits |
| 2147system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits | 2230system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits |
| 2148system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits | 2231system.l2c.demand_hits::cpu3.inst 422 # number of demand (read+write) hits |
| 2149system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits | 2232system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits |
| 2150system.l2c.demand_hits::total 1445 # number of demand (read+write) hits 2151system.l2c.overall_hits::cpu0.inst 230 # number of overall hits | 2233system.l2c.demand_hits::total 1443 # number of demand (read+write) hits 2234system.l2c.overall_hits::cpu0.inst 229 # number of overall hits |
| 2152system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2153system.l2c.overall_hits::cpu1.inst 343 # number of overall hits 2154system.l2c.overall_hits::cpu1.data 5 # number of overall hits | 2235system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2236system.l2c.overall_hits::cpu1.inst 343 # number of overall hits 2237system.l2c.overall_hits::cpu1.data 5 # number of overall hits |
| 2155system.l2c.overall_hits::cpu2.inst 416 # number of overall hits | 2238system.l2c.overall_hits::cpu2.inst 417 # number of overall hits |
| 2156system.l2c.overall_hits::cpu2.data 11 # number of overall hits | 2239system.l2c.overall_hits::cpu2.data 11 # number of overall hits |
| 2157system.l2c.overall_hits::cpu3.inst 424 # number of overall hits | 2240system.l2c.overall_hits::cpu3.inst 422 # number of overall hits |
| 2158system.l2c.overall_hits::cpu3.data 11 # number of overall hits | 2241system.l2c.overall_hits::cpu3.data 11 # number of overall hits |
| 2159system.l2c.overall_hits::total 1445 # number of overall hits 2160system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses | 2242system.l2c.overall_hits::total 1443 # number of overall hits 2243system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses |
| 2161system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2162system.l2c.ReadReq_misses::cpu1.inst 82 # number of ReadReq misses 2163system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses | 2244system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2245system.l2c.ReadReq_misses::cpu1.inst 82 # number of ReadReq misses 2246system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses |
| 2164system.l2c.ReadReq_misses::cpu2.inst 14 # number of ReadReq misses | 2247system.l2c.ReadReq_misses::cpu2.inst 11 # number of ReadReq misses |
| 2165system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses | 2248system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses |
| 2166system.l2c.ReadReq_misses::cpu3.inst 5 # number of ReadReq misses | 2249system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses |
| 2167system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses | 2250system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses |
| 2168system.l2c.ReadReq_misses::total 544 # number of ReadReq misses 2169system.l2c.UpgradeReq_misses::cpu0.data 18 # number of UpgradeReq misses 2170system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 2171system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 2172system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 2173system.l2c.UpgradeReq_misses::total 74 # number of UpgradeReq misses | 2251system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 2252system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 2253system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 2254system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 2255system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 2256system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses |
| 2174system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2175system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2176system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2177system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2178system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses | 2257system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2258system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2259system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2260system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2261system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses |
| 2179system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses | 2262system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses |
| 2180system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2181system.l2c.demand_misses::cpu1.inst 82 # number of demand (read+write) misses 2182system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses | 2263system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2264system.l2c.demand_misses::cpu1.inst 82 # number of demand (read+write) misses 2265system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses |
| 2183system.l2c.demand_misses::cpu2.inst 14 # number of demand (read+write) misses | 2266system.l2c.demand_misses::cpu2.inst 11 # number of demand (read+write) misses |
| 2184system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses | 2267system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses |
| 2185system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses | 2268system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses |
| 2186system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses | 2269system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses |
| 2187system.l2c.demand_misses::total 675 # number of demand (read+write) misses 2188system.l2c.overall_misses::cpu0.inst 360 # number of overall misses | 2270system.l2c.demand_misses::total 674 # number of demand (read+write) misses 2271system.l2c.overall_misses::cpu0.inst 359 # number of overall misses |
| 2189system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2190system.l2c.overall_misses::cpu1.inst 82 # number of overall misses 2191system.l2c.overall_misses::cpu1.data 20 # number of overall misses | 2272system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2273system.l2c.overall_misses::cpu1.inst 82 # number of overall misses 2274system.l2c.overall_misses::cpu1.data 20 # number of overall misses |
| 2192system.l2c.overall_misses::cpu2.inst 14 # number of overall misses | 2275system.l2c.overall_misses::cpu2.inst 11 # number of overall misses |
| 2193system.l2c.overall_misses::cpu2.data 13 # number of overall misses | 2276system.l2c.overall_misses::cpu2.data 13 # number of overall misses |
| 2194system.l2c.overall_misses::cpu3.inst 5 # number of overall misses | 2277system.l2c.overall_misses::cpu3.inst 8 # number of overall misses |
| 2195system.l2c.overall_misses::cpu3.data 13 # number of overall misses | 2278system.l2c.overall_misses::cpu3.data 13 # number of overall misses |
| 2196system.l2c.overall_misses::total 675 # number of overall misses 2197system.l2c.ReadReq_miss_latency::cpu0.inst 18249500 # number of ReadReq miss cycles 2198system.l2c.ReadReq_miss_latency::cpu0.data 4603000 # number of ReadReq miss cycles 2199system.l2c.ReadReq_miss_latency::cpu1.inst 4327000 # number of ReadReq miss cycles 2200system.l2c.ReadReq_miss_latency::cpu1.data 666000 # number of ReadReq miss cycles 2201system.l2c.ReadReq_miss_latency::cpu2.inst 840500 # number of ReadReq miss cycles 2202system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles 2203system.l2c.ReadReq_miss_latency::cpu3.inst 216500 # number of ReadReq miss cycles 2204system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles 2205system.l2c.ReadReq_miss_latency::total 29039500 # number of ReadReq miss cycles 2206system.l2c.ReadExReq_miss_latency::cpu0.data 5402500 # number of ReadExReq miss cycles 2207system.l2c.ReadExReq_miss_latency::cpu1.data 997000 # number of ReadExReq miss cycles 2208system.l2c.ReadExReq_miss_latency::cpu2.data 868500 # number of ReadExReq miss cycles 2209system.l2c.ReadExReq_miss_latency::cpu3.data 757000 # number of ReadExReq miss cycles 2210system.l2c.ReadExReq_miss_latency::total 8025000 # number of ReadExReq miss cycles 2211system.l2c.demand_miss_latency::cpu0.inst 18249500 # number of demand (read+write) miss cycles 2212system.l2c.demand_miss_latency::cpu0.data 10005500 # number of demand (read+write) miss cycles 2213system.l2c.demand_miss_latency::cpu1.inst 4327000 # number of demand (read+write) miss cycles 2214system.l2c.demand_miss_latency::cpu1.data 1663000 # number of demand (read+write) miss cycles 2215system.l2c.demand_miss_latency::cpu2.inst 840500 # number of demand (read+write) miss cycles 2216system.l2c.demand_miss_latency::cpu2.data 937000 # number of demand (read+write) miss cycles 2217system.l2c.demand_miss_latency::cpu3.inst 216500 # number of demand (read+write) miss cycles 2218system.l2c.demand_miss_latency::cpu3.data 825500 # number of demand (read+write) miss cycles 2219system.l2c.demand_miss_latency::total 37064500 # number of demand (read+write) miss cycles 2220system.l2c.overall_miss_latency::cpu0.inst 18249500 # number of overall miss cycles 2221system.l2c.overall_miss_latency::cpu0.data 10005500 # number of overall miss cycles 2222system.l2c.overall_miss_latency::cpu1.inst 4327000 # number of overall miss cycles 2223system.l2c.overall_miss_latency::cpu1.data 1663000 # number of overall miss cycles 2224system.l2c.overall_miss_latency::cpu2.inst 840500 # number of overall miss cycles 2225system.l2c.overall_miss_latency::cpu2.data 937000 # number of overall miss cycles 2226system.l2c.overall_miss_latency::cpu3.inst 216500 # number of overall miss cycles 2227system.l2c.overall_miss_latency::cpu3.data 825500 # number of overall miss cycles 2228system.l2c.overall_miss_latency::total 37064500 # number of overall miss cycles 2229system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) | 2279system.l2c.overall_misses::total 674 # number of overall misses 2280system.l2c.ReadReq_miss_latency::cpu0.inst 24109000 # number of ReadReq miss cycles 2281system.l2c.ReadReq_miss_latency::cpu0.data 5458500 # number of ReadReq miss cycles 2282system.l2c.ReadReq_miss_latency::cpu1.inst 5845000 # number of ReadReq miss cycles 2283system.l2c.ReadReq_miss_latency::cpu1.data 521000 # number of ReadReq miss cycles 2284system.l2c.ReadReq_miss_latency::cpu2.inst 717000 # number of ReadReq miss cycles 2285system.l2c.ReadReq_miss_latency::cpu2.data 88500 # number of ReadReq miss cycles 2286system.l2c.ReadReq_miss_latency::cpu3.inst 521500 # number of ReadReq miss cycles 2287system.l2c.ReadReq_miss_latency::cpu3.data 88500 # number of ReadReq miss cycles 2288system.l2c.ReadReq_miss_latency::total 37349000 # number of ReadReq miss cycles 2289system.l2c.ReadExReq_miss_latency::cpu0.data 7419500 # number of ReadExReq miss cycles 2290system.l2c.ReadExReq_miss_latency::cpu1.data 1013000 # number of ReadExReq miss cycles 2291system.l2c.ReadExReq_miss_latency::cpu2.data 901500 # number of ReadExReq miss cycles 2292system.l2c.ReadExReq_miss_latency::cpu3.data 851000 # number of ReadExReq miss cycles 2293system.l2c.ReadExReq_miss_latency::total 10185000 # number of ReadExReq miss cycles 2294system.l2c.demand_miss_latency::cpu0.inst 24109000 # number of demand (read+write) miss cycles 2295system.l2c.demand_miss_latency::cpu0.data 12878000 # number of demand (read+write) miss cycles 2296system.l2c.demand_miss_latency::cpu1.inst 5845000 # number of demand (read+write) miss cycles 2297system.l2c.demand_miss_latency::cpu1.data 1534000 # number of demand (read+write) miss cycles 2298system.l2c.demand_miss_latency::cpu2.inst 717000 # number of demand (read+write) miss cycles 2299system.l2c.demand_miss_latency::cpu2.data 990000 # number of demand (read+write) miss cycles 2300system.l2c.demand_miss_latency::cpu3.inst 521500 # number of demand (read+write) miss cycles 2301system.l2c.demand_miss_latency::cpu3.data 939500 # number of demand (read+write) miss cycles 2302system.l2c.demand_miss_latency::total 47534000 # number of demand (read+write) miss cycles 2303system.l2c.overall_miss_latency::cpu0.inst 24109000 # number of overall miss cycles 2304system.l2c.overall_miss_latency::cpu0.data 12878000 # number of overall miss cycles 2305system.l2c.overall_miss_latency::cpu1.inst 5845000 # number of overall miss cycles 2306system.l2c.overall_miss_latency::cpu1.data 1534000 # number of overall miss cycles 2307system.l2c.overall_miss_latency::cpu2.inst 717000 # number of overall miss cycles 2308system.l2c.overall_miss_latency::cpu2.data 990000 # number of overall miss cycles 2309system.l2c.overall_miss_latency::cpu3.inst 521500 # number of overall miss cycles 2310system.l2c.overall_miss_latency::cpu3.data 939500 # number of overall miss cycles 2311system.l2c.overall_miss_latency::total 47534000 # number of overall miss cycles 2312system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) |
| 2230system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2231system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2232system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) | 2313system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2314system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2315system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) |
| 2233system.l2c.ReadReq_accesses::cpu2.inst 430 # number of ReadReq accesses(hits+misses) | 2316system.l2c.ReadReq_accesses::cpu2.inst 428 # number of ReadReq accesses(hits+misses) |
| 2234system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) | 2317system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) |
| 2235system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) | 2318system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) |
| 2236system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) | 2319system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) |
| 2237system.l2c.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) | 2320system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) |
| 2238system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2239system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) | 2321system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2322system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) |
| 2240system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) 2241system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 2242system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 2243system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 2244system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses) | 2323system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 2324system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 2325system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 2326system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 2327system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) |
| 2245system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2246system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2247system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2248system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2249system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) | 2328system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2329system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2330system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2331system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2332system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) |
| 2250system.l2c.demand_accesses::cpu0.inst 590 # number of demand (read+write) accesses | 2333system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses |
| 2251system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2252system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2253system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses | 2334system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2335system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2336system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses |
| 2254system.l2c.demand_accesses::cpu2.inst 430 # number of demand (read+write) accesses | 2337system.l2c.demand_accesses::cpu2.inst 428 # number of demand (read+write) accesses |
| 2255system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses | 2338system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses |
| 2256system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses | 2339system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses |
| 2257system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses | 2340system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses |
| 2258system.l2c.demand_accesses::total 2120 # number of demand (read+write) accesses 2259system.l2c.overall_accesses::cpu0.inst 590 # number of overall (read+write) accesses | 2341system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses 2342system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses |
| 2260system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2261system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2262system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses | 2343system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2344system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2345system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses |
| 2263system.l2c.overall_accesses::cpu2.inst 430 # number of overall (read+write) accesses | 2346system.l2c.overall_accesses::cpu2.inst 428 # number of overall (read+write) accesses |
| 2264system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses | 2347system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses |
| 2265system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses | 2348system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses |
| 2266system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses | 2349system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses |
| 2267system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses 2268system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses | 2350system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses 2351system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses |
| 2269system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2270system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses 2271system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses | 2352system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2353system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses 2354system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses |
| 2272system.l2c.ReadReq_miss_rate::cpu2.inst 0.032558 # miss rate for ReadReq accesses | 2355system.l2c.ReadReq_miss_rate::cpu2.inst 0.025701 # miss rate for ReadReq accesses |
| 2273system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses | 2356system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses |
| 2274system.l2c.ReadReq_miss_rate::cpu3.inst 0.011655 # miss rate for ReadReq accesses | 2357system.l2c.ReadReq_miss_rate::cpu3.inst 0.018605 # miss rate for ReadReq accesses |
| 2275system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses | 2358system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses |
| 2276system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses 2277system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses | 2359system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses 2360system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses |
| 2278system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2279system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2280system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 2361system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2362system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2363system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 2281system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses | 2364system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses |
| 2282system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2283system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2284system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2285system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2286system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 2365system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2366system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2367system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2368system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2369system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 2287system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses | 2370system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses |
| 2288system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2289system.l2c.demand_miss_rate::cpu1.inst 0.192941 # miss rate for demand accesses 2290system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses | 2371system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2372system.l2c.demand_miss_rate::cpu1.inst 0.192941 # miss rate for demand accesses 2373system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses |
| 2291system.l2c.demand_miss_rate::cpu2.inst 0.032558 # miss rate for demand accesses | 2374system.l2c.demand_miss_rate::cpu2.inst 0.025701 # miss rate for demand accesses |
| 2292system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses | 2375system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses |
| 2293system.l2c.demand_miss_rate::cpu3.inst 0.011655 # miss rate for demand accesses | 2376system.l2c.demand_miss_rate::cpu3.inst 0.018605 # miss rate for demand accesses |
| 2294system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses | 2377system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses |
| 2295system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses 2296system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses | 2378system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses 2379system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses |
| 2297system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2298system.l2c.overall_miss_rate::cpu1.inst 0.192941 # miss rate for overall accesses 2299system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses | 2380system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2381system.l2c.overall_miss_rate::cpu1.inst 0.192941 # miss rate for overall accesses 2382system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses |
| 2300system.l2c.overall_miss_rate::cpu2.inst 0.032558 # miss rate for overall accesses | 2383system.l2c.overall_miss_rate::cpu2.inst 0.025701 # miss rate for overall accesses |
| 2301system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses | 2384system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses |
| 2302system.l2c.overall_miss_rate::cpu3.inst 0.011655 # miss rate for overall accesses | 2385system.l2c.overall_miss_rate::cpu3.inst 0.018605 # miss rate for overall accesses |
| 2303system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses | 2386system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses |
| 2304system.l2c.overall_miss_rate::total 0.318396 # miss rate for overall accesses 2305system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50693.055556 # average ReadReq miss latency 2306system.l2c.ReadReq_avg_miss_latency::cpu0.data 62202.702703 # average ReadReq miss latency 2307system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52768.292683 # average ReadReq miss latency 2308system.l2c.ReadReq_avg_miss_latency::cpu1.data 95142.857143 # average ReadReq miss latency 2309system.l2c.ReadReq_avg_miss_latency::cpu2.inst 60035.714286 # average ReadReq miss latency 2310system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency 2311system.l2c.ReadReq_avg_miss_latency::cpu3.inst 43300 # average ReadReq miss latency 2312system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency 2313system.l2c.ReadReq_avg_miss_latency::total 53381.433824 # average ReadReq miss latency 2314system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57473.404255 # average ReadExReq miss latency 2315system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76692.307692 # average ReadExReq miss latency 2316system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72375 # average ReadExReq miss latency 2317system.l2c.ReadExReq_avg_miss_latency::cpu3.data 63083.333333 # average ReadExReq miss latency 2318system.l2c.ReadExReq_avg_miss_latency::total 61259.541985 # average ReadExReq miss latency 2319system.l2c.demand_avg_miss_latency::cpu0.inst 50693.055556 # average overall miss latency 2320system.l2c.demand_avg_miss_latency::cpu0.data 59556.547619 # average overall miss latency 2321system.l2c.demand_avg_miss_latency::cpu1.inst 52768.292683 # average overall miss latency 2322system.l2c.demand_avg_miss_latency::cpu1.data 83150 # average overall miss latency 2323system.l2c.demand_avg_miss_latency::cpu2.inst 60035.714286 # average overall miss latency 2324system.l2c.demand_avg_miss_latency::cpu2.data 72076.923077 # average overall miss latency 2325system.l2c.demand_avg_miss_latency::cpu3.inst 43300 # average overall miss latency 2326system.l2c.demand_avg_miss_latency::cpu3.data 63500 # average overall miss latency 2327system.l2c.demand_avg_miss_latency::total 54910.370370 # average overall miss latency 2328system.l2c.overall_avg_miss_latency::cpu0.inst 50693.055556 # average overall miss latency 2329system.l2c.overall_avg_miss_latency::cpu0.data 59556.547619 # average overall miss latency 2330system.l2c.overall_avg_miss_latency::cpu1.inst 52768.292683 # average overall miss latency 2331system.l2c.overall_avg_miss_latency::cpu1.data 83150 # average overall miss latency 2332system.l2c.overall_avg_miss_latency::cpu2.inst 60035.714286 # average overall miss latency 2333system.l2c.overall_avg_miss_latency::cpu2.data 72076.923077 # average overall miss latency 2334system.l2c.overall_avg_miss_latency::cpu3.inst 43300 # average overall miss latency 2335system.l2c.overall_avg_miss_latency::cpu3.data 63500 # average overall miss latency 2336system.l2c.overall_avg_miss_latency::total 54910.370370 # average overall miss latency | 2387system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses 2388system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67155.988858 # average ReadReq miss latency 2389system.l2c.ReadReq_avg_miss_latency::cpu0.data 73763.513514 # average ReadReq miss latency 2390system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71280.487805 # average ReadReq miss latency 2391system.l2c.ReadReq_avg_miss_latency::cpu1.data 74428.571429 # average ReadReq miss latency 2392system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65181.818182 # average ReadReq miss latency 2393system.l2c.ReadReq_avg_miss_latency::cpu2.data 88500 # average ReadReq miss latency 2394system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65187.500000 # average ReadReq miss latency 2395system.l2c.ReadReq_avg_miss_latency::cpu3.data 88500 # average ReadReq miss latency 2396system.l2c.ReadReq_avg_miss_latency::total 68782.688766 # average ReadReq miss latency 2397system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78930.851064 # average ReadExReq miss latency 2398system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.076923 # average ReadExReq miss latency 2399system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75125 # average ReadExReq miss latency 2400system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70916.666667 # average ReadExReq miss latency 2401system.l2c.ReadExReq_avg_miss_latency::total 77748.091603 # average ReadExReq miss latency 2402system.l2c.demand_avg_miss_latency::cpu0.inst 67155.988858 # average overall miss latency 2403system.l2c.demand_avg_miss_latency::cpu0.data 76654.761905 # average overall miss latency 2404system.l2c.demand_avg_miss_latency::cpu1.inst 71280.487805 # average overall miss latency 2405system.l2c.demand_avg_miss_latency::cpu1.data 76700 # average overall miss latency 2406system.l2c.demand_avg_miss_latency::cpu2.inst 65181.818182 # average overall miss latency 2407system.l2c.demand_avg_miss_latency::cpu2.data 76153.846154 # average overall miss latency 2408system.l2c.demand_avg_miss_latency::cpu3.inst 65187.500000 # average overall miss latency 2409system.l2c.demand_avg_miss_latency::cpu3.data 72269.230769 # average overall miss latency 2410system.l2c.demand_avg_miss_latency::total 70525.222552 # average overall miss latency 2411system.l2c.overall_avg_miss_latency::cpu0.inst 67155.988858 # average overall miss latency 2412system.l2c.overall_avg_miss_latency::cpu0.data 76654.761905 # average overall miss latency 2413system.l2c.overall_avg_miss_latency::cpu1.inst 71280.487805 # average overall miss latency 2414system.l2c.overall_avg_miss_latency::cpu1.data 76700 # average overall miss latency 2415system.l2c.overall_avg_miss_latency::cpu2.inst 65181.818182 # average overall miss latency 2416system.l2c.overall_avg_miss_latency::cpu2.data 76153.846154 # average overall miss latency 2417system.l2c.overall_avg_miss_latency::cpu3.inst 65187.500000 # average overall miss latency 2418system.l2c.overall_avg_miss_latency::cpu3.data 72269.230769 # average overall miss latency 2419system.l2c.overall_avg_miss_latency::total 70525.222552 # average overall miss latency |
| 2337system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2338system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2339system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2340system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2341system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2342system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2343system.l2c.fast_writes 0 # number of fast writes performed 2344system.l2c.cache_copies 0 # number of cache copies performed 2345system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits | 2420system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2421system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2422system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2423system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2424system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2425system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2426system.l2c.fast_writes 0 # number of fast writes performed 2427system.l2c.cache_copies 0 # number of cache copies performed 2428system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits |
| 2346system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits 2347system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits | 2429system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 2430system.l2c.ReadReq_mshr_hits::cpu2.inst 8 # number of ReadReq MSHR hits |
| 2348system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits 2349system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 2350system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits | 2431system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits 2432system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 2433system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits |
| 2351system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2352system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits | 2434system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2435system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits |
| 2353system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits 2354system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 2355system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits | 2436system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits 2437system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 2438system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits |
| 2356system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2357system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits | 2439system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2440system.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits |
| 2358system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits 2359system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits | 2441system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits 2442system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits |
| 2360system.l2c.ReadReq_mshr_misses::cpu0.inst 358 # number of ReadReq MSHR misses | 2443system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses |
| 2361system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses | 2444system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses |
| 2362system.l2c.ReadReq_mshr_misses::cpu1.inst 78 # number of ReadReq MSHR misses | 2445system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses |
| 2363system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses | 2446system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses |
| 2364system.l2c.ReadReq_mshr_misses::cpu2.inst 8 # number of ReadReq MSHR misses | 2447system.l2c.ReadReq_mshr_misses::cpu2.inst 3 # number of ReadReq MSHR misses |
| 2365system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses | 2448system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses |
| 2366system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses | 2449system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses |
| 2367system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses | 2450system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses |
| 2368system.l2c.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses 2369system.l2c.UpgradeReq_mshr_misses::cpu0.data 18 # number of UpgradeReq MSHR misses 2370system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses 2371system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses 2372system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses 2373system.l2c.UpgradeReq_mshr_misses::total 74 # number of UpgradeReq MSHR misses | 2451system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses 2452system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses 2453system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses 2454system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 2455system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses 2456system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses |
| 2374system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2375system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2376system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2377system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2378system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses | 2457system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2458system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2459system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2460system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2461system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses |
| 2379system.l2c.demand_mshr_misses::cpu0.inst 358 # number of demand (read+write) MSHR misses | 2462system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses |
| 2380system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses | 2463system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses |
| 2381system.l2c.demand_mshr_misses::cpu1.inst 78 # number of demand (read+write) MSHR misses | 2464system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses |
| 2382system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses | 2465system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses |
| 2383system.l2c.demand_mshr_misses::cpu2.inst 8 # number of demand (read+write) MSHR misses | 2466system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses |
| 2384system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses | 2467system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses |
| 2385system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses | 2468system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses |
| 2386system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses | 2469system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses |
| 2387system.l2c.demand_mshr_misses::total 661 # number of demand (read+write) MSHR misses 2388system.l2c.overall_mshr_misses::cpu0.inst 358 # number of overall MSHR misses | 2470system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 2471system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses |
| 2389system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses | 2472system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses |
| 2390system.l2c.overall_mshr_misses::cpu1.inst 78 # number of overall MSHR misses | 2473system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses |
| 2391system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses | 2474system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses |
| 2392system.l2c.overall_mshr_misses::cpu2.inst 8 # number of overall MSHR misses | 2475system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses |
| 2393system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses | 2476system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses |
| 2394system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses | 2477system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses |
| 2395system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses | 2478system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses |
| 2396system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses 2397system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13764287 # number of ReadReq MSHR miss cycles 2398system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3693044 # number of ReadReq MSHR miss cycles 2399system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3149062 # number of ReadReq MSHR miss cycles 2400system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles 2401system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 315757 # number of ReadReq MSHR miss cycles 2402system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles 2403system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 113753 # number of ReadReq MSHR miss cycles 2404system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles 2405system.l2c.ReadReq_mshr_miss_latency::total 21726661 # number of ReadReq MSHR miss cycles 2406system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles 2407system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 201018 # number of UpgradeReq MSHR miss cycles 2408system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 172013 # number of UpgradeReq MSHR miss cycles 2409system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200514 # number of UpgradeReq MSHR miss cycles 2410system.l2c.UpgradeReq_mshr_miss_latency::total 757555 # number of UpgradeReq MSHR miss cycles 2411system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles 2412system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 839755 # number of ReadExReq MSHR miss cycles 2413system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles 2414system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 608510 # number of ReadExReq MSHR miss cycles 2415system.l2c.ReadExReq_mshr_miss_latency::total 6415333 # number of ReadExReq MSHR miss cycles 2416system.l2c.demand_mshr_miss_latency::cpu0.inst 13764287 # number of demand (read+write) MSHR miss cycles 2417system.l2c.demand_mshr_miss_latency::cpu0.data 7940102 # number of demand (read+write) MSHR miss cycles 2418system.l2c.demand_mshr_miss_latency::cpu1.inst 3149062 # number of demand (read+write) MSHR miss cycles 2419system.l2c.demand_mshr_miss_latency::cpu1.data 1418011 # number of demand (read+write) MSHR miss cycles 2420system.l2c.demand_mshr_miss_latency::cpu2.inst 315757 # number of demand (read+write) MSHR miss cycles 2421system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles 2422system.l2c.demand_mshr_miss_latency::cpu3.inst 113753 # number of demand (read+write) MSHR miss cycles 2423system.l2c.demand_mshr_miss_latency::cpu3.data 664761 # number of demand (read+write) MSHR miss cycles 2424system.l2c.demand_mshr_miss_latency::total 28141994 # number of demand (read+write) MSHR miss cycles 2425system.l2c.overall_mshr_miss_latency::cpu0.inst 13764287 # number of overall MSHR miss cycles 2426system.l2c.overall_mshr_miss_latency::cpu0.data 7940102 # number of overall MSHR miss cycles 2427system.l2c.overall_mshr_miss_latency::cpu1.inst 3149062 # number of overall MSHR miss cycles 2428system.l2c.overall_mshr_miss_latency::cpu1.data 1418011 # number of overall MSHR miss cycles 2429system.l2c.overall_mshr_miss_latency::cpu2.inst 315757 # number of overall MSHR miss cycles 2430system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles 2431system.l2c.overall_mshr_miss_latency::cpu3.inst 113753 # number of overall MSHR miss cycles 2432system.l2c.overall_mshr_miss_latency::cpu3.data 664761 # number of overall MSHR miss cycles 2433system.l2c.overall_mshr_miss_latency::total 28141994 # number of overall MSHR miss cycles 2434system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses | 2479system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses 2480system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19614500 # number of ReadReq MSHR miss cycles 2481system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4554750 # number of ReadReq MSHR miss cycles 2482system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4712500 # number of ReadReq MSHR miss cycles 2483system.l2c.ReadReq_mshr_miss_latency::cpu1.data 435750 # number of ReadReq MSHR miss cycles 2484system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 181750 # number of ReadReq MSHR miss cycles 2485system.l2c.ReadReq_mshr_miss_latency::cpu2.data 76250 # number of ReadReq MSHR miss cycles 2486system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 368750 # number of ReadReq MSHR miss cycles 2487system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles 2488system.l2c.ReadReq_mshr_miss_latency::total 30020500 # number of ReadReq MSHR miss cycles 2489system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles 2490system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190019 # number of UpgradeReq MSHR miss cycles 2491system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 169015 # number of UpgradeReq MSHR miss cycles 2492system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 180018 # number of UpgradeReq MSHR miss cycles 2493system.l2c.UpgradeReq_mshr_miss_latency::total 759074 # number of UpgradeReq MSHR miss cycles 2494system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6263250 # number of ReadExReq MSHR miss cycles 2495system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 854250 # number of ReadExReq MSHR miss cycles 2496system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 755250 # number of ReadExReq MSHR miss cycles 2497system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 703250 # number of ReadExReq MSHR miss cycles 2498system.l2c.ReadExReq_mshr_miss_latency::total 8576000 # number of ReadExReq MSHR miss cycles 2499system.l2c.demand_mshr_miss_latency::cpu0.inst 19614500 # number of demand (read+write) MSHR miss cycles 2500system.l2c.demand_mshr_miss_latency::cpu0.data 10818000 # number of demand (read+write) MSHR miss cycles 2501system.l2c.demand_mshr_miss_latency::cpu1.inst 4712500 # number of demand (read+write) MSHR miss cycles 2502system.l2c.demand_mshr_miss_latency::cpu1.data 1290000 # number of demand (read+write) MSHR miss cycles 2503system.l2c.demand_mshr_miss_latency::cpu2.inst 181750 # number of demand (read+write) MSHR miss cycles 2504system.l2c.demand_mshr_miss_latency::cpu2.data 831500 # number of demand (read+write) MSHR miss cycles 2505system.l2c.demand_mshr_miss_latency::cpu3.inst 368750 # number of demand (read+write) MSHR miss cycles 2506system.l2c.demand_mshr_miss_latency::cpu3.data 779500 # number of demand (read+write) MSHR miss cycles 2507system.l2c.demand_mshr_miss_latency::total 38596500 # number of demand (read+write) MSHR miss cycles 2508system.l2c.overall_mshr_miss_latency::cpu0.inst 19614500 # number of overall MSHR miss cycles 2509system.l2c.overall_mshr_miss_latency::cpu0.data 10818000 # number of overall MSHR miss cycles 2510system.l2c.overall_mshr_miss_latency::cpu1.inst 4712500 # number of overall MSHR miss cycles 2511system.l2c.overall_mshr_miss_latency::cpu1.data 1290000 # number of overall MSHR miss cycles 2512system.l2c.overall_mshr_miss_latency::cpu2.inst 181750 # number of overall MSHR miss cycles 2513system.l2c.overall_mshr_miss_latency::cpu2.data 831500 # number of overall MSHR miss cycles 2514system.l2c.overall_mshr_miss_latency::cpu3.inst 368750 # number of overall MSHR miss cycles 2515system.l2c.overall_mshr_miss_latency::cpu3.data 779500 # number of overall MSHR miss cycles 2516system.l2c.overall_mshr_miss_latency::total 38596500 # number of overall MSHR miss cycles 2517system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses |
| 2435system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses | 2518system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses |
| 2436system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for ReadReq accesses | 2519system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses |
| 2437system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses | 2520system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses |
| 2438system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for ReadReq accesses | 2521system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses |
| 2439system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses | 2522system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses |
| 2440system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses | 2523system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses |
| 2441system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses | 2524system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses |
| 2442system.l2c.ReadReq_mshr_miss_rate::total 0.266466 # mshr miss rate for ReadReq accesses 2443system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 # mshr miss rate for UpgradeReq accesses | 2525system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses 2526system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses |
| 2444system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2445system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2446system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 2527system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2528system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2529system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 2447system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses | 2530system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses |
| 2448system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2449system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2450system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2451system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2452system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 2531system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2532system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2533system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2534system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2535system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 2453system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses | 2536system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses |
| 2454system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses | 2537system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses |
| 2455system.l2c.demand_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for demand accesses | 2538system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses |
| 2456system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses | 2539system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses |
| 2457system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for demand accesses | 2540system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for demand accesses |
| 2458system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses | 2541system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses |
| 2459system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses | 2542system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses |
| 2460system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses | 2543system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses |
| 2461system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses 2462system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses | 2544system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses 2545system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses |
| 2463system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses | 2546system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses |
| 2464system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses | 2547system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses |
| 2465system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses | 2548system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses |
| 2466system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses | 2549system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for overall accesses |
| 2467system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses | 2550system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses |
| 2468system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses | 2551system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses |
| 2469system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses | 2552system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses |
| 2470system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses 2471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency 2472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency 2473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency 2474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency 2475system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency 2476system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency 2477system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency 2478system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency 2479system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency 2480system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency 2481system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency 2482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency 2483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency 2484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency 2485system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency 2486system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency 2487system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency 2488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency 2489system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency 2490system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency 2491system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency 2492system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency 2493system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency 2494system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency 2495system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2496system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency 2497system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency 2498system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency 2499system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency 2500system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency 2501system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency 2502system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency 2503system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency 2504system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2505system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency 2506system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency 2507system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency | 2553system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses 2554system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average ReadReq mshr miss latency 2555system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61550.675676 # average ReadReq mshr miss latency 2556system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average ReadReq mshr miss latency 2557system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62250 # average ReadReq mshr miss latency 2558system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average ReadReq mshr miss latency 2559system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 76250 # average ReadReq mshr miss latency 2560system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average ReadReq mshr miss latency 2561system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency 2562system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency 2563system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 2564system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 2565system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency 2566system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 2567system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency 2568system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency 2569system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency 2570system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency 2571system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency 2572system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency 2573system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency 2574system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency 2575system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency 2576system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency 2577system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency 2578system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency 2579system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency 2580system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency 2581system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency 2582system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency 2583system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency 2584system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency 2585system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency 2586system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency 2587system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency 2588system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency 2589system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency 2590system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency |
| 2508system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2509 2510---------- End Simulation Statistics ---------- | 2591system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2592 2593---------- End Simulation Statistics ---------- |