| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105801500 # Number of ticks simulated 5final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105801500 # Number of ticks simulated 5final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 99938 # Simulator instruction rate (inst/s) 8host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10207562 # Simulator tick rate (ticks/s) 10host_mem_usage 247464 # Number of bytes of host memory used 11host_seconds 10.37 # Real time elapsed on the host | 7host_inst_rate 173787 # Simulator instruction rate (inst/s) 8host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17750545 # Simulator tick rate (ticks/s) 10host_mem_usage 247480 # Number of bytes of host memory used 11host_seconds 5.96 # Real time elapsed on the host |
| 12sim_insts 1035849 # Number of instructions simulated 13sim_ops 1035849 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 34 unchanged lines hidden (view full) --- 54system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 661 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen | 12sim_insts 1035849 # Number of instructions simulated 13sim_ops 1035849 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory --- 34 unchanged lines hidden (view full) --- 54system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 661 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen |
| 62system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady | 62system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady |
| 63system.physmem.bytesRead 42240 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 68system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis --- 32 unchanged lines hidden (view full) --- 103system.physmem.totGap 105773500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes 110system.physmem.readPktSize::6 661 # Categorize read packet sizes | 63system.physmem.bytesRead 42240 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 68system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis --- 32 unchanged lines hidden (view full) --- 103system.physmem.totGap 105773500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes 110system.physmem.readPktSize::6 661 # Categorize read packet sizes |
| 111system.physmem.readPktSize::7 0 # Categorize read packet sizes 112system.physmem.readPktSize::8 0 # Categorize read packet sizes 113system.physmem.writePktSize::0 0 # categorize write packet sizes 114system.physmem.writePktSize::1 0 # categorize write packet sizes 115system.physmem.writePktSize::2 0 # categorize write packet sizes 116system.physmem.writePktSize::3 0 # categorize write packet sizes 117system.physmem.writePktSize::4 0 # categorize write packet sizes 118system.physmem.writePktSize::5 0 # categorize write packet sizes 119system.physmem.writePktSize::6 0 # categorize write packet sizes 120system.physmem.writePktSize::7 0 # categorize write packet sizes 121system.physmem.writePktSize::8 0 # categorize write packet sizes 122system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 123system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 124system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 125system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 126system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 127system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 128system.physmem.neitherpktsize::6 71 # categorize neither packet sizes 129system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 130system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 111system.physmem.writePktSize::0 0 # Categorize write packet sizes 112system.physmem.writePktSize::1 0 # Categorize write packet sizes 113system.physmem.writePktSize::2 0 # Categorize write packet sizes 114system.physmem.writePktSize::3 0 # Categorize write packet sizes 115system.physmem.writePktSize::4 0 # Categorize write packet sizes 116system.physmem.writePktSize::5 0 # Categorize write packet sizes 117system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 131system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 155system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 118system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 142system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 163system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | |
| 164system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 196system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 197system.physmem.totQLat 4077160 # Total cycles spent in queuing delays 198system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests | 182system.physmem.totQLat 4076500 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests |
| 199system.physmem.totBusLat 3305000 # Total cycles spent in databus access 200system.physmem.totBankLat 13310000 # Total cycles spent in bank access | 184system.physmem.totBusLat 3305000 # Total cycles spent in databus access 185system.physmem.totBankLat 13310000 # Total cycles spent in bank access |
| 201system.physmem.avgQLat 6168.17 # Average queueing delay per request | 186system.physmem.avgQLat 6167.17 # Average queueing delay per request |
| 202system.physmem.avgBankLat 20136.16 # Average bank access latency per request 203system.physmem.avgBusLat 5000.00 # Average bus latency per request | 187system.physmem.avgBankLat 20136.16 # Average bank access latency per request 188system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 204system.physmem.avgMemAccLat 31304.33 # Average memory access latency | 189system.physmem.avgMemAccLat 31303.33 # Average memory access latency |
| 205system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 207system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s 208system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 210system.physmem.busUtil 3.12 # Data bus utilization in percentage 211system.physmem.avgRdQLen 0.20 # Average read queue length over time 212system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 1899 unchanged lines hidden (view full) --- 2112system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency 2113system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency 2114system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2115system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2116system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2117system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2118system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2119system.l2c.replacements 0 # number of replacements | 190system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s 191system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 192system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s 193system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 195system.physmem.busUtil 3.12 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.20 # Average read queue length over time 197system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 1899 unchanged lines hidden (view full) --- 2097system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency 2098system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency 2099system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2100system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2101system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2102system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2103system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2104system.l2c.replacements 0 # number of replacements |
| 2120system.l2c.tagsinuse 425.230692 # Cycle average of tags in use | 2105system.l2c.tagsinuse 425.230696 # Cycle average of tags in use |
| 2121system.l2c.total_refs 1445 # Total number of references to valid blocks. 2122system.l2c.sampled_refs 527 # Sample count of references to valid blocks. 2123system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. 2124system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2125system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor | 2106system.l2c.total_refs 1445 # Total number of references to valid blocks. 2107system.l2c.sampled_refs 527 # Sample count of references to valid blocks. 2108system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. 2109system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2110system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor |
| 2126system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor | 2111system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor |
| 2127system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor | 2112system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor |
| 2128system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor | 2113system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor |
| 2129system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor | 2114system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor |
| 2130system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor | 2115system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor |
| 2131system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor 2132system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor 2133system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor 2134system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 2135system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy 2136system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy 2137system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy 2138system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy --- 265 unchanged lines hidden (view full) --- 2404system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 2405system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses 2406system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses 2407system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses 2408system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses 2409system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses 2410system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2411system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses | 2116system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor 2117system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor 2118system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor 2119system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 2120system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy 2121system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy 2122system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy 2123system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy --- 265 unchanged lines hidden (view full) --- 2389system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 2390system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses 2391system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses 2392system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses 2393system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses 2394system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses 2395system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2396system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses |
| 2412system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles 2413system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles 2414system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles 2415system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles 2416system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles 2417system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles 2418system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles 2419system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles 2420system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles | 2397system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13752787 # number of ReadReq MSHR miss cycles 2398system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705044 # number of ReadReq MSHR miss cycles 2399system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257064 # number of ReadReq MSHR miss cycles 2400system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles 2401system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230755 # number of ReadReq MSHR miss cycles 2402system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles 2403system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86253 # number of ReadReq MSHR miss cycles 2404system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles 2405system.l2c.ReadReq_mshr_miss_latency::total 21722661 # number of ReadReq MSHR miss cycles |
| 2421system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles 2422system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles 2423system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles 2424system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles 2425system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles | 2406system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles 2407system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles 2408system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles 2409system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles 2410system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles |
| 2426system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles 2427system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles 2428system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles 2429system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles 2430system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles 2431system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles 2432system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles 2433system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles 2434system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles 2435system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles 2436system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles 2437system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles 2438system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles 2439system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles 2440system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles 2441system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles 2442system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles 2443system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles 2444system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles 2445system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles 2446system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles 2447system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles 2448system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles | 2411system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles 2412system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838755 # number of ReadExReq MSHR miss cycles 2413system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles 2414system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607510 # number of ReadExReq MSHR miss cycles 2415system.l2c.ReadExReq_mshr_miss_latency::total 6413333 # number of ReadExReq MSHR miss cycles 2416system.l2c.demand_mshr_miss_latency::cpu0.inst 13752787 # number of demand (read+write) MSHR miss cycles 2417system.l2c.demand_mshr_miss_latency::cpu0.data 7952102 # number of demand (read+write) MSHR miss cycles 2418system.l2c.demand_mshr_miss_latency::cpu1.inst 3257064 # number of demand (read+write) MSHR miss cycles 2419system.l2c.demand_mshr_miss_latency::cpu1.data 1417011 # number of demand (read+write) MSHR miss cycles 2420system.l2c.demand_mshr_miss_latency::cpu2.inst 230755 # number of demand (read+write) MSHR miss cycles 2421system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles 2422system.l2c.demand_mshr_miss_latency::cpu3.inst 86253 # number of demand (read+write) MSHR miss cycles 2423system.l2c.demand_mshr_miss_latency::cpu3.data 663761 # number of demand (read+write) MSHR miss cycles 2424system.l2c.demand_mshr_miss_latency::total 28135994 # number of demand (read+write) MSHR miss cycles 2425system.l2c.overall_mshr_miss_latency::cpu0.inst 13752787 # number of overall MSHR miss cycles 2426system.l2c.overall_mshr_miss_latency::cpu0.data 7952102 # number of overall MSHR miss cycles 2427system.l2c.overall_mshr_miss_latency::cpu1.inst 3257064 # number of overall MSHR miss cycles 2428system.l2c.overall_mshr_miss_latency::cpu1.data 1417011 # number of overall MSHR miss cycles 2429system.l2c.overall_mshr_miss_latency::cpu2.inst 230755 # number of overall MSHR miss cycles 2430system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles 2431system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles 2432system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles 2433system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles |
| 2449system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses 2450system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2451system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses 2452system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses 2453system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses 2454system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses 2455system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses 2456system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses --- 21 unchanged lines hidden (view full) --- 2478system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses 2480system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2481system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses 2482system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2483system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses 2484system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2485system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses | 2434system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses 2435system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2436system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses 2437system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses 2438system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses 2439system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses 2440system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses 2441system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses --- 21 unchanged lines hidden (view full) --- 2463system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2464system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses 2465system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2466system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses 2467system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2468system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses 2469system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2470system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses |
| 2486system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency 2487system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency 2488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency 2489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency 2490system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency 2491system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency 2492system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency 2493system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency 2494system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency | 2471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency 2472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency 2473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency 2474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency 2475system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency 2476system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency 2477system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency 2478system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency 2479system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency |
| 2495system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency 2496system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency 2497system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency 2498system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency 2499system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency | 2480system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency 2481system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency 2482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency 2483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency 2484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency |
| 2500system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency 2501system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency 2502system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency 2503system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency 2504system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency 2505system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency 2506system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency 2507system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency 2508system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency 2509system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency 2510system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency 2511system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency 2512system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency 2513system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency 2514system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency 2515system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency 2516system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency 2517system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency 2518system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency 2519system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency 2520system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency 2521system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency 2522system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency | 2485system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency 2486system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency 2487system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency 2488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency 2489system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency 2490system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency 2491system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency 2492system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency 2493system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency 2494system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency 2495system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2496system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency 2497system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency 2498system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency 2499system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency 2500system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency 2501system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency 2502system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency 2503system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency 2504system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency 2505system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency 2506system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency 2507system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency |
| 2523system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2524 2525---------- End Simulation Statistics ---------- | 2508system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2509 2510---------- End Simulation Statistics ---------- |