| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000105 # Number of seconds simulated 4sim_ticks 104832500 # Number of ticks simulated 5final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 105801500 # Number of ticks simulated 5final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 81452 # Simulator instruction rate (inst/s) 8host_op_rate 81452 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8250764 # Simulator tick rate (ticks/s) 10host_mem_usage 293492 # Number of bytes of host memory used 11host_seconds 12.71 # Real time elapsed on the host 12sim_insts 1034907 # Number of instructions simulated 13sim_ops 1034907 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory | 7host_inst_rate 99938 # Simulator instruction rate (inst/s) 8host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10207562 # Simulator tick rate (ticks/s) 10host_mem_usage 247464 # Number of bytes of host memory used 11host_seconds 10.37 # Real time elapsed on the host 12sim_insts 1035849 # Number of instructions simulated 13sim_ops 1035849 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 42112 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory | 22system.physmem.bytes_read::total 42240 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::total 658 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 659 # Total number of read requests seen | 36system.physmem.num_reads::total 660 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 661 # Total number of read requests seen |
| 61system.physmem.writeReqs 0 # Total number of write requests seen | 61system.physmem.writeReqs 0 # Total number of write requests seen |
| 62system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady 63system.physmem.bytesRead 42112 # Total number of bytes read from memory | 62system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady 63system.physmem.bytesRead 42240 # Total number of bytes read from memory |
| 64system.physmem.bytesWritten 0 # Total number of bytes written to memory | 64system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 65system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() | 65system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() |
| 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q |
| 68system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis | 68system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis |
| 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 103system.physmem.totGap 104804500 # Total gap between requests | 103system.physmem.totGap 105773500 # Total gap between requests |
| 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes | 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 110system.physmem.readPktSize::6 659 # Categorize read packet sizes | 110system.physmem.readPktSize::6 661 # Categorize read packet sizes |
| 111system.physmem.readPktSize::7 0 # Categorize read packet sizes 112system.physmem.readPktSize::8 0 # Categorize read packet sizes 113system.physmem.writePktSize::0 0 # categorize write packet sizes 114system.physmem.writePktSize::1 0 # categorize write packet sizes 115system.physmem.writePktSize::2 0 # categorize write packet sizes 116system.physmem.writePktSize::3 0 # categorize write packet sizes 117system.physmem.writePktSize::4 0 # categorize write packet sizes 118system.physmem.writePktSize::5 0 # categorize write packet sizes 119system.physmem.writePktSize::6 0 # categorize write packet sizes 120system.physmem.writePktSize::7 0 # categorize write packet sizes 121system.physmem.writePktSize::8 0 # categorize write packet sizes 122system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 123system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 124system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 125system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 126system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 127system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 111system.physmem.readPktSize::7 0 # Categorize read packet sizes 112system.physmem.readPktSize::8 0 # Categorize read packet sizes 113system.physmem.writePktSize::0 0 # categorize write packet sizes 114system.physmem.writePktSize::1 0 # categorize write packet sizes 115system.physmem.writePktSize::2 0 # categorize write packet sizes 116system.physmem.writePktSize::3 0 # categorize write packet sizes 117system.physmem.writePktSize::4 0 # categorize write packet sizes 118system.physmem.writePktSize::5 0 # categorize write packet sizes 119system.physmem.writePktSize::6 0 # categorize write packet sizes 120system.physmem.writePktSize::7 0 # categorize write packet sizes 121system.physmem.writePktSize::8 0 # categorize write packet sizes 122system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 123system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 124system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 125system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 126system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 127system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| 128system.physmem.neitherpktsize::6 72 # categorize neither packet sizes | 128system.physmem.neitherpktsize::6 71 # categorize neither packet sizes |
| 129system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 130system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 129system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 130system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 131system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see | 131system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see |
| 136system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 136system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 197system.physmem.totQLat 2976655 # Total cycles spent in queuing delays 198system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests 199system.physmem.totBusLat 2636000 # Total cycles spent in databus access 200system.physmem.totBankLat 12138000 # Total cycles spent in bank access 201system.physmem.avgQLat 4516.93 # Average queueing delay per request 202system.physmem.avgBankLat 18418.82 # Average bank access latency per request 203system.physmem.avgBusLat 4000.00 # Average bus latency per request 204system.physmem.avgMemAccLat 26935.74 # Average memory access latency 205system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s | 197system.physmem.totQLat 4077160 # Total cycles spent in queuing delays 198system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests 199system.physmem.totBusLat 3305000 # Total cycles spent in databus access 200system.physmem.totBankLat 13310000 # Total cycles spent in bank access 201system.physmem.avgQLat 6168.17 # Average queueing delay per request 202system.physmem.avgBankLat 20136.16 # Average bank access latency per request 203system.physmem.avgBusLat 5000.00 # Average bus latency per request 204system.physmem.avgMemAccLat 31304.33 # Average memory access latency 205system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s |
| 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 207system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s | 207system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s |
| 208system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s | 208system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s |
| 209system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 210system.physmem.busUtil 2.51 # Data bus utilization in percentage 211system.physmem.avgRdQLen 0.17 # Average read queue length over time | 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 210system.physmem.busUtil 3.12 # Data bus utilization in percentage 211system.physmem.avgRdQLen 0.20 # Average read queue length over time |
| 212system.physmem.avgWrQLen 0.00 # Average write queue length over time | 212system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 213system.physmem.readRowHits 506 # Number of row buffer hits during reads | 213system.physmem.readRowHits 465 # Number of row buffer hits during reads |
| 214system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 214system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 215system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads | 215system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads |
| 216system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 216system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 217system.physmem.avgGap 159035.66 # Average gap between requests 218system.cpu0.branchPred.lookups 82004 # Number of BP lookups 219system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted 220system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect 221system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups 222system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits | 217system.physmem.avgGap 160020.42 # Average gap between requests 218system.cpu0.branchPred.lookups 82232 # Number of BP lookups 219system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted 220system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect 221system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups 222system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits |
| 223system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 223system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 224system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage 225system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target. | 224system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage 225system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. |
| 226system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 227system.cpu0.workload.num_syscalls 89 # Number of system calls | 226system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 227system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 228system.cpu0.numCycles 209666 # number of cpu cycles simulated | 228system.cpu0.numCycles 211604 # number of cpu cycles simulated |
| 229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 231system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss 232system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed 233system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered 234system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken 235system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked 236system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing 237system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked | 231system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss 232system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed 233system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered 234system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken 235system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked 236system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing 237system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked |
| 238system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 238system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 239system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps 240system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched 241system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed 242system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) 243system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) 244system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) | 239system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps 240system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched 241system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed 242system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) 243system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) 244system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) |
| 245system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 245system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 246system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) 247system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) 248system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) 249system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) 250system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) 251system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) 252system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) 253system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) 254system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) | 246system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) 247system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) 248system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) 249system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) 250system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) 251system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) 252system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) 253system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) 254system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) |
| 255system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 256system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 257system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 255system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 256system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 257system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 258system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) 259system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle 260system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle 261system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle 262system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked 263system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running 264system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking 265system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing 266system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode 267system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing 268system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle 269system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking 270system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst 271system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running 272system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking 273system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename | 258system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) 259system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle 260system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle 261system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle 262system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked 263system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running 264system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking 265system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing 266system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode 267system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing 268system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle 269system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking 270system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst 271system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running 272system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking 273system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename |
| 274system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full | 274system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full |
| 275system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full 276system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed 277system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made 278system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups 279system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed 280system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing 281system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed 282system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed 283system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer 284system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. 285system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. 286system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. 287system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. 288system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) 289system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ 290system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued 291system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 292system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling 293system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph 294system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed 295system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle 296system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle 297system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle | 275system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full 276system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed 277system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made 278system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups 279system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed 280system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing 281system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed 282system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed 283system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer 284system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. 285system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. 286system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. 287system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. 288system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) 289system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ 290system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued 291system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued 292system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling 293system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph 294system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed 295system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle 296system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle 297system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle |
| 298system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 298system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 299system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle 300system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle 301system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle 302system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle 303system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle 304system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle 305system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle 306system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle 307system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle | 299system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle 300system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle 301system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle 302system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle 303system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle 304system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle 305system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle 306system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle 307system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle |
| 308system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 309system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 310system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 308system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 309system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 310system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 311system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle | 311system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle |
| 312system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 312system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 313system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available 314system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available 315system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available 316system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available 317system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available 318system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available 319system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available 320system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available 321system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available 322system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available 323system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available 324system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available 325system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available 326system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available 327system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available 328system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available 329system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available 330system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available 331system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available 332system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available 333system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available 334system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available 335system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available 336system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available 337system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available 338system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available 339system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available 340system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available 341system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available 342system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available 343system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available | 313system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available 314system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available 315system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available 316system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available 317system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available 318system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available 319system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available 320system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available 321system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available 322system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available 323system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available 324system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available 325system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available 326system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available 327system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available 328system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available 329system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available 330system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available 331system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available 332system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available 333system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available 334system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available 335system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available 336system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available 337system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available 338system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available 339system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available 340system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available 341system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available 342system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available 343system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available |
| 344system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 346system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 344system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 346system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 347system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued 348system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued 349system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued 350system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued 351system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued 352system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued 353system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued 354system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued 355system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued 356system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued 357system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued 358system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued 359system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued 360system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued 361system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued 362system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued 363system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued 364system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued 365system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued 366system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued 367system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued 368system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued 369system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued 370system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued 371system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued 372system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued 373system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued 374system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued 375system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued 376system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued 377system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued | 347system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued 348system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued 349system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued 350system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued 351system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued 352system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued 353system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued 354system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued 355system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued 356system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued 357system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued 358system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued 359system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued 360system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued 361system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued 362system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued 363system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued 364system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued 365system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued 366system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued 367system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued 368system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued 369system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued 370system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued 371system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued 372system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued 373system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued 374system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued 375system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued 376system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued 377system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued |
| 378system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 379system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 378system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 379system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 380system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued 381system.cpu0.iq.rate 1.905664 # Inst issue rate 382system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested 383system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) 384system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads 385system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes 386system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses | 380system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued 381system.cpu0.iq.rate 1.891623 # Inst issue rate 382system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested 383system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) 384system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads 385system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes 386system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses |
| 387system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 388system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 389system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 387system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 388system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 389system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 390system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses | 390system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses |
| 391system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 391system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 392system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores | 392system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores |
| 393system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 393system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 394system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed 395system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 396system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 397system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed | 394system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed 395system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 396system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations 397system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed |
| 398system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 399system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 400system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 398system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 399system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 400system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 401system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked | 401system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked |
| 402system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 402system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 403system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing 404system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking 405system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking 406system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ 407system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch 408system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions 409system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions 410system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions 411system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall | 403system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing 404system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking 405system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 406system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ 407system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch 408system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions 409system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions 410system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions 411system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall |
| 412system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 412system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 413system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations 414system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly 415system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly 416system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute 417system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions 418system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed 419system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute | 413system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations 414system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly 415system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly 416system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute 417system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions 418system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed 419system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute |
| 420system.cpu0.iew.exec_swp 0 # number of swp insts executed | 420system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 421system.cpu0.iew.exec_nop 75469 # number of nop insts executed 422system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed 423system.cpu0.iew.exec_branches 79152 # Number of branches executed 424system.cpu0.iew.exec_stores 77032 # Number of stores executed 425system.cpu0.iew.exec_rate 1.900537 # Inst execution rate 426system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit 427system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back 428system.cpu0.iew.wb_producers 235728 # num instructions producing a value 429system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value | 421system.cpu0.iew.exec_nop 75651 # number of nop insts executed 422system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed 423system.cpu0.iew.exec_branches 79264 # Number of branches executed 424system.cpu0.iew.exec_stores 77169 # Number of stores executed 425system.cpu0.iew.exec_rate 1.886439 # Inst execution rate 426system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit 427system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back 428system.cpu0.iew.wb_producers 236156 # num instructions producing a value 429system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value |
| 430system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 430system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 431system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle 432system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back | 431system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle 432system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back |
| 433system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 433system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 434system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit | 434system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit |
| 435system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards | 435system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards |
| 436system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 437system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle 438system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle 439system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle | 436system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted 437system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle 438system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle 439system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle |
| 440system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 440system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 441system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle 442system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle 443system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle 444system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle 445system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle 446system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle 447system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle 448system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle 449system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle | 441system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle 442system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle 443system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle 444system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle 445system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle 446system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle 447system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle 448system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle 449system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle |
| 450system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 451system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 452system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 450system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 451system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 452system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 453system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle 454system.cpu0.commit.committedInsts 466344 # Number of instructions committed 455system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed | 453system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle 454system.cpu0.commit.committedInsts 467088 # Number of instructions committed 455system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed |
| 456system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 456system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 457system.cpu0.commit.refs 227887 # Number of memory references committed 458system.cpu0.commit.loads 151587 # Number of loads committed | 457system.cpu0.commit.refs 228259 # Number of memory references committed 458system.cpu0.commit.loads 151835 # Number of loads committed |
| 459system.cpu0.commit.membars 84 # Number of memory barriers committed | 459system.cpu0.commit.membars 84 # Number of memory barriers committed |
| 460system.cpu0.commit.branches 78187 # Number of branches committed | 460system.cpu0.commit.branches 78311 # Number of branches committed |
| 461system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 461system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
| 462system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. | 462system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. |
| 463system.cpu0.commit.function_calls 223 # Number of function calls committed. | 463system.cpu0.commit.function_calls 223 # Number of function calls committed. |
| 464system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached | 464system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached |
| 465system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 465system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 466system.cpu0.rob.rob_reads 667504 # The number of ROB reads 467system.cpu0.rob.rob_writes 959472 # The number of ROB writes 468system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself 469system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling 470system.cpu0.committedInsts 391341 # Number of Instructions Simulated 471system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated 472system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated 473system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction 474system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads 475system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle 476system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads 477system.cpu0.int_regfile_reads 712766 # number of integer regfile reads 478system.cpu0.int_regfile_writes 321389 # number of integer regfile writes | 466system.cpu0.rob.rob_reads 669667 # The number of ROB reads 467system.cpu0.rob.rob_writes 961765 # The number of ROB writes 468system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself 469system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling 470system.cpu0.committedInsts 391961 # Number of Instructions Simulated 471system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated 472system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated 473system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction 474system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads 475system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle 476system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads 477system.cpu0.int_regfile_reads 714059 # number of integer regfile reads 478system.cpu0.int_regfile_writes 321926 # number of integer regfile writes |
| 479system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 479system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
| 480system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads | 480system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads |
| 481system.cpu0.misc_regfile_writes 564 # number of misc regfile writes | 481system.cpu0.misc_regfile_writes 564 # number of misc regfile writes |
| 482system.cpu0.icache.replacements 297 # number of replacements 483system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use 484system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. 485system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. 486system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. | 482system.cpu0.icache.replacements 298 # number of replacements 483system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use 484system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. 485system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. 486system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. |
| 487system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 487system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 488system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor 489system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy 490system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy 491system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits 492system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits 493system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits 494system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits 495system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits 496system.cpu0.icache.overall_hits::total 5129 # number of overall hits 497system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses 498system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses 499system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses 500system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses 501system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses 502system.cpu0.icache.overall_misses::total 742 # number of overall misses 503system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles 504system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles 505system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles 506system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles 507system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles 508system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles 509system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) 510system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) 511system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses 512system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses 513system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses 514system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses 515system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses 516system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses 517system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses 518system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses 519system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses 520system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses 521system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency 522system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency 523system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency 524system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency 525system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency 526system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency | 488system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor 489system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy 490system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy 491system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits 492system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits 493system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits 494system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits 495system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits 496system.cpu0.icache.overall_hits::total 5162 # number of overall hits 497system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses 498system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses 499system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses 500system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses 501system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses 502system.cpu0.icache.overall_misses::total 744 # number of overall misses 503system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles 504system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles 505system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles 506system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles 507system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles 508system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles 509system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) 510system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) 511system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses 512system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses 513system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses 514system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses 515system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses 516system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses 517system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses 518system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses 519system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses 520system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses 521system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency 522system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency 523system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency 524system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency 525system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency 526system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency |
| 527system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 528system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 529system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 530system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 531system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 532system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 533system.cpu0.icache.fast_writes 0 # number of fast writes performed 534system.cpu0.icache.cache_copies 0 # number of cache copies performed 535system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits 536system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits 537system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits 538system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits 539system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits 540system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits | 527system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 528system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 529system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 530system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 531system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 532system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 533system.cpu0.icache.fast_writes 0 # number of fast writes performed 534system.cpu0.icache.cache_copies 0 # number of cache copies performed 535system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits 536system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits 537system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits 538system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits 539system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits 540system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits |
| 541system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 542system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 543system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 544system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 545system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 546system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 547system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles 548system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles 549system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles 550system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles 551system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles 552system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles 553system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses 554system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses 555system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses 556system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses 557system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses 558system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses 559system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency 560system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency 561system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency 562system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency 563system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency 564system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency | 541system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses 542system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses 543system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses 544system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses 545system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses 546system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses 547system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles 548system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles 549system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles 550system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles 551system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles 552system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles 553system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses 554system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses 555system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses 556system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses 557system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses 558system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses 559system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency 560system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency 561system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency 562system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency 563system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency 564system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency |
| 565system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 566system.cpu0.dcache.replacements 2 # number of replacements | 565system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 566system.cpu0.dcache.replacements 2 # number of replacements |
| 567system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use 568system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. | 567system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use 568system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. |
| 569system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. | 569system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. |
| 570system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. | 570system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. |
| 571system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 571system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 572system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor 573system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy 574system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy 575system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits 576system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits 577system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits 578system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits 579system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits 580system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits 581system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits 582system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits 583system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits 584system.cpu0.dcache.overall_hits::total 153639 # number of overall hits 585system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses 586system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses 587system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses 588system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses 589system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses 590system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses 591system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses 592system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses 593system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses 594system.cpu0.dcache.overall_misses::total 1021 # number of overall misses 595system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles 596system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles 598system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles 599system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles 600system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles 601system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles 602system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles 603system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles 604system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles 605system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) 606system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) 607system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) 608system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) | 572system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor 573system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy 574system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy 575system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits 576system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits 577system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits 578system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits 579system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 580system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 581system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits 582system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits 583system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits 584system.cpu0.dcache.overall_hits::total 153944 # number of overall hits 585system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses 586system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses 587system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses 588system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses 589system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 590system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 591system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses 592system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses 593system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses 594system.cpu0.dcache.overall_misses::total 1018 # number of overall misses 595system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles 596system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles 598system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles 599system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles 600system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles 601system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles 602system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles 603system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles 604system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles 605system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) 606system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) 607system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) 608system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) |
| 609system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 610system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 609system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 610system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 611system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses 612system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses 613system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses 614system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses 615system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses 616system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses 617system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses 618system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses 619system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses 620system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses 621system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses 622system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses 623system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses 624system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses 625system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency 626system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency 627system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency 628system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency 629system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency 630system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency 631system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency 632system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency 633system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency 634system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency 635system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked | 611system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses 612system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses 613system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses 614system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses 615system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses 616system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses 617system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses 618system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses 619system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 620system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 621system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses 622system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses 623system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses 624system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses 625system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency 626system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency 627system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency 628system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency 629system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency 630system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency 631system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency 632system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency 633system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency 634system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency 635system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked |
| 636system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 638system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 636system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 638system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 639system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked | 639system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked |
| 640system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu0.dcache.fast_writes 0 # number of fast writes performed 642system.cpu0.dcache.cache_copies 0 # number of cache copies performed 643system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 644system.cpu0.dcache.writebacks::total 1 # number of writebacks | 640system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu0.dcache.fast_writes 0 # number of fast writes performed 642system.cpu0.dcache.cache_copies 0 # number of cache copies performed 643system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 644system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 645system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits 646system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits 647system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits 648system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits 649system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits 650system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits 651system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits 652system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits 653system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses 654system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses 655system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses 656system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses 657system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses 658system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses 659system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 660system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 661system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 662system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses 663system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles 664system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles 665system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles 666system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles 667system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles 668system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles 669system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles 670system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles 671system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles 672system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles 673system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses 674system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses 675system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses 676system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses 677system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses 678system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses 679system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses 680system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses 681system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses 682system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses 683system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency 684system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency 685system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency 686system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency 687system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency 688system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency 689system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency 690system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency 691system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency 692system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency | 645system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits 646system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits 647system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits 648system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits 649system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits 650system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits 651system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits 652system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits 653system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses 654system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses 655system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses 656system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses 657system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 658system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 659system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses 660system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses 661system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses 662system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses 663system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles 664system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles 665system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles 666system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles 667system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles 668system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles 669system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles 670system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles 671system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles 672system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles 673system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses 674system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses 675system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses 676system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses 677system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 678system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 679system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses 680system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses 681system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses 682system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses 683system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency 684system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency 685system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency 686system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency 687system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency 688system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency 689system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency 690system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency 691system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency 692system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency |
| 693system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 693system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 694system.cpu1.branchPred.lookups 52905 # Number of BP lookups 695system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted 696system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect 697system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups 698system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits | 694system.cpu1.branchPred.lookups 58098 # Number of BP lookups 695system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted 696system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect 697system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups 698system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits |
| 699system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 699system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 700system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage 701system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. | 700system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage 701system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. |
| 702system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 702system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 703system.cpu1.numCycles 174086 # number of cpu cycles simulated | 703system.cpu1.numCycles 174790 # number of cpu cycles simulated |
| 704system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 705system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 704system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 705system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 706system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss 707system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed 708system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered 709system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken 710system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked 711system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing 712system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked 713system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 714system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from 715system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps 716system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched 717system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed 718system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) 719system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) 720system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) | 706system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss 707system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed 708system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered 709system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken 710system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked 711system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing 712system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked 713system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 714system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from 715system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps 716system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched 717system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed 718system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) 719system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) 720system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) |
| 721system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 721system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 722system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) 723system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) 724system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) 725system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) 726system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) 727system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) 728system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) 729system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) 730system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) | 722system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) 723system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) 724system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) 725system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) 726system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) 727system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) 728system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) 729system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) 730system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 731system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 732system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 733system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 731system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 732system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 733system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 734system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) 735system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle 736system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle 737system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle 738system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked 739system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running 740system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking 741system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing 742system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode 743system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing 744system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle 745system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking 746system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst 747system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running 748system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking 749system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename 750system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full 751system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed 752system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made 753system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups 754system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed 755system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing 756system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed 757system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed 758system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer 759system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. 760system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. 761system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. 762system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. 763system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) 764system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ 765system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued 766system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued 767system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling 768system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph 769system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed 770system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle 771system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle 772system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle | 734system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) 735system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle 736system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle 737system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle 738system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked 739system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running 740system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking 741system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing 742system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode 743system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing 744system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle 745system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking 746system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst 747system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running 748system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking 749system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename 750system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 751system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full 752system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed 753system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made 754system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups 755system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed 756system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing 757system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed 758system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed 759system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer 760system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. 761system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. 762system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. 763system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. 764system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) 765system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ 766system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued 767system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued 768system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling 769system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph 770system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed 771system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle 772system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle 773system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle |
| 773system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 774system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 774system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle 775system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle 776system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle 777system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle 778system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle 779system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle 780system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle | 775system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle 776system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle 777system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle 778system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle 779system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle 780system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle 781system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle |
| 781system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 782system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 783system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 784system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 785system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 782system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 783system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 784system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 785system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 786system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 786system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle | 787system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle |
| 787system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 788system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 788system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available 789system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available 790system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available 791system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available 792system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available 793system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available 794system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available 795system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available 796system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available 797system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available 798system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available 799system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available 800system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available 801system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available 802system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available 803system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available 804system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available 805system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available 806system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available 807system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available 808system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available 809system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available 810system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available 811system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available 812system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available 813system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available 814system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available 815system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available 816system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available 817system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available 818system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available | 789system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available 790system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available 791system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available 792system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available 793system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available 794system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available 795system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available 796system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available 797system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available 798system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available 799system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available 800system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available 801system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available 802system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available 803system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available 804system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available 805system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available 806system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available 807system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available 808system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available 809system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available 810system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available 811system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available 812system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available 813system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available 814system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available 815system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available 816system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available 817system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available 818system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available 819system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available |
| 819system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 820system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 821system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 820system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 821system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 822system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 822system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued 823system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued 824system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued 825system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued 826system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued 827system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued 828system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued 829system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued 830system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued 831system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued 832system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued 833system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued 834system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued 835system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued 836system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued 837system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued 838system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued 839system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued 840system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued 841system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued 842system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued 843system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued 844system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued 845system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued 846system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued 847system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued 848system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued 849system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued 850system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued 851system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued 852system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued | 823system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued 824system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued 825system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued 826system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued 827system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued 828system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued 829system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued 830system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued 831system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued 832system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued 833system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued 834system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued 835system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued 836system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued 837system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued 838system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued 839system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued 840system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued 841system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued 842system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued 843system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued 844system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued 845system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued 846system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued 847system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued 848system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued 849system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued 850system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued 851system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued 852system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued 853system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued |
| 853system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 854system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 854system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 855system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 855system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued 856system.cpu1.iq.rate 1.404111 # Inst issue rate 857system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested 858system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) 859system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads 860system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes 861system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses | 856system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued 857system.cpu1.iq.rate 1.564203 # Inst issue rate 858system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested 859system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) 860system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads 861system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes 862system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses |
| 862system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 863system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 864system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 863system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 864system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 865system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 865system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses | 866system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses |
| 866system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 867system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 867system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores | 868system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores |
| 868system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 869system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 869system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed | 870system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed |
| 870system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 871system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations | 871system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 872system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations |
| 872system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed | 873system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed |
| 873system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 874system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 875system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 876system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 877system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 874system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 875system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 876system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 877system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 878system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 878system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing 879system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking 880system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking 881system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ 882system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch 883system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions 884system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions 885system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions 886system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall | 879system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing 880system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking 881system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking 882system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ 883system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch 884system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions 885system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions 886system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions 887system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall |
| 887system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 888system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations | 888system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 889system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations |
| 889system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly 890system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly 891system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 892system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions 893system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed 894system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute | 890system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly 891system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly 892system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute 893system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions 894system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed 895system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute |
| 895system.cpu1.iew.exec_swp 0 # number of swp insts executed | 896system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 896system.cpu1.iew.exec_nop 40453 # number of nop insts executed 897system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed 898system.cpu1.iew.exec_branches 49718 # Number of branches executed 899system.cpu1.iew.exec_stores 39064 # Number of stores executed 900system.cpu1.iew.exec_rate 1.397453 # Inst execution rate 901system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit 902system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back 903system.cpu1.iew.wb_producers 138076 # num instructions producing a value 904system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value | 897system.cpu1.iew.exec_nop 45600 # number of nop insts executed 898system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed 899system.cpu1.iew.exec_branches 54914 # Number of branches executed 900system.cpu1.iew.exec_stores 45718 # Number of stores executed 901system.cpu1.iew.exec_rate 1.557349 # Inst execution rate 902system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit 903system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back 904system.cpu1.iew.wb_producers 156621 # num instructions producing a value 905system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value |
| 905system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 906system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 906system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle 907system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back | 907system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle 908system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back |
| 908system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 909system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 909system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit 910system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards 911system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted 912system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle 913system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle 914system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle | 910system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit 911system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards 912system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted 913system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle 914system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle 915system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle |
| 915system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 916system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 916system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle 917system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle 918system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle 919system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle 920system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle 921system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle 922system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle 923system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle 924system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle | 917system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle 918system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle 919system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle 920system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle 921system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle 922system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle 923system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle 924system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle 925system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle |
| 925system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 926system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 927system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 926system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 927system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 928system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 928system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle 929system.cpu1.commit.committedInsts 276703 # Number of instructions committed 930system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed | 929system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle 930system.cpu1.commit.committedInsts 310743 # Number of instructions committed 931system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed |
| 931system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 932system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 932system.cpu1.commit.refs 119194 # Number of memory references committed 933system.cpu1.commit.loads 80803 # Number of loads committed 934system.cpu1.commit.membars 4532 # Number of memory barriers committed 935system.cpu1.commit.branches 48886 # Number of branches committed | 933system.cpu1.commit.refs 137689 # Number of memory references committed 934system.cpu1.commit.loads 92644 # Number of loads committed 935system.cpu1.commit.membars 3055 # Number of memory barriers committed 936system.cpu1.commit.branches 54067 # Number of branches committed |
| 936system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 937system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
| 937system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. | 938system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. |
| 938system.cpu1.commit.function_calls 322 # Number of function calls committed. | 939system.cpu1.commit.function_calls 322 # Number of function calls committed. |
| 939system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached | 940system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached |
| 940system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 941system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 941system.cpu1.rob.rob_reads 448873 # The number of ROB reads 942system.cpu1.rob.rob_writes 580482 # The number of ROB writes 943system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself 944system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling 945system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 946system.cpu1.committedInsts 232494 # Number of Instructions Simulated 947system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated 948system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated 949system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction 950system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads 951system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle 952system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads 953system.cpu1.int_regfile_reads 422524 # number of integer regfile reads 954system.cpu1.int_regfile_writes 197153 # number of integer regfile writes | 942system.cpu1.rob.rob_reads 483263 # The number of ROB reads 943system.cpu1.rob.rob_writes 648465 # The number of ROB writes 944system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself 945system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling 946system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 947system.cpu1.committedInsts 262828 # Number of Instructions Simulated 948system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated 949system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated 950system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction 951system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads 952system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle 953system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads 954system.cpu1.int_regfile_reads 478110 # number of integer regfile reads 955system.cpu1.int_regfile_writes 222397 # number of integer regfile writes |
| 955system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 956system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
| 956system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads | 957system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads |
| 957system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 958system.cpu1.icache.replacements 317 # number of replacements | 958system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 959system.cpu1.icache.replacements 317 # number of replacements |
| 959system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use 960system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. | 960system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use 961system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. |
| 961system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. | 962system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. |
| 962system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. | 963system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. |
| 963system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 964system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 964system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor 965system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy 966system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy 967system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits 968system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits 969system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits 970system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits 971system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits 972system.cpu1.icache.overall_hits::total 18178 # number of overall hits | 965system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor 966system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy 967system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy 968system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits 969system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits 970system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits 971system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits 972system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits 973system.cpu1.icache.overall_hits::total 15102 # number of overall hits |
| 973system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses 974system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses 975system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses 976system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses 977system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses 978system.cpu1.icache.overall_misses::total 482 # number of overall misses | 974system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses 975system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses 976system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses 977system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses 978system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses 979system.cpu1.icache.overall_misses::total 482 # number of overall misses |
| 979system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles 980system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles 981system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles 982system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles 983system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles 984system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles 985system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) 986system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) 987system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses 988system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses 989system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses 990system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses 991system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses 992system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses 993system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses 994system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses 995system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses 996system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses 997system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency 998system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency 999system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency 1000system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency 1001system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency 1002system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency | 980system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles 981system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles 982system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles 983system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles 984system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles 985system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles 986system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) 987system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) 988system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses 989system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses 990system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses 991system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses 992system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses 993system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses 994system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses 995system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses 996system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses 997system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses 998system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency 999system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency 1000system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency 1001system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency 1002system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency 1003system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency |
| 1003system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked 1004system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1005system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1006system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1007system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked 1008system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1009system.cpu1.icache.fast_writes 0 # number of fast writes performed 1010system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1015system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits 1016system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits 1017system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1018system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1019system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1020system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1021system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1022system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses | 1004system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked 1005system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1007system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked 1009system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1010system.cpu1.icache.fast_writes 0 # number of fast writes performed 1011system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1016system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits 1017system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits 1018system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1019system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1020system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1021system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1022system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1023system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses |
| 1023system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles 1024system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles 1025system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles 1026system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles 1027system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles 1028system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles 1029system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses 1030system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses 1031system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses 1032system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses 1033system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses 1034system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses 1035system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency 1036system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency 1037system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency 1038system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency 1039system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency 1040system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency | 1024system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8302000 # number of ReadReq MSHR miss cycles 1025system.cpu1.icache.ReadReq_mshr_miss_latency::total 8302000 # number of ReadReq MSHR miss cycles 1026system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8302000 # number of demand (read+write) MSHR miss cycles 1027system.cpu1.icache.demand_mshr_miss_latency::total 8302000 # number of demand (read+write) MSHR miss cycles 1028system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8302000 # number of overall MSHR miss cycles 1029system.cpu1.icache.overall_mshr_miss_latency::total 8302000 # number of overall MSHR miss cycles 1030system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for ReadReq accesses 1031system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027272 # mshr miss rate for ReadReq accesses 1032system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for demand accesses 1033system.cpu1.icache.demand_mshr_miss_rate::total 0.027272 # mshr miss rate for demand accesses 1034system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for overall accesses 1035system.cpu1.icache.overall_mshr_miss_rate::total 0.027272 # mshr miss rate for overall accesses 1036system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average ReadReq mshr miss latency 1037system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647 # average ReadReq mshr miss latency 1038system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency 1039system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency 1040system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency 1041system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency |
| 1041system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1042system.cpu1.dcache.replacements 0 # number of replacements | 1042system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1043system.cpu1.dcache.replacements 0 # number of replacements |
| 1043system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use 1044system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks. | 1044system.cpu1.dcache.tagsinuse 27.071497 # Cycle average of tags in use 1045system.cpu1.dcache.total_refs 51063 # Total number of references to valid blocks. |
| 1045system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. | 1046system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. |
| 1046system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. | 1047system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. |
| 1047system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1048system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1048system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor 1049system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy 1050system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy 1051system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits 1052system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits 1053system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits 1054system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits 1055system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1056system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1057system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits 1058system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits 1059system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits 1060system.cpu1.dcache.overall_hits::total 85442 # number of overall hits 1061system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses 1062system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses 1063system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses 1064system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses 1065system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses 1066system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses 1067system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses 1068system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses 1069system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses 1070system.cpu1.dcache.overall_misses::total 544 # number of overall misses 1071system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles 1072system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles 1073system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles 1074system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles 1075system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles 1076system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles 1077system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles 1078system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles 1079system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles 1080system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles 1081system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses) 1082system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses) 1083system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses) 1084system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses) 1085system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) 1086system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 1087system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses 1088system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses 1089system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses 1090system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses 1091system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses 1092system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses 1093system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses 1094system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses 1095system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses 1096system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses 1097system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses 1098system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses 1099system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses 1100system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses 1101system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency 1102system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency 1103system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # average WriteReq miss latency 1104system.cpu1.dcache.WriteReq_avg_miss_latency::total 19277.372263 # average WriteReq miss latency 1105system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency 1106system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency 1107system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency 1108system.cpu1.dcache.demand_avg_miss_latency::total 16177.389706 # average overall miss latency 1109system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency 1110system.cpu1.dcache.overall_avg_miss_latency::total 16177.389706 # average overall miss latency | 1049system.cpu1.dcache.occ_blocks::cpu1.data 27.071497 # Average occupied blocks per requestor 1050system.cpu1.dcache.occ_percent::cpu1.data 0.052874 # Average percentage of cache occupancy 1051system.cpu1.dcache.occ_percent::total 0.052874 # Average percentage of cache occupancy 1052system.cpu1.dcache.ReadReq_hits::cpu1.data 52421 # number of ReadReq hits 1053system.cpu1.dcache.ReadReq_hits::total 52421 # number of ReadReq hits 1054system.cpu1.dcache.WriteReq_hits::cpu1.data 44839 # number of WriteReq hits 1055system.cpu1.dcache.WriteReq_hits::total 44839 # number of WriteReq hits 1056system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits 1057system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits 1058system.cpu1.dcache.demand_hits::cpu1.data 97260 # number of demand (read+write) hits 1059system.cpu1.dcache.demand_hits::total 97260 # number of demand (read+write) hits 1060system.cpu1.dcache.overall_hits::cpu1.data 97260 # number of overall hits 1061system.cpu1.dcache.overall_hits::total 97260 # number of overall hits 1062system.cpu1.dcache.ReadReq_misses::cpu1.data 438 # number of ReadReq misses 1063system.cpu1.dcache.ReadReq_misses::total 438 # number of ReadReq misses 1064system.cpu1.dcache.WriteReq_misses::cpu1.data 141 # number of WriteReq misses 1065system.cpu1.dcache.WriteReq_misses::total 141 # number of WriteReq misses 1066system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses 1067system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses 1068system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses 1069system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses 1070system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses 1071system.cpu1.dcache.overall_misses::total 579 # number of overall misses 1072system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8533500 # number of ReadReq miss cycles 1073system.cpu1.dcache.ReadReq_miss_latency::total 8533500 # number of ReadReq miss cycles 1074system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3160000 # number of WriteReq miss cycles 1075system.cpu1.dcache.WriteReq_miss_latency::total 3160000 # number of WriteReq miss cycles 1076system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 510000 # number of SwapReq miss cycles 1077system.cpu1.dcache.SwapReq_miss_latency::total 510000 # number of SwapReq miss cycles 1078system.cpu1.dcache.demand_miss_latency::cpu1.data 11693500 # number of demand (read+write) miss cycles 1079system.cpu1.dcache.demand_miss_latency::total 11693500 # number of demand (read+write) miss cycles 1080system.cpu1.dcache.overall_miss_latency::cpu1.data 11693500 # number of overall miss cycles 1081system.cpu1.dcache.overall_miss_latency::total 11693500 # number of overall miss cycles 1082system.cpu1.dcache.ReadReq_accesses::cpu1.data 52859 # number of ReadReq accesses(hits+misses) 1083system.cpu1.dcache.ReadReq_accesses::total 52859 # number of ReadReq accesses(hits+misses) 1084system.cpu1.dcache.WriteReq_accesses::cpu1.data 44980 # number of WriteReq accesses(hits+misses) 1085system.cpu1.dcache.WriteReq_accesses::total 44980 # number of WriteReq accesses(hits+misses) 1086system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) 1087system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) 1088system.cpu1.dcache.demand_accesses::cpu1.data 97839 # number of demand (read+write) accesses 1089system.cpu1.dcache.demand_accesses::total 97839 # number of demand (read+write) accesses 1090system.cpu1.dcache.overall_accesses::cpu1.data 97839 # number of overall (read+write) accesses 1091system.cpu1.dcache.overall_accesses::total 97839 # number of overall (read+write) accesses 1092system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008286 # miss rate for ReadReq accesses 1093system.cpu1.dcache.ReadReq_miss_rate::total 0.008286 # miss rate for ReadReq accesses 1094system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003135 # miss rate for WriteReq accesses 1095system.cpu1.dcache.WriteReq_miss_rate::total 0.003135 # miss rate for WriteReq accesses 1096system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.830769 # miss rate for SwapReq accesses 1097system.cpu1.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses 1098system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005918 # miss rate for demand accesses 1099system.cpu1.dcache.demand_miss_rate::total 0.005918 # miss rate for demand accesses 1100system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005918 # miss rate for overall accesses 1101system.cpu1.dcache.overall_miss_rate::total 0.005918 # miss rate for overall accesses 1102system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712 # average ReadReq miss latency 1103system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency 1104system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency 1105system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency 1106system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency 1107system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency 1108system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency 1109system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency 1110system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency 1111system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency |
| 1111system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1112system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1113system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1114system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1115system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1116system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1117system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1118system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1112system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1113system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1114system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1115system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1116system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1117system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1118system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1119system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1119system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits 1120system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits 1121system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1122system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1123system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits 1124system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits 1125system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits 1126system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits 1127system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses 1128system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses 1129system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 1130system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1131system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses 1132system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 1133system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses 1134system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 1135system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses 1136system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses 1137system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles 1138system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles 1139system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles 1140system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles 1141system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles 1142system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles 1143system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles 1144system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles 1145system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles 1146system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles 1147system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses 1148system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses 1149system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses 1150system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses 1151system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses 1152system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses 1153system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses 1154system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses 1155system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses 1156system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses 1157system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency 1158system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency 1159system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency 1160system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency 1161system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency 1162system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency 1163system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency 1164system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency 1165system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency 1166system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency | 1120system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits 1121system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits 1122system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 1123system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 1124system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits 1125system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits 1126system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits 1127system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits 1128system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses 1129system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 1130system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1131system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1132system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses 1133system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 1134system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses 1135system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 1136system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses 1137system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses 1138system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles 1139system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles 1140system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles 1141system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles 1142system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles 1143system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles 1144system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles 1145system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles 1146system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles 1147system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles 1148system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses 1149system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses 1150system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses 1151system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses 1152system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses 1153system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses 1154system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses 1155system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses 1156system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses 1157system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses 1158system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency 1159system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency 1160system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency 1161system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency 1162system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency 1163system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency 1164system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency 1165system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency 1166system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency 1167system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency |
| 1167system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1168system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1168system.cpu2.branchPred.lookups 43658 # Number of BP lookups 1169system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted 1170system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect 1171system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups 1172system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits | 1169system.cpu2.branchPred.lookups 45099 # Number of BP lookups 1170system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted 1171system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect 1172system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups 1173system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits |
| 1173system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1174system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1174system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage 1175system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. | 1175system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage 1176system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. |
| 1176system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1177system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1177system.cpu2.numCycles 173761 # number of cpu cycles simulated | 1178system.cpu2.numCycles 174459 # number of cpu cycles simulated |
| 1178system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1179system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1179system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1180system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1180system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss 1181system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed 1182system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered 1183system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken 1184system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked 1185system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing 1186system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked 1187system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1188system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from 1189system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps 1190system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched 1191system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed 1192system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) 1193system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) 1194system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) | 1181system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss 1182system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed 1183system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered 1184system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken 1185system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked 1186system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing 1187system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked 1188system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1189system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from 1190system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps 1191system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched 1192system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed 1193system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) 1194system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) 1195system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) |
| 1195system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1196system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1196system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) 1197system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) 1198system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) 1199system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) 1200system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) 1201system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) 1202system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) 1203system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) 1204system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) | 1197system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) 1198system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) 1199system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) 1200system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) 1201system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) 1202system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) 1203system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) 1204system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) 1205system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) |
| 1205system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1206system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1207system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1206system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1207system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1208system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1208system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) 1209system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle 1210system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle 1211system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle 1212system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked 1213system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running 1214system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking 1215system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing 1216system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode 1217system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing 1218system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle 1219system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking 1220system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst 1221system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running 1222system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking 1223system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename 1224system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1225system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full 1226system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed 1227system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made 1228system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups 1229system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed 1230system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing 1231system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed 1232system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed 1233system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer 1234system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. 1235system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. 1236system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. 1237system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. 1238system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) 1239system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ 1240system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued 1241system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued 1242system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling 1243system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph 1244system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed 1245system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle 1246system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle 1247system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle | 1209system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) 1210system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle 1211system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle 1212system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle 1213system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked 1214system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running 1215system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking 1216system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing 1217system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode 1218system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing 1219system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle 1220system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking 1221system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst 1222system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running 1223system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking 1224system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename 1225system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 1226system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full 1227system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed 1228system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made 1229system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups 1230system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed 1231system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing 1232system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed 1233system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed 1234system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer 1235system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. 1236system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. 1237system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. 1238system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. 1239system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) 1240system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ 1241system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued 1242system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued 1243system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling 1244system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph 1245system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed 1246system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle 1247system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle 1248system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle |
| 1248system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1249system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1249system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle 1250system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle 1251system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle 1252system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle 1253system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle 1254system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle 1255system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle | 1250system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle 1251system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle 1252system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle 1253system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle 1254system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle 1255system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle 1256system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle |
| 1256system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle | 1257system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle |
| 1257system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle | 1258system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle |
| 1258system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1259system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1260system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1259system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1260system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1261system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1261system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle | 1262system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle |
| 1262system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1263system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1263system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available 1264system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available 1265system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available 1266system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1267system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1268system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1269system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available 1270system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1271system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1272system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available 1273system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available 1274system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available 1275system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available 1276system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available 1277system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available 1278system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available 1279system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1280system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available 1281system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available 1282system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available 1283system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1284system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available 1285system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1286system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1287system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1288system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available 1289system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available 1290system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1291system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1292system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available 1293system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available | 1264system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available 1265system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available 1266system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available 1267system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available 1268system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available 1269system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available 1270system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available 1271system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available 1272system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available 1273system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available 1274system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available 1275system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available 1276system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available 1277system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available 1278system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available 1279system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available 1280system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available 1281system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available 1282system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available 1283system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available 1284system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available 1285system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available 1286system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available 1287system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available 1288system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available 1289system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available 1290system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available 1291system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available 1292system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available 1293system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available 1294system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available |
| 1294system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1295system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1296system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1295system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1296system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1297system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1297system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued 1298system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued 1299system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued 1300system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued 1301system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued 1302system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued 1303system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued 1304system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued 1305system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued 1306system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued 1307system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued 1308system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued 1309system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued 1310system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued 1311system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued 1312system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued 1313system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued 1314system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued 1315system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued 1316system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued 1317system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued 1318system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued 1319system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued 1320system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued 1321system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued 1322system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued 1323system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued 1324system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued 1325system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued 1326system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued 1327system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued | 1298system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued 1299system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued 1300system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued 1301system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued 1302system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued 1303system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued 1304system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued 1305system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued 1306system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued 1307system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued 1308system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued 1309system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued 1310system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued 1311system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued 1312system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued 1313system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued 1314system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued 1315system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued 1316system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued 1317system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued 1318system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued 1319system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued 1320system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued 1321system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued 1322system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued 1323system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued 1324system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued 1325system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued 1326system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued 1327system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued 1328system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued |
| 1328system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1329system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1329system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1330system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1330system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued 1331system.cpu2.iq.rate 1.099165 # Inst issue rate 1332system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested 1333system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) 1334system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads 1335system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes 1336system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses | 1331system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued 1332system.cpu2.iq.rate 1.143380 # Inst issue rate 1333system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested 1334system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) 1335system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads 1336system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes 1337system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses |
| 1337system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1338system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1339system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1338system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1339system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1340system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1340system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses | 1341system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses |
| 1341system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1342system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1342system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores | 1343system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores |
| 1343system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1344system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1344system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed | 1345system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed |
| 1345system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1346system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 1346system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 1347system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed | 1347system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1348system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed |
| 1348system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1349system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1350system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1351system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1352system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1349system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1350system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1351system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1352system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1353system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1353system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing 1354system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking 1355system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking 1356system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ 1357system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch 1358system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions 1359system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions 1360system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions 1361system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall | 1354system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing 1355system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking 1356system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking 1357system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ 1358system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch 1359system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions 1360system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions 1361system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions 1362system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall |
| 1362system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1363system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 1363system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations 1364system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1365system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly 1366system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute 1367system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions 1368system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed 1369system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute | 1364system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations 1365system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 1366system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly 1367system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute 1368system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions 1369system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed 1370system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute |
| 1370system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1371system.cpu2.iew.exec_swp 0 # number of swp insts executed |
| 1371system.cpu2.iew.exec_nop 31084 # number of nop insts executed 1372system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed 1373system.cpu2.iew.exec_branches 40244 # Number of branches executed 1374system.cpu2.iew.exec_stores 26584 # Number of stores executed 1375system.cpu2.iew.exec_rate 1.092414 # Inst execution rate 1376system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit 1377system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back 1378system.cpu2.iew.wb_producers 103581 # num instructions producing a value 1379system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value | 1372system.cpu2.iew.exec_nop 32635 # number of nop insts executed 1373system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed 1374system.cpu2.iew.exec_branches 41831 # Number of branches executed 1375system.cpu2.iew.exec_stores 28461 # Number of stores executed 1376system.cpu2.iew.exec_rate 1.136726 # Inst execution rate 1377system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit 1378system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back 1379system.cpu2.iew.wb_producers 108943 # num instructions producing a value 1380system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value |
| 1380system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1381system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1381system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle 1382system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back | 1382system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle 1383system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back |
| 1383system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1384system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1384system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit 1385system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards 1386system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted 1387system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle 1388system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle 1389system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle | 1385system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit 1386system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards 1387system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted 1388system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle 1389system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle 1390system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle |
| 1390system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1391system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1391system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle 1392system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle 1393system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle 1394system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle 1395system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle 1396system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle 1397system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle 1398system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle 1399system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle | 1392system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle 1393system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle 1394system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle 1395system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle 1396system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle 1397system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle 1398system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle 1399system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle 1400system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle |
| 1400system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1401system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1402system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1401system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1402system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1403system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1403system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle 1404system.cpu2.commit.committedInsts 213870 # Number of instructions committed 1405system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed | 1404system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle 1405system.cpu2.commit.committedInsts 223981 # Number of instructions committed 1406system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed |
| 1406system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 1407system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
| 1407system.cpu2.commit.refs 84718 # Number of memory references committed 1408system.cpu2.commit.loads 58829 # Number of loads committed 1409system.cpu2.commit.membars 7592 # Number of memory barriers committed 1410system.cpu2.commit.branches 39438 # Number of branches committed | 1408system.cpu2.commit.refs 90122 # Number of memory references committed 1409system.cpu2.commit.loads 62324 # Number of loads committed 1410system.cpu2.commit.membars 7244 # Number of memory barriers committed 1411system.cpu2.commit.branches 41003 # Number of branches committed |
| 1411system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 1412system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1412system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. | 1413system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. |
| 1413system.cpu2.commit.function_calls 322 # Number of function calls committed. | 1414system.cpu2.commit.function_calls 322 # Number of function calls committed. |
| 1414system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached | 1415system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached |
| 1415system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits | 1416system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1416system.cpu2.rob.rob_reads 388660 # The number of ROB reads 1417system.cpu2.rob.rob_writes 455572 # The number of ROB writes 1418system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 1419system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling 1420system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1421system.cpu2.committedInsts 176057 # Number of Instructions Simulated 1422system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated 1423system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated 1424system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction 1425system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads 1426system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle 1427system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads 1428system.cpu2.int_regfile_reads 319023 # number of integer regfile reads 1429system.cpu2.int_regfile_writes 150022 # number of integer regfile writes | 1417system.cpu2.rob.rob_reads 398976 # The number of ROB reads 1418system.cpu2.rob.rob_writes 475157 # The number of ROB writes 1419system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 1420system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling 1421system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1422system.cpu2.committedInsts 184944 # Number of Instructions Simulated 1423system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated 1424system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated 1425system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction 1426system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads 1427system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle 1428system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads 1429system.cpu2.int_regfile_reads 335090 # number of integer regfile reads 1430system.cpu2.int_regfile_writes 157371 # number of integer regfile writes |
| 1430system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 1431system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
| 1431system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads | 1432system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads |
| 1432system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1433system.cpu2.icache.replacements 319 # number of replacements | 1433system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1434system.cpu2.icache.replacements 319 # number of replacements |
| 1434system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use 1435system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. 1436system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. 1437system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. | 1435system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use 1436system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. 1437system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. 1438system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. |
| 1438system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1439system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1439system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor 1440system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy 1441system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy 1442system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits 1443system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits 1444system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits 1445system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits 1446system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits 1447system.cpu2.icache.overall_hits::total 24566 # number of overall hits 1448system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses 1449system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses 1450system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses 1451system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses 1452system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses 1453system.cpu2.icache.overall_misses::total 475 # number of overall misses 1454system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles 1455system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles 1456system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles 1457system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles 1458system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles 1459system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles 1460system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) 1461system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) 1462system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses 1463system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses 1464system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses 1465system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses 1466system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses 1467system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses 1468system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses 1469system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses 1470system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses 1471system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses 1472system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency 1473system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency 1474system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency 1475system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency 1476system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency 1477system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency | 1440system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor 1441system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy 1442system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy 1443system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits 1444system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits 1445system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits 1446system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits 1447system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits 1448system.cpu2.icache.overall_hits::total 23791 # number of overall hits 1449system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses 1450system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses 1451system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses 1452system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses 1453system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses 1454system.cpu2.icache.overall_misses::total 478 # number of overall misses 1455system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles 1456system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles 1457system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles 1458system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles 1459system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles 1460system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles 1461system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) 1462system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) 1463system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses 1464system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses 1465system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses 1466system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses 1467system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses 1468system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses 1469system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses 1470system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses 1471system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses 1472system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses 1473system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency 1474system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency 1475system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency 1476system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency 1477system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency 1478system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency |
| 1478system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1479system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1480system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1481system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1482system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1483system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1484system.cpu2.icache.fast_writes 0 # number of fast writes performed 1485system.cpu2.icache.cache_copies 0 # number of cache copies performed | 1479system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1480system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1481system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1482system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1483system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1484system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1485system.cpu2.icache.fast_writes 0 # number of fast writes performed 1486system.cpu2.icache.cache_copies 0 # number of cache copies performed |
| 1486system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits 1487system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1488system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits 1489system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1490system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits 1491system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1492system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses 1493system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 1494system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses 1495system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 1496system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses 1497system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 1498system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles 1499system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles 1500system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles 1501system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles 1502system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles 1503system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles 1504system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses 1505system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses 1506system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses 1507system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses 1508system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses 1509system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses 1510system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency 1511system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency 1512system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency 1513system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency 1514system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency 1515system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency | 1487system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits 1488system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1489system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits 1490system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1491system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits 1492system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1493system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses 1494system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 1495system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses 1496system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 1497system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses 1498system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 1499system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles 1500system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles 1501system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles 1502system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles 1503system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles 1504system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles 1505system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses 1506system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses 1507system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses 1508system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses 1509system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses 1510system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses 1511system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency 1512system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency 1513system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency 1514system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency 1515system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency 1516system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency |
| 1516system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1517system.cpu2.dcache.replacements 0 # number of replacements | 1517system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1518system.cpu2.dcache.replacements 0 # number of replacements |
| 1518system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use 1519system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. | 1519system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use 1520system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. |
| 1520system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. | 1521system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. |
| 1521system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. | 1522system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. |
| 1522system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1523system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1523system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor 1524system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy 1525system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy 1526system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits 1527system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits 1528system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits 1529system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits 1530system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits 1531system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1532system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits 1533system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits 1534system.cpu2.dcache.overall_hits::cpu2.data 63469 # number of overall hits 1535system.cpu2.dcache.overall_hits::total 63469 # number of overall hits 1536system.cpu2.dcache.ReadReq_misses::cpu2.data 397 # number of ReadReq misses 1537system.cpu2.dcache.ReadReq_misses::total 397 # number of ReadReq misses 1538system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses 1539system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses 1540system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses 1541system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses 1542system.cpu2.dcache.demand_misses::cpu2.data 530 # number of demand (read+write) misses 1543system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses 1544system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses 1545system.cpu2.dcache.overall_misses::total 530 # number of overall misses 1546system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles 1547system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles 1548system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles 1549system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles 1550system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles 1551system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles 1552system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles 1553system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles 1554system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles 1555system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles 1556system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) 1557system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) 1558system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) 1559system.cpu2.dcache.WriteReq_accesses::total 25814 # number of WriteReq accesses(hits+misses) 1560system.cpu2.dcache.SwapReq_accesses::cpu2.data 75 # number of SwapReq accesses(hits+misses) 1561system.cpu2.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) 1562system.cpu2.dcache.demand_accesses::cpu2.data 63999 # number of demand (read+write) accesses 1563system.cpu2.dcache.demand_accesses::total 63999 # number of demand (read+write) accesses 1564system.cpu2.dcache.overall_accesses::cpu2.data 63999 # number of overall (read+write) accesses 1565system.cpu2.dcache.overall_accesses::total 63999 # number of overall (read+write) accesses 1566system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010397 # miss rate for ReadReq accesses 1567system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses 1568system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses 1569system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses 1570system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses 1571system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses 1572system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses 1573system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses 1574system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses 1575system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses 1576system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency 1577system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency 1578system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency 1579system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency 1580system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency 1581system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency 1582system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency 1583system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency 1584system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency 1585system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency | 1524system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor 1525system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy 1526system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy 1527system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits 1528system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits 1529system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits 1530system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits 1531system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits 1532system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 1533system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits 1534system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits 1535system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits 1536system.cpu2.dcache.overall_hits::total 66937 # number of overall hits 1537system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses 1538system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses 1539system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses 1540system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses 1541system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses 1542system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses 1543system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses 1544system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses 1545system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses 1546system.cpu2.dcache.overall_misses::total 540 # number of overall misses 1547system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles 1548system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles 1549system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles 1550system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles 1551system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles 1552system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles 1553system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles 1554system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles 1555system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles 1556system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles 1557system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) 1558system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) 1559system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) 1560system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) 1561system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 1562system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 1563system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses 1564system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses 1565system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses 1566system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses 1567system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses 1568system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses 1569system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses 1570system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses 1571system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses 1572system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses 1573system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses 1574system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses 1575system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses 1576system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses 1577system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency 1578system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency 1579system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency 1580system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency 1581system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency 1582system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency 1583system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency 1584system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency 1585system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency 1586system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency |
| 1586system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1587system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1588system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1589system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1590system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1591system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1592system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1593system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 1587system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1588system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1589system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1590system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1591system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1592system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1593system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1594system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 1594system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits 1595system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits 1596system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits 1597system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1598system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits 1599system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits 1600system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits 1601system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits 1602system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses 1603system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 1604system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses 1605system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses 1606system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses 1607system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 1608system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 1609system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 1610system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 1611system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 1612system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles 1613system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles 1614system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles 1615system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles 1616system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles 1617system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles 1618system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles 1619system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles 1620system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles 1621system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles 1622system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses 1623system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses 1624system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses 1625system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses 1626system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses 1627system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses 1628system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses 1629system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses 1630system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses 1631system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses 1632system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency 1633system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency 1634system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency 1635system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency 1636system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency 1637system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency 1638system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency 1639system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency 1640system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency 1641system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency | 1595system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits 1596system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits 1597system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 1598system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 1599system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits 1600system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits 1601system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits 1602system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits 1603system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses 1604system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1605system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 1606system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1607system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses 1608system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 1609system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses 1610system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses 1611system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses 1612system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses 1613system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles 1614system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles 1615system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles 1616system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles 1617system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles 1618system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles 1619system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles 1620system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles 1621system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles 1622system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles 1623system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses 1624system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses 1625system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses 1626system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses 1627system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses 1628system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses 1629system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses 1630system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses 1631system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses 1632system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses 1633system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency 1634system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency 1635system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency 1636system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency 1637system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency 1638system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency 1639system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency 1640system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency 1641system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency 1642system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency |
| 1642system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1643system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1643system.cpu3.branchPred.lookups 53689 # Number of BP lookups 1644system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted 1645system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect 1646system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups 1647system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits | 1644system.cpu3.branchPred.lookups 47073 # Number of BP lookups 1645system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted 1646system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect 1647system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups 1648system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits |
| 1648system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1649system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1649system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage 1650system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target. | 1650system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage 1651system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. |
| 1651system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. | 1652system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. |
| 1652system.cpu3.numCycles 173451 # number of cpu cycles simulated | 1653system.cpu3.numCycles 174149 # number of cpu cycles simulated |
| 1653system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1654system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 1654system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1655system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1655system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss 1656system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed 1657system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered 1658system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken 1659system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked 1660system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing 1661system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked | 1656system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss 1657system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed 1658system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered 1659system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken 1660system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked 1661system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing 1662system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked |
| 1662system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 1663system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1663system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from 1664system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps 1665system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched 1666system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 1667system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) 1668system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) 1669system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) | 1664system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from 1665system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps 1666system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched 1667system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed 1668system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) 1669system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) 1670system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) |
| 1670system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1671system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1671system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) 1672system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) 1673system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) 1674system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) 1675system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) 1676system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) 1677system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) 1678system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) 1679system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) | 1672system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) 1673system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) 1674system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) 1675system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) 1676system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) 1677system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) 1678system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) 1679system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) 1680system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) |
| 1680system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1681system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1682system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1681system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1682system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1683system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1683system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) 1684system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle 1685system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle 1686system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle 1687system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked 1688system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running 1689system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking 1690system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing 1691system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode 1692system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing 1693system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle 1694system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking 1695system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst 1696system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running 1697system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking 1698system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename 1699system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 1700system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full 1701system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed 1702system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made 1703system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups 1704system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed 1705system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing 1706system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed 1707system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed 1708system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer 1709system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. 1710system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. 1711system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. 1712system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. 1713system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) 1714system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ 1715system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued 1716system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued 1717system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling 1718system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph 1719system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed 1720system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle 1721system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle 1722system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle | 1684system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) 1685system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle 1686system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle 1687system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle 1688system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked 1689system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running 1690system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking 1691system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing 1692system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode 1693system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing 1694system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle 1695system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking 1696system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst 1697system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running 1698system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking 1699system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename 1700system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1701system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full 1702system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed 1703system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made 1704system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups 1705system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed 1706system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing 1707system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed 1708system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed 1709system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer 1710system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. 1711system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. 1712system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. 1713system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. 1714system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) 1715system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ 1716system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued 1717system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued 1718system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling 1719system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph 1720system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed 1721system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle 1722system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle 1723system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle |
| 1723system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1724system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1724system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle 1725system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle 1726system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle 1727system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle 1728system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle 1729system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle 1730system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle 1731system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle | 1725system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle 1726system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle 1727system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle 1728system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle 1729system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle 1730system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle 1731system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle 1732system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle |
| 1732system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle 1733system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1734system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1735system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1733system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle 1734system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1735system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1736system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1736system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle | 1737system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle |
| 1737system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1738system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1738system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available 1739system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available 1740system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available 1741system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1742system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1743system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1744system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available 1745system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1746system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1747system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available 1748system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available 1749system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available 1750system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available 1751system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available 1752system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available 1753system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available 1754system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1755system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available 1756system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available 1757system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available 1758system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1759system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available 1760system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1761system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1762system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1763system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available 1764system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available 1765system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1766system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1767system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available 1768system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available | 1739system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available 1740system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available 1741system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available 1742system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available 1743system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available 1744system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available 1745system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available 1746system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available 1747system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 1748system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available 1749system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available 1750system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available 1751system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available 1752system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available 1753system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available 1754system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available 1755system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available 1756system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available 1757system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available 1758system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available 1759system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available 1760system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available 1761system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available 1762system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available 1763system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available 1764system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available 1765system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available 1766system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available 1767system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 1768system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available 1769system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available |
| 1769system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1770system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1771system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1770system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1771system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1772system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1772system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued 1773system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued 1774system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued 1775system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued 1776system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued 1777system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued 1778system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued 1779system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued 1780system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued 1781system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued 1782system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued 1783system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued 1784system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued 1785system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued 1786system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued 1787system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued 1788system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued 1789system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued 1790system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued 1791system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued 1792system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued 1793system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued 1794system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued 1795system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued 1796system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued 1797system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued 1798system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued 1799system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued 1800system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued 1801system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued 1802system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued | 1773system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued 1774system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued 1775system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued 1776system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued 1777system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued 1778system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued 1779system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued 1780system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued 1781system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued 1782system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued 1783system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued 1784system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued 1785system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued 1786system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued 1787system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued 1788system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued 1789system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued 1790system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued 1791system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued 1792system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued 1793system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued 1794system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued 1795system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued 1796system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued 1797system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued 1798system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued 1799system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued 1800system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued 1801system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued 1802system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued 1803system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued |
| 1803system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1804system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1804system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1805system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1805system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued 1806system.cpu3.iq.rate 1.425578 # Inst issue rate 1807system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested 1808system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) 1809system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads 1810system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes 1811system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses | 1806system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued 1807system.cpu3.iq.rate 1.206438 # Inst issue rate 1808system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested 1809system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) 1810system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads 1811system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes 1812system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses |
| 1812system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1813system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1814system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1813system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1814system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1815system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1815system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses | 1816system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses |
| 1816system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1817system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1817system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores | 1818system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores |
| 1818system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1819system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1819system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed | 1820system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed |
| 1820system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1821system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 1821system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 1822system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed | 1822system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations 1823system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed |
| 1823system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1824system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1825system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1826system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1827system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1824system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1825system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1826system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1827system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1828system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1828system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing 1829system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking 1830system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking 1831system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ 1832system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch 1833system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions 1834system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions 1835system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions 1836system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall | 1829system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing 1830system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking 1831system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking 1832system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ 1833system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch 1834system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions 1835system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions 1836system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions 1837system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall |
| 1837system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1838system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 1838system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations 1839system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly 1840system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly 1841system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute 1842system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions 1843system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed 1844system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute | 1839system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations 1840system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly 1841system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly 1842system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute 1843system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions 1844system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed 1845system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute |
| 1845system.cpu3.iew.exec_swp 0 # number of swp insts executed | 1846system.cpu3.iew.exec_swp 0 # number of swp insts executed |
| 1846system.cpu3.iew.exec_nop 41144 # number of nop insts executed 1847system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed 1848system.cpu3.iew.exec_branches 50378 # Number of branches executed 1849system.cpu3.iew.exec_stores 39506 # Number of stores executed 1850system.cpu3.iew.exec_rate 1.418798 # Inst execution rate 1851system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit 1852system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back 1853system.cpu3.iew.wb_producers 139611 # num instructions producing a value 1854system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value | 1847system.cpu3.iew.exec_nop 34512 # number of nop insts executed 1848system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed 1849system.cpu3.iew.exec_branches 43690 # Number of branches executed 1850system.cpu3.iew.exec_stores 30979 # Number of stores executed 1851system.cpu3.iew.exec_rate 1.199743 # Inst execution rate 1852system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit 1853system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back 1854system.cpu3.iew.wb_producers 115832 # num instructions producing a value 1855system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value |
| 1855system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1856system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1856system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle 1857system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back | 1857system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle 1858system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back |
| 1858system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1859system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1859system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit 1860system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards 1861system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted 1862system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle 1863system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle 1864system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle | 1860system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit 1861system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards 1862system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted 1863system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle 1864system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle 1865system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle |
| 1865system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1866system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1866system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle 1867system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle 1868system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle 1869system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle 1870system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle 1871system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle 1872system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle 1873system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle | 1867system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle 1868system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle 1869system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle 1870system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle 1871system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle 1872system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle 1873system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle 1874system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle |
| 1874system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle 1875system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1876system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1877system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1875system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle 1876system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1877system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1878system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1878system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle 1879system.cpu3.commit.committedInsts 280126 # Number of instructions committed 1880system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed | 1879system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle 1880system.cpu3.commit.committedInsts 236445 # Number of instructions committed 1881system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed |
| 1881system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 1882system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
| 1882system.cpu3.commit.refs 120655 # Number of memory references committed 1883system.cpu3.commit.loads 81860 # Number of loads committed 1884system.cpu3.commit.membars 4779 # Number of memory barriers committed 1885system.cpu3.commit.branches 49541 # Number of branches committed | 1883system.cpu3.commit.refs 96940 # Number of memory references committed 1884system.cpu3.commit.loads 66666 # Number of loads committed 1885system.cpu3.commit.membars 6656 # Number of memory barriers committed 1886system.cpu3.commit.branches 42889 # Number of branches committed |
| 1886system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 1887system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1887system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. | 1888system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. |
| 1888system.cpu3.commit.function_calls 322 # Number of function calls committed. 1889system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached 1890system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits | 1889system.cpu3.commit.function_calls 322 # Number of function calls committed. 1890system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached 1891system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1891system.cpu3.rob.rob_reads 454770 # The number of ROB reads 1892system.cpu3.rob.rob_writes 587696 # The number of ROB writes 1893system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself 1894system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling 1895system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1896system.cpu3.committedInsts 235015 # Number of Instructions Simulated 1897system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated 1898system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated 1899system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction 1900system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads 1901system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle 1902system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads 1903system.cpu3.int_regfile_reads 427046 # number of integer regfile reads 1904system.cpu3.int_regfile_writes 198986 # number of integer regfile writes | 1892system.cpu3.rob.rob_reads 411444 # The number of ROB reads 1893system.cpu3.rob.rob_writes 500477 # The number of ROB writes 1894system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 1895system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling 1896system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1897system.cpu3.committedInsts 196116 # Number of Instructions Simulated 1898system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated 1899system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated 1900system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction 1901system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads 1902system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle 1903system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads 1904system.cpu3.int_regfile_reads 355696 # number of integer regfile reads 1905system.cpu3.int_regfile_writes 166589 # number of integer regfile writes |
| 1905system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 1906system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
| 1906system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads | 1907system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads |
| 1907system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 1908system.cpu3.icache.replacements 318 # number of replacements | 1908system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 1909system.cpu3.icache.replacements 318 # number of replacements |
| 1909system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use 1910system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. 1911system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. 1912system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. | 1910system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use 1911system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. 1912system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. 1913system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. |
| 1913system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1914system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1914system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor 1915system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy 1916system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy 1917system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits 1918system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits 1919system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits 1920system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits 1921system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits 1922system.cpu3.icache.overall_hits::total 18731 # number of overall hits 1923system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses 1924system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses 1925system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses 1926system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses 1927system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses 1928system.cpu3.icache.overall_misses::total 474 # number of overall misses 1929system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles 1930system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles 1931system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles 1932system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles 1933system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles 1934system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles 1935system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) 1936system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) 1937system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses 1938system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses 1939system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses 1940system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses 1941system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses 1942system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses 1943system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses 1944system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses 1945system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses 1946system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses 1947system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency 1948system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency 1949system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency 1950system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency 1951system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency 1952system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency | 1915system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor 1916system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy 1917system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy 1918system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits 1919system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits 1920system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits 1921system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits 1922system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits 1923system.cpu3.icache.overall_hits::total 22614 # number of overall hits 1924system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses 1925system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses 1926system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses 1927system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses 1928system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses 1929system.cpu3.icache.overall_misses::total 477 # number of overall misses 1930system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles 1931system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles 1932system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles 1933system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles 1934system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles 1935system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles 1936system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) 1937system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) 1938system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses 1939system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses 1940system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses 1941system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses 1942system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses 1943system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses 1944system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses 1945system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses 1946system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses 1947system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses 1948system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency 1949system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency 1950system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency 1951system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency 1952system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency 1953system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency |
| 1953system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1954system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1955system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1956system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1957system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1958system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1959system.cpu3.icache.fast_writes 0 # number of fast writes performed 1960system.cpu3.icache.cache_copies 0 # number of cache copies performed | 1954system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1955system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1956system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1957system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1958system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1959system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1960system.cpu3.icache.fast_writes 0 # number of fast writes performed 1961system.cpu3.icache.cache_copies 0 # number of cache copies performed |
| 1961system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits 1962system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1963system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits 1964system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1965system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 1966system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1967system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses 1968system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1969system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand (read+write) MSHR misses 1970system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1971system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses 1972system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1973system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles 1974system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles 1975system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles 1976system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles 1977system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles 1978system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles 1979system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses 1980system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses 1981system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses 1982system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses 1983system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses 1984system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses 1985system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average ReadReq mshr miss latency 1986system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11610.981308 # average ReadReq mshr miss latency 1987system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency 1988system.cpu3.icache.demand_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency 1989system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency 1990system.cpu3.icache.overall_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency | 1962system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 48 # number of ReadReq MSHR hits 1963system.cpu3.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1964system.cpu3.icache.demand_mshr_hits::cpu3.inst 48 # number of demand (read+write) MSHR hits 1965system.cpu3.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1966system.cpu3.icache.overall_mshr_hits::cpu3.inst 48 # number of overall MSHR hits 1967system.cpu3.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1968system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 1969system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 1970system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 1971system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 1972system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 1973system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 1974system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles 1975system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles 1976system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles 1977system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles 1978system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles 1979system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles 1980system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses 1981system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses 1982system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses 1983system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # mshr miss rate for demand accesses 1984system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for overall accesses 1985system.cpu3.icache.overall_mshr_miss_rate::total 0.018579 # mshr miss rate for overall accesses 1986system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average ReadReq mshr miss latency 1987system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11637.529138 # average ReadReq mshr miss latency 1988system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency 1989system.cpu3.icache.demand_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency 1990system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency 1991system.cpu3.icache.overall_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency |
| 1991system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1992system.cpu3.dcache.replacements 0 # number of replacements | 1992system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1993system.cpu3.dcache.replacements 0 # number of replacements |
| 1993system.cpu3.dcache.tagsinuse 25.854191 # Cycle average of tags in use 1994system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. | 1994system.cpu3.dcache.tagsinuse 24.557568 # Cycle average of tags in use 1995system.cpu3.dcache.total_refs 36284 # Total number of references to valid blocks. |
| 1995system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. | 1996system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. |
| 1996system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. | 1997system.cpu3.dcache.avg_refs 1295.857143 # Average number of references to valid blocks. |
| 1997system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1998system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1998system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor 1999system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy 2000system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy 2001system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits 2002system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits 2003system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # number of WriteReq hits 2004system.cpu3.dcache.WriteReq_hits::total 38586 # number of WriteReq hits 2005system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 2006system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 2007system.cpu3.dcache.demand_hits::cpu3.data 86488 # number of demand (read+write) hits 2008system.cpu3.dcache.demand_hits::total 86488 # number of demand (read+write) hits 2009system.cpu3.dcache.overall_hits::cpu3.data 86488 # number of overall hits 2010system.cpu3.dcache.overall_hits::total 86488 # number of overall hits 2011system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses 2012system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses 2013system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses 2014system.cpu3.dcache.WriteReq_misses::total 142 # number of WriteReq misses 2015system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses 2016system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses 2017system.cpu3.dcache.demand_misses::cpu3.data 568 # number of demand (read+write) misses 2018system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses 2019system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses 2020system.cpu3.dcache.overall_misses::total 568 # number of overall misses 2021system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5341000 # number of ReadReq miss cycles 2022system.cpu3.dcache.ReadReq_miss_latency::total 5341000 # number of ReadReq miss cycles 2023system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2325000 # number of WriteReq miss cycles 2024system.cpu3.dcache.WriteReq_miss_latency::total 2325000 # number of WriteReq miss cycles 2025system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles 2026system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles 2027system.cpu3.dcache.demand_miss_latency::cpu3.data 7666000 # number of demand (read+write) miss cycles 2028system.cpu3.dcache.demand_miss_latency::total 7666000 # number of demand (read+write) miss cycles 2029system.cpu3.dcache.overall_miss_latency::cpu3.data 7666000 # number of overall miss cycles 2030system.cpu3.dcache.overall_miss_latency::total 7666000 # number of overall miss cycles 2031system.cpu3.dcache.ReadReq_accesses::cpu3.data 48328 # number of ReadReq accesses(hits+misses) 2032system.cpu3.dcache.ReadReq_accesses::total 48328 # number of ReadReq accesses(hits+misses) 2033system.cpu3.dcache.WriteReq_accesses::cpu3.data 38728 # number of WriteReq accesses(hits+misses) 2034system.cpu3.dcache.WriteReq_accesses::total 38728 # number of WriteReq accesses(hits+misses) 2035system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) 2036system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 2037system.cpu3.dcache.demand_accesses::cpu3.data 87056 # number of demand (read+write) accesses 2038system.cpu3.dcache.demand_accesses::total 87056 # number of demand (read+write) accesses 2039system.cpu3.dcache.overall_accesses::cpu3.data 87056 # number of overall (read+write) accesses 2040system.cpu3.dcache.overall_accesses::total 87056 # number of overall (read+write) accesses 2041system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses 2042system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses 2043system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses 2044system.cpu3.dcache.WriteReq_miss_rate::total 0.003667 # miss rate for WriteReq accesses 2045system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses 2046system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses 2047system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 # miss rate for demand accesses 2048system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses 2049system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses 2050system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses 2051system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12537.558685 # average ReadReq miss latency 2052system.cpu3.dcache.ReadReq_avg_miss_latency::total 12537.558685 # average ReadReq miss latency 2053system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16373.239437 # average WriteReq miss latency 2054system.cpu3.dcache.WriteReq_avg_miss_latency::total 16373.239437 # average WriteReq miss latency 2055system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency 2056system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency 2057system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency 2058system.cpu3.dcache.demand_avg_miss_latency::total 13496.478873 # average overall miss latency 2059system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency 2060system.cpu3.dcache.overall_avg_miss_latency::total 13496.478873 # average overall miss latency | 1999system.cpu3.dcache.occ_blocks::cpu3.data 24.557568 # Average occupied blocks per requestor 2000system.cpu3.dcache.occ_percent::cpu3.data 0.047964 # Average percentage of cache occupancy 2001system.cpu3.dcache.occ_percent::total 0.047964 # Average percentage of cache occupancy 2002system.cpu3.dcache.ReadReq_hits::cpu3.data 41265 # number of ReadReq hits 2003system.cpu3.dcache.ReadReq_hits::total 41265 # number of ReadReq hits 2004system.cpu3.dcache.WriteReq_hits::cpu3.data 30070 # number of WriteReq hits 2005system.cpu3.dcache.WriteReq_hits::total 30070 # number of WriteReq hits 2006system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 2007system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 2008system.cpu3.dcache.demand_hits::cpu3.data 71335 # number of demand (read+write) hits 2009system.cpu3.dcache.demand_hits::total 71335 # number of demand (read+write) hits 2010system.cpu3.dcache.overall_hits::cpu3.data 71335 # number of overall hits 2011system.cpu3.dcache.overall_hits::total 71335 # number of overall hits 2012system.cpu3.dcache.ReadReq_misses::cpu3.data 376 # number of ReadReq misses 2013system.cpu3.dcache.ReadReq_misses::total 376 # number of ReadReq misses 2014system.cpu3.dcache.WriteReq_misses::cpu3.data 130 # number of WriteReq misses 2015system.cpu3.dcache.WriteReq_misses::total 130 # number of WriteReq misses 2016system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses 2017system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses 2018system.cpu3.dcache.demand_misses::cpu3.data 506 # number of demand (read+write) misses 2019system.cpu3.dcache.demand_misses::total 506 # number of demand (read+write) misses 2020system.cpu3.dcache.overall_misses::cpu3.data 506 # number of overall misses 2021system.cpu3.dcache.overall_misses::total 506 # number of overall misses 2022system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4881500 # number of ReadReq miss cycles 2023system.cpu3.dcache.ReadReq_miss_latency::total 4881500 # number of ReadReq miss cycles 2024system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2539500 # number of WriteReq miss cycles 2025system.cpu3.dcache.WriteReq_miss_latency::total 2539500 # number of WriteReq miss cycles 2026system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 546000 # number of SwapReq miss cycles 2027system.cpu3.dcache.SwapReq_miss_latency::total 546000 # number of SwapReq miss cycles 2028system.cpu3.dcache.demand_miss_latency::cpu3.data 7421000 # number of demand (read+write) miss cycles 2029system.cpu3.dcache.demand_miss_latency::total 7421000 # number of demand (read+write) miss cycles 2030system.cpu3.dcache.overall_miss_latency::cpu3.data 7421000 # number of overall miss cycles 2031system.cpu3.dcache.overall_miss_latency::total 7421000 # number of overall miss cycles 2032system.cpu3.dcache.ReadReq_accesses::cpu3.data 41641 # number of ReadReq accesses(hits+misses) 2033system.cpu3.dcache.ReadReq_accesses::total 41641 # number of ReadReq accesses(hits+misses) 2034system.cpu3.dcache.WriteReq_accesses::cpu3.data 30200 # number of WriteReq accesses(hits+misses) 2035system.cpu3.dcache.WriteReq_accesses::total 30200 # number of WriteReq accesses(hits+misses) 2036system.cpu3.dcache.SwapReq_accesses::cpu3.data 74 # number of SwapReq accesses(hits+misses) 2037system.cpu3.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) 2038system.cpu3.dcache.demand_accesses::cpu3.data 71841 # number of demand (read+write) accesses 2039system.cpu3.dcache.demand_accesses::total 71841 # number of demand (read+write) accesses 2040system.cpu3.dcache.overall_accesses::cpu3.data 71841 # number of overall (read+write) accesses 2041system.cpu3.dcache.overall_accesses::total 71841 # number of overall (read+write) accesses 2042system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009030 # miss rate for ReadReq accesses 2043system.cpu3.dcache.ReadReq_miss_rate::total 0.009030 # miss rate for ReadReq accesses 2044system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004305 # miss rate for WriteReq accesses 2045system.cpu3.dcache.WriteReq_miss_rate::total 0.004305 # miss rate for WriteReq accesses 2046system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797297 # miss rate for SwapReq accesses 2047system.cpu3.dcache.SwapReq_miss_rate::total 0.797297 # miss rate for SwapReq accesses 2048system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007043 # miss rate for demand accesses 2049system.cpu3.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses 2050system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007043 # miss rate for overall accesses 2051system.cpu3.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses 2052system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12982.712766 # average ReadReq miss latency 2053system.cpu3.dcache.ReadReq_avg_miss_latency::total 12982.712766 # average ReadReq miss latency 2054system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19534.615385 # average WriteReq miss latency 2055system.cpu3.dcache.WriteReq_avg_miss_latency::total 19534.615385 # average WriteReq miss latency 2056system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9254.237288 # average SwapReq miss latency 2057system.cpu3.dcache.SwapReq_avg_miss_latency::total 9254.237288 # average SwapReq miss latency 2058system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency 2059system.cpu3.dcache.demand_avg_miss_latency::total 14666.007905 # average overall miss latency 2060system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency 2061system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905 # average overall miss latency |
| 2061system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2062system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2063system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2064system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2065system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2066system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2067system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2068system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 2062system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2063system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2064system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2065system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2066system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2067system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2068system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2069system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 2069system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits 2070system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits 2071system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2072system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2073system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits 2074system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits 2075system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of overall MSHR hits 2076system.cpu3.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits 2077system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 153 # number of ReadReq MSHR misses 2078system.cpu3.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses 2079system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses 2080system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 2081system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 2082system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 2083system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses 2084system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 2085system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses 2086system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses 2087system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles 2088system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles 2089system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles 2090system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles 2091system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles 2092system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles 2093system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles 2094system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles 2095system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles 2096system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles 2097system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses 2098system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses 2099system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses 2100system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses 2101system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses 2102system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses 2103system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses 2104system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses 2105system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses 2106system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses 2107system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency 2108system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency 2109system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency 2110system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency 2111system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency 2112system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency 2113system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency 2114system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency 2115system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency 2116system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency | 2070system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 218 # number of ReadReq MSHR hits 2071system.cpu3.dcache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits 2072system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 30 # number of WriteReq MSHR hits 2073system.cpu3.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits 2074system.cpu3.dcache.demand_mshr_hits::cpu3.data 248 # number of demand (read+write) MSHR hits 2075system.cpu3.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 2076system.cpu3.dcache.overall_mshr_hits::cpu3.data 248 # number of overall MSHR hits 2077system.cpu3.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 2078system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses 2079system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 2080system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses 2081system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses 2082system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses 2083system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 2084system.cpu3.dcache.demand_mshr_misses::cpu3.data 258 # number of demand (read+write) MSHR misses 2085system.cpu3.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses 2086system.cpu3.dcache.overall_mshr_misses::cpu3.data 258 # number of overall MSHR misses 2087system.cpu3.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses 2088system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1328000 # number of ReadReq MSHR miss cycles 2089system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1328000 # number of ReadReq MSHR miss cycles 2090system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1243000 # number of WriteReq MSHR miss cycles 2091system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1243000 # number of WriteReq MSHR miss cycles 2092system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 428000 # number of SwapReq MSHR miss cycles 2093system.cpu3.dcache.SwapReq_mshr_miss_latency::total 428000 # number of SwapReq MSHR miss cycles 2094system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2571000 # number of demand (read+write) MSHR miss cycles 2095system.cpu3.dcache.demand_mshr_miss_latency::total 2571000 # number of demand (read+write) MSHR miss cycles 2096system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2571000 # number of overall MSHR miss cycles 2097system.cpu3.dcache.overall_mshr_miss_latency::total 2571000 # number of overall MSHR miss cycles 2098system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003794 # mshr miss rate for ReadReq accesses 2099system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003794 # mshr miss rate for ReadReq accesses 2100system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003311 # mshr miss rate for WriteReq accesses 2101system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003311 # mshr miss rate for WriteReq accesses 2102system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797297 # mshr miss rate for SwapReq accesses 2103system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797297 # mshr miss rate for SwapReq accesses 2104system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses 2105system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses 2106system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses 2107system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses 2108system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8405.063291 # average ReadReq mshr miss latency 2109system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8405.063291 # average ReadReq mshr miss latency 2110system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12430 # average WriteReq mshr miss latency 2111system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12430 # average WriteReq mshr miss latency 2112system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency 2113system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency 2114system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2115system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency 2116system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency 2117system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency |
| 2117system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2118system.l2c.replacements 0 # number of replacements | 2118system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2119system.l2c.replacements 0 # number of replacements |
| 2119system.l2c.tagsinuse 425.291959 # Cycle average of tags in use 2120system.l2c.total_refs 1448 # Total number of references to valid blocks. 2121system.l2c.sampled_refs 525 # Sample count of references to valid blocks. 2122system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. | 2120system.l2c.tagsinuse 425.230692 # Cycle average of tags in use 2121system.l2c.total_refs 1445 # Total number of references to valid blocks. 2122system.l2c.sampled_refs 527 # Sample count of references to valid blocks. 2123system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. |
| 2123system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2124system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2124system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor 2125system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor 2126system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor 2127system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor 2128system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor 2129system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor 2130system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor 2131system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor 2132system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor | 2125system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor 2126system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor 2127system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor 2128system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor 2129system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor 2130system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor 2131system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor 2132system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor 2133system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor |
| 2133system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy | 2134system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy |
| 2134system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy 2135system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy 2136system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy | 2135system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy 2136system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy 2137system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy |
| 2137system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy | 2138system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy |
| 2138system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy 2139system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy 2140system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy 2141system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy | 2139system.l2c.occ_percent::cpu2.inst 0.000067 # Average percentage of cache occupancy 2140system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy 2141system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy 2142system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy |
| 2142system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy | 2143system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy |
| 2143system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits | 2144system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits |
| 2144system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2145system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits 2146system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits | 2145system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2146system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits 2147system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits |
| 2147system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits | 2148system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits |
| 2148system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits | 2149system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits |
| 2149system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits | 2150system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits |
| 2150system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits | 2151system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits |
| 2151system.l2c.ReadReq_hits::total 1448 # number of ReadReq hits | 2152system.l2c.ReadReq_hits::total 1445 # number of ReadReq hits |
| 2152system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2153system.l2c.Writeback_hits::total 1 # number of Writeback hits 2154system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2155system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits | 2153system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2154system.l2c.Writeback_hits::total 1 # number of Writeback hits 2155system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2156system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
| 2156system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits | 2157system.l2c.demand_hits::cpu0.inst 230 # number of demand (read+write) hits |
| 2157system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2158system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits 2159system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits | 2158system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2159system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits 2160system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits |
| 2160system.l2c.demand_hits::cpu2.inst 421 # number of demand (read+write) hits | 2161system.l2c.demand_hits::cpu2.inst 418 # number of demand (read+write) hits |
| 2161system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits | 2162system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits |
| 2162system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits | 2163system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits |
| 2163system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits | 2164system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits |
| 2164system.l2c.demand_hits::total 1448 # number of demand (read+write) hits 2165system.l2c.overall_hits::cpu0.inst 229 # number of overall hits | 2165system.l2c.demand_hits::total 1445 # number of demand (read+write) hits 2166system.l2c.overall_hits::cpu0.inst 230 # number of overall hits |
| 2166system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2167system.l2c.overall_hits::cpu1.inst 342 # number of overall hits 2168system.l2c.overall_hits::cpu1.data 5 # number of overall hits | 2167system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2168system.l2c.overall_hits::cpu1.inst 342 # number of overall hits 2169system.l2c.overall_hits::cpu1.data 5 # number of overall hits |
| 2169system.l2c.overall_hits::cpu2.inst 421 # number of overall hits | 2170system.l2c.overall_hits::cpu2.inst 418 # number of overall hits |
| 2170system.l2c.overall_hits::cpu2.data 11 # number of overall hits | 2171system.l2c.overall_hits::cpu2.data 11 # number of overall hits |
| 2171system.l2c.overall_hits::cpu3.inst 424 # number of overall hits | 2172system.l2c.overall_hits::cpu3.inst 423 # number of overall hits |
| 2172system.l2c.overall_hits::cpu3.data 11 # number of overall hits | 2173system.l2c.overall_hits::cpu3.data 11 # number of overall hits |
| 2173system.l2c.overall_hits::total 1448 # number of overall hits 2174system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses | 2174system.l2c.overall_hits::total 1445 # number of overall hits 2175system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses |
| 2175system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2176system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses 2177system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses | 2176system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2177system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses 2178system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses |
| 2178system.l2c.ReadReq_misses::cpu2.inst 8 # number of ReadReq misses | 2179system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses |
| 2179system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses | 2180system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses |
| 2180system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses | 2181system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses |
| 2181system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses | 2182system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses |
| 2182system.l2c.ReadReq_misses::total 537 # number of ReadReq misses 2183system.l2c.UpgradeReq_misses::cpu0.data 19 # number of UpgradeReq misses 2184system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 2185system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 2186system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 2187system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses | 2183system.l2c.ReadReq_misses::total 544 # number of ReadReq misses 2184system.l2c.UpgradeReq_misses::cpu0.data 18 # number of UpgradeReq misses 2185system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 2186system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 2187system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 2188system.l2c.UpgradeReq_misses::total 71 # number of UpgradeReq misses |
| 2188system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2189system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2190system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2191system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2192system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses | 2189system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2190system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2191system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2192system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2193system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses |
| 2193system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses | 2194system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses |
| 2194system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2195system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses 2196system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses | 2195system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2196system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses 2197system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses |
| 2197system.l2c.demand_misses::cpu2.inst 8 # number of demand (read+write) misses | 2198system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses |
| 2198system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses | 2199system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses |
| 2199system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses | 2200system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses |
| 2200system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses | 2201system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses |
| 2201system.l2c.demand_misses::total 668 # number of demand (read+write) misses 2202system.l2c.overall_misses::cpu0.inst 359 # number of overall misses | 2202system.l2c.demand_misses::total 675 # number of demand (read+write) misses 2203system.l2c.overall_misses::cpu0.inst 360 # number of overall misses |
| 2203system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2204system.l2c.overall_misses::cpu1.inst 83 # number of overall misses 2205system.l2c.overall_misses::cpu1.data 20 # number of overall misses | 2204system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2205system.l2c.overall_misses::cpu1.inst 83 # number of overall misses 2206system.l2c.overall_misses::cpu1.data 20 # number of overall misses |
| 2206system.l2c.overall_misses::cpu2.inst 8 # number of overall misses | 2207system.l2c.overall_misses::cpu2.inst 12 # number of overall misses |
| 2207system.l2c.overall_misses::cpu2.data 13 # number of overall misses | 2208system.l2c.overall_misses::cpu2.data 13 # number of overall misses |
| 2208system.l2c.overall_misses::cpu3.inst 4 # number of overall misses | 2209system.l2c.overall_misses::cpu3.inst 6 # number of overall misses |
| 2209system.l2c.overall_misses::cpu3.data 13 # number of overall misses | 2210system.l2c.overall_misses::cpu3.data 13 # number of overall misses |
| 2210system.l2c.overall_misses::total 668 # number of overall misses 2211system.l2c.ReadReq_miss_latency::cpu0.inst 17552500 # number of ReadReq miss cycles 2212system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles 2213system.l2c.ReadReq_miss_latency::cpu1.inst 4145500 # number of ReadReq miss cycles 2214system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles 2215system.l2c.ReadReq_miss_latency::cpu2.inst 395000 # number of ReadReq miss cycles | 2211system.l2c.overall_misses::total 675 # number of overall misses 2212system.l2c.ReadReq_miss_latency::cpu0.inst 18237500 # number of ReadReq miss cycles 2213system.l2c.ReadReq_miss_latency::cpu0.data 4615000 # number of ReadReq miss cycles 2214system.l2c.ReadReq_miss_latency::cpu1.inst 4399500 # number of ReadReq miss cycles 2215system.l2c.ReadReq_miss_latency::cpu1.data 666000 # number of ReadReq miss cycles 2216system.l2c.ReadReq_miss_latency::cpu2.inst 728500 # number of ReadReq miss cycles |
| 2216system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles | 2217system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles |
| 2217system.l2c.ReadReq_miss_latency::cpu3.inst 232000 # number of ReadReq miss cycles | 2218system.l2c.ReadReq_miss_latency::cpu3.inst 248500 # number of ReadReq miss cycles |
| 2218system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles | 2219system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles |
| 2219system.l2c.ReadReq_miss_latency::total 26912000 # number of ReadReq miss cycles 2220system.l2c.ReadExReq_miss_latency::cpu0.data 5008000 # number of ReadExReq miss cycles 2221system.l2c.ReadExReq_miss_latency::cpu1.data 878500 # number of ReadExReq miss cycles 2222system.l2c.ReadExReq_miss_latency::cpu2.data 701000 # number of ReadExReq miss cycles 2223system.l2c.ReadExReq_miss_latency::cpu3.data 660000 # number of ReadExReq miss cycles 2224system.l2c.ReadExReq_miss_latency::total 7247500 # number of ReadExReq miss cycles 2225system.l2c.demand_miss_latency::cpu0.inst 17552500 # number of demand (read+write) miss cycles 2226system.l2c.demand_miss_latency::cpu0.data 9077000 # number of demand (read+write) miss cycles 2227system.l2c.demand_miss_latency::cpu1.inst 4145500 # number of demand (read+write) miss cycles 2228system.l2c.demand_miss_latency::cpu1.data 1259500 # number of demand (read+write) miss cycles 2229system.l2c.demand_miss_latency::cpu2.inst 395000 # number of demand (read+write) miss cycles 2230system.l2c.demand_miss_latency::cpu2.data 769500 # number of demand (read+write) miss cycles 2231system.l2c.demand_miss_latency::cpu3.inst 232000 # number of demand (read+write) miss cycles 2232system.l2c.demand_miss_latency::cpu3.data 728500 # number of demand (read+write) miss cycles 2233system.l2c.demand_miss_latency::total 34159500 # number of demand (read+write) miss cycles 2234system.l2c.overall_miss_latency::cpu0.inst 17552500 # number of overall miss cycles 2235system.l2c.overall_miss_latency::cpu0.data 9077000 # number of overall miss cycles 2236system.l2c.overall_miss_latency::cpu1.inst 4145500 # number of overall miss cycles 2237system.l2c.overall_miss_latency::cpu1.data 1259500 # number of overall miss cycles 2238system.l2c.overall_miss_latency::cpu2.inst 395000 # number of overall miss cycles 2239system.l2c.overall_miss_latency::cpu2.data 769500 # number of overall miss cycles 2240system.l2c.overall_miss_latency::cpu3.inst 232000 # number of overall miss cycles 2241system.l2c.overall_miss_latency::cpu3.data 728500 # number of overall miss cycles 2242system.l2c.overall_miss_latency::total 34159500 # number of overall miss cycles 2243system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) | 2220system.l2c.ReadReq_miss_latency::total 29032000 # number of ReadReq miss cycles 2221system.l2c.ReadExReq_miss_latency::cpu0.data 5403000 # number of ReadExReq miss cycles 2222system.l2c.ReadExReq_miss_latency::cpu1.data 996000 # number of ReadExReq miss cycles 2223system.l2c.ReadExReq_miss_latency::cpu2.data 869000 # number of ReadExReq miss cycles 2224system.l2c.ReadExReq_miss_latency::cpu3.data 756000 # number of ReadExReq miss cycles 2225system.l2c.ReadExReq_miss_latency::total 8024000 # number of ReadExReq miss cycles 2226system.l2c.demand_miss_latency::cpu0.inst 18237500 # number of demand (read+write) miss cycles 2227system.l2c.demand_miss_latency::cpu0.data 10018000 # number of demand (read+write) miss cycles 2228system.l2c.demand_miss_latency::cpu1.inst 4399500 # number of demand (read+write) miss cycles 2229system.l2c.demand_miss_latency::cpu1.data 1662000 # number of demand (read+write) miss cycles 2230system.l2c.demand_miss_latency::cpu2.inst 728500 # number of demand (read+write) miss cycles 2231system.l2c.demand_miss_latency::cpu2.data 937500 # number of demand (read+write) miss cycles 2232system.l2c.demand_miss_latency::cpu3.inst 248500 # number of demand (read+write) miss cycles 2233system.l2c.demand_miss_latency::cpu3.data 824500 # number of demand (read+write) miss cycles 2234system.l2c.demand_miss_latency::total 37056000 # number of demand (read+write) miss cycles 2235system.l2c.overall_miss_latency::cpu0.inst 18237500 # number of overall miss cycles 2236system.l2c.overall_miss_latency::cpu0.data 10018000 # number of overall miss cycles 2237system.l2c.overall_miss_latency::cpu1.inst 4399500 # number of overall miss cycles 2238system.l2c.overall_miss_latency::cpu1.data 1662000 # number of overall miss cycles 2239system.l2c.overall_miss_latency::cpu2.inst 728500 # number of overall miss cycles 2240system.l2c.overall_miss_latency::cpu2.data 937500 # number of overall miss cycles 2241system.l2c.overall_miss_latency::cpu3.inst 248500 # number of overall miss cycles 2242system.l2c.overall_miss_latency::cpu3.data 824500 # number of overall miss cycles 2243system.l2c.overall_miss_latency::total 37056000 # number of overall miss cycles 2244system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) |
| 2244system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2245system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2246system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) | 2245system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2246system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2247system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) |
| 2247system.l2c.ReadReq_accesses::cpu2.inst 429 # number of ReadReq accesses(hits+misses) | 2248system.l2c.ReadReq_accesses::cpu2.inst 430 # number of ReadReq accesses(hits+misses) |
| 2248system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) | 2249system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) |
| 2249system.l2c.ReadReq_accesses::cpu3.inst 428 # number of ReadReq accesses(hits+misses) | 2250system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) |
| 2250system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) | 2251system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) |
| 2251system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) | 2252system.l2c.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) |
| 2252system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2253system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) | 2253system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2254system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) |
| 2254system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses) 2255system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 2256system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 2257system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 2258system.l2c.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) | 2255system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) 2256system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 2257system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 2258system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 2259system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) |
| 2259system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2260system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2261system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2262system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2263system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) | 2260system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2261system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2262system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2263system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2264system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) |
| 2264system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses | 2265system.l2c.demand_accesses::cpu0.inst 590 # number of demand (read+write) accesses |
| 2265system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2266system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2267system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses | 2266system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2267system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2268system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses |
| 2268system.l2c.demand_accesses::cpu2.inst 429 # number of demand (read+write) accesses | 2269system.l2c.demand_accesses::cpu2.inst 430 # number of demand (read+write) accesses |
| 2269system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses | 2270system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses |
| 2270system.l2c.demand_accesses::cpu3.inst 428 # number of demand (read+write) accesses | 2271system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses |
| 2271system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses | 2272system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses |
| 2272system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses 2273system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses | 2273system.l2c.demand_accesses::total 2120 # number of demand (read+write) accesses 2274system.l2c.overall_accesses::cpu0.inst 590 # number of overall (read+write) accesses |
| 2274system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2275system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2276system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses | 2275system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2276system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2277system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses |
| 2277system.l2c.overall_accesses::cpu2.inst 429 # number of overall (read+write) accesses | 2278system.l2c.overall_accesses::cpu2.inst 430 # number of overall (read+write) accesses |
| 2278system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses | 2279system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses |
| 2279system.l2c.overall_accesses::cpu3.inst 428 # number of overall (read+write) accesses | 2280system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses |
| 2280system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses | 2281system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses |
| 2281system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses 2282system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses | 2282system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses 2283system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses |
| 2283system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2284system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses 2285system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses | 2284system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2285system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses 2286system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses |
| 2286system.l2c.ReadReq_miss_rate::cpu2.inst 0.018648 # miss rate for ReadReq accesses | 2287system.l2c.ReadReq_miss_rate::cpu2.inst 0.027907 # miss rate for ReadReq accesses |
| 2287system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses | 2288system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses |
| 2288system.l2c.ReadReq_miss_rate::cpu3.inst 0.009346 # miss rate for ReadReq accesses | 2289system.l2c.ReadReq_miss_rate::cpu3.inst 0.013986 # miss rate for ReadReq accesses |
| 2289system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses | 2290system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses |
| 2290system.l2c.ReadReq_miss_rate::total 0.270529 # miss rate for ReadReq accesses 2291system.l2c.UpgradeReq_miss_rate::cpu0.data 0.863636 # miss rate for UpgradeReq accesses | 2291system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses 2292system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses |
| 2292system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2293system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2294system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 2293system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2294system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2295system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 2295system.l2c.UpgradeReq_miss_rate::total 0.960000 # miss rate for UpgradeReq accesses | 2296system.l2c.UpgradeReq_miss_rate::total 0.959459 # miss rate for UpgradeReq accesses |
| 2296system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2297system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2298system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2299system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2300system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 2297system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2298system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2299system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2300system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2301system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 2301system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses | 2302system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses |
| 2302system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2303system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses 2304system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses | 2303system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2304system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses 2305system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses |
| 2305system.l2c.demand_miss_rate::cpu2.inst 0.018648 # miss rate for demand accesses | 2306system.l2c.demand_miss_rate::cpu2.inst 0.027907 # miss rate for demand accesses |
| 2306system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses | 2307system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses |
| 2307system.l2c.demand_miss_rate::cpu3.inst 0.009346 # miss rate for demand accesses | 2308system.l2c.demand_miss_rate::cpu3.inst 0.013986 # miss rate for demand accesses |
| 2308system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses | 2309system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses |
| 2309system.l2c.demand_miss_rate::total 0.315690 # miss rate for demand accesses 2310system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses | 2310system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses 2311system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses |
| 2311system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2312system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses 2313system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses | 2312system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2313system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses 2314system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses |
| 2314system.l2c.overall_miss_rate::cpu2.inst 0.018648 # miss rate for overall accesses | 2315system.l2c.overall_miss_rate::cpu2.inst 0.027907 # miss rate for overall accesses |
| 2315system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses | 2316system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses |
| 2316system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses | 2317system.l2c.overall_miss_rate::cpu3.inst 0.013986 # miss rate for overall accesses |
| 2317system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses | 2318system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses |
| 2318system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses 2319system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48892.757660 # average ReadReq miss latency 2320system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency 2321system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49945.783133 # average ReadReq miss latency 2322system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency 2323system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49375 # average ReadReq miss latency | 2319system.l2c.overall_miss_rate::total 0.318396 # miss rate for overall accesses 2320system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50659.722222 # average ReadReq miss latency 2321system.l2c.ReadReq_avg_miss_latency::cpu0.data 62364.864865 # average ReadReq miss latency 2322system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53006.024096 # average ReadReq miss latency 2323system.l2c.ReadReq_avg_miss_latency::cpu1.data 95142.857143 # average ReadReq miss latency 2324system.l2c.ReadReq_avg_miss_latency::cpu2.inst 60708.333333 # average ReadReq miss latency |
| 2324system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency | 2325system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency |
| 2325system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58000 # average ReadReq miss latency | 2326system.l2c.ReadReq_avg_miss_latency::cpu3.inst 41416.666667 # average ReadReq miss latency |
| 2326system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency | 2327system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency |
| 2327system.l2c.ReadReq_avg_miss_latency::total 50115.456238 # average ReadReq miss latency 2328system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53276.595745 # average ReadExReq miss latency 2329system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67576.923077 # average ReadExReq miss latency 2330system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58416.666667 # average ReadExReq miss latency 2331system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55000 # average ReadExReq miss latency 2332system.l2c.ReadExReq_avg_miss_latency::total 55324.427481 # average ReadExReq miss latency 2333system.l2c.demand_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency 2334system.l2c.demand_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency 2335system.l2c.demand_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency 2336system.l2c.demand_avg_miss_latency::cpu1.data 62975 # average overall miss latency 2337system.l2c.demand_avg_miss_latency::cpu2.inst 49375 # average overall miss latency 2338system.l2c.demand_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency 2339system.l2c.demand_avg_miss_latency::cpu3.inst 58000 # average overall miss latency 2340system.l2c.demand_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency 2341system.l2c.demand_avg_miss_latency::total 51136.976048 # average overall miss latency 2342system.l2c.overall_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency 2343system.l2c.overall_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency 2344system.l2c.overall_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency 2345system.l2c.overall_avg_miss_latency::cpu1.data 62975 # average overall miss latency 2346system.l2c.overall_avg_miss_latency::cpu2.inst 49375 # average overall miss latency 2347system.l2c.overall_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency 2348system.l2c.overall_avg_miss_latency::cpu3.inst 58000 # average overall miss latency 2349system.l2c.overall_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency 2350system.l2c.overall_avg_miss_latency::total 51136.976048 # average overall miss latency | 2328system.l2c.ReadReq_avg_miss_latency::total 53367.647059 # average ReadReq miss latency 2329system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57478.723404 # average ReadExReq miss latency 2330system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76615.384615 # average ReadExReq miss latency 2331system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72416.666667 # average ReadExReq miss latency 2332system.l2c.ReadExReq_avg_miss_latency::cpu3.data 63000 # average ReadExReq miss latency 2333system.l2c.ReadExReq_avg_miss_latency::total 61251.908397 # average ReadExReq miss latency 2334system.l2c.demand_avg_miss_latency::cpu0.inst 50659.722222 # average overall miss latency 2335system.l2c.demand_avg_miss_latency::cpu0.data 59630.952381 # average overall miss latency 2336system.l2c.demand_avg_miss_latency::cpu1.inst 53006.024096 # average overall miss latency 2337system.l2c.demand_avg_miss_latency::cpu1.data 83100 # average overall miss latency 2338system.l2c.demand_avg_miss_latency::cpu2.inst 60708.333333 # average overall miss latency 2339system.l2c.demand_avg_miss_latency::cpu2.data 72115.384615 # average overall miss latency 2340system.l2c.demand_avg_miss_latency::cpu3.inst 41416.666667 # average overall miss latency 2341system.l2c.demand_avg_miss_latency::cpu3.data 63423.076923 # average overall miss latency 2342system.l2c.demand_avg_miss_latency::total 54897.777778 # average overall miss latency 2343system.l2c.overall_avg_miss_latency::cpu0.inst 50659.722222 # average overall miss latency 2344system.l2c.overall_avg_miss_latency::cpu0.data 59630.952381 # average overall miss latency 2345system.l2c.overall_avg_miss_latency::cpu1.inst 53006.024096 # average overall miss latency 2346system.l2c.overall_avg_miss_latency::cpu1.data 83100 # average overall miss latency 2347system.l2c.overall_avg_miss_latency::cpu2.inst 60708.333333 # average overall miss latency 2348system.l2c.overall_avg_miss_latency::cpu2.data 72115.384615 # average overall miss latency 2349system.l2c.overall_avg_miss_latency::cpu3.inst 41416.666667 # average overall miss latency 2350system.l2c.overall_avg_miss_latency::cpu3.data 63423.076923 # average overall miss latency 2351system.l2c.overall_avg_miss_latency::total 54897.777778 # average overall miss latency |
| 2351system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2352system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2353system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2354system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2355system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2356system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2357system.l2c.fast_writes 0 # number of fast writes performed 2358system.l2c.cache_copies 0 # number of cache copies performed 2359system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits | 2352system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2353system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2354system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2355system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2356system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2357system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2358system.l2c.fast_writes 0 # number of fast writes performed 2359system.l2c.cache_copies 0 # number of cache copies performed 2360system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits |
| 2360system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 2361system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits 2362system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits | 2361system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2362system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits 2363system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits 2364system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits |
| 2363system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits | 2365system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits |
| 2364system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2365system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits 2366system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits | 2366system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2367system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits 2368system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits 2369system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits |
| 2367system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits | 2370system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits |
| 2368system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2369system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits 2370system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits 2371system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses | 2371system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2372system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits 2373system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits 2374system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 2375system.l2c.ReadReq_mshr_misses::cpu0.inst 358 # number of ReadReq MSHR misses |
| 2372system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses | 2376system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses |
| 2373system.l2c.ReadReq_mshr_misses::cpu1.inst 81 # number of ReadReq MSHR misses | 2377system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses |
| 2374system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses | 2378system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses |
| 2375system.l2c.ReadReq_mshr_misses::cpu2.inst 3 # number of ReadReq MSHR misses | 2379system.l2c.ReadReq_mshr_misses::cpu2.inst 6 # number of ReadReq MSHR misses |
| 2376system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses | 2380system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses |
| 2377system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses | 2381system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses |
| 2378system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses | 2382system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses |
| 2379system.l2c.ReadReq_mshr_misses::total 528 # number of ReadReq MSHR misses 2380system.l2c.UpgradeReq_mshr_misses::cpu0.data 19 # number of UpgradeReq MSHR misses 2381system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses 2382system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses 2383system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 2384system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses | 2383system.l2c.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses 2384system.l2c.UpgradeReq_mshr_misses::cpu0.data 18 # number of UpgradeReq MSHR misses 2385system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses 2386system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses 2387system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses 2388system.l2c.UpgradeReq_mshr_misses::total 71 # number of UpgradeReq MSHR misses |
| 2385system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2386system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2387system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2388system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2389system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses | 2389system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2390system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2391system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2392system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2393system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses |
| 2390system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses | 2394system.l2c.demand_mshr_misses::cpu0.inst 358 # number of demand (read+write) MSHR misses |
| 2391system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses | 2395system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses |
| 2392system.l2c.demand_mshr_misses::cpu1.inst 81 # number of demand (read+write) MSHR misses | 2396system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses |
| 2393system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses | 2397system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses |
| 2394system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses | 2398system.l2c.demand_mshr_misses::cpu2.inst 6 # number of demand (read+write) MSHR misses |
| 2395system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses | 2399system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses |
| 2396system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses | 2400system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses |
| 2397system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses | 2401system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses |
| 2398system.l2c.demand_mshr_misses::total 659 # number of demand (read+write) MSHR misses 2399system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses | 2402system.l2c.demand_mshr_misses::total 661 # number of demand (read+write) MSHR misses 2403system.l2c.overall_mshr_misses::cpu0.inst 358 # number of overall MSHR misses |
| 2400system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses | 2404system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses |
| 2401system.l2c.overall_mshr_misses::cpu1.inst 81 # number of overall MSHR misses | 2405system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses |
| 2402system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses | 2406system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses |
| 2403system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses | 2407system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses |
| 2404system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses | 2408system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses |
| 2405system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses | 2409system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses |
| 2406system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses | 2410system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses |
| 2407system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses 2408system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13005059 # number of ReadReq MSHR miss cycles 2409system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles 2410system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles 2411system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles 2412system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles 2413system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles 2414system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 180507 # number of ReadReq MSHR miss cycles 2415system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles 2416system.l2c.ReadReq_mshr_miss_latency::total 19870284 # number of ReadReq MSHR miss cycles 2417system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles 2418system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles 2419system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles 2420system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles 2421system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles 2422system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3834610 # number of ReadExReq MSHR miss cycles 2423system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 717513 # number of ReadExReq MSHR miss cycles 2424system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 550018 # number of ReadExReq MSHR miss cycles 2425system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 510018 # number of ReadExReq MSHR miss cycles 2426system.l2c.ReadExReq_mshr_miss_latency::total 5612159 # number of ReadExReq MSHR miss cycles 2427system.l2c.demand_mshr_miss_latency::cpu0.inst 13005059 # number of demand (read+write) MSHR miss cycles 2428system.l2c.demand_mshr_miss_latency::cpu0.data 6985186 # number of demand (read+write) MSHR miss cycles 2429system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles 2430system.l2c.demand_mshr_miss_latency::cpu1.data 1010523 # number of demand (read+write) MSHR miss cycles 2431system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles 2432system.l2c.demand_mshr_miss_latency::cpu2.data 606020 # number of demand (read+write) MSHR miss cycles 2433system.l2c.demand_mshr_miss_latency::cpu3.inst 180507 # number of demand (read+write) MSHR miss cycles 2434system.l2c.demand_mshr_miss_latency::cpu3.data 566020 # number of demand (read+write) MSHR miss cycles 2435system.l2c.demand_mshr_miss_latency::total 25482443 # number of demand (read+write) MSHR miss cycles 2436system.l2c.overall_mshr_miss_latency::cpu0.inst 13005059 # number of overall MSHR miss cycles 2437system.l2c.overall_mshr_miss_latency::cpu0.data 6985186 # number of overall MSHR miss cycles 2438system.l2c.overall_mshr_miss_latency::cpu1.inst 3026126 # number of overall MSHR miss cycles 2439system.l2c.overall_mshr_miss_latency::cpu1.data 1010523 # number of overall MSHR miss cycles 2440system.l2c.overall_mshr_miss_latency::cpu2.inst 103002 # number of overall MSHR miss cycles 2441system.l2c.overall_mshr_miss_latency::cpu2.data 606020 # number of overall MSHR miss cycles 2442system.l2c.overall_mshr_miss_latency::cpu3.inst 180507 # number of overall MSHR miss cycles 2443system.l2c.overall_mshr_miss_latency::cpu3.data 566020 # number of overall MSHR miss cycles 2444system.l2c.overall_mshr_miss_latency::total 25482443 # number of overall MSHR miss cycles 2445system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses | 2411system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses 2412system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles 2413system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles 2414system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles 2415system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles 2416system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles 2417system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles 2418system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles 2419system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles 2420system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles 2421system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles 2422system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles 2423system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles 2424system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles 2425system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles 2426system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles 2427system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles 2428system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles 2429system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles 2430system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles 2431system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles 2432system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles 2433system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles 2434system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles 2435system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles 2436system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles 2437system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles 2438system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles 2439system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles 2440system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles 2441system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles 2442system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles 2443system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles 2444system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles 2445system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles 2446system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles 2447system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles 2448system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles 2449system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses |
| 2446system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses | 2450system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses |
| 2447system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses | 2451system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses |
| 2448system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses | 2452system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses |
| 2449system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for ReadReq accesses | 2453system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses |
| 2450system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses | 2454system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses |
| 2451system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for ReadReq accesses | 2455system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses |
| 2452system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses | 2456system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses |
| 2453system.l2c.ReadReq_mshr_miss_rate::total 0.265995 # mshr miss rate for ReadReq accesses 2454system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.863636 # mshr miss rate for UpgradeReq accesses | 2457system.l2c.ReadReq_mshr_miss_rate::total 0.266466 # mshr miss rate for ReadReq accesses 2458system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 # mshr miss rate for UpgradeReq accesses |
| 2455system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2456system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2457system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 2459system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2460system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2461system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 2458system.l2c.UpgradeReq_mshr_miss_rate::total 0.960000 # mshr miss rate for UpgradeReq accesses | 2462system.l2c.UpgradeReq_mshr_miss_rate::total 0.959459 # mshr miss rate for UpgradeReq accesses |
| 2459system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2460system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2461system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2462system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2463system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 2463system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2464system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2465system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2466system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2467system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 2464system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses | 2468system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses |
| 2465system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses | 2469system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses |
| 2466system.l2c.demand_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for demand accesses | 2470system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses |
| 2467system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses | 2471system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses |
| 2468system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for demand accesses | 2472system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses |
| 2469system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses | 2473system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses |
| 2470system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for demand accesses | 2474system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses |
| 2471system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses | 2475system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses |
| 2472system.l2c.demand_mshr_miss_rate::total 0.311437 # mshr miss rate for demand accesses 2473system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses | 2476system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses 2477system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses |
| 2474system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses | 2478system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses |
| 2475system.l2c.overall_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for overall accesses | 2479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses |
| 2476system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses | 2480system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses |
| 2477system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for overall accesses | 2481system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses |
| 2478system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses | 2482system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses |
| 2479system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses | 2483system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses |
| 2480system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses | 2484system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses |
| 2481system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses 2482system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average ReadReq mshr miss latency 2483system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency 2484system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency 2485system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency 2486system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency 2487system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency 2488system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average ReadReq mshr miss latency 2489system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency 2490system.l2c.ReadReq_avg_mshr_miss_latency::total 37633.113636 # average ReadReq mshr miss latency 2491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency 2492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency 2493system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency 2494system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency 2495system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency 2496system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40793.723404 # average ReadExReq mshr miss latency 2497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55193.307692 # average ReadExReq mshr miss latency 2498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.833333 # average ReadExReq mshr miss latency 2499system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42501.500000 # average ReadExReq mshr miss latency 2500system.l2c.ReadExReq_avg_mshr_miss_latency::total 42840.908397 # average ReadExReq mshr miss latency 2501system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency 2502system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency 2503system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency 2504system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency 2505system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency 2506system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency 2507system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency 2508system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency 2509system.l2c.demand_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency 2510system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency 2511system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency 2512system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency 2513system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency 2514system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency 2515system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency 2516system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency 2517system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency 2518system.l2c.overall_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency | 2485system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses 2486system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency 2487system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency 2488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency 2489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency 2490system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency 2491system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency 2492system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency 2493system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency 2494system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency 2495system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency 2496system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency 2497system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency 2498system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency 2499system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency 2500system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency 2501system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency 2502system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency 2503system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency 2504system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency 2505system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency 2506system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency 2507system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency 2508system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency 2509system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency 2510system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency 2511system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency 2512system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency 2513system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency 2514system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency 2515system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency 2516system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency 2517system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency 2518system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency 2519system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency 2520system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency 2521system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency 2522system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency |
| 2519system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2520 2521---------- End Simulation Statistics ---------- | 2523system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2524 2525---------- End Simulation Statistics ---------- |