1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000112 # Number of seconds simulated
4sim_ticks 111594500 # Number of ticks simulated
5final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.000114 # Number of seconds simulated
4sim_ticks 113941500 # Number of ticks simulated
5final_tick 113941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 200629 # Simulator instruction rate (inst/s)
8host_op_rate 200629 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20568067 # Simulator tick rate (ticks/s)
10host_mem_usage 235024 # Number of bytes of host memory used
11host_seconds 5.43 # Real time elapsed on the host
12sim_insts 1088531 # Number of instructions simulated
13sim_ops 1088531 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory
| 7host_inst_rate 130117 # Simulator instruction rate (inst/s)
8host_op_rate 130117 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 13474596 # Simulator tick rate (ticks/s)
10host_mem_usage 234988 # Number of bytes of host memory used
11host_seconds 8.46 # Real time elapsed on the host
12sim_insts 1100269 # Number of instructions simulated
13sim_ops 1100269 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory
|
17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
| 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
|
18system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
| 18system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
|
19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
| 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
|
20system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
| 20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
|
21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
| 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
|
22system.physmem.bytes_read::total 42880 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory
28system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory
| 22system.physmem.bytes_read::total 43008 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory
28system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory
|
31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
| 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
|
32system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
| 32system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
|
33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
| 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
|
34system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
| 34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
|
35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
| 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
|
36system.physmem.num_reads::total 670 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s)
| 36system.physmem.num_reads::total 672 # Number of read requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 203894104 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 94364213 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.inst 47182107 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.data 11233835 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu2.inst 2808459 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu2.data 7301993 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu3.inst 3370150 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu3.data 7301993 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::total 377456853 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_inst_read::cpu0.inst 203894104 # Instruction read bandwidth from this memory (bytes/s)
47system.physmem.bw_inst_read::cpu1.inst 47182107 # Instruction read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu2.inst 2808459 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu3.inst 3370150 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::total 257254819 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_total::cpu0.inst 203894104 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu0.data 94364213 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 47182107 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 11233835 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu2.inst 2808459 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu2.data 7301993 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu3.inst 3370150 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu3.data 7301993 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::total 377456853 # Total bandwidth to/from this memory (bytes/s)
|
60system.cpu0.workload.num_syscalls 89 # Number of system calls
| 60system.cpu0.workload.num_syscalls 89 # Number of system calls
|
61system.cpu0.numCycles 223190 # number of cpu cycles simulated
| 61system.cpu0.numCycles 227884 # number of cpu cycles simulated
|
62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
| 62system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
63system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
64system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups
65system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted
66system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect
67system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups
68system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits
| 64system.cpu0.BPredUnit.lookups 88195 # Number of BP lookups
65system.cpu0.BPredUnit.condPredicted 85894 # Number of conditional branches predicted
66system.cpu0.BPredUnit.condIncorrect 1314 # Number of conditional branches incorrect
67system.cpu0.BPredUnit.BTBLookups 85741 # Number of BTB lookups
68system.cpu0.BPredUnit.BTBHits 83416 # Number of BTB hits
|
69system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 69system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
70system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target.
| 70system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target.
|
71system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
| 71system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
|
72system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss
73system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed
74system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered
75system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken
76system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked
77system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing
78system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked
| 72system.cpu0.fetch.icacheStallCycles 17885 # Number of cycles fetch is stalled on an Icache miss
73system.cpu0.fetch.Insts 523742 # Number of instructions fetch has processed
74system.cpu0.fetch.Branches 88195 # Number of branches that fetch encountered
75system.cpu0.fetch.predictedBranches 83933 # Number of branches that fetch has predicted taken
76system.cpu0.fetch.Cycles 172058 # Number of cycles fetch has run and was not squashing or blocked
77system.cpu0.fetch.SquashCycles 4069 # Number of cycles fetch has spent squashing
78system.cpu0.fetch.BlockedCycles 15014 # Number of cycles fetch has spent blocked
|
79system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
| 79system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
80system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps
81system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched
82system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed
83system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total)
84system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total)
85system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total)
| 80system.cpu0.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps
81system.cpu0.fetch.CacheLines 6122 # Number of cache lines fetched
82system.cpu0.fetch.IcacheSquashes 517 # Number of outstanding Icache misses that were squashed
83system.cpu0.fetch.rateDist::samples 209007 # Number of instructions fetched each cycle (Total)
84system.cpu0.fetch.rateDist::mean 2.505859 # Number of instructions fetched each cycle (Total)
85system.cpu0.fetch.rateDist::stdev 2.211450 # Number of instructions fetched each cycle (Total)
|
86system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 86system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
87system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total)
88system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total)
89system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total)
90system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total)
91system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total)
92system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total)
93system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total)
94system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total)
95system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total)
| 87system.cpu0.fetch.rateDist::0 36949 17.68% 17.68% # Number of instructions fetched each cycle (Total)
88system.cpu0.fetch.rateDist::1 85270 40.80% 58.48% # Number of instructions fetched each cycle (Total)
89system.cpu0.fetch.rateDist::2 593 0.28% 58.76% # Number of instructions fetched each cycle (Total)
90system.cpu0.fetch.rateDist::3 1005 0.48% 59.24% # Number of instructions fetched each cycle (Total)
91system.cpu0.fetch.rateDist::4 500 0.24% 59.48% # Number of instructions fetched each cycle (Total)
92system.cpu0.fetch.rateDist::5 81190 38.85% 98.33% # Number of instructions fetched each cycle (Total)
93system.cpu0.fetch.rateDist::6 659 0.32% 98.64% # Number of instructions fetched each cycle (Total)
94system.cpu0.fetch.rateDist::7 361 0.17% 98.81% # Number of instructions fetched each cycle (Total)
95system.cpu0.fetch.rateDist::8 2480 1.19% 100.00% # Number of instructions fetched each cycle (Total)
|
96system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
97system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
98system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 96system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
97system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
98system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
99system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total)
100system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle
101system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle
102system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle
103system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked
104system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running
105system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking
106system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing
107system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode
108system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing
109system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle
110system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking
111system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst
112system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running
113system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking
114system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename
115system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
116system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full
117system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed
118system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made
119system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups
120system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed
121system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing
122system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed
123system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed
124system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer
125system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit.
126system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit.
127system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads.
128system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores.
129system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec)
130system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ
131system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued
132system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued
133system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling
134system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph
135system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed
136system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle
137system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle
138system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle
| 99system.cpu0.fetch.rateDist::total 209007 # Number of instructions fetched each cycle (Total)
100system.cpu0.fetch.branchRate 0.387017 # Number of branch fetches per cycle
101system.cpu0.fetch.rate 2.298283 # Number of inst fetches per cycle
102system.cpu0.decode.IdleCycles 18552 # Number of cycles decode is idle
103system.cpu0.decode.BlockedCycles 16516 # Number of cycles decode is blocked
104system.cpu0.decode.RunCycles 170985 # Number of cycles decode is running
105system.cpu0.decode.UnblockCycles 348 # Number of cycles decode is unblocking
106system.cpu0.decode.SquashCycles 2606 # Number of cycles decode is squashing
107system.cpu0.decode.DecodedInsts 520718 # Number of instructions handled by decode
108system.cpu0.rename.SquashCycles 2606 # Number of cycles rename is squashing
109system.cpu0.rename.IdleCycles 19281 # Number of cycles rename is idle
110system.cpu0.rename.BlockCycles 2206 # Number of cycles rename is blocking
111system.cpu0.rename.serializeStallCycles 13583 # count of cycles rename stalled for serializing inst
112system.cpu0.rename.RunCycles 170639 # Number of cycles rename is running
113system.cpu0.rename.UnblockCycles 692 # Number of cycles rename is unblocking
114system.cpu0.rename.RenamedInsts 517471 # Number of instructions processed by rename
115system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
116system.cpu0.rename.LSQFullEvents 300 # Number of times rename has blocked due to LSQ full
117system.cpu0.rename.RenamedOperands 353567 # Number of destination operands rename has renamed
118system.cpu0.rename.RenameLookups 1032190 # Number of register rename lookups that rename has made
119system.cpu0.rename.int_rename_lookups 1032190 # Number of integer rename lookups
120system.cpu0.rename.CommittedMaps 339600 # Number of HB maps that are committed
121system.cpu0.rename.UndoneMaps 13967 # Number of HB maps that are undone due to squashing
122system.cpu0.rename.serializingInsts 909 # count of serializing insts renamed
123system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed
124system.cpu0.rename.skidInsts 4082 # count of insts added to the skid buffer
125system.cpu0.memDep0.insertedLoads 165924 # Number of loads inserted to the mem dependence unit.
126system.cpu0.memDep0.insertedStores 83735 # Number of stores inserted to the mem dependence unit.
127system.cpu0.memDep0.conflictingLoads 81055 # Number of conflicting loads.
128system.cpu0.memDep0.conflictingStores 80764 # Number of conflicting stores.
129system.cpu0.iq.iqInstsAdded 432543 # Number of instructions added to the IQ (excludes non-spec)
130system.cpu0.iq.iqNonSpecInstsAdded 950 # Number of non-speculative instructions added to the IQ
131system.cpu0.iq.iqInstsIssued 429278 # Number of instructions issued
132system.cpu0.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued
133system.cpu0.iq.iqSquashedInstsExamined 11501 # Number of squashed instructions iterated over during squash; mainly for profiling
134system.cpu0.iq.iqSquashedOperandsExamined 11387 # Number of squashed operands that are examined and possibly removed from graph
135system.cpu0.iq.iqSquashedNonSpecRemoved 391 # Number of squashed non-spec instructions that were removed
136system.cpu0.iq.issued_per_cycle::samples 209007 # Number of insts issued each cycle
137system.cpu0.iq.issued_per_cycle::mean 2.053893 # Number of insts issued each cycle
138system.cpu0.iq.issued_per_cycle::stdev 1.097042 # Number of insts issued each cycle
|
139system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 139system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
140system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle
141system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle
142system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle
143system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle
144system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle
145system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle
146system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle
147system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle
148system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
| 140system.cpu0.iq.issued_per_cycle::0 36203 17.32% 17.32% # Number of insts issued each cycle
141system.cpu0.iq.issued_per_cycle::1 5360 2.56% 19.89% # Number of insts issued each cycle
142system.cpu0.iq.issued_per_cycle::2 82686 39.56% 59.45% # Number of insts issued each cycle
143system.cpu0.iq.issued_per_cycle::3 82056 39.26% 98.71% # Number of insts issued each cycle
144system.cpu0.iq.issued_per_cycle::4 1635 0.78% 99.49% # Number of insts issued each cycle
145system.cpu0.iq.issued_per_cycle::5 680 0.33% 99.81% # Number of insts issued each cycle
146system.cpu0.iq.issued_per_cycle::6 282 0.13% 99.95% # Number of insts issued each cycle
147system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle
148system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle
|
149system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
150system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
151system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 149system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
150system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
151system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
152system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle
| 152system.cpu0.iq.issued_per_cycle::total 209007 # Number of insts issued each cycle
|
153system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 153system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
154system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available
155system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available
156system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available
157system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available
158system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available
159system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available
160system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available
161system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available
162system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available
163system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available
164system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available
165system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available
166system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available
167system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available
168system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available
169system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available
170system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available
171system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available
172system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available
173system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available
174system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available
175system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available
176system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available
177system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available
178system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available
179system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available
180system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available
181system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available
182system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available
183system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available
184system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available
| 154system.cpu0.iq.fu_full::IntAlu 43 16.23% 16.23% # attempts to use FU when none available
155system.cpu0.iq.fu_full::IntMult 0 0.00% 16.23% # attempts to use FU when none available
156system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.23% # attempts to use FU when none available
157system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.23% # attempts to use FU when none available
158system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.23% # attempts to use FU when none available
159system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.23% # attempts to use FU when none available
160system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.23% # attempts to use FU when none available
161system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.23% # attempts to use FU when none available
162system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.23% # attempts to use FU when none available
163system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.23% # attempts to use FU when none available
164system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.23% # attempts to use FU when none available
165system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.23% # attempts to use FU when none available
166system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.23% # attempts to use FU when none available
167system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.23% # attempts to use FU when none available
168system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.23% # attempts to use FU when none available
169system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.23% # attempts to use FU when none available
170system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.23% # attempts to use FU when none available
171system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.23% # attempts to use FU when none available
172system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.23% # attempts to use FU when none available
173system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.23% # attempts to use FU when none available
174system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.23% # attempts to use FU when none available
175system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.23% # attempts to use FU when none available
176system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.23% # attempts to use FU when none available
177system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.23% # attempts to use FU when none available
178system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.23% # attempts to use FU when none available
179system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.23% # attempts to use FU when none available
180system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.23% # attempts to use FU when none available
181system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.23% # attempts to use FU when none available
182system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.23% # attempts to use FU when none available
183system.cpu0.iq.fu_full::MemRead 110 41.51% 57.74% # attempts to use FU when none available
184system.cpu0.iq.fu_full::MemWrite 112 42.26% 100.00% # attempts to use FU when none available
|
185system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
186system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
187system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
| 185system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
186system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
187system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
188system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued
189system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
190system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
191system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
192system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
193system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
194system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
195system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
196system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
197system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
198system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
199system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
200system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
201system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
202system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
203system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
204system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
205system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
206system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
207system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
208system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
209system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
210system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
211system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
212system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
213system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
214system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
215system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
216system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
217system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued
218system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued
| 188system.cpu0.iq.FU_type_0::IntAlu 180966 42.16% 42.16% # Type of FU issued
189system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.16% # Type of FU issued
190system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued
191system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued
192system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued
193system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued
194system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued
195system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued
196system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued
197system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued
198system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued
199system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued
200system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued
201system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued
202system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.16% # Type of FU issued
203system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued
204system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued
205system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued
206system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.16% # Type of FU issued
207system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued
208system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued
209system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued
210system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued
211system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued
212system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued
213system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.16% # Type of FU issued
214system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued
215system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.16% # Type of FU issued
216system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued
217system.cpu0.iq.FU_type_0::MemRead 165240 38.49% 80.65% # Type of FU issued
218system.cpu0.iq.FU_type_0::MemWrite 83072 19.35% 100.00% # Type of FU issued
|
219system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
220system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 219system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
220system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
221system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued
222system.cpu0.iq.rate 1.905816 # Inst issue rate
223system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested
224system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst)
225system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads
226system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes
227system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses
| 221system.cpu0.iq.FU_type_0::total 429278 # Type of FU issued
222system.cpu0.iq.rate 1.883757 # Inst issue rate
223system.cpu0.iq.fu_busy_cnt 265 # FU busy when requested
224system.cpu0.iq.fu_busy_rate 0.000617 # FU busy rate (busy events/executed inst)
225system.cpu0.iq.int_inst_queue_reads 1068049 # Number of integer instruction queue reads
226system.cpu0.iq.int_inst_queue_writes 445050 # Number of integer instruction queue writes
227system.cpu0.iq.int_inst_queue_wakeup_accesses 427325 # Number of integer instruction queue wakeup accesses
|
228system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
229system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
230system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
| 228system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
229system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
230system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
231system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses
| 231system.cpu0.iq.int_alu_accesses 429543 # Number of integer alu accesses
|
232system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
| 232system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
233system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores
| 233system.cpu0.iew.lsq.thread0.forwLoads 80408 # Number of loads that had data forwarded from stores
|
234system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 234system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
235system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed
| 235system.cpu0.iew.lsq.thread0.squashedLoads 2540 # Number of loads squashed
|
236system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
| 236system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
237system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations
238system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed
| 237system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations
238system.cpu0.iew.lsq.thread0.squashedStores 1537 # Number of stores squashed
|
239system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
240system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
241system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
| 239system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
240system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
241system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
242system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
| 242system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
243system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 243system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
244system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing
245system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking
246system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking
247system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ
248system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch
249system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions
250system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions
251system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions
252system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall
| 244system.cpu0.iew.iewSquashCycles 2606 # Number of cycles IEW is squashing
245system.cpu0.iew.iewBlockCycles 1701 # Number of cycles IEW is blocking
246system.cpu0.iew.iewUnblockCycles 86 # Number of cycles IEW is unblocking
247system.cpu0.iew.iewDispatchedInsts 515038 # Number of instructions dispatched to IQ
248system.cpu0.iew.iewDispSquashedInsts 368 # Number of squashed instructions skipped by dispatch
249system.cpu0.iew.iewDispLoadInsts 165924 # Number of dispatched load instructions
250system.cpu0.iew.iewDispStoreInsts 83735 # Number of dispatched store instructions
251system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions
252system.cpu0.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
|
253system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
| 253system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
254system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations
255system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly
256system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly
257system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute
258system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions
259system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed
260system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute
| 254system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations
255system.cpu0.iew.predictedTakenIncorrect 370 # Number of branches that were predicted taken incorrectly
256system.cpu0.iew.predictedNotTakenIncorrect 1149 # Number of branches that were predicted not taken incorrectly
257system.cpu0.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute
258system.cpu0.iew.iewExecutedInsts 428170 # Number of executed instructions
259system.cpu0.iew.iewExecLoadInsts 164921 # Number of load instructions executed
260system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute
|
261system.cpu0.iew.exec_swp 0 # number of swp insts executed
| 261system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
262system.cpu0.iew.exec_nop 80672 # number of nop insts executed
263system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed
264system.cpu0.iew.exec_branches 84313 # Number of branches executed
265system.cpu0.iew.exec_stores 82132 # Number of stores executed
266system.cpu0.iew.exec_rate 1.900793 # Inst execution rate
267system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit
268system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back
269system.cpu0.iew.wb_producers 250898 # num instructions producing a value
270system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value
| 262system.cpu0.iew.exec_nop 81545 # number of nop insts executed
263system.cpu0.iew.exec_refs 247840 # number of memory reference insts executed
264system.cpu0.iew.exec_branches 85100 # Number of branches executed
265system.cpu0.iew.exec_stores 82919 # Number of stores executed
266system.cpu0.iew.exec_rate 1.878895 # Inst execution rate
267system.cpu0.iew.wb_sent 427676 # cumulative count of insts sent to commit
268system.cpu0.iew.wb_count 427325 # cumulative count of insts written-back
269system.cpu0.iew.wb_producers 253224 # num instructions producing a value
270system.cpu0.iew.wb_consumers 255650 # num instructions consuming a value
|
271system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 271system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
272system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle
273system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back
| 272system.cpu0.iew.wb_rate 1.875186 # insts written-back per cycle
273system.cpu0.iew.wb_fanout 0.990510 # average fanout of values written-back
|
274system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
| 274system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
275system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions
276system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions
277system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit
| 275system.cpu0.commit.commitCommittedInsts 501745 # The number of committed instructions
276system.cpu0.commit.commitCommittedOps 501745 # The number of committed instructions
277system.cpu0.commit.commitSquashedInsts 13260 # The number of squashed insts skipped by commit
|
278system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
| 278system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
279system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted
280system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle
281system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle
282system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle
| 279system.cpu0.commit.branchMispredicts 1314 # The number of times a branch was mispredicted
280system.cpu0.commit.committed_per_cycle::samples 206418 # Number of insts commited each cycle
281system.cpu0.commit.committed_per_cycle::mean 2.430723 # Number of insts commited each cycle
282system.cpu0.commit.committed_per_cycle::stdev 2.136815 # Number of insts commited each cycle
|
283system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 283system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
284system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle
285system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle
286system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle
287system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle
288system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle
289system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle
290system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle
291system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle
292system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle
| 284system.cpu0.commit.committed_per_cycle::0 36760 17.81% 17.81% # Number of insts commited each cycle
285system.cpu0.commit.committed_per_cycle::1 84779 41.07% 58.88% # Number of insts commited each cycle
286system.cpu0.commit.committed_per_cycle::2 2446 1.18% 60.07% # Number of insts commited each cycle
287system.cpu0.commit.committed_per_cycle::3 715 0.35% 60.41% # Number of insts commited each cycle
288system.cpu0.commit.committed_per_cycle::4 578 0.28% 60.69% # Number of insts commited each cycle
289system.cpu0.commit.committed_per_cycle::5 80055 38.78% 99.47% # Number of insts commited each cycle
290system.cpu0.commit.committed_per_cycle::6 554 0.27% 99.74% # Number of insts commited each cycle
291system.cpu0.commit.committed_per_cycle::7 230 0.11% 99.85% # Number of insts commited each cycle
292system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle
|
293system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
294system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
295system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 293system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
294system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
295system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
296system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle
297system.cpu0.commit.committedInsts 496825 # Number of instructions committed
298system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed
| 296system.cpu0.commit.committed_per_cycle::total 206418 # Number of insts commited each cycle
297system.cpu0.commit.committedInsts 501745 # Number of instructions committed
298system.cpu0.commit.committedOps 501745 # Number of ops (including micro ops) committed
|
299system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
| 299system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
300system.cpu0.commit.refs 243122 # Number of memory references committed
301system.cpu0.commit.loads 161744 # Number of loads committed
| 300system.cpu0.commit.refs 245582 # Number of memory references committed
301system.cpu0.commit.loads 163384 # Number of loads committed
|
302system.cpu0.commit.membars 84 # Number of memory barriers committed
| 302system.cpu0.commit.membars 84 # Number of memory barriers committed
|
303system.cpu0.commit.branches 83266 # Number of branches committed
| 303system.cpu0.commit.branches 84086 # Number of branches committed
|
304system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
| 304system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
305system.cpu0.commit.int_insts 334650 # Number of committed integer instructions.
| 305system.cpu0.commit.int_insts 337930 # Number of committed integer instructions.
|
306system.cpu0.commit.function_calls 223 # Number of function calls committed.
| 306system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
307system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached
| 307system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached
|
308system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
| 308system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
309system.cpu0.rob.rob_reads 710993 # The number of ROB reads
310system.cpu0.rob.rob_writes 1022511 # The number of ROB writes
311system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself
312system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling
313system.cpu0.committedInsts 416744 # Number of Instructions Simulated
314system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated
315system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated
316system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction
317system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads
318system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle
319system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads
320system.cpu0.int_regfile_reads 758967 # number of integer regfile reads
321system.cpu0.int_regfile_writes 341941 # number of integer regfile writes
| 309system.cpu0.rob.rob_reads 719961 # The number of ROB reads
310system.cpu0.rob.rob_writes 1032633 # The number of ROB writes
311system.cpu0.timesIdled 343 # Number of times that the entire CPU went into an idle state and unscheduled itself
312system.cpu0.idleCycles 18877 # Total number of cycles that the CPU has spent unscheduled due to idling
313system.cpu0.committedInsts 420844 # Number of Instructions Simulated
314system.cpu0.committedOps 420844 # Number of Ops (including micro ops) Simulated
315system.cpu0.committedInsts_total 420844 # Number of Instructions Simulated
316system.cpu0.cpi 0.541493 # CPI: Cycles Per Instruction
317system.cpu0.cpi_total 0.541493 # CPI: Total CPI of All Threads
318system.cpu0.ipc 1.846747 # IPC: Instructions Per Cycle
319system.cpu0.ipc_total 1.846747 # IPC: Total IPC of All Threads
320system.cpu0.int_regfile_reads 766075 # number of integer regfile reads
321system.cpu0.int_regfile_writes 345063 # number of integer regfile writes
|
322system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
| 322system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
323system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads
| 323system.cpu0.misc_regfile_reads 249668 # number of misc regfile reads
|
324system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
| 324system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
325system.cpu0.icache.replacements 307 # number of replacements
326system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use
327system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks.
328system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks.
329system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks.
| 325system.cpu0.icache.replacements 308 # number of replacements
326system.cpu0.icache.tagsinuse 248.197747 # Cycle average of tags in use
327system.cpu0.icache.total_refs 5361 # Total number of references to valid blocks.
328system.cpu0.icache.sampled_refs 601 # Sample count of references to valid blocks.
329system.cpu0.icache.avg_refs 8.920133 # Average number of references to valid blocks.
|
330system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 330system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
331system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor
332system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy
333system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy
334system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits
335system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits
336system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits
337system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits
338system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits
339system.cpu0.icache.overall_hits::total 5393 # number of overall hits
340system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses
341system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses
342system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses
343system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses
344system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses
345system.cpu0.icache.overall_misses::total 759 # number of overall misses
346system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles
347system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles
348system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles
349system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles
350system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles
351system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles
352system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses)
353system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses)
354system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses
355system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses
356system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses
357system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses
358system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses
359system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses
360system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses
361system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses
362system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses
363system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses
364system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency
365system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency
366system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency
367system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency
368system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency
369system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency
370system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
| 331system.cpu0.icache.occ_blocks::cpu0.inst 248.197747 # Average occupied blocks per requestor
332system.cpu0.icache.occ_percent::cpu0.inst 0.484761 # Average percentage of cache occupancy
333system.cpu0.icache.occ_percent::total 0.484761 # Average percentage of cache occupancy
334system.cpu0.icache.ReadReq_hits::cpu0.inst 5361 # number of ReadReq hits
335system.cpu0.icache.ReadReq_hits::total 5361 # number of ReadReq hits
336system.cpu0.icache.demand_hits::cpu0.inst 5361 # number of demand (read+write) hits
337system.cpu0.icache.demand_hits::total 5361 # number of demand (read+write) hits
338system.cpu0.icache.overall_hits::cpu0.inst 5361 # number of overall hits
339system.cpu0.icache.overall_hits::total 5361 # number of overall hits
340system.cpu0.icache.ReadReq_misses::cpu0.inst 761 # number of ReadReq misses
341system.cpu0.icache.ReadReq_misses::total 761 # number of ReadReq misses
342system.cpu0.icache.demand_misses::cpu0.inst 761 # number of demand (read+write) misses
343system.cpu0.icache.demand_misses::total 761 # number of demand (read+write) misses
344system.cpu0.icache.overall_misses::cpu0.inst 761 # number of overall misses
345system.cpu0.icache.overall_misses::total 761 # number of overall misses
346system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29540500 # number of ReadReq miss cycles
347system.cpu0.icache.ReadReq_miss_latency::total 29540500 # number of ReadReq miss cycles
348system.cpu0.icache.demand_miss_latency::cpu0.inst 29540500 # number of demand (read+write) miss cycles
349system.cpu0.icache.demand_miss_latency::total 29540500 # number of demand (read+write) miss cycles
350system.cpu0.icache.overall_miss_latency::cpu0.inst 29540500 # number of overall miss cycles
351system.cpu0.icache.overall_miss_latency::total 29540500 # number of overall miss cycles
352system.cpu0.icache.ReadReq_accesses::cpu0.inst 6122 # number of ReadReq accesses(hits+misses)
353system.cpu0.icache.ReadReq_accesses::total 6122 # number of ReadReq accesses(hits+misses)
354system.cpu0.icache.demand_accesses::cpu0.inst 6122 # number of demand (read+write) accesses
355system.cpu0.icache.demand_accesses::total 6122 # number of demand (read+write) accesses
356system.cpu0.icache.overall_accesses::cpu0.inst 6122 # number of overall (read+write) accesses
357system.cpu0.icache.overall_accesses::total 6122 # number of overall (read+write) accesses
358system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.124306 # miss rate for ReadReq accesses
359system.cpu0.icache.ReadReq_miss_rate::total 0.124306 # miss rate for ReadReq accesses
360system.cpu0.icache.demand_miss_rate::cpu0.inst 0.124306 # miss rate for demand accesses
361system.cpu0.icache.demand_miss_rate::total 0.124306 # miss rate for demand accesses
362system.cpu0.icache.overall_miss_rate::cpu0.inst 0.124306 # miss rate for overall accesses
363system.cpu0.icache.overall_miss_rate::total 0.124306 # miss rate for overall accesses
364system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628 # average ReadReq miss latency
365system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628 # average ReadReq miss latency
366system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency
367system.cpu0.icache.demand_avg_miss_latency::total 38818.002628 # average overall miss latency
368system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency
369system.cpu0.icache.overall_avg_miss_latency::total 38818.002628 # average overall miss latency
370system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked
|
371system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
373system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
| 371system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
373system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
374system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked
| 374system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked
|
375system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376system.cpu0.icache.fast_writes 0 # number of fast writes performed
377system.cpu0.icache.cache_copies 0 # number of cache copies performed
| 375system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376system.cpu0.icache.fast_writes 0 # number of fast writes performed
377system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
378system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits
379system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits
380system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits
381system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits
382system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits
383system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits
384system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses
385system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
386system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses
387system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
388system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses
389system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
390system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles
391system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles
392system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles
393system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles
394system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles
395system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles
396system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses
397system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses
398system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses
399system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses
400system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses
401system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses
402system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency
403system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency
404system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency
405system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency
406system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency
407system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency
| 378system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 159 # number of ReadReq MSHR hits
379system.cpu0.icache.ReadReq_mshr_hits::total 159 # number of ReadReq MSHR hits
380system.cpu0.icache.demand_mshr_hits::cpu0.inst 159 # number of demand (read+write) MSHR hits
381system.cpu0.icache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits
382system.cpu0.icache.overall_mshr_hits::cpu0.inst 159 # number of overall MSHR hits
383system.cpu0.icache.overall_mshr_hits::total 159 # number of overall MSHR hits
384system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 602 # number of ReadReq MSHR misses
385system.cpu0.icache.ReadReq_mshr_misses::total 602 # number of ReadReq MSHR misses
386system.cpu0.icache.demand_mshr_misses::cpu0.inst 602 # number of demand (read+write) MSHR misses
387system.cpu0.icache.demand_mshr_misses::total 602 # number of demand (read+write) MSHR misses
388system.cpu0.icache.overall_mshr_misses::cpu0.inst 602 # number of overall MSHR misses
389system.cpu0.icache.overall_mshr_misses::total 602 # number of overall MSHR misses
390system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22436000 # number of ReadReq MSHR miss cycles
391system.cpu0.icache.ReadReq_mshr_miss_latency::total 22436000 # number of ReadReq MSHR miss cycles
392system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22436000 # number of demand (read+write) MSHR miss cycles
393system.cpu0.icache.demand_mshr_miss_latency::total 22436000 # number of demand (read+write) MSHR miss cycles
394system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22436000 # number of overall MSHR miss cycles
395system.cpu0.icache.overall_mshr_miss_latency::total 22436000 # number of overall MSHR miss cycles
396system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for ReadReq accesses
397system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098334 # mshr miss rate for ReadReq accesses
398system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for demand accesses
399system.cpu0.icache.demand_mshr_miss_rate::total 0.098334 # mshr miss rate for demand accesses
400system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for overall accesses
401system.cpu0.icache.overall_mshr_miss_rate::total 0.098334 # mshr miss rate for overall accesses
402system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average ReadReq mshr miss latency
403system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990 # average ReadReq mshr miss latency
404system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency
405system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency
406system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency
407system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency
|
408system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu0.dcache.replacements 2 # number of replacements
| 408system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu0.dcache.replacements 2 # number of replacements
|
410system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use
411system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks.
412system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks.
413system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks.
| 410system.cpu0.dcache.tagsinuse 144.386808 # Cycle average of tags in use
411system.cpu0.dcache.total_refs 165433 # Total number of references to valid blocks.
412system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
413system.cpu0.dcache.avg_refs 973.135294 # Average number of references to valid blocks.
|
414system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 414system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
415system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor
416system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy
417system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy
418system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits
419system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits
420system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits
421system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits
422system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
423system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
424system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits
425system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits
426system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits
427system.cpu0.dcache.overall_hits::total 163940 # number of overall hits
428system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses
429system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses
430system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses
431system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses
432system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
433system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
434system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses
435system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses
436system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses
437system.cpu0.dcache.overall_misses::total 1046 # number of overall misses
438system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles
439system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles
440system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles
441system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles
442system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles
443system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles
444system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles
445system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles
446system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles
447system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles
448system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses)
449system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses)
450system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses)
451system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses)
| 415system.cpu0.dcache.occ_blocks::cpu0.data 144.386808 # Average occupied blocks per requestor
416system.cpu0.dcache.occ_percent::cpu0.data 0.282005 # Average percentage of cache occupancy
417system.cpu0.dcache.occ_percent::total 0.282005 # Average percentage of cache occupancy
418system.cpu0.dcache.ReadReq_hits::cpu0.data 83919 # number of ReadReq hits
419system.cpu0.dcache.ReadReq_hits::total 83919 # number of ReadReq hits
420system.cpu0.dcache.WriteReq_hits::cpu0.data 81593 # number of WriteReq hits
421system.cpu0.dcache.WriteReq_hits::total 81593 # number of WriteReq hits
422system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits
423system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits
424system.cpu0.dcache.demand_hits::cpu0.data 165512 # number of demand (read+write) hits
425system.cpu0.dcache.demand_hits::total 165512 # number of demand (read+write) hits
426system.cpu0.dcache.overall_hits::cpu0.data 165512 # number of overall hits
427system.cpu0.dcache.overall_hits::total 165512 # number of overall hits
428system.cpu0.dcache.ReadReq_misses::cpu0.data 525 # number of ReadReq misses
429system.cpu0.dcache.ReadReq_misses::total 525 # number of ReadReq misses
430system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses
431system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses
432system.cpu0.dcache.SwapReq_misses::cpu0.data 24 # number of SwapReq misses
433system.cpu0.dcache.SwapReq_misses::total 24 # number of SwapReq misses
434system.cpu0.dcache.demand_misses::cpu0.data 1088 # number of demand (read+write) misses
435system.cpu0.dcache.demand_misses::total 1088 # number of demand (read+write) misses
436system.cpu0.dcache.overall_misses::cpu0.data 1088 # number of overall misses
437system.cpu0.dcache.overall_misses::total 1088 # number of overall misses
438system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16325500 # number of ReadReq miss cycles
439system.cpu0.dcache.ReadReq_miss_latency::total 16325500 # number of ReadReq miss cycles
440system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28838494 # number of WriteReq miss cycles
441system.cpu0.dcache.WriteReq_miss_latency::total 28838494 # number of WriteReq miss cycles
442system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 480000 # number of SwapReq miss cycles
443system.cpu0.dcache.SwapReq_miss_latency::total 480000 # number of SwapReq miss cycles
444system.cpu0.dcache.demand_miss_latency::cpu0.data 45163994 # number of demand (read+write) miss cycles
445system.cpu0.dcache.demand_miss_latency::total 45163994 # number of demand (read+write) miss cycles
446system.cpu0.dcache.overall_miss_latency::cpu0.data 45163994 # number of overall miss cycles
447system.cpu0.dcache.overall_miss_latency::total 45163994 # number of overall miss cycles
448system.cpu0.dcache.ReadReq_accesses::cpu0.data 84444 # number of ReadReq accesses(hits+misses)
449system.cpu0.dcache.ReadReq_accesses::total 84444 # number of ReadReq accesses(hits+misses)
450system.cpu0.dcache.WriteReq_accesses::cpu0.data 82156 # number of WriteReq accesses(hits+misses)
451system.cpu0.dcache.WriteReq_accesses::total 82156 # number of WriteReq accesses(hits+misses)
|
452system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
453system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
| 452system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
453system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
454system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses
455system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses
456system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses
457system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses
458system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses
459system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses
460system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses
461system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses
462system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
463system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
464system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses
465system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses
466system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses
467system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses
468system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency
469system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency
470system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency
471system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency
472system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency
473system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency
474system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency
475system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency
476system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency
477system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency
478system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked
| 454system.cpu0.dcache.demand_accesses::cpu0.data 166600 # number of demand (read+write) accesses
455system.cpu0.dcache.demand_accesses::total 166600 # number of demand (read+write) accesses
456system.cpu0.dcache.overall_accesses::cpu0.data 166600 # number of overall (read+write) accesses
457system.cpu0.dcache.overall_accesses::total 166600 # number of overall (read+write) accesses
458system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006217 # miss rate for ReadReq accesses
459system.cpu0.dcache.ReadReq_miss_rate::total 0.006217 # miss rate for ReadReq accesses
460system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006853 # miss rate for WriteReq accesses
461system.cpu0.dcache.WriteReq_miss_rate::total 0.006853 # miss rate for WriteReq accesses
462system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses
463system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses
464system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006531 # miss rate for demand accesses
465system.cpu0.dcache.demand_miss_rate::total 0.006531 # miss rate for demand accesses
466system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006531 # miss rate for overall accesses
467system.cpu0.dcache.overall_miss_rate::total 0.006531 # miss rate for overall accesses
468system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476 # average ReadReq miss latency
469system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476 # average ReadReq miss latency
470system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309 # average WriteReq miss latency
471system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309 # average WriteReq miss latency
472system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20000 # average SwapReq miss latency
473system.cpu0.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency
474system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency
475system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897 # average overall miss latency
476system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency
477system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897 # average overall miss latency
478system.cpu0.dcache.blocked_cycles::no_mshrs 119500 # number of cycles access was blocked
|
479system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
| 479system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
480system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
| 480system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked
|
481system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
| 481system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
482system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked
| 482system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6638.888889 # average number of cycles each access was blocked
|
483system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
484system.cpu0.dcache.fast_writes 0 # number of fast writes performed
485system.cpu0.dcache.cache_copies 0 # number of cache copies performed
486system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
487system.cpu0.dcache.writebacks::total 1 # number of writebacks
| 483system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
484system.cpu0.dcache.fast_writes 0 # number of fast writes performed
485system.cpu0.dcache.cache_copies 0 # number of cache copies performed
486system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
487system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
488system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits
489system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits
490system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits
491system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits
492system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits
493system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits
494system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits
495system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits
| 488system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 345 # number of ReadReq MSHR hits
489system.cpu0.dcache.ReadReq_mshr_hits::total 345 # number of ReadReq MSHR hits
490system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 392 # number of WriteReq MSHR hits
491system.cpu0.dcache.WriteReq_mshr_hits::total 392 # number of WriteReq MSHR hits
492system.cpu0.dcache.demand_mshr_hits::cpu0.data 737 # number of demand (read+write) MSHR hits
493system.cpu0.dcache.demand_mshr_hits::total 737 # number of demand (read+write) MSHR hits
494system.cpu0.dcache.overall_mshr_hits::cpu0.data 737 # number of overall MSHR hits
495system.cpu0.dcache.overall_mshr_hits::total 737 # number of overall MSHR hits
|
496system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses
497system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses
| 496system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses
497system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses
|
498system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
499system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
500system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
501system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
502system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses
503system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses
504system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses
505system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses
506system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles
507system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles
508system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles
509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles
510system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles
511system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles
512system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles
513system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles
514system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles
515system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles
516system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses
517system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses
518system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses
519system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses
520system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
521system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
522system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for demand accesses
523system.cpu0.dcache.demand_mshr_miss_rate::total 0.002152 # mshr miss rate for demand accesses
524system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for overall accesses
525system.cpu0.dcache.overall_mshr_miss_rate::total 0.002152 # mshr miss rate for overall accesses
526system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556 # average ReadReq mshr miss latency
527system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556 # average ReadReq mshr miss latency
528system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35860 # average WriteReq mshr miss latency
529system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35860 # average WriteReq mshr miss latency
530system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095 # average SwapReq mshr miss latency
531system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency
532system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency
533system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency
534system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency
535system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency
| 498system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses
499system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses
500system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses
501system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses
502system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses
503system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
504system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses
505system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
506system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5693511 # number of ReadReq MSHR miss cycles
507system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5693511 # number of ReadReq MSHR miss cycles
508system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6731000 # number of WriteReq MSHR miss cycles
509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6731000 # number of WriteReq MSHR miss cycles
510system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 405000 # number of SwapReq MSHR miss cycles
511system.cpu0.dcache.SwapReq_mshr_miss_latency::total 405000 # number of SwapReq MSHR miss cycles
512system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12424511 # number of demand (read+write) MSHR miss cycles
513system.cpu0.dcache.demand_mshr_miss_latency::total 12424511 # number of demand (read+write) MSHR miss cycles
514system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12424511 # number of overall MSHR miss cycles
515system.cpu0.dcache.overall_mshr_miss_latency::total 12424511 # number of overall MSHR miss cycles
516system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002132 # mshr miss rate for ReadReq accesses
517system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002132 # mshr miss rate for ReadReq accesses
518system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002081 # mshr miss rate for WriteReq accesses
519system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002081 # mshr miss rate for WriteReq accesses
520system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses
521system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses
522system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for demand accesses
523system.cpu0.dcache.demand_mshr_miss_rate::total 0.002107 # mshr miss rate for demand accesses
524system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for overall accesses
525system.cpu0.dcache.overall_mshr_miss_rate::total 0.002107 # mshr miss rate for overall accesses
526system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667 # average ReadReq mshr miss latency
527system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667 # average ReadReq mshr miss latency
528system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099 # average WriteReq mshr miss latency
529system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099 # average WriteReq mshr miss latency
530system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16875 # average SwapReq mshr miss latency
531system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16875 # average SwapReq mshr miss latency
532system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency
533system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency
534system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency
535system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency
|
536system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 536system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
537system.cpu1.numCycles 187839 # number of cpu cycles simulated
| 537system.cpu1.numCycles 191339 # number of cpu cycles simulated
|
538system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
539system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
| 538system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
539system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
540system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups
541system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted
542system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect
543system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups
544system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits
| 540system.cpu1.BPredUnit.lookups 49631 # Number of BP lookups
541system.cpu1.BPredUnit.condPredicted 46572 # Number of conditional branches predicted
542system.cpu1.BPredUnit.condIncorrect 1528 # Number of conditional branches incorrect
543system.cpu1.BPredUnit.BTBLookups 42950 # Number of BTB lookups
544system.cpu1.BPredUnit.BTBHits 41997 # Number of BTB hits
|
545system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 545system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
546system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target.
| 546system.cpu1.BPredUnit.usedRAS 805 # Number of times the RAS was used to get a target.
|
547system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
| 547system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
548system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss
549system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed
550system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered
551system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken
552system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked
553system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing
554system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked
| 548system.cpu1.fetch.icacheStallCycles 33375 # Number of cycles fetch is stalled on an Icache miss
549system.cpu1.fetch.Insts 271825 # Number of instructions fetch has processed
550system.cpu1.fetch.Branches 49631 # Number of branches that fetch encountered
551system.cpu1.fetch.predictedBranches 42802 # Number of branches that fetch has predicted taken
552system.cpu1.fetch.Cycles 98758 # Number of cycles fetch has run and was not squashing or blocked
553system.cpu1.fetch.SquashCycles 4453 # Number of cycles fetch has spent squashing
554system.cpu1.fetch.BlockedCycles 42292 # Number of cycles fetch has spent blocked
|
555system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
| 555system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
556system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from
557system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps
558system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched
559system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed
560system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total)
561system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total)
562system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total)
| 556system.cpu1.fetch.NoActiveThreadStallCycles 6725 # Number of stall cycles due to no active thread to fetch from
557system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
558system.cpu1.fetch.CacheLines 23889 # Number of cache lines fetched
559system.cpu1.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
560system.cpu1.fetch.rateDist::samples 185079 # Number of instructions fetched each cycle (Total)
561system.cpu1.fetch.rateDist::mean 1.468697 # Number of instructions fetched each cycle (Total)
562system.cpu1.fetch.rateDist::stdev 2.066601 # Number of instructions fetched each cycle (Total)
|
563system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 563system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
564system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total)
565system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total)
566system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total)
567system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total)
568system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total)
569system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total)
570system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total)
571system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total)
572system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total)
| 564system.cpu1.fetch.rateDist::0 86321 46.64% 46.64% # Number of instructions fetched each cycle (Total)
565system.cpu1.fetch.rateDist::1 51121 27.62% 74.26% # Number of instructions fetched each cycle (Total)
566system.cpu1.fetch.rateDist::2 7925 4.28% 78.54% # Number of instructions fetched each cycle (Total)
567system.cpu1.fetch.rateDist::3 3336 1.80% 80.35% # Number of instructions fetched each cycle (Total)
568system.cpu1.fetch.rateDist::4 734 0.40% 80.74% # Number of instructions fetched each cycle (Total)
569system.cpu1.fetch.rateDist::5 30013 16.22% 96.96% # Number of instructions fetched each cycle (Total)
570system.cpu1.fetch.rateDist::6 1151 0.62% 97.58% # Number of instructions fetched each cycle (Total)
571system.cpu1.fetch.rateDist::7 885 0.48% 98.06% # Number of instructions fetched each cycle (Total)
572system.cpu1.fetch.rateDist::8 3593 1.94% 100.00% # Number of instructions fetched each cycle (Total)
|
573system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
574system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
575system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 573system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
574system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
575system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
576system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total)
577system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle
578system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle
579system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle
580system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked
581system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running
582system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking
583system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing
584system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode
585system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing
586system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle
587system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking
588system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst
589system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running
590system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking
591system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename
592system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full
593system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full
594system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed
595system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made
596system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups
597system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed
598system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing
599system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed
600system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed
601system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer
602system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit.
603system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit.
604system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads.
605system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores.
606system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec)
607system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ
608system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued
609system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued
610system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling
611system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph
612system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed
613system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle
614system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle
615system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle
| 576system.cpu1.fetch.rateDist::total 185079 # Number of instructions fetched each cycle (Total)
577system.cpu1.fetch.branchRate 0.259388 # Number of branch fetches per cycle
578system.cpu1.fetch.rate 1.420646 # Number of inst fetches per cycle
579system.cpu1.decode.IdleCycles 40472 # Number of cycles decode is idle
580system.cpu1.decode.BlockedCycles 37211 # Number of cycles decode is blocked
581system.cpu1.decode.RunCycles 91012 # Number of cycles decode is running
582system.cpu1.decode.UnblockCycles 6805 # Number of cycles decode is unblocking
583system.cpu1.decode.SquashCycles 2854 # Number of cycles decode is squashing
584system.cpu1.decode.DecodedInsts 267804 # Number of instructions handled by decode
585system.cpu1.rename.SquashCycles 2854 # Number of cycles rename is squashing
586system.cpu1.rename.IdleCycles 41302 # Number of cycles rename is idle
587system.cpu1.rename.BlockCycles 21637 # Number of cycles rename is blocking
588system.cpu1.rename.serializeStallCycles 14674 # count of cycles rename stalled for serializing inst
589system.cpu1.rename.RunCycles 84497 # Number of cycles rename is running
590system.cpu1.rename.UnblockCycles 13390 # Number of cycles rename is unblocking
591system.cpu1.rename.RenamedInsts 265308 # Number of instructions processed by rename
592system.cpu1.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
593system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full
594system.cpu1.rename.RenamedOperands 184298 # Number of destination operands rename has renamed
595system.cpu1.rename.RenameLookups 499771 # Number of register rename lookups that rename has made
596system.cpu1.rename.int_rename_lookups 499771 # Number of integer rename lookups
597system.cpu1.rename.CommittedMaps 168579 # Number of HB maps that are committed
598system.cpu1.rename.UndoneMaps 15719 # Number of HB maps that are undone due to squashing
599system.cpu1.rename.serializingInsts 1236 # count of serializing insts renamed
600system.cpu1.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed
601system.cpu1.rename.skidInsts 16177 # count of insts added to the skid buffer
602system.cpu1.memDep0.insertedLoads 72909 # Number of loads inserted to the mem dependence unit.
603system.cpu1.memDep0.insertedStores 33507 # Number of stores inserted to the mem dependence unit.
604system.cpu1.memDep0.conflictingLoads 35450 # Number of conflicting loads.
605system.cpu1.memDep0.conflictingStores 28267 # Number of conflicting stores.
606system.cpu1.iq.iqInstsAdded 217311 # Number of instructions added to the IQ (excludes non-spec)
607system.cpu1.iq.iqNonSpecInstsAdded 8226 # Number of non-speculative instructions added to the IQ
608system.cpu1.iq.iqInstsIssued 220400 # Number of instructions issued
609system.cpu1.iq.iqSquashedInstsIssued 173 # Number of squashed instructions issued
610system.cpu1.iq.iqSquashedInstsExamined 13138 # Number of squashed instructions iterated over during squash; mainly for profiling
611system.cpu1.iq.iqSquashedOperandsExamined 12222 # Number of squashed operands that are examined and possibly removed from graph
612system.cpu1.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed
613system.cpu1.iq.issued_per_cycle::samples 185079 # Number of insts issued each cycle
614system.cpu1.iq.issued_per_cycle::mean 1.190843 # Number of insts issued each cycle
615system.cpu1.iq.issued_per_cycle::stdev 1.296813 # Number of insts issued each cycle
|
616system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 616system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
617system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle
618system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle
619system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle
620system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle
621system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle
622system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle
623system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle
624system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle
| 617system.cpu1.iq.issued_per_cycle::0 84217 45.50% 45.50% # Number of insts issued each cycle
618system.cpu1.iq.issued_per_cycle::1 27917 15.08% 60.59% # Number of insts issued each cycle
619system.cpu1.iq.issued_per_cycle::2 33688 18.20% 78.79% # Number of insts issued each cycle
620system.cpu1.iq.issued_per_cycle::3 34243 18.50% 97.29% # Number of insts issued each cycle
621system.cpu1.iq.issued_per_cycle::4 3324 1.80% 99.09% # Number of insts issued each cycle
622system.cpu1.iq.issued_per_cycle::5 1232 0.67% 99.75% # Number of insts issued each cycle
623system.cpu1.iq.issued_per_cycle::6 345 0.19% 99.94% # Number of insts issued each cycle
624system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
|
625system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
626system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
627system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
628system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 625system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
626system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
627system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
628system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
629system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle
| 629system.cpu1.iq.issued_per_cycle::total 185079 # Number of insts issued each cycle
|
630system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 630system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
631system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available
632system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available
633system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available
634system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available
635system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available
636system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available
637system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available
638system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available
639system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available
640system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available
641system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available
642system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available
643system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available
644system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available
645system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available
646system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available
647system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available
648system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available
649system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available
650system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available
651system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available
652system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available
653system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available
654system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available
655system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available
656system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available
657system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available
658system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available
659system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available
660system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available
661system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available
| 631system.cpu1.iq.fu_full::IntAlu 21 6.60% 6.60% # attempts to use FU when none available
632system.cpu1.iq.fu_full::IntMult 0 0.00% 6.60% # attempts to use FU when none available
633system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.60% # attempts to use FU when none available
634system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.60% # attempts to use FU when none available
635system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.60% # attempts to use FU when none available
636system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.60% # attempts to use FU when none available
637system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.60% # attempts to use FU when none available
638system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.60% # attempts to use FU when none available
639system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.60% # attempts to use FU when none available
640system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.60% # attempts to use FU when none available
641system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.60% # attempts to use FU when none available
642system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.60% # attempts to use FU when none available
643system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.60% # attempts to use FU when none available
644system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.60% # attempts to use FU when none available
645system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.60% # attempts to use FU when none available
646system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.60% # attempts to use FU when none available
647system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.60% # attempts to use FU when none available
648system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.60% # attempts to use FU when none available
649system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.60% # attempts to use FU when none available
650system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.60% # attempts to use FU when none available
651system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.60% # attempts to use FU when none available
652system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.60% # attempts to use FU when none available
653system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.60% # attempts to use FU when none available
654system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.60% # attempts to use FU when none available
655system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.60% # attempts to use FU when none available
656system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.60% # attempts to use FU when none available
657system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.60% # attempts to use FU when none available
658system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.60% # attempts to use FU when none available
659system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.60% # attempts to use FU when none available
660system.cpu1.iq.fu_full::MemRead 87 27.36% 33.96% # attempts to use FU when none available
661system.cpu1.iq.fu_full::MemWrite 210 66.04% 100.00% # attempts to use FU when none available
|
662system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
663system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
664system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
| 662system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
663system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
664system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
665system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued
666system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued
667system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued
668system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued
669system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued
670system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued
671system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued
672system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued
673system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued
674system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued
675system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued
676system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued
677system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued
678system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued
679system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued
680system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued
681system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued
682system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued
683system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued
684system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued
685system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued
686system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued
687system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued
688system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued
689system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued
690system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued
691system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued
692system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued
693system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued
694system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued
695system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued
| 665system.cpu1.iq.FU_type_0::IntAlu 108844 49.38% 49.38% # Type of FU issued
666system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.38% # Type of FU issued
667system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.38% # Type of FU issued
668system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.38% # Type of FU issued
669system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.38% # Type of FU issued
670system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.38% # Type of FU issued
671system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.38% # Type of FU issued
672system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.38% # Type of FU issued
673system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.38% # Type of FU issued
674system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.38% # Type of FU issued
675system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.38% # Type of FU issued
676system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.38% # Type of FU issued
677system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.38% # Type of FU issued
678system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.38% # Type of FU issued
679system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.38% # Type of FU issued
680system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.38% # Type of FU issued
681system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.38% # Type of FU issued
682system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.38% # Type of FU issued
683system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.38% # Type of FU issued
684system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.38% # Type of FU issued
685system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.38% # Type of FU issued
686system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.38% # Type of FU issued
687system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.38% # Type of FU issued
688system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.38% # Type of FU issued
689system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
690system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.38% # Type of FU issued
691system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.38% # Type of FU issued
692system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.38% # Type of FU issued
693system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.38% # Type of FU issued
694system.cpu1.iq.FU_type_0::MemRead 78735 35.72% 85.11% # Type of FU issued
695system.cpu1.iq.FU_type_0::MemWrite 32821 14.89% 100.00% # Type of FU issued
|
696system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
697system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 696system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
697system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
698system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued
699system.cpu1.iq.rate 1.216584 # Inst issue rate
700system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested
701system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst)
702system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads
703system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes
704system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses
| 698system.cpu1.iq.FU_type_0::total 220400 # Type of FU issued
699system.cpu1.iq.rate 1.151882 # Inst issue rate
700system.cpu1.iq.fu_busy_cnt 318 # FU busy when requested
701system.cpu1.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst)
702system.cpu1.iq.int_inst_queue_reads 626370 # Number of integer instruction queue reads
703system.cpu1.iq.int_inst_queue_writes 238714 # Number of integer instruction queue writes
704system.cpu1.iq.int_inst_queue_wakeup_accesses 218326 # Number of integer instruction queue wakeup accesses
|
705system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
706system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
707system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
| 705system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
706system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
707system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
708system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses
| 708system.cpu1.iq.int_alu_accesses 220718 # Number of integer alu accesses
|
709system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
| 709system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
710system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores
| 710system.cpu1.iew.lsq.thread0.forwLoads 28122 # Number of loads that had data forwarded from stores
|
711system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 711system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
712system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed
713system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
714system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
715system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed
| 712system.cpu1.iew.lsq.thread0.squashedLoads 2824 # Number of loads squashed
713system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
714system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
715system.cpu1.iew.lsq.thread0.squashedStores 1558 # Number of stores squashed
|
716system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
717system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
718system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
719system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
720system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 716system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
717system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
718system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
719system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
720system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
721system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing
722system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking
723system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
724system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ
725system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch
726system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions
727system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions
728system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions
729system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
| 721system.cpu1.iew.iewSquashCycles 2854 # Number of cycles IEW is squashing
722system.cpu1.iew.iewBlockCycles 2376 # Number of cycles IEW is blocking
723system.cpu1.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
724system.cpu1.iew.iewDispatchedInsts 261974 # Number of instructions dispatched to IQ
725system.cpu1.iew.iewDispSquashedInsts 434 # Number of squashed instructions skipped by dispatch
726system.cpu1.iew.iewDispLoadInsts 72909 # Number of dispatched load instructions
727system.cpu1.iew.iewDispStoreInsts 33507 # Number of dispatched store instructions
728system.cpu1.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions
729system.cpu1.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall
|
730system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
| 730system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
731system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
732system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly
733system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly
734system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute
735system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions
736system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed
737system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute
| 731system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
732system.cpu1.iew.predictedTakenIncorrect 510 # Number of branches that were predicted taken incorrectly
733system.cpu1.iew.predictedNotTakenIncorrect 1187 # Number of branches that were predicted not taken incorrectly
734system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute
735system.cpu1.iew.iewExecutedInsts 219051 # Number of executed instructions
736system.cpu1.iew.iewExecLoadInsts 71704 # Number of load instructions executed
737system.cpu1.iew.iewExecSquashedInsts 1349 # Number of squashed instructions skipped in execute
|
738system.cpu1.iew.exec_swp 0 # number of swp insts executed
| 738system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
739system.cpu1.iew.exec_nop 37787 # number of nop insts executed
740system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed
741system.cpu1.iew.exec_branches 47145 # Number of branches executed
742system.cpu1.iew.exec_stores 34668 # Number of stores executed
743system.cpu1.iew.exec_rate 1.209472 # Inst execution rate
744system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit
745system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back
746system.cpu1.iew.wb_producers 126631 # num instructions producing a value
747system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value
| 739system.cpu1.iew.exec_nop 36437 # number of nop insts executed
740system.cpu1.iew.exec_refs 104435 # number of memory reference insts executed
741system.cpu1.iew.exec_branches 45735 # Number of branches executed
742system.cpu1.iew.exec_stores 32731 # Number of stores executed
743system.cpu1.iew.exec_rate 1.144832 # Inst execution rate
744system.cpu1.iew.wb_sent 218612 # cumulative count of insts sent to commit
745system.cpu1.iew.wb_count 218326 # cumulative count of insts written-back
746system.cpu1.iew.wb_producers 121254 # num instructions producing a value
747system.cpu1.iew.wb_consumers 126110 # num instructions consuming a value
|
748system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 748system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
749system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle
750system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back
| 749system.cpu1.iew.wb_rate 1.141043 # insts written-back per cycle
750system.cpu1.iew.wb_fanout 0.961494 # average fanout of values written-back
|
751system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
| 751system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
752system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions
753system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions
754system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit
755system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards
756system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted
757system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle
758system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle
759system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle
| 752system.cpu1.commit.commitCommittedInsts 246738 # The number of committed instructions
753system.cpu1.commit.commitCommittedOps 246738 # The number of committed instructions
754system.cpu1.commit.commitSquashedInsts 15223 # The number of squashed insts skipped by commit
755system.cpu1.commit.commitNonSpecStalls 7427 # The number of times commit has been forced to stall to communicate backwards
756system.cpu1.commit.branchMispredicts 1528 # The number of times a branch was mispredicted
757system.cpu1.commit.committed_per_cycle::samples 175501 # Number of insts commited each cycle
758system.cpu1.commit.committed_per_cycle::mean 1.405907 # Number of insts commited each cycle
759system.cpu1.commit.committed_per_cycle::stdev 1.932846 # Number of insts commited each cycle
|
760system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 760system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
761system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle
762system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle
763system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle
764system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle
765system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle
766system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle
767system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle
768system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle
769system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle
| 761system.cpu1.commit.committed_per_cycle::0 84843 48.34% 48.34% # Number of insts commited each cycle
762system.cpu1.commit.committed_per_cycle::1 43671 24.88% 73.23% # Number of insts commited each cycle
763system.cpu1.commit.committed_per_cycle::2 6232 3.55% 76.78% # Number of insts commited each cycle
764system.cpu1.commit.committed_per_cycle::3 8331 4.75% 81.52% # Number of insts commited each cycle
765system.cpu1.commit.committed_per_cycle::4 1551 0.88% 82.41% # Number of insts commited each cycle
766system.cpu1.commit.committed_per_cycle::5 28453 16.21% 98.62% # Number of insts commited each cycle
767system.cpu1.commit.committed_per_cycle::6 613 0.35% 98.97% # Number of insts commited each cycle
768system.cpu1.commit.committed_per_cycle::7 993 0.57% 99.54% # Number of insts commited each cycle
769system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle
|
770system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
771system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
772system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 770system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
771system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
772system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
773system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle
774system.cpu1.commit.committedInsts 256347 # Number of instructions committed
775system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed
| 773system.cpu1.commit.committed_per_cycle::total 175501 # Number of insts commited each cycle
774system.cpu1.commit.committedInsts 246738 # Number of instructions committed
775system.cpu1.commit.committedOps 246738 # Number of ops (including micro ops) committed
|
776system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
| 776system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
777system.cpu1.commit.refs 107314 # Number of memory references committed
778system.cpu1.commit.loads 73449 # Number of loads committed
779system.cpu1.commit.membars 6235 # Number of memory barriers committed
780system.cpu1.commit.branches 46061 # Number of branches committed
| 777system.cpu1.commit.refs 102034 # Number of memory references committed
778system.cpu1.commit.loads 70085 # Number of loads committed
779system.cpu1.commit.membars 6711 # Number of memory barriers committed
780system.cpu1.commit.branches 44619 # Number of branches committed
|
781system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
| 781system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
782system.cpu1.commit.int_insts 175498 # Number of committed integer instructions.
| 782system.cpu1.commit.int_insts 168775 # Number of committed integer instructions.
|
783system.cpu1.commit.function_calls 322 # Number of function calls committed.
| 783system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
784system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached
| 784system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached
|
785system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
| 785system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
786system.cpu1.rob.rob_reads 442417 # The number of ROB reads
787system.cpu1.rob.rob_writes 545088 # The number of ROB writes
788system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
789system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling
790system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
791system.cpu1.committedInsts 213261 # Number of Instructions Simulated
792system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated
793system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated
794system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction
795system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads
796system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle
797system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads
798system.cpu1.int_regfile_reads 389025 # number of integer regfile reads
799system.cpu1.int_regfile_writes 181950 # number of integer regfile writes
| 786system.cpu1.rob.rob_reads 436061 # The number of ROB reads
787system.cpu1.rob.rob_writes 526790 # The number of ROB writes
788system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
789system.cpu1.idleCycles 6260 # Total number of cycles that the CPU has spent unscheduled due to idling
790system.cpu1.quiesceCycles 36543 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
791system.cpu1.committedInsts 204620 # Number of Instructions Simulated
792system.cpu1.committedOps 204620 # Number of Ops (including micro ops) Simulated
793system.cpu1.committedInsts_total 204620 # Number of Instructions Simulated
794system.cpu1.cpi 0.935094 # CPI: Cycles Per Instruction
795system.cpu1.cpi_total 0.935094 # CPI: Total CPI of All Threads
796system.cpu1.ipc 1.069411 # IPC: Instructions Per Cycle
797system.cpu1.ipc_total 1.069411 # IPC: Total IPC of All Threads
798system.cpu1.int_regfile_reads 373202 # number of integer regfile reads
799system.cpu1.int_regfile_writes 174771 # number of integer regfile writes
|
800system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
| 800system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
801system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads
| 801system.cpu1.misc_regfile_reads 106146 # number of misc regfile reads
|
802system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
| 802system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
|
803system.cpu1.icache.replacements 321 # number of replacements
804system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use
805system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks.
| 803system.cpu1.icache.replacements 322 # number of replacements
804system.cpu1.icache.tagsinuse 90.902674 # Cycle average of tags in use
805system.cpu1.icache.total_refs 23372 # Total number of references to valid blocks.
|
806system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
| 806system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
|
807system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks.
| 807system.cpu1.icache.avg_refs 53.605505 # Average number of references to valid blocks.
|
808system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 808system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
809system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor
810system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy
811system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy
812system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits
813system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits
814system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits
815system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits
816system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits
817system.cpu1.icache.overall_hits::total 22247 # number of overall hits
818system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses
819system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses
820system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses
821system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses
822system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses
823system.cpu1.icache.overall_misses::total 510 # number of overall misses
824system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles
825system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles
826system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles
827system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles
828system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles
829system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles
830system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses)
831system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses)
832system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses
833system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses
834system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses
835system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses
836system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses
837system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses
838system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses
839system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses
840system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall accesses
841system.cpu1.icache.overall_miss_rate::total 0.022411 # miss rate for overall accesses
842system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22250 # average ReadReq miss latency
843system.cpu1.icache.ReadReq_avg_miss_latency::total 22250 # average ReadReq miss latency
844system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22250 # average overall miss latency
845system.cpu1.icache.demand_avg_miss_latency::total 22250 # average overall miss latency
846system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22250 # average overall miss latency
847system.cpu1.icache.overall_avg_miss_latency::total 22250 # average overall miss latency
848system.cpu1.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
| 809system.cpu1.icache.occ_blocks::cpu1.inst 90.902674 # Average occupied blocks per requestor
810system.cpu1.icache.occ_percent::cpu1.inst 0.177544 # Average percentage of cache occupancy
811system.cpu1.icache.occ_percent::total 0.177544 # Average percentage of cache occupancy
812system.cpu1.icache.ReadReq_hits::cpu1.inst 23372 # number of ReadReq hits
813system.cpu1.icache.ReadReq_hits::total 23372 # number of ReadReq hits
814system.cpu1.icache.demand_hits::cpu1.inst 23372 # number of demand (read+write) hits
815system.cpu1.icache.demand_hits::total 23372 # number of demand (read+write) hits
816system.cpu1.icache.overall_hits::cpu1.inst 23372 # number of overall hits
817system.cpu1.icache.overall_hits::total 23372 # number of overall hits
818system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses
819system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses
820system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses
821system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses
822system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses
823system.cpu1.icache.overall_misses::total 517 # number of overall misses
824system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11874500 # number of ReadReq miss cycles
825system.cpu1.icache.ReadReq_miss_latency::total 11874500 # number of ReadReq miss cycles
826system.cpu1.icache.demand_miss_latency::cpu1.inst 11874500 # number of demand (read+write) miss cycles
827system.cpu1.icache.demand_miss_latency::total 11874500 # number of demand (read+write) miss cycles
828system.cpu1.icache.overall_miss_latency::cpu1.inst 11874500 # number of overall miss cycles
829system.cpu1.icache.overall_miss_latency::total 11874500 # number of overall miss cycles
830system.cpu1.icache.ReadReq_accesses::cpu1.inst 23889 # number of ReadReq accesses(hits+misses)
831system.cpu1.icache.ReadReq_accesses::total 23889 # number of ReadReq accesses(hits+misses)
832system.cpu1.icache.demand_accesses::cpu1.inst 23889 # number of demand (read+write) accesses
833system.cpu1.icache.demand_accesses::total 23889 # number of demand (read+write) accesses
834system.cpu1.icache.overall_accesses::cpu1.inst 23889 # number of overall (read+write) accesses
835system.cpu1.icache.overall_accesses::total 23889 # number of overall (read+write) accesses
836system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021642 # miss rate for ReadReq accesses
837system.cpu1.icache.ReadReq_miss_rate::total 0.021642 # miss rate for ReadReq accesses
838system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021642 # miss rate for demand accesses
839system.cpu1.icache.demand_miss_rate::total 0.021642 # miss rate for demand accesses
840system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021642 # miss rate for overall accesses
841system.cpu1.icache.overall_miss_rate::total 0.021642 # miss rate for overall accesses
842system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106 # average ReadReq miss latency
843system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106 # average ReadReq miss latency
844system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency
845system.cpu1.icache.demand_avg_miss_latency::total 22968.085106 # average overall miss latency
846system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency
847system.cpu1.icache.overall_avg_miss_latency::total 22968.085106 # average overall miss latency
848system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked
|
849system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
850system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
851system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
| 849system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
850system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
851system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
852system.cpu1.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked
| 852system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked
|
853system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
854system.cpu1.icache.fast_writes 0 # number of fast writes performed
855system.cpu1.icache.cache_copies 0 # number of cache copies performed
| 853system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
854system.cpu1.icache.fast_writes 0 # number of fast writes performed
855system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
856system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits
857system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
858system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits
859system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
860system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits
861system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits
| 856system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
857system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
858system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
859system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
860system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
861system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
|
862system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses
863system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
864system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses
865system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
866system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses
867system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
| 862system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses
863system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
864system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses
865system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
866system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses
867system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
|
868system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8591500 # number of ReadReq MSHR miss cycles
869system.cpu1.icache.ReadReq_mshr_miss_latency::total 8591500 # number of ReadReq MSHR miss cycles
870system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8591500 # number of demand (read+write) MSHR miss cycles
871system.cpu1.icache.demand_mshr_miss_latency::total 8591500 # number of demand (read+write) MSHR miss cycles
872system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8591500 # number of overall MSHR miss cycles
873system.cpu1.icache.overall_mshr_miss_latency::total 8591500 # number of overall MSHR miss cycles
874system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for ReadReq accesses
875system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019159 # mshr miss rate for ReadReq accesses
876system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for demand accesses
877system.cpu1.icache.demand_mshr_miss_rate::total 0.019159 # mshr miss rate for demand accesses
878system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for overall accesses
879system.cpu1.icache.overall_mshr_miss_rate::total 0.019159 # mshr miss rate for overall accesses
880system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average ReadReq mshr miss latency
881system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229 # average ReadReq mshr miss latency
882system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency
883system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency
884system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency
885system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency
| 868system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8863000 # number of ReadReq MSHR miss cycles
869system.cpu1.icache.ReadReq_mshr_miss_latency::total 8863000 # number of ReadReq MSHR miss cycles
870system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8863000 # number of demand (read+write) MSHR miss cycles
871system.cpu1.icache.demand_mshr_miss_latency::total 8863000 # number of demand (read+write) MSHR miss cycles
872system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8863000 # number of overall MSHR miss cycles
873system.cpu1.icache.overall_mshr_miss_latency::total 8863000 # number of overall MSHR miss cycles
874system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for ReadReq accesses
875system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018251 # mshr miss rate for ReadReq accesses
876system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for demand accesses
877system.cpu1.icache.demand_mshr_miss_rate::total 0.018251 # mshr miss rate for demand accesses
878system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for overall accesses
879system.cpu1.icache.overall_mshr_miss_rate::total 0.018251 # mshr miss rate for overall accesses
880system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average ReadReq mshr miss latency
881system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20327.981651 # average ReadReq mshr miss latency
882system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average overall mshr miss latency
883system.cpu1.icache.demand_avg_mshr_miss_latency::total 20327.981651 # average overall mshr miss latency
884system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average overall mshr miss latency
885system.cpu1.icache.overall_avg_mshr_miss_latency::total 20327.981651 # average overall mshr miss latency
|
886system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
887system.cpu1.dcache.replacements 0 # number of replacements
| 886system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
887system.cpu1.dcache.replacements 0 # number of replacements
|
888system.cpu1.dcache.tagsinuse 27.650583 # Cycle average of tags in use
889system.cpu1.dcache.total_refs 40148 # Total number of references to valid blocks.
| 888system.cpu1.dcache.tagsinuse 27.508331 # Cycle average of tags in use
889system.cpu1.dcache.total_refs 38240 # Total number of references to valid blocks.
|
890system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
| 890system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
891system.cpu1.dcache.avg_refs 1384.413793 # Average number of references to valid blocks.
| 891system.cpu1.dcache.avg_refs 1318.620690 # Average number of references to valid blocks.
|
892system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 892system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
893system.cpu1.dcache.occ_blocks::cpu1.data 27.650583 # Average occupied blocks per requestor
894system.cpu1.dcache.occ_percent::cpu1.data 0.054005 # Average percentage of cache occupancy
895system.cpu1.dcache.occ_percent::total 0.054005 # Average percentage of cache occupancy
896system.cpu1.dcache.ReadReq_hits::cpu1.data 44622 # number of ReadReq hits
897system.cpu1.dcache.ReadReq_hits::total 44622 # number of ReadReq hits
898system.cpu1.dcache.WriteReq_hits::cpu1.data 33643 # number of WriteReq hits
899system.cpu1.dcache.WriteReq_hits::total 33643 # number of WriteReq hits
900system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
901system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
902system.cpu1.dcache.demand_hits::cpu1.data 78265 # number of demand (read+write) hits
903system.cpu1.dcache.demand_hits::total 78265 # number of demand (read+write) hits
904system.cpu1.dcache.overall_hits::cpu1.data 78265 # number of overall hits
905system.cpu1.dcache.overall_hits::total 78265 # number of overall hits
906system.cpu1.dcache.ReadReq_misses::cpu1.data 425 # number of ReadReq misses
907system.cpu1.dcache.ReadReq_misses::total 425 # number of ReadReq misses
908system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses
909system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses
910system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses
911system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses
912system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses
913system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses
914system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses
915system.cpu1.dcache.overall_misses::total 579 # number of overall misses
916system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9294500 # number of ReadReq miss cycles
917system.cpu1.dcache.ReadReq_miss_latency::total 9294500 # number of ReadReq miss cycles
918system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3142500 # number of WriteReq miss cycles
919system.cpu1.dcache.WriteReq_miss_latency::total 3142500 # number of WriteReq miss cycles
920system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1219000 # number of SwapReq miss cycles
921system.cpu1.dcache.SwapReq_miss_latency::total 1219000 # number of SwapReq miss cycles
922system.cpu1.dcache.demand_miss_latency::cpu1.data 12437000 # number of demand (read+write) miss cycles
923system.cpu1.dcache.demand_miss_latency::total 12437000 # number of demand (read+write) miss cycles
924system.cpu1.dcache.overall_miss_latency::cpu1.data 12437000 # number of overall miss cycles
925system.cpu1.dcache.overall_miss_latency::total 12437000 # number of overall miss cycles
926system.cpu1.dcache.ReadReq_accesses::cpu1.data 45047 # number of ReadReq accesses(hits+misses)
927system.cpu1.dcache.ReadReq_accesses::total 45047 # number of ReadReq accesses(hits+misses)
928system.cpu1.dcache.WriteReq_accesses::cpu1.data 33797 # number of WriteReq accesses(hits+misses)
929system.cpu1.dcache.WriteReq_accesses::total 33797 # number of WriteReq accesses(hits+misses)
930system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses)
931system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
932system.cpu1.dcache.demand_accesses::cpu1.data 78844 # number of demand (read+write) accesses
933system.cpu1.dcache.demand_accesses::total 78844 # number of demand (read+write) accesses
934system.cpu1.dcache.overall_accesses::cpu1.data 78844 # number of overall (read+write) accesses
935system.cpu1.dcache.overall_accesses::total 78844 # number of overall (read+write) accesses
936system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009435 # miss rate for ReadReq accesses
937system.cpu1.dcache.ReadReq_miss_rate::total 0.009435 # miss rate for ReadReq accesses
938system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004557 # miss rate for WriteReq accesses
939system.cpu1.dcache.WriteReq_miss_rate::total 0.004557 # miss rate for WriteReq accesses
940system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.764706 # miss rate for SwapReq accesses
941system.cpu1.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses
942system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007344 # miss rate for demand accesses
943system.cpu1.dcache.demand_miss_rate::total 0.007344 # miss rate for demand accesses
944system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007344 # miss rate for overall accesses
945system.cpu1.dcache.overall_miss_rate::total 0.007344 # miss rate for overall accesses
946system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765 # average ReadReq miss latency
947system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765 # average ReadReq miss latency
948system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156 # average WriteReq miss latency
949system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156 # average WriteReq miss latency
950system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692 # average SwapReq miss latency
951system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692 # average SwapReq miss latency
952system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency
953system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169 # average overall miss latency
954system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency
955system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169 # average overall miss latency
| 893system.cpu1.dcache.occ_blocks::cpu1.data 27.508331 # Average occupied blocks per requestor
894system.cpu1.dcache.occ_percent::cpu1.data 0.053727 # Average percentage of cache occupancy
895system.cpu1.dcache.occ_percent::total 0.053727 # Average percentage of cache occupancy
896system.cpu1.dcache.ReadReq_hits::cpu1.data 43171 # number of ReadReq hits
897system.cpu1.dcache.ReadReq_hits::total 43171 # number of ReadReq hits
898system.cpu1.dcache.WriteReq_hits::cpu1.data 31745 # number of WriteReq hits
899system.cpu1.dcache.WriteReq_hits::total 31745 # number of WriteReq hits
900system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits
901system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits
902system.cpu1.dcache.demand_hits::cpu1.data 74916 # number of demand (read+write) hits
903system.cpu1.dcache.demand_hits::total 74916 # number of demand (read+write) hits
904system.cpu1.dcache.overall_hits::cpu1.data 74916 # number of overall hits
905system.cpu1.dcache.overall_hits::total 74916 # number of overall hits
906system.cpu1.dcache.ReadReq_misses::cpu1.data 395 # number of ReadReq misses
907system.cpu1.dcache.ReadReq_misses::total 395 # number of ReadReq misses
908system.cpu1.dcache.WriteReq_misses::cpu1.data 134 # number of WriteReq misses
909system.cpu1.dcache.WriteReq_misses::total 134 # number of WriteReq misses
910system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
911system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
912system.cpu1.dcache.demand_misses::cpu1.data 529 # number of demand (read+write) misses
913system.cpu1.dcache.demand_misses::total 529 # number of demand (read+write) misses
914system.cpu1.dcache.overall_misses::cpu1.data 529 # number of overall misses
915system.cpu1.dcache.overall_misses::total 529 # number of overall misses
916system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11922500 # number of ReadReq miss cycles
917system.cpu1.dcache.ReadReq_miss_latency::total 11922500 # number of ReadReq miss cycles
918system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3308000 # number of WriteReq miss cycles
919system.cpu1.dcache.WriteReq_miss_latency::total 3308000 # number of WriteReq miss cycles
920system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1319000 # number of SwapReq miss cycles
921system.cpu1.dcache.SwapReq_miss_latency::total 1319000 # number of SwapReq miss cycles
922system.cpu1.dcache.demand_miss_latency::cpu1.data 15230500 # number of demand (read+write) miss cycles
923system.cpu1.dcache.demand_miss_latency::total 15230500 # number of demand (read+write) miss cycles
924system.cpu1.dcache.overall_miss_latency::cpu1.data 15230500 # number of overall miss cycles
925system.cpu1.dcache.overall_miss_latency::total 15230500 # number of overall miss cycles
926system.cpu1.dcache.ReadReq_accesses::cpu1.data 43566 # number of ReadReq accesses(hits+misses)
927system.cpu1.dcache.ReadReq_accesses::total 43566 # number of ReadReq accesses(hits+misses)
928system.cpu1.dcache.WriteReq_accesses::cpu1.data 31879 # number of WriteReq accesses(hits+misses)
929system.cpu1.dcache.WriteReq_accesses::total 31879 # number of WriteReq accesses(hits+misses)
930system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
931system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
932system.cpu1.dcache.demand_accesses::cpu1.data 75445 # number of demand (read+write) accesses
933system.cpu1.dcache.demand_accesses::total 75445 # number of demand (read+write) accesses
934system.cpu1.dcache.overall_accesses::cpu1.data 75445 # number of overall (read+write) accesses
935system.cpu1.dcache.overall_accesses::total 75445 # number of overall (read+write) accesses
936system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009067 # miss rate for ReadReq accesses
937system.cpu1.dcache.ReadReq_miss_rate::total 0.009067 # miss rate for ReadReq accesses
938system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004203 # miss rate for WriteReq accesses
939system.cpu1.dcache.WriteReq_miss_rate::total 0.004203 # miss rate for WriteReq accesses
940system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses
941system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
942system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007012 # miss rate for demand accesses
943system.cpu1.dcache.demand_miss_rate::total 0.007012 # miss rate for demand accesses
944system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007012 # miss rate for overall accesses
945system.cpu1.dcache.overall_miss_rate::total 0.007012 # miss rate for overall accesses
946system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304 # average ReadReq miss latency
947system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304 # average ReadReq miss latency
948system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164 # average WriteReq miss latency
949system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164 # average WriteReq miss latency
950system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182 # average SwapReq miss latency
951system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182 # average SwapReq miss latency
952system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency
953system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312 # average overall miss latency
954system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency
955system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312 # average overall miss latency
|
956system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
957system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
958system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
959system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
960system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
961system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
962system.cpu1.dcache.fast_writes 0 # number of fast writes performed
963system.cpu1.dcache.cache_copies 0 # number of cache copies performed
| 956system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
957system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
958system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
959system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
960system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
961system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
962system.cpu1.dcache.fast_writes 0 # number of fast writes performed
963system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
964system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits
965system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits
966system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits
967system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits
968system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits
969system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits
970system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits
971system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits
972system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses
973system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
974system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
975system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
976system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses
977system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
| 964system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229 # number of ReadReq MSHR hits
965system.cpu1.dcache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits
966system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
967system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
968system.cpu1.dcache.demand_mshr_hits::cpu1.data 263 # number of demand (read+write) MSHR hits
969system.cpu1.dcache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits
970system.cpu1.dcache.overall_mshr_hits::cpu1.data 263 # number of overall MSHR hits
971system.cpu1.dcache.overall_mshr_hits::total 263 # number of overall MSHR hits
972system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses
973system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
974system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses
975system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
976system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
977system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
978system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses
979system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
980system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses
981system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
| 978system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses
979system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
980system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses
981system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
|
982system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles
983system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles
984system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles
985system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles
986system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles
987system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles
988system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles
989system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles
990system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles
991system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles
992system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses
993system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses
994system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses
995system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses
996system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses
997system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses
998system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses
999system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses
1000system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses
1001system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses
1002system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency
1003system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency
1004system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency
1005system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency
1006system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency
1007system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency
1008system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency
1009system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency
1010system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency
1011system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency
| 982system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3273504 # number of ReadReq MSHR miss cycles
983system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3273504 # number of ReadReq MSHR miss cycles
984system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1639000 # number of WriteReq MSHR miss cycles
985system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1639000 # number of WriteReq MSHR miss cycles
986system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1148500 # number of SwapReq MSHR miss cycles
987system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles
988system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4912504 # number of demand (read+write) MSHR miss cycles
989system.cpu1.dcache.demand_mshr_miss_latency::total 4912504 # number of demand (read+write) MSHR miss cycles
990system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4912504 # number of overall MSHR miss cycles
991system.cpu1.dcache.overall_mshr_miss_latency::total 4912504 # number of overall MSHR miss cycles
992system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003810 # mshr miss rate for ReadReq accesses
993system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003810 # mshr miss rate for ReadReq accesses
994system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003137 # mshr miss rate for WriteReq accesses
995system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003137 # mshr miss rate for WriteReq accesses
996system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses
997system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses
998system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for demand accesses
999system.cpu1.dcache.demand_mshr_miss_rate::total 0.003526 # mshr miss rate for demand accesses
1000system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for overall accesses
1001system.cpu1.dcache.overall_mshr_miss_rate::total 0.003526 # mshr miss rate for overall accesses
1002system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614 # average ReadReq mshr miss latency
1003system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614 # average ReadReq mshr miss latency
1004system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16390 # average WriteReq mshr miss latency
1005system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16390 # average WriteReq mshr miss latency
1006system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182 # average SwapReq mshr miss latency
1007system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182 # average SwapReq mshr miss latency
1008system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency
1009system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency
1010system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency
1011system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency
|
1012system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 1012system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1013system.cpu2.numCycles 187552 # number of cpu cycles simulated
| 1013system.cpu2.numCycles 191032 # number of cpu cycles simulated
|
1014system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1015system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
| 1014system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1015system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
1016system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups
1017system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted
1018system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect
1019system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups
1020system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits
| 1016system.cpu2.BPredUnit.lookups 57390 # Number of BP lookups
1017system.cpu2.BPredUnit.condPredicted 54193 # Number of conditional branches predicted
1018system.cpu2.BPredUnit.condIncorrect 1550 # Number of conditional branches incorrect
1019system.cpu2.BPredUnit.BTBLookups 50681 # Number of BTB lookups
1020system.cpu2.BPredUnit.BTBHits 49645 # Number of BTB hits
|
1021system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 1021system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
1022system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target.
| 1022system.cpu2.BPredUnit.usedRAS 804 # Number of times the RAS was used to get a target.
|
1023system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
| 1023system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
1024system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss
1025system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed
1026system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered
1027system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken
1028system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked
1029system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing
1030system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked
| 1024system.cpu2.fetch.icacheStallCycles 29539 # Number of cycles fetch is stalled on an Icache miss
1025system.cpu2.fetch.Insts 321276 # Number of instructions fetch has processed
1026system.cpu2.fetch.Branches 57390 # Number of branches that fetch encountered
1027system.cpu2.fetch.predictedBranches 50449 # Number of branches that fetch has predicted taken
1028system.cpu2.fetch.Cycles 112230 # Number of cycles fetch has run and was not squashing or blocked
1029system.cpu2.fetch.SquashCycles 4473 # Number of cycles fetch has spent squashing
1030system.cpu2.fetch.BlockedCycles 35583 # Number of cycles fetch has spent blocked
|
1031system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
| 1031system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
1032system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from
1033system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps
1034system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched
1035system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
1036system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total)
1037system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total)
1038system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total)
| 1032system.cpu2.fetch.NoActiveThreadStallCycles 6761 # Number of stall cycles due to no active thread to fetch from
1033system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps
1034system.cpu2.fetch.CacheLines 20533 # Number of cache lines fetched
1035system.cpu2.fetch.IcacheSquashes 334 # Number of outstanding Icache misses that were squashed
1036system.cpu2.fetch.rateDist::samples 188044 # Number of instructions fetched each cycle (Total)
1037system.cpu2.fetch.rateDist::mean 1.708515 # Number of instructions fetched each cycle (Total)
1038system.cpu2.fetch.rateDist::stdev 2.158633 # Number of instructions fetched each cycle (Total)
|
1039system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 1039system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
1040system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total)
1041system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total)
1042system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total)
1043system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total)
1044system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total)
1045system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total)
1046system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total)
1047system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total)
1048system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total)
| 1040system.cpu2.fetch.rateDist::0 75814 40.32% 40.32% # Number of instructions fetched each cycle (Total)
1041system.cpu2.fetch.rateDist::1 56962 30.29% 70.61% # Number of instructions fetched each cycle (Total)
1042system.cpu2.fetch.rateDist::2 6138 3.26% 73.87% # Number of instructions fetched each cycle (Total)
1043system.cpu2.fetch.rateDist::3 3348 1.78% 75.65% # Number of instructions fetched each cycle (Total)
1044system.cpu2.fetch.rateDist::4 769 0.41% 76.06% # Number of instructions fetched each cycle (Total)
1045system.cpu2.fetch.rateDist::5 39287 20.89% 96.95% # Number of instructions fetched each cycle (Total)
1046system.cpu2.fetch.rateDist::6 1207 0.64% 97.60% # Number of instructions fetched each cycle (Total)
1047system.cpu2.fetch.rateDist::7 911 0.48% 98.08% # Number of instructions fetched each cycle (Total)
1048system.cpu2.fetch.rateDist::8 3608 1.92% 100.00% # Number of instructions fetched each cycle (Total)
|
1049system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1050system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1051system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 1049system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1050system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1051system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
1052system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total)
1053system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle
1054system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle
1055system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle
1056system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked
1057system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running
1058system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking
1059system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing
1060system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode
1061system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing
1062system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle
1063system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking
1064system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst
1065system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running
1066system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking
1067system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename
1068system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
1069system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full
1070system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed
1071system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made
1072system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups
1073system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed
1074system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing
1075system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed
1076system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed
1077system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer
1078system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit.
1079system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit.
1080system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads.
1081system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores.
1082system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec)
1083system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ
1084system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued
1085system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
1086system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling
1087system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph
1088system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed
1089system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle
1090system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle
1091system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle
| 1052system.cpu2.fetch.rateDist::total 188044 # Number of instructions fetched each cycle (Total)
1053system.cpu2.fetch.branchRate 0.300421 # Number of branch fetches per cycle
1054system.cpu2.fetch.rate 1.681792 # Number of inst fetches per cycle
1055system.cpu2.decode.IdleCycles 35225 # Number of cycles decode is idle
1056system.cpu2.decode.BlockedCycles 31967 # Number of cycles decode is blocked
1057system.cpu2.decode.RunCycles 106013 # Number of cycles decode is running
1058system.cpu2.decode.UnblockCycles 5229 # Number of cycles decode is unblocking
1059system.cpu2.decode.SquashCycles 2849 # Number of cycles decode is squashing
1060system.cpu2.decode.DecodedInsts 316907 # Number of instructions handled by decode
1061system.cpu2.rename.SquashCycles 2849 # Number of cycles rename is squashing
1062system.cpu2.rename.IdleCycles 36004 # Number of cycles rename is idle
1063system.cpu2.rename.BlockCycles 16323 # Number of cycles rename is blocking
1064system.cpu2.rename.serializeStallCycles 14784 # count of cycles rename stalled for serializing inst
1065system.cpu2.rename.RunCycles 101094 # Number of cycles rename is running
1066system.cpu2.rename.UnblockCycles 10229 # Number of cycles rename is unblocking
1067system.cpu2.rename.RenamedInsts 314547 # Number of instructions processed by rename
1068system.cpu2.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
1069system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
1070system.cpu2.rename.RenamedOperands 220052 # Number of destination operands rename has renamed
1071system.cpu2.rename.RenameLookups 605102 # Number of register rename lookups that rename has made
1072system.cpu2.rename.int_rename_lookups 605102 # Number of integer rename lookups
1073system.cpu2.rename.CommittedMaps 204228 # Number of HB maps that are committed
1074system.cpu2.rename.UndoneMaps 15824 # Number of HB maps that are undone due to squashing
1075system.cpu2.rename.serializingInsts 1236 # count of serializing insts renamed
1076system.cpu2.rename.tempSerializingInsts 1356 # count of temporary serializing insts renamed
1077system.cpu2.rename.skidInsts 12873 # count of insts added to the skid buffer
1078system.cpu2.memDep0.insertedLoads 89800 # Number of loads inserted to the mem dependence unit.
1079system.cpu2.memDep0.insertedStores 42907 # Number of stores inserted to the mem dependence unit.
1080system.cpu2.memDep0.conflictingLoads 42940 # Number of conflicting loads.
1081system.cpu2.memDep0.conflictingStores 37601 # Number of conflicting stores.
1082system.cpu2.iq.iqInstsAdded 260749 # Number of instructions added to the IQ (excludes non-spec)
1083system.cpu2.iq.iqNonSpecInstsAdded 6485 # Number of non-speculative instructions added to the IQ
1084system.cpu2.iq.iqInstsIssued 262481 # Number of instructions issued
1085system.cpu2.iq.iqSquashedInstsIssued 146 # Number of squashed instructions issued
1086system.cpu2.iq.iqSquashedInstsExamined 13131 # Number of squashed instructions iterated over during squash; mainly for profiling
1087system.cpu2.iq.iqSquashedOperandsExamined 11780 # Number of squashed operands that are examined and possibly removed from graph
1088system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed
1089system.cpu2.iq.issued_per_cycle::samples 188044 # Number of insts issued each cycle
1090system.cpu2.iq.issued_per_cycle::mean 1.395849 # Number of insts issued each cycle
1091system.cpu2.iq.issued_per_cycle::stdev 1.314415 # Number of insts issued each cycle
|
1092system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 1092system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
1093system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle
1094system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle
1095system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle
1096system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle
1097system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle
1098system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle
1099system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle
1100system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
1101system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
| 1093system.cpu2.iq.issued_per_cycle::0 73292 38.98% 38.98% # Number of insts issued each cycle
1094system.cpu2.iq.issued_per_cycle::1 23055 12.26% 51.24% # Number of insts issued each cycle
1095system.cpu2.iq.issued_per_cycle::2 43065 22.90% 74.14% # Number of insts issued each cycle
1096system.cpu2.iq.issued_per_cycle::3 43582 23.18% 97.31% # Number of insts issued each cycle
1097system.cpu2.iq.issued_per_cycle::4 3340 1.78% 99.09% # Number of insts issued each cycle
1098system.cpu2.iq.issued_per_cycle::5 1248 0.66% 99.75% # Number of insts issued each cycle
1099system.cpu2.iq.issued_per_cycle::6 346 0.18% 99.94% # Number of insts issued each cycle
1100system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
1101system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
|
1102system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1103system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1104system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 1102system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1103system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1104system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
1105system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle
| 1105system.cpu2.iq.issued_per_cycle::total 188044 # Number of insts issued each cycle
|
1106system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 1106system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
1107system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available
1108system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available
1109system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available
1110system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available
1111system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available
1112system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available
1113system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available
1114system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available
1115system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available
1116system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available
1117system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available
1118system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available
1119system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available
1120system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available
1121system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available
1122system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available
1123system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available
1124system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available
1125system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available
1126system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available
1127system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available
1128system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available
1129system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available
1130system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available
1131system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available
1132system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available
1133system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available
1134system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available
1135system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available
1136system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available
1137system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available
| 1107system.cpu2.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available
1108system.cpu2.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available
1109system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available
1110system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available
1111system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available
1112system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available
1113system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available
1114system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available
1115system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
1116system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available
1117system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available
1118system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available
1119system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available
1120system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available
1121system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available
1122system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available
1123system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available
1124system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available
1125system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available
1126system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available
1127system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available
1128system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available
1129system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available
1130system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available
1131system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available
1132system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available
1133system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available
1134system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available
1135system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available
1136system.cpu2.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available
1137system.cpu2.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available
|
1138system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1139system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1140system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
| 1138system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1139system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1140system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
1141system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued
1142system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued
1143system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued
1144system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued
1145system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued
1146system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued
1147system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued
1148system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued
1149system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued
1150system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued
1151system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued
1152system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued
1153system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued
1154system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued
1155system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued
1156system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued
1157system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued
1158system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued
1159system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued
1160system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued
1161system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued
1162system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued
1163system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued
1164system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued
1165system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued
1166system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued
1167system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued
1168system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued
1169system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued
1170system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued
1171system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued
| 1141system.cpu2.iq.FU_type_0::IntAlu 126143 48.06% 48.06% # Type of FU issued
1142system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.06% # Type of FU issued
1143system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.06% # Type of FU issued
1144system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.06% # Type of FU issued
1145system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.06% # Type of FU issued
1146system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.06% # Type of FU issued
1147system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.06% # Type of FU issued
1148system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.06% # Type of FU issued
1149system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.06% # Type of FU issued
1150system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.06% # Type of FU issued
1151system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.06% # Type of FU issued
1152system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.06% # Type of FU issued
1153system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.06% # Type of FU issued
1154system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.06% # Type of FU issued
1155system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.06% # Type of FU issued
1156system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.06% # Type of FU issued
1157system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.06% # Type of FU issued
1158system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.06% # Type of FU issued
1159system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.06% # Type of FU issued
1160system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.06% # Type of FU issued
1161system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.06% # Type of FU issued
1162system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.06% # Type of FU issued
1163system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.06% # Type of FU issued
1164system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.06% # Type of FU issued
1165system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.06% # Type of FU issued
1166system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.06% # Type of FU issued
1167system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued
1168system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued
1169system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued
1170system.cpu2.iq.FU_type_0::MemRead 94161 35.87% 83.93% # Type of FU issued
1171system.cpu2.iq.FU_type_0::MemWrite 42177 16.07% 100.00% # Type of FU issued
|
1172system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1173system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 1172system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1173system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
1174system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued
1175system.cpu2.iq.rate 1.158932 # Inst issue rate
1176system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested
1177system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst)
1178system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads
1179system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes
1180system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses
| 1174system.cpu2.iq.FU_type_0::total 262481 # Type of FU issued
1175system.cpu2.iq.rate 1.374016 # Inst issue rate
1176system.cpu2.iq.fu_busy_cnt 316 # FU busy when requested
1177system.cpu2.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst)
1178system.cpu2.iq.int_inst_queue_reads 713468 # Number of integer instruction queue reads
1179system.cpu2.iq.int_inst_queue_writes 280402 # Number of integer instruction queue writes
1180system.cpu2.iq.int_inst_queue_wakeup_accesses 260315 # Number of integer instruction queue wakeup accesses
|
1181system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1182system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1183system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
| 1181system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1182system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1183system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
1184system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses
| 1184system.cpu2.iq.int_alu_accesses 262797 # Number of integer alu accesses
|
1185system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
| 1185system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
1186system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores
| 1186system.cpu2.iew.lsq.thread0.forwLoads 37443 # Number of loads that had data forwarded from stores
|
1187system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 1187system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
1188system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed
1189system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
1190system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations
1191system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed
| 1188system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed
1189system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
1190system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
1191system.cpu2.iew.lsq.thread0.squashedStores 1644 # Number of stores squashed
|
1192system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1193system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1194system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1195system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1196system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 1192system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1193system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1194system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1195system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1196system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
1197system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing
1198system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking
1199system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking
1200system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ
1201system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch
1202system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions
1203system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions
1204system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions
1205system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
| 1197system.cpu2.iew.iewSquashCycles 2849 # Number of cycles IEW is squashing
1198system.cpu2.iew.iewBlockCycles 1860 # Number of cycles IEW is blocking
1199system.cpu2.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
1200system.cpu2.iew.iewDispatchedInsts 311245 # Number of instructions dispatched to IQ
1201system.cpu2.iew.iewDispSquashedInsts 407 # Number of squashed instructions skipped by dispatch
1202system.cpu2.iew.iewDispLoadInsts 89800 # Number of dispatched load instructions
1203system.cpu2.iew.iewDispStoreInsts 42907 # Number of dispatched store instructions
1204system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions
1205system.cpu2.iew.iewIQFullEvents 74 # Number of times the IQ has become full, causing a stall
|
1206system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
| 1206system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
1207system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations
1208system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
1209system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly
1210system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute
1211system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions
1212system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed
1213system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute
| 1207system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations
1208system.cpu2.iew.predictedTakenIncorrect 516 # Number of branches that were predicted taken incorrectly
1209system.cpu2.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly
1210system.cpu2.iew.branchMispredicts 1717 # Number of branch mispredicts detected at execute
1211system.cpu2.iew.iewExecutedInsts 261072 # Number of executed instructions
1212system.cpu2.iew.iewExecLoadInsts 88760 # Number of load instructions executed
1213system.cpu2.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute
|
1214system.cpu2.iew.exec_swp 0 # number of swp insts executed
| 1214system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
1215system.cpu2.iew.exec_nop 35864 # number of nop insts executed
1216system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed
1217system.cpu2.iew.exec_branches 45260 # Number of branches executed
1218system.cpu2.iew.exec_stores 31855 # Number of stores executed
1219system.cpu2.iew.exec_rate 1.151585 # Inst execution rate
1220system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit
1221system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back
1222system.cpu2.iew.wb_producers 119078 # num instructions producing a value
1223system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value
| 1215system.cpu2.iew.exec_nop 44011 # number of nop insts executed
1216system.cpu2.iew.exec_refs 130847 # number of memory reference insts executed
1217system.cpu2.iew.exec_branches 53503 # Number of branches executed
1218system.cpu2.iew.exec_stores 42087 # Number of stores executed
1219system.cpu2.iew.exec_rate 1.366640 # Inst execution rate
1220system.cpu2.iew.wb_sent 260613 # cumulative count of insts sent to commit
1221system.cpu2.iew.wb_count 260315 # cumulative count of insts written-back
1222system.cpu2.iew.wb_producers 147697 # num instructions producing a value
1223system.cpu2.iew.wb_consumers 152590 # num instructions consuming a value
|
1224system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 1224system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
1225system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle
1226system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back
| 1225system.cpu2.iew.wb_rate 1.362677 # insts written-back per cycle
1226system.cpu2.iew.wb_fanout 0.967934 # average fanout of values written-back
|
1227system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
| 1227system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
1228system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions
1229system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions
1230system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit
1231system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards
1232system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted
1233system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle
1234system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle
1235system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle
| 1228system.cpu2.commit.commitCommittedInsts 296145 # The number of committed instructions
1229system.cpu2.commit.commitCommittedOps 296145 # The number of committed instructions
1230system.cpu2.commit.commitSquashedInsts 15092 # The number of squashed insts skipped by commit
1231system.cpu2.commit.commitNonSpecStalls 5798 # The number of times commit has been forced to stall to communicate backwards
1232system.cpu2.commit.branchMispredicts 1550 # The number of times a branch was mispredicted
1233system.cpu2.commit.committed_per_cycle::samples 178435 # Number of insts commited each cycle
1234system.cpu2.commit.committed_per_cycle::mean 1.659680 # Number of insts commited each cycle
1235system.cpu2.commit.committed_per_cycle::stdev 2.032759 # Number of insts commited each cycle
|
1236system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 1236system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
1237system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle
1238system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle
1239system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle
1240system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle
1241system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle
1242system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle
1243system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle
1244system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle
1245system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle
| 1237system.cpu2.commit.committed_per_cycle::0 72400 40.57% 40.57% # Number of insts commited each cycle
1238system.cpu2.commit.committed_per_cycle::1 51371 28.79% 69.36% # Number of insts commited each cycle
1239system.cpu2.commit.committed_per_cycle::2 6245 3.50% 72.86% # Number of insts commited each cycle
1240system.cpu2.commit.committed_per_cycle::3 6660 3.73% 76.60% # Number of insts commited each cycle
1241system.cpu2.commit.committed_per_cycle::4 1539 0.86% 77.46% # Number of insts commited each cycle
1242system.cpu2.commit.committed_per_cycle::5 37793 21.18% 98.64% # Number of insts commited each cycle
1243system.cpu2.commit.committed_per_cycle::6 621 0.35% 98.99% # Number of insts commited each cycle
1244system.cpu2.commit.committed_per_cycle::7 991 0.56% 99.54% # Number of insts commited each cycle
1245system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle
|
1246system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1247system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1248system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 1246system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1247system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1248system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
1249system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle
1250system.cpu2.commit.committedInsts 242999 # Number of instructions committed
1251system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed
| 1249system.cpu2.commit.committed_per_cycle::total 178435 # Number of insts commited each cycle
1250system.cpu2.commit.committedInsts 296145 # Number of instructions committed
1251system.cpu2.commit.committedOps 296145 # Number of ops (including micro ops) committed
|
1252system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
| 1252system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
1253system.cpu2.commit.refs 99705 # Number of memory references committed
1254system.cpu2.commit.loads 68688 # Number of loads committed
1255system.cpu2.commit.membars 7170 # Number of memory barriers committed
1256system.cpu2.commit.branches 44148 # Number of branches committed
| 1253system.cpu2.commit.refs 128361 # Number of memory references committed
1254system.cpu2.commit.loads 87098 # Number of loads committed
1255system.cpu2.commit.membars 5084 # Number of memory barriers committed
1256system.cpu2.commit.branches 52312 # Number of branches committed
|
1257system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
| 1257system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
1258system.cpu2.commit.int_insts 165976 # Number of committed integer instructions.
| 1258system.cpu2.commit.int_insts 202794 # Number of committed integer instructions.
|
1259system.cpu2.commit.function_calls 322 # Number of function calls committed.
| 1259system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
1260system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached
| 1260system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached
|
1261system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
| 1261system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
1262system.cpu2.rob.rob_reads 431829 # The number of ROB reads
1263system.cpu2.rob.rob_writes 519243 # The number of ROB writes
1264system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
1265system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling
1266system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1267system.cpu2.committedInsts 200891 # Number of Instructions Simulated
1268system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated
1269system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated
1270system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction
1271system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads
1272system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle
1273system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads
1274system.cpu2.int_regfile_reads 366578 # number of integer regfile reads
1275system.cpu2.int_regfile_writes 171642 # number of integer regfile writes
| 1262system.cpu2.rob.rob_reads 488270 # The number of ROB reads
1263system.cpu2.rob.rob_writes 625337 # The number of ROB writes
1264system.cpu2.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
1265system.cpu2.idleCycles 2988 # Total number of cycles that the CPU has spent unscheduled due to idling
1266system.cpu2.quiesceCycles 36850 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1267system.cpu2.committedInsts 247959 # Number of Instructions Simulated
1268system.cpu2.committedOps 247959 # Number of Ops (including micro ops) Simulated
1269system.cpu2.committedInsts_total 247959 # Number of Instructions Simulated
1270system.cpu2.cpi 0.770418 # CPI: Cycles Per Instruction
1271system.cpu2.cpi_total 0.770418 # CPI: Total CPI of All Threads
1272system.cpu2.ipc 1.297997 # IPC: Instructions Per Cycle
1273system.cpu2.ipc_total 1.297997 # IPC: Total IPC of All Threads
1274system.cpu2.int_regfile_reads 452595 # number of integer regfile reads
1275system.cpu2.int_regfile_writes 210629 # number of integer regfile writes
|
1276system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
| 1276system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
1277system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads
| 1277system.cpu2.misc_regfile_reads 132559 # number of misc regfile reads
|
1278system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
| 1278system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
|
1279system.cpu2.icache.replacements 324 # number of replacements
1280system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use
1281system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks.
| 1279system.cpu2.icache.replacements 322 # number of replacements
1280system.cpu2.icache.tagsinuse 84.182173 # Cycle average of tags in use
1281system.cpu2.icache.total_refs 20037 # Total number of references to valid blocks.
|
1282system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks.
| 1282system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks.
|
1283system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks.
| 1283system.cpu2.icache.avg_refs 45.746575 # Average number of references to valid blocks.
|
1284system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1284system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1285system.cpu2.icache.occ_blocks::cpu2.inst 83.306019 # Average occupied blocks per requestor
1286system.cpu2.icache.occ_percent::cpu2.inst 0.162707 # Average percentage of cache occupancy
1287system.cpu2.icache.occ_percent::total 0.162707 # Average percentage of cache occupancy
1288system.cpu2.icache.ReadReq_hits::cpu2.inst 24210 # number of ReadReq hits
1289system.cpu2.icache.ReadReq_hits::total 24210 # number of ReadReq hits
1290system.cpu2.icache.demand_hits::cpu2.inst 24210 # number of demand (read+write) hits
1291system.cpu2.icache.demand_hits::total 24210 # number of demand (read+write) hits
1292system.cpu2.icache.overall_hits::cpu2.inst 24210 # number of overall hits
1293system.cpu2.icache.overall_hits::total 24210 # number of overall hits
1294system.cpu2.icache.ReadReq_misses::cpu2.inst 506 # number of ReadReq misses
1295system.cpu2.icache.ReadReq_misses::total 506 # number of ReadReq misses
1296system.cpu2.icache.demand_misses::cpu2.inst 506 # number of demand (read+write) misses
1297system.cpu2.icache.demand_misses::total 506 # number of demand (read+write) misses
1298system.cpu2.icache.overall_misses::cpu2.inst 506 # number of overall misses
1299system.cpu2.icache.overall_misses::total 506 # number of overall misses
1300system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7060500 # number of ReadReq miss cycles
1301system.cpu2.icache.ReadReq_miss_latency::total 7060500 # number of ReadReq miss cycles
1302system.cpu2.icache.demand_miss_latency::cpu2.inst 7060500 # number of demand (read+write) miss cycles
1303system.cpu2.icache.demand_miss_latency::total 7060500 # number of demand (read+write) miss cycles
1304system.cpu2.icache.overall_miss_latency::cpu2.inst 7060500 # number of overall miss cycles
1305system.cpu2.icache.overall_miss_latency::total 7060500 # number of overall miss cycles
1306system.cpu2.icache.ReadReq_accesses::cpu2.inst 24716 # number of ReadReq accesses(hits+misses)
1307system.cpu2.icache.ReadReq_accesses::total 24716 # number of ReadReq accesses(hits+misses)
1308system.cpu2.icache.demand_accesses::cpu2.inst 24716 # number of demand (read+write) accesses
1309system.cpu2.icache.demand_accesses::total 24716 # number of demand (read+write) accesses
1310system.cpu2.icache.overall_accesses::cpu2.inst 24716 # number of overall (read+write) accesses
1311system.cpu2.icache.overall_accesses::total 24716 # number of overall (read+write) accesses
1312system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020473 # miss rate for ReadReq accesses
1313system.cpu2.icache.ReadReq_miss_rate::total 0.020473 # miss rate for ReadReq accesses
1314system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020473 # miss rate for demand accesses
1315system.cpu2.icache.demand_miss_rate::total 0.020473 # miss rate for demand accesses
1316system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020473 # miss rate for overall accesses
1317system.cpu2.icache.overall_miss_rate::total 0.020473 # miss rate for overall accesses
1318system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312 # average ReadReq miss latency
1319system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312 # average ReadReq miss latency
1320system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency
1321system.cpu2.icache.demand_avg_miss_latency::total 13953.557312 # average overall miss latency
1322system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency
1323system.cpu2.icache.overall_avg_miss_latency::total 13953.557312 # average overall miss latency
| 1285system.cpu2.icache.occ_blocks::cpu2.inst 84.182173 # Average occupied blocks per requestor
1286system.cpu2.icache.occ_percent::cpu2.inst 0.164418 # Average percentage of cache occupancy
1287system.cpu2.icache.occ_percent::total 0.164418 # Average percentage of cache occupancy
1288system.cpu2.icache.ReadReq_hits::cpu2.inst 20037 # number of ReadReq hits
1289system.cpu2.icache.ReadReq_hits::total 20037 # number of ReadReq hits
1290system.cpu2.icache.demand_hits::cpu2.inst 20037 # number of demand (read+write) hits
1291system.cpu2.icache.demand_hits::total 20037 # number of demand (read+write) hits
1292system.cpu2.icache.overall_hits::cpu2.inst 20037 # number of overall hits
1293system.cpu2.icache.overall_hits::total 20037 # number of overall hits
1294system.cpu2.icache.ReadReq_misses::cpu2.inst 496 # number of ReadReq misses
1295system.cpu2.icache.ReadReq_misses::total 496 # number of ReadReq misses
1296system.cpu2.icache.demand_misses::cpu2.inst 496 # number of demand (read+write) misses
1297system.cpu2.icache.demand_misses::total 496 # number of demand (read+write) misses
1298system.cpu2.icache.overall_misses::cpu2.inst 496 # number of overall misses
1299system.cpu2.icache.overall_misses::total 496 # number of overall misses
1300system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7608500 # number of ReadReq miss cycles
1301system.cpu2.icache.ReadReq_miss_latency::total 7608500 # number of ReadReq miss cycles
1302system.cpu2.icache.demand_miss_latency::cpu2.inst 7608500 # number of demand (read+write) miss cycles
1303system.cpu2.icache.demand_miss_latency::total 7608500 # number of demand (read+write) miss cycles
1304system.cpu2.icache.overall_miss_latency::cpu2.inst 7608500 # number of overall miss cycles
1305system.cpu2.icache.overall_miss_latency::total 7608500 # number of overall miss cycles
1306system.cpu2.icache.ReadReq_accesses::cpu2.inst 20533 # number of ReadReq accesses(hits+misses)
1307system.cpu2.icache.ReadReq_accesses::total 20533 # number of ReadReq accesses(hits+misses)
1308system.cpu2.icache.demand_accesses::cpu2.inst 20533 # number of demand (read+write) accesses
1309system.cpu2.icache.demand_accesses::total 20533 # number of demand (read+write) accesses
1310system.cpu2.icache.overall_accesses::cpu2.inst 20533 # number of overall (read+write) accesses
1311system.cpu2.icache.overall_accesses::total 20533 # number of overall (read+write) accesses
1312system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024156 # miss rate for ReadReq accesses
1313system.cpu2.icache.ReadReq_miss_rate::total 0.024156 # miss rate for ReadReq accesses
1314system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024156 # miss rate for demand accesses
1315system.cpu2.icache.demand_miss_rate::total 0.024156 # miss rate for demand accesses
1316system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024156 # miss rate for overall accesses
1317system.cpu2.icache.overall_miss_rate::total 0.024156 # miss rate for overall accesses
1318system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742 # average ReadReq miss latency
1319system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742 # average ReadReq miss latency
1320system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency
1321system.cpu2.icache.demand_avg_miss_latency::total 15339.717742 # average overall miss latency
1322system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency
1323system.cpu2.icache.overall_avg_miss_latency::total 15339.717742 # average overall miss latency
|
1324system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1325system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1326system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1327system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1328system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1329system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1330system.cpu2.icache.fast_writes 0 # number of fast writes performed
1331system.cpu2.icache.cache_copies 0 # number of cache copies performed
| 1324system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1325system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1326system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1327system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1328system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1329system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1330system.cpu2.icache.fast_writes 0 # number of fast writes performed
1331system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
1332system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits
1333system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
1334system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits
1335system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
1336system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
1337system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
| 1332system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits
1333system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
1334system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits
1335system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
1336system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits
1337system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
1338system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses
1339system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
1340system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses
1341system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
1342system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses
1343system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
| 1338system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses
1339system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
1340system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses
1341system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
1342system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses
1343system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
|
1344system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5136000 # number of ReadReq MSHR miss cycles
1345system.cpu2.icache.ReadReq_mshr_miss_latency::total 5136000 # number of ReadReq MSHR miss cycles
1346system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5136000 # number of demand (read+write) MSHR miss cycles
1347system.cpu2.icache.demand_mshr_miss_latency::total 5136000 # number of demand (read+write) MSHR miss cycles
1348system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5136000 # number of overall MSHR miss cycles
1349system.cpu2.icache.overall_mshr_miss_latency::total 5136000 # number of overall MSHR miss cycles
1350system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for ReadReq accesses
1351system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017721 # mshr miss rate for ReadReq accesses
1352system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for demand accesses
1353system.cpu2.icache.demand_mshr_miss_rate::total 0.017721 # mshr miss rate for demand accesses
1354system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for overall accesses
1355system.cpu2.icache.overall_mshr_miss_rate::total 0.017721 # mshr miss rate for overall accesses
1356system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average ReadReq mshr miss latency
1357system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397 # average ReadReq mshr miss latency
1358system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency
1359system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency
1360system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency
1361system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency
| 1344system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5673500 # number of ReadReq MSHR miss cycles
1345system.cpu2.icache.ReadReq_mshr_miss_latency::total 5673500 # number of ReadReq MSHR miss cycles
1346system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5673500 # number of demand (read+write) MSHR miss cycles
1347system.cpu2.icache.demand_mshr_miss_latency::total 5673500 # number of demand (read+write) MSHR miss cycles
1348system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5673500 # number of overall MSHR miss cycles
1349system.cpu2.icache.overall_mshr_miss_latency::total 5673500 # number of overall MSHR miss cycles
1350system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for ReadReq accesses
1351system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021332 # mshr miss rate for ReadReq accesses
1352system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for demand accesses
1353system.cpu2.icache.demand_mshr_miss_rate::total 0.021332 # mshr miss rate for demand accesses
1354system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for overall accesses
1355system.cpu2.icache.overall_mshr_miss_rate::total 0.021332 # mshr miss rate for overall accesses
1356system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average ReadReq mshr miss latency
1357system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347 # average ReadReq mshr miss latency
1358system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency
1359system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency
1360system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency
1361system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency
|
1362system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1363system.cpu2.dcache.replacements 0 # number of replacements
| 1362system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1363system.cpu2.dcache.replacements 0 # number of replacements
|
1364system.cpu2.dcache.tagsinuse 24.973314 # Cycle average of tags in use
1365system.cpu2.dcache.total_refs 37203 # Total number of references to valid blocks.
| 1364system.cpu2.dcache.tagsinuse 24.868946 # Cycle average of tags in use
1365system.cpu2.dcache.total_refs 47444 # Total number of references to valid blocks.
|
1366system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
| 1366system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
1367system.cpu2.dcache.avg_refs 1328.678571 # Average number of references to valid blocks.
| 1367system.cpu2.dcache.avg_refs 1694.428571 # Average number of references to valid blocks.
|
1368system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1368system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1369system.cpu2.dcache.occ_blocks::cpu2.data 24.973314 # Average occupied blocks per requestor
1370system.cpu2.dcache.occ_percent::cpu2.data 0.048776 # Average percentage of cache occupancy
1371system.cpu2.dcache.occ_percent::total 0.048776 # Average percentage of cache occupancy
1372system.cpu2.dcache.ReadReq_hits::cpu2.data 42731 # number of ReadReq hits
1373system.cpu2.dcache.ReadReq_hits::total 42731 # number of ReadReq hits
1374system.cpu2.dcache.WriteReq_hits::cpu2.data 30798 # number of WriteReq hits
1375system.cpu2.dcache.WriteReq_hits::total 30798 # number of WriteReq hits
1376system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
1377system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1378system.cpu2.dcache.demand_hits::cpu2.data 73529 # number of demand (read+write) hits
1379system.cpu2.dcache.demand_hits::total 73529 # number of demand (read+write) hits
1380system.cpu2.dcache.overall_hits::cpu2.data 73529 # number of overall hits
1381system.cpu2.dcache.overall_hits::total 73529 # number of overall hits
1382system.cpu2.dcache.ReadReq_misses::cpu2.data 443 # number of ReadReq misses
1383system.cpu2.dcache.ReadReq_misses::total 443 # number of ReadReq misses
1384system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses
1385system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses
1386system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
1387system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
1388system.cpu2.dcache.demand_misses::cpu2.data 594 # number of demand (read+write) misses
1389system.cpu2.dcache.demand_misses::total 594 # number of demand (read+write) misses
1390system.cpu2.dcache.overall_misses::cpu2.data 594 # number of overall misses
1391system.cpu2.dcache.overall_misses::total 594 # number of overall misses
1392system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9862000 # number of ReadReq miss cycles
1393system.cpu2.dcache.ReadReq_miss_latency::total 9862000 # number of ReadReq miss cycles
1394system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2806000 # number of WriteReq miss cycles
1395system.cpu2.dcache.WriteReq_miss_latency::total 2806000 # number of WriteReq miss cycles
1396system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1173500 # number of SwapReq miss cycles
1397system.cpu2.dcache.SwapReq_miss_latency::total 1173500 # number of SwapReq miss cycles
1398system.cpu2.dcache.demand_miss_latency::cpu2.data 12668000 # number of demand (read+write) miss cycles
1399system.cpu2.dcache.demand_miss_latency::total 12668000 # number of demand (read+write) miss cycles
1400system.cpu2.dcache.overall_miss_latency::cpu2.data 12668000 # number of overall miss cycles
1401system.cpu2.dcache.overall_miss_latency::total 12668000 # number of overall miss cycles
1402system.cpu2.dcache.ReadReq_accesses::cpu2.data 43174 # number of ReadReq accesses(hits+misses)
1403system.cpu2.dcache.ReadReq_accesses::total 43174 # number of ReadReq accesses(hits+misses)
1404system.cpu2.dcache.WriteReq_accesses::cpu2.data 30949 # number of WriteReq accesses(hits+misses)
1405system.cpu2.dcache.WriteReq_accesses::total 30949 # number of WriteReq accesses(hits+misses)
| 1369system.cpu2.dcache.occ_blocks::cpu2.data 24.868946 # Average occupied blocks per requestor
1370system.cpu2.dcache.occ_percent::cpu2.data 0.048572 # Average percentage of cache occupancy
1371system.cpu2.dcache.occ_percent::total 0.048572 # Average percentage of cache occupancy
1372system.cpu2.dcache.ReadReq_hits::cpu2.data 50906 # number of ReadReq hits
1373system.cpu2.dcache.ReadReq_hits::total 50906 # number of ReadReq hits
1374system.cpu2.dcache.WriteReq_hits::cpu2.data 41055 # number of WriteReq hits
1375system.cpu2.dcache.WriteReq_hits::total 41055 # number of WriteReq hits
1376system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
1377system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1378system.cpu2.dcache.demand_hits::cpu2.data 91961 # number of demand (read+write) hits
1379system.cpu2.dcache.demand_hits::total 91961 # number of demand (read+write) hits
1380system.cpu2.dcache.overall_hits::cpu2.data 91961 # number of overall hits
1381system.cpu2.dcache.overall_hits::total 91961 # number of overall hits
1382system.cpu2.dcache.ReadReq_misses::cpu2.data 392 # number of ReadReq misses
1383system.cpu2.dcache.ReadReq_misses::total 392 # number of ReadReq misses
1384system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses
1385system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses
1386system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
1387system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
1388system.cpu2.dcache.demand_misses::cpu2.data 532 # number of demand (read+write) misses
1389system.cpu2.dcache.demand_misses::total 532 # number of demand (read+write) misses
1390system.cpu2.dcache.overall_misses::cpu2.data 532 # number of overall misses
1391system.cpu2.dcache.overall_misses::total 532 # number of overall misses
1392system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10132000 # number of ReadReq miss cycles
1393system.cpu2.dcache.ReadReq_miss_latency::total 10132000 # number of ReadReq miss cycles
1394system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3391500 # number of WriteReq miss cycles
1395system.cpu2.dcache.WriteReq_miss_latency::total 3391500 # number of WriteReq miss cycles
1396system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1227500 # number of SwapReq miss cycles
1397system.cpu2.dcache.SwapReq_miss_latency::total 1227500 # number of SwapReq miss cycles
1398system.cpu2.dcache.demand_miss_latency::cpu2.data 13523500 # number of demand (read+write) miss cycles
1399system.cpu2.dcache.demand_miss_latency::total 13523500 # number of demand (read+write) miss cycles
1400system.cpu2.dcache.overall_miss_latency::cpu2.data 13523500 # number of overall miss cycles
1401system.cpu2.dcache.overall_miss_latency::total 13523500 # number of overall miss cycles
1402system.cpu2.dcache.ReadReq_accesses::cpu2.data 51298 # number of ReadReq accesses(hits+misses)
1403system.cpu2.dcache.ReadReq_accesses::total 51298 # number of ReadReq accesses(hits+misses)
1404system.cpu2.dcache.WriteReq_accesses::cpu2.data 41195 # number of WriteReq accesses(hits+misses)
1405system.cpu2.dcache.WriteReq_accesses::total 41195 # number of WriteReq accesses(hits+misses)
|
1406system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
1407system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
| 1406system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
1407system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
|
1408system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses
1409system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses
1410system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses
1411system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses
1412system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses
1413system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses
1414system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses
1415system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses
1416system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses
1417system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
1418system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses
1419system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses
1420system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses
1421system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses
1422system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency
1423system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency
1424system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency
1425system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency
1426system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency
1427system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency
1428system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency
1429system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency
1430system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency
1431system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency
| 1408system.cpu2.dcache.demand_accesses::cpu2.data 92493 # number of demand (read+write) accesses
1409system.cpu2.dcache.demand_accesses::total 92493 # number of demand (read+write) accesses
1410system.cpu2.dcache.overall_accesses::cpu2.data 92493 # number of overall (read+write) accesses
1411system.cpu2.dcache.overall_accesses::total 92493 # number of overall (read+write) accesses
1412system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007642 # miss rate for ReadReq accesses
1413system.cpu2.dcache.ReadReq_miss_rate::total 0.007642 # miss rate for ReadReq accesses
1414system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003398 # miss rate for WriteReq accesses
1415system.cpu2.dcache.WriteReq_miss_rate::total 0.003398 # miss rate for WriteReq accesses
1416system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses
1417system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses
1418system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005752 # miss rate for demand accesses
1419system.cpu2.dcache.demand_miss_rate::total 0.005752 # miss rate for demand accesses
1420system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005752 # miss rate for overall accesses
1421system.cpu2.dcache.overall_miss_rate::total 0.005752 # miss rate for overall accesses
1422system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776 # average ReadReq miss latency
1423system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776 # average ReadReq miss latency
1424system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24225 # average WriteReq miss latency
1425system.cpu2.dcache.WriteReq_avg_miss_latency::total 24225 # average WriteReq miss latency
1426system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857 # average SwapReq miss latency
1427system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857 # average SwapReq miss latency
1428system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency
1429system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782 # average overall miss latency
1430system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency
1431system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782 # average overall miss latency
|
1432system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1433system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1434system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1435system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1436system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1437system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1438system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1439system.cpu2.dcache.cache_copies 0 # number of cache copies performed
| 1432system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1433system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1434system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1435system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1436system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1437system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1438system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1439system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
1440system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits
1441system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits
1442system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits
1443system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits
1444system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits
1445system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits
1446system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits
1447system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits
1448system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses
1449system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
1450system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses
1451system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1452system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses
1453system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
1454system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
1455system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1456system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
1457system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1458system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles
1459system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles
1460system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles
1461system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles
1462system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles
1463system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles
1464system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles
1465system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles
1466system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles
1467system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles
1468system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses
1469system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses
1470system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses
1471system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses
1472system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses
1473system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses
1474system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses
1475system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses
1476system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses
1477system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses
1478system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency
1479system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency
1480system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency
1481system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency
1482system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency
1483system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency
1484system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency
1485system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency
1486system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency
1487system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency
| 1440system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits
1441system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits
1442system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits
1443system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
1444system.cpu2.dcache.demand_mshr_hits::cpu2.data 276 # number of demand (read+write) MSHR hits
1445system.cpu2.dcache.demand_mshr_hits::total 276 # number of demand (read+write) MSHR hits
1446system.cpu2.dcache.overall_mshr_hits::cpu2.data 276 # number of overall MSHR hits
1447system.cpu2.dcache.overall_mshr_hits::total 276 # number of overall MSHR hits
1448system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses
1449system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
1450system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
1451system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
1452system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
1453system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
1454system.cpu2.dcache.demand_mshr_misses::cpu2.data 256 # number of demand (read+write) MSHR misses
1455system.cpu2.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
1456system.cpu2.dcache.overall_mshr_misses::cpu2.data 256 # number of overall MSHR misses
1457system.cpu2.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses
1458system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2456507 # number of ReadReq MSHR miss cycles
1459system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2456507 # number of ReadReq MSHR miss cycles
1460system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1732500 # number of WriteReq MSHR miss cycles
1461system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1732500 # number of WriteReq MSHR miss cycles
1462system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1052000 # number of SwapReq MSHR miss cycles
1463system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1052000 # number of SwapReq MSHR miss cycles
1464system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4189007 # number of demand (read+write) MSHR miss cycles
1465system.cpu2.dcache.demand_mshr_miss_latency::total 4189007 # number of demand (read+write) MSHR miss cycles
1466system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4189007 # number of overall MSHR miss cycles
1467system.cpu2.dcache.overall_mshr_miss_latency::total 4189007 # number of overall MSHR miss cycles
1468system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002944 # mshr miss rate for ReadReq accesses
1469system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses
1470system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002549 # mshr miss rate for WriteReq accesses
1471system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002549 # mshr miss rate for WriteReq accesses
1472system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses
1473system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses
1474system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for demand accesses
1475system.cpu2.dcache.demand_mshr_miss_rate::total 0.002768 # mshr miss rate for demand accesses
1476system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for overall accesses
1477system.cpu2.dcache.overall_mshr_miss_rate::total 0.002768 # mshr miss rate for overall accesses
1478system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278 # average ReadReq mshr miss latency
1479system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278 # average ReadReq mshr miss latency
1480system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16500 # average WriteReq mshr miss latency
1481system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16500 # average WriteReq mshr miss latency
1482system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286 # average SwapReq mshr miss latency
1483system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286 # average SwapReq mshr miss latency
1484system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency
1485system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency
1486system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency
1487system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency
|
1488system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 1488system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1489system.cpu3.numCycles 187286 # number of cpu cycles simulated
| 1489system.cpu3.numCycles 190752 # number of cpu cycles simulated
|
1490system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1491system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
| 1490system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1491system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
1492system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups
1493system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted
1494system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect
1495system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups
1496system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits
| 1492system.cpu3.BPredUnit.lookups 53643 # Number of BP lookups
1493system.cpu3.BPredUnit.condPredicted 50394 # Number of conditional branches predicted
1494system.cpu3.BPredUnit.condIncorrect 1547 # Number of conditional branches incorrect
1495system.cpu3.BPredUnit.BTBLookups 46912 # Number of BTB lookups
1496system.cpu3.BPredUnit.BTBHits 45897 # Number of BTB hits
|
1497system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 1497system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
1498system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target.
| 1498system.cpu3.BPredUnit.usedRAS 838 # Number of times the RAS was used to get a target.
|
1499system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
| 1499system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
1500system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss
1501system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed
1502system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered
1503system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken
1504system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked
1505system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing
1506system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked
| 1500system.cpu3.fetch.icacheStallCycles 31381 # Number of cycles fetch is stalled on an Icache miss
1501system.cpu3.fetch.Insts 296607 # Number of instructions fetch has processed
1502system.cpu3.fetch.Branches 53643 # Number of branches that fetch encountered
1503system.cpu3.fetch.predictedBranches 46735 # Number of branches that fetch has predicted taken
1504system.cpu3.fetch.Cycles 105748 # Number of cycles fetch has run and was not squashing or blocked
1505system.cpu3.fetch.SquashCycles 4379 # Number of cycles fetch has spent squashing
1506system.cpu3.fetch.BlockedCycles 39758 # Number of cycles fetch has spent blocked
|
1507system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
| 1507system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
1508system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from
1509system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps
1510system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched
1511system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed
1512system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total)
1513system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total)
1514system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total)
| 1508system.cpu3.fetch.NoActiveThreadStallCycles 6743 # Number of stall cycles due to no active thread to fetch from
1509system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
1510system.cpu3.fetch.CacheLines 22503 # Number of cache lines fetched
1511system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed
1512system.cpu3.fetch.rateDist::samples 187456 # Number of instructions fetched each cycle (Total)
1513system.cpu3.fetch.rateDist::mean 1.582275 # Number of instructions fetched each cycle (Total)
1514system.cpu3.fetch.rateDist::stdev 2.112091 # Number of instructions fetched each cycle (Total)
|
1515system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 1515system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
1516system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total)
1517system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total)
1518system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total)
1519system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total)
1520system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total)
1521system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total)
1522system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total)
1523system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total)
1524system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total)
| 1516system.cpu3.fetch.rateDist::0 81708 43.59% 43.59% # Number of instructions fetched each cycle (Total)
1517system.cpu3.fetch.rateDist::1 54260 28.95% 72.53% # Number of instructions fetched each cycle (Total)
1518system.cpu3.fetch.rateDist::2 7170 3.82% 76.36% # Number of instructions fetched each cycle (Total)
1519system.cpu3.fetch.rateDist::3 3258 1.74% 78.10% # Number of instructions fetched each cycle (Total)
1520system.cpu3.fetch.rateDist::4 706 0.38% 78.47% # Number of instructions fetched each cycle (Total)
1521system.cpu3.fetch.rateDist::5 34710 18.52% 96.99% # Number of instructions fetched each cycle (Total)
1522system.cpu3.fetch.rateDist::6 1204 0.64% 97.63% # Number of instructions fetched each cycle (Total)
1523system.cpu3.fetch.rateDist::7 885 0.47% 98.10% # Number of instructions fetched each cycle (Total)
1524system.cpu3.fetch.rateDist::8 3555 1.90% 100.00% # Number of instructions fetched each cycle (Total)
|
1525system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1526system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1527system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 1525system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1526system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1527system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
1528system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total)
1529system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle
1530system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle
1531system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle
1532system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked
1533system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running
1534system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking
1535system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing
1536system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode
1537system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing
1538system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle
1539system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking
1540system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst
1541system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running
1542system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking
1543system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename
1544system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full
1545system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full
1546system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed
1547system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made
1548system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups
1549system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed
1550system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing
1551system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed
1552system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed
1553system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer
1554system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit.
1555system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit.
1556system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads.
1557system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores.
1558system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec)
1559system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ
1560system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued
| 1528system.cpu3.fetch.rateDist::total 187456 # Number of instructions fetched each cycle (Total)
1529system.cpu3.fetch.branchRate 0.281219 # Number of branch fetches per cycle
1530system.cpu3.fetch.rate 1.554935 # Number of inst fetches per cycle
1531system.cpu3.decode.IdleCycles 37941 # Number of cycles decode is idle
1532system.cpu3.decode.BlockedCycles 35250 # Number of cycles decode is blocked
1533system.cpu3.decode.RunCycles 98653 # Number of cycles decode is running
1534system.cpu3.decode.UnblockCycles 6106 # Number of cycles decode is unblocking
1535system.cpu3.decode.SquashCycles 2763 # Number of cycles decode is squashing
1536system.cpu3.decode.DecodedInsts 292333 # Number of instructions handled by decode
1537system.cpu3.rename.SquashCycles 2763 # Number of cycles rename is squashing
1538system.cpu3.rename.IdleCycles 38724 # Number of cycles rename is idle
1539system.cpu3.rename.BlockCycles 18900 # Number of cycles rename is blocking
1540system.cpu3.rename.serializeStallCycles 15518 # count of cycles rename stalled for serializing inst
1541system.cpu3.rename.RunCycles 92845 # Number of cycles rename is running
1542system.cpu3.rename.UnblockCycles 11963 # Number of cycles rename is unblocking
1543system.cpu3.rename.RenamedInsts 289904 # Number of instructions processed by rename
1544system.cpu3.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
1545system.cpu3.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
1546system.cpu3.rename.RenamedOperands 201915 # Number of destination operands rename has renamed
1547system.cpu3.rename.RenameLookups 552179 # Number of register rename lookups that rename has made
1548system.cpu3.rename.int_rename_lookups 552179 # Number of integer rename lookups
1549system.cpu3.rename.CommittedMaps 186764 # Number of HB maps that are committed
1550system.cpu3.rename.UndoneMaps 15151 # Number of HB maps that are undone due to squashing
1551system.cpu3.rename.serializingInsts 1285 # count of serializing insts renamed
1552system.cpu3.rename.tempSerializingInsts 1418 # count of temporary serializing insts renamed
1553system.cpu3.rename.skidInsts 14719 # count of insts added to the skid buffer
1554system.cpu3.memDep0.insertedLoads 81367 # Number of loads inserted to the mem dependence unit.
1555system.cpu3.memDep0.insertedStores 38245 # Number of stores inserted to the mem dependence unit.
1556system.cpu3.memDep0.conflictingLoads 39205 # Number of conflicting loads.
1557system.cpu3.memDep0.conflictingStores 32957 # Number of conflicting stores.
1558system.cpu3.iq.iqInstsAdded 238924 # Number of instructions added to the IQ (excludes non-spec)
1559system.cpu3.iq.iqNonSpecInstsAdded 7473 # Number of non-speculative instructions added to the IQ
1560system.cpu3.iq.iqInstsIssued 241868 # Number of instructions issued
|
1561system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
| 1561system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
|
1562system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling
1563system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph
1564system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed
1565system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle
1566system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle
1567system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle
| 1562system.cpu3.iq.iqSquashedInstsExamined 12521 # Number of squashed instructions iterated over during squash; mainly for profiling
1563system.cpu3.iq.iqSquashedOperandsExamined 10991 # Number of squashed operands that are examined and possibly removed from graph
1564system.cpu3.iq.iqSquashedNonSpecRemoved 722 # Number of squashed non-spec instructions that were removed
1565system.cpu3.iq.issued_per_cycle::samples 187456 # Number of insts issued each cycle
1566system.cpu3.iq.issued_per_cycle::mean 1.290265 # Number of insts issued each cycle
1567system.cpu3.iq.issued_per_cycle::stdev 1.307286 # Number of insts issued each cycle
|
1568system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 1568system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
1569system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle
1570system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle
1571system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle
1572system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle
1573system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle
1574system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle
1575system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
| 1569system.cpu3.iq.issued_per_cycle::0 79218 42.26% 42.26% # Number of insts issued each cycle
1570system.cpu3.iq.issued_per_cycle::1 25849 13.79% 56.05% # Number of insts issued each cycle
1571system.cpu3.iq.issued_per_cycle::2 38415 20.49% 76.54% # Number of insts issued each cycle
1572system.cpu3.iq.issued_per_cycle::3 38999 20.80% 97.35% # Number of insts issued each cycle
1573system.cpu3.iq.issued_per_cycle::4 3297 1.76% 99.10% # Number of insts issued each cycle
1574system.cpu3.iq.issued_per_cycle::5 1241 0.66% 99.77% # Number of insts issued each cycle
1575system.cpu3.iq.issued_per_cycle::6 322 0.17% 99.94% # Number of insts issued each cycle
|
1576system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
| 1576system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
|
1577system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
| 1577system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
|
1578system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1579system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1580system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 1578system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1579system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1580system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
1581system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle
| 1581system.cpu3.iq.issued_per_cycle::total 187456 # Number of insts issued each cycle
|
1582system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 1582system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
1583system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available
1584system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available
1585system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available
1586system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available
1587system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available
1588system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available
1589system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available
1590system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available
1591system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available
1592system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available
1593system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available
1594system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available
1595system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available
1596system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available
1597system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available
1598system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available
1599system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available
1600system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available
1601system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available
1602system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available
1603system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available
1604system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available
1605system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available
1606system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available
1607system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available
1608system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available
1609system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available
1610system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available
1611system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available
1612system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available
1613system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available
| 1583system.cpu3.iq.fu_full::IntAlu 22 7.19% 7.19% # attempts to use FU when none available
1584system.cpu3.iq.fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available
1585system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available
1586system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available
1587system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available
1588system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available
1589system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available
1590system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available
1591system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
1592system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available
1593system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available
1594system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available
1595system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available
1596system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available
1597system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available
1598system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available
1599system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available
1600system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available
1601system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available
1602system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available
1603system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available
1604system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available
1605system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available
1606system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available
1607system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available
1608system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available
1609system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available
1610system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available
1611system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
1612system.cpu3.iq.fu_full::MemRead 74 24.18% 31.37% # attempts to use FU when none available
1613system.cpu3.iq.fu_full::MemWrite 210 68.63% 100.00% # attempts to use FU when none available
|
1614system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1615system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1616system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
| 1614system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1615system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1616system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
1617system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued
1618system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued
1619system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued
1620system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued
1621system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued
1622system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued
1623system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued
1624system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued
1625system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued
1626system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued
1627system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued
1628system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued
1629system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued
1630system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued
1631system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued
1632system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued
1633system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued
1634system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued
1635system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued
1636system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued
1637system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued
1638system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued
1639system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued
1640system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued
1641system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued
1642system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued
1643system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued
1644system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued
1645system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued
1646system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued
1647system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued
| 1617system.cpu3.iq.FU_type_0::IntAlu 117603 48.62% 48.62% # Type of FU issued
1618system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.62% # Type of FU issued
1619system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.62% # Type of FU issued
1620system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.62% # Type of FU issued
1621system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.62% # Type of FU issued
1622system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.62% # Type of FU issued
1623system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.62% # Type of FU issued
1624system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.62% # Type of FU issued
1625system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.62% # Type of FU issued
1626system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.62% # Type of FU issued
1627system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.62% # Type of FU issued
1628system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.62% # Type of FU issued
1629system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.62% # Type of FU issued
1630system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.62% # Type of FU issued
1631system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.62% # Type of FU issued
1632system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.62% # Type of FU issued
1633system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.62% # Type of FU issued
1634system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.62% # Type of FU issued
1635system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.62% # Type of FU issued
1636system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.62% # Type of FU issued
1637system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.62% # Type of FU issued
1638system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.62% # Type of FU issued
1639system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.62% # Type of FU issued
1640system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.62% # Type of FU issued
1641system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.62% # Type of FU issued
1642system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.62% # Type of FU issued
1643system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.62% # Type of FU issued
1644system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.62% # Type of FU issued
1645system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.62% # Type of FU issued
1646system.cpu3.iq.FU_type_0::MemRead 86736 35.86% 84.48% # Type of FU issued
1647system.cpu3.iq.FU_type_0::MemWrite 37529 15.52% 100.00% # Type of FU issued
|
1648system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1649system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 1648system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1649system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
1650system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued
1651system.cpu3.iq.rate 1.448848 # Inst issue rate
1652system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested
1653system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst)
1654system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads
1655system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes
1656system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses
| 1650system.cpu3.iq.FU_type_0::total 241868 # Type of FU issued
1651system.cpu3.iq.rate 1.267971 # Inst issue rate
1652system.cpu3.iq.fu_busy_cnt 306 # FU busy when requested
1653system.cpu3.iq.fu_busy_rate 0.001265 # FU busy rate (busy events/executed inst)
1654system.cpu3.iq.int_inst_queue_reads 671615 # Number of integer instruction queue reads
1655system.cpu3.iq.int_inst_queue_writes 258950 # Number of integer instruction queue writes
1656system.cpu3.iq.int_inst_queue_wakeup_accesses 239863 # Number of integer instruction queue wakeup accesses
|
1657system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1658system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1659system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
| 1657system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1658system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1659system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
1660system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses
| 1660system.cpu3.iq.int_alu_accesses 242174 # Number of integer alu accesses
|
1661system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
| 1661system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
1662system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores
| 1662system.cpu3.iew.lsq.thread0.forwLoads 32833 # Number of loads that had data forwarded from stores
|
1663system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 1663system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
1664system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed
1665system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
1666system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
1667system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed
| 1664system.cpu3.iew.lsq.thread0.squashedLoads 2526 # Number of loads squashed
1665system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
1666system.cpu3.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations
1667system.cpu3.iew.lsq.thread0.squashedStores 1583 # Number of stores squashed
|
1668system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1669system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1670system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1671system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1672system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 1668system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1669system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1670system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1671system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1672system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
1673system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing
1674system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking
| 1673system.cpu3.iew.iewSquashCycles 2763 # Number of cycles IEW is squashing
1674system.cpu3.iew.iewBlockCycles 1788 # Number of cycles IEW is blocking
|
1675system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
| 1675system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
|
1676system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ
1677system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch
1678system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions
1679system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions
1680system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions
1681system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall
| 1676system.cpu3.iew.iewDispatchedInsts 286739 # Number of instructions dispatched to IQ
1677system.cpu3.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch
1678system.cpu3.iew.iewDispLoadInsts 81367 # Number of dispatched load instructions
1679system.cpu3.iew.iewDispStoreInsts 38245 # Number of dispatched store instructions
1680system.cpu3.iew.iewDispNonSpecInsts 1210 # Number of dispatched non-speculative instructions
1681system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall
|
1682system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
| 1682system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
1683system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations
1684system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly
1685system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly
1686system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute
1687system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions
1688system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed
1689system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute
| 1683system.cpu3.iew.memOrderViolationEvents 32 # Number of memory order violations
1684system.cpu3.iew.predictedTakenIncorrect 503 # Number of branches that were predicted taken incorrectly
1685system.cpu3.iew.predictedNotTakenIncorrect 1210 # Number of branches that were predicted not taken incorrectly
1686system.cpu3.iew.branchMispredicts 1713 # Number of branch mispredicts detected at execute
1687system.cpu3.iew.iewExecutedInsts 240581 # Number of executed instructions
1688system.cpu3.iew.iewExecLoadInsts 80413 # Number of load instructions executed
1689system.cpu3.iew.iewExecSquashedInsts 1287 # Number of squashed instructions skipped in execute
|
1690system.cpu3.iew.exec_swp 0 # number of swp insts executed
| 1690system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
1691system.cpu3.iew.exec_nop 45763 # number of nop insts executed
1692system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed
1693system.cpu3.iew.exec_branches 55022 # Number of branches executed
1694system.cpu3.iew.exec_stores 44284 # Number of stores executed
1695system.cpu3.iew.exec_rate 1.441587 # Inst execution rate
1696system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit
1697system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back
1698system.cpu3.iew.wb_producers 153664 # num instructions producing a value
1699system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value
| 1691system.cpu3.iew.exec_nop 40342 # number of nop insts executed
1692system.cpu3.iew.exec_refs 117868 # number of memory reference insts executed
1693system.cpu3.iew.exec_branches 49825 # Number of branches executed
1694system.cpu3.iew.exec_stores 37455 # Number of stores executed
1695system.cpu3.iew.exec_rate 1.261224 # Inst execution rate
1696system.cpu3.iew.wb_sent 240146 # cumulative count of insts sent to commit
1697system.cpu3.iew.wb_count 239863 # cumulative count of insts written-back
1698system.cpu3.iew.wb_producers 134653 # num instructions producing a value
1699system.cpu3.iew.wb_consumers 139524 # num instructions consuming a value
|
1700system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 1700system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
1701system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle
1702system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back
| 1701system.cpu3.iew.wb_rate 1.257460 # insts written-back per cycle
1702system.cpu3.iew.wb_fanout 0.965088 # average fanout of values written-back
|
1703system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
| 1703system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
1704system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions
1705system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions
1706system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit
1707system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards
1708system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted
1709system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle
1710system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle
1711system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle
| 1704system.cpu3.commit.commitCommittedInsts 272332 # The number of committed instructions
1705system.cpu3.commit.commitCommittedOps 272332 # The number of committed instructions
1706system.cpu3.commit.commitSquashedInsts 14381 # The number of squashed insts skipped by commit
1707system.cpu3.commit.commitNonSpecStalls 6751 # The number of times commit has been forced to stall to communicate backwards
1708system.cpu3.commit.branchMispredicts 1547 # The number of times a branch was mispredicted
1709system.cpu3.commit.committed_per_cycle::samples 177951 # Number of insts commited each cycle
1710system.cpu3.commit.committed_per_cycle::mean 1.530376 # Number of insts commited each cycle
1711system.cpu3.commit.committed_per_cycle::stdev 1.985731 # Number of insts commited each cycle
|
1712system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 1712system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
1713system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle
1714system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle
1715system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle
1716system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle
1717system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle
1718system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle
1719system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle
1720system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle
| 1713system.cpu3.commit.committed_per_cycle::0 79207 44.51% 44.51% # Number of insts commited each cycle
1714system.cpu3.commit.committed_per_cycle::1 47739 26.83% 71.34% # Number of insts commited each cycle
1715system.cpu3.commit.committed_per_cycle::2 6222 3.50% 74.83% # Number of insts commited each cycle
1716system.cpu3.commit.committed_per_cycle::3 7617 4.28% 79.11% # Number of insts commited each cycle
1717system.cpu3.commit.committed_per_cycle::4 1549 0.87% 79.98% # Number of insts commited each cycle
1718system.cpu3.commit.committed_per_cycle::5 33224 18.67% 98.66% # Number of insts commited each cycle
1719system.cpu3.commit.committed_per_cycle::6 582 0.33% 98.98% # Number of insts commited each cycle
1720system.cpu3.commit.committed_per_cycle::7 998 0.56% 99.54% # Number of insts commited each cycle
|
1721system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle
1722system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1723system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1724system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 1721system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle
1722system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1723system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1724system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
1725system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle
1726system.cpu3.commit.committedInsts 306791 # Number of instructions committed
1727system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed
| 1725system.cpu3.commit.committed_per_cycle::total 177951 # Number of insts commited each cycle
1726system.cpu3.commit.committedInsts 272332 # Number of instructions committed
1727system.cpu3.commit.committedOps 272332 # Number of ops (including micro ops) committed
|
1728system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
| 1728system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
1729system.cpu3.commit.refs 134284 # Number of memory references committed
1730system.cpu3.commit.loads 90840 # Number of loads committed
1731system.cpu3.commit.membars 4481 # Number of memory barriers committed
1732system.cpu3.commit.branches 53890 # Number of branches committed
| 1729system.cpu3.commit.refs 115503 # Number of memory references committed
1730system.cpu3.commit.loads 78841 # Number of loads committed
1731system.cpu3.commit.membars 6036 # Number of memory barriers committed
1732system.cpu3.commit.branches 48661 # Number of branches committed
|
1733system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
| 1733system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
1734system.cpu3.commit.int_insts 210289 # Number of committed integer instructions.
| 1734system.cpu3.commit.int_insts 186284 # Number of committed integer instructions.
|
1735system.cpu3.commit.function_calls 322 # Number of function calls committed.
1736system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached
1737system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
| 1735system.cpu3.commit.function_calls 322 # Number of function calls committed.
1736system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached
1737system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
|
1738system.cpu3.rob.rob_reads 496513 # The number of ROB reads
1739system.cpu3.rob.rob_writes 647676 # The number of ROB writes
1740system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
1741system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling
1742system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1743system.cpu3.committedInsts 257635 # Number of Instructions Simulated
1744system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated
1745system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated
1746system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction
1747system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads
1748system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle
1749system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads
1750system.cpu3.int_regfile_reads 470214 # number of integer regfile reads
1751system.cpu3.int_regfile_writes 218594 # number of integer regfile writes
| 1738system.cpu3.rob.rob_reads 463264 # The number of ROB reads
1739system.cpu3.rob.rob_writes 576197 # The number of ROB writes
1740system.cpu3.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
1741system.cpu3.idleCycles 3296 # Total number of cycles that the CPU has spent unscheduled due to idling
1742system.cpu3.quiesceCycles 37130 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1743system.cpu3.committedInsts 226846 # Number of Instructions Simulated
1744system.cpu3.committedOps 226846 # Number of Ops (including micro ops) Simulated
1745system.cpu3.committedInsts_total 226846 # Number of Instructions Simulated
1746system.cpu3.cpi 0.840888 # CPI: Cycles Per Instruction
1747system.cpu3.cpi_total 0.840888 # CPI: Total CPI of All Threads
1748system.cpu3.ipc 1.189220 # IPC: Instructions Per Cycle
1749system.cpu3.ipc_total 1.189220 # IPC: Total IPC of All Threads
1750system.cpu3.int_regfile_reads 413495 # number of integer regfile reads
1751system.cpu3.int_regfile_writes 192863 # number of integer regfile writes
|
1752system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
| 1752system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
1753system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads
| 1753system.cpu3.misc_regfile_reads 119579 # number of misc regfile reads
|
1754system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
| 1754system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
|
1755system.cpu3.icache.replacements 322 # number of replacements
1756system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use
1757system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks.
1758system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks.
1759system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks.
| 1755system.cpu3.icache.replacements 323 # number of replacements
1756system.cpu3.icache.tagsinuse 88.254899 # Cycle average of tags in use
1757system.cpu3.icache.total_refs 21999 # Total number of references to valid blocks.
1758system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks.
1759system.cpu3.icache.avg_refs 50.111617 # Average number of references to valid blocks.
|
1760system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1760system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1761system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor
1762system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy
1763system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy
1764system.cpu3.icache.ReadReq_hits::cpu3.inst 18566 # number of ReadReq hits
1765system.cpu3.icache.ReadReq_hits::total 18566 # number of ReadReq hits
1766system.cpu3.icache.demand_hits::cpu3.inst 18566 # number of demand (read+write) hits
1767system.cpu3.icache.demand_hits::total 18566 # number of demand (read+write) hits
1768system.cpu3.icache.overall_hits::cpu3.inst 18566 # number of overall hits
1769system.cpu3.icache.overall_hits::total 18566 # number of overall hits
1770system.cpu3.icache.ReadReq_misses::cpu3.inst 496 # number of ReadReq misses
1771system.cpu3.icache.ReadReq_misses::total 496 # number of ReadReq misses
1772system.cpu3.icache.demand_misses::cpu3.inst 496 # number of demand (read+write) misses
1773system.cpu3.icache.demand_misses::total 496 # number of demand (read+write) misses
1774system.cpu3.icache.overall_misses::cpu3.inst 496 # number of overall misses
1775system.cpu3.icache.overall_misses::total 496 # number of overall misses
1776system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6966500 # number of ReadReq miss cycles
1777system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles
1778system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles
1779system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles
1780system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles
1781system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles
1782system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses)
1783system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses)
1784system.cpu3.icache.demand_accesses::cpu3.inst 19062 # number of demand (read+write) accesses
1785system.cpu3.icache.demand_accesses::total 19062 # number of demand (read+write) accesses
1786system.cpu3.icache.overall_accesses::cpu3.inst 19062 # number of overall (read+write) accesses
1787system.cpu3.icache.overall_accesses::total 19062 # number of overall (read+write) accesses
1788system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026020 # miss rate for ReadReq accesses
1789system.cpu3.icache.ReadReq_miss_rate::total 0.026020 # miss rate for ReadReq accesses
1790system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026020 # miss rate for demand accesses
1791system.cpu3.icache.demand_miss_rate::total 0.026020 # miss rate for demand accesses
1792system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026020 # miss rate for overall accesses
1793system.cpu3.icache.overall_miss_rate::total 0.026020 # miss rate for overall accesses
1794system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903 # average ReadReq miss latency
1795system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903 # average ReadReq miss latency
1796system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency
1797system.cpu3.icache.demand_avg_miss_latency::total 14045.362903 # average overall miss latency
1798system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency
1799system.cpu3.icache.overall_avg_miss_latency::total 14045.362903 # average overall miss latency
| 1761system.cpu3.icache.occ_blocks::cpu3.inst 88.254899 # Average occupied blocks per requestor
1762system.cpu3.icache.occ_percent::cpu3.inst 0.172373 # Average percentage of cache occupancy
1763system.cpu3.icache.occ_percent::total 0.172373 # Average percentage of cache occupancy
1764system.cpu3.icache.ReadReq_hits::cpu3.inst 21999 # number of ReadReq hits
1765system.cpu3.icache.ReadReq_hits::total 21999 # number of ReadReq hits
1766system.cpu3.icache.demand_hits::cpu3.inst 21999 # number of demand (read+write) hits
1767system.cpu3.icache.demand_hits::total 21999 # number of demand (read+write) hits
1768system.cpu3.icache.overall_hits::cpu3.inst 21999 # number of overall hits
1769system.cpu3.icache.overall_hits::total 21999 # number of overall hits
1770system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses
1771system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses
1772system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses
1773system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses
1774system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses
1775system.cpu3.icache.overall_misses::total 504 # number of overall misses
1776system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7701000 # number of ReadReq miss cycles
1777system.cpu3.icache.ReadReq_miss_latency::total 7701000 # number of ReadReq miss cycles
1778system.cpu3.icache.demand_miss_latency::cpu3.inst 7701000 # number of demand (read+write) miss cycles
1779system.cpu3.icache.demand_miss_latency::total 7701000 # number of demand (read+write) miss cycles
1780system.cpu3.icache.overall_miss_latency::cpu3.inst 7701000 # number of overall miss cycles
1781system.cpu3.icache.overall_miss_latency::total 7701000 # number of overall miss cycles
1782system.cpu3.icache.ReadReq_accesses::cpu3.inst 22503 # number of ReadReq accesses(hits+misses)
1783system.cpu3.icache.ReadReq_accesses::total 22503 # number of ReadReq accesses(hits+misses)
1784system.cpu3.icache.demand_accesses::cpu3.inst 22503 # number of demand (read+write) accesses
1785system.cpu3.icache.demand_accesses::total 22503 # number of demand (read+write) accesses
1786system.cpu3.icache.overall_accesses::cpu3.inst 22503 # number of overall (read+write) accesses
1787system.cpu3.icache.overall_accesses::total 22503 # number of overall (read+write) accesses
1788system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022397 # miss rate for ReadReq accesses
1789system.cpu3.icache.ReadReq_miss_rate::total 0.022397 # miss rate for ReadReq accesses
1790system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022397 # miss rate for demand accesses
1791system.cpu3.icache.demand_miss_rate::total 0.022397 # miss rate for demand accesses
1792system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022397 # miss rate for overall accesses
1793system.cpu3.icache.overall_miss_rate::total 0.022397 # miss rate for overall accesses
1794system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905 # average ReadReq miss latency
1795system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905 # average ReadReq miss latency
1796system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15279.761905 # average overall miss latency
1797system.cpu3.icache.demand_avg_miss_latency::total 15279.761905 # average overall miss latency
1798system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905 # average overall miss latency
1799system.cpu3.icache.overall_avg_miss_latency::total 15279.761905 # average overall miss latency
|
1800system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1801system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1802system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1803system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1804system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1805system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1806system.cpu3.icache.fast_writes 0 # number of fast writes performed
1807system.cpu3.icache.cache_copies 0 # number of cache copies performed
| 1800system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1801system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1802system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1803system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
1804system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1805system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1806system.cpu3.icache.fast_writes 0 # number of fast writes performed
1807system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
1808system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 60 # number of ReadReq MSHR hits
1809system.cpu3.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
1810system.cpu3.icache.demand_mshr_hits::cpu3.inst 60 # number of demand (read+write) MSHR hits
1811system.cpu3.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits
1812system.cpu3.icache.overall_mshr_hits::cpu3.inst 60 # number of overall MSHR hits
1813system.cpu3.icache.overall_mshr_hits::total 60 # number of overall MSHR hits
1814system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses
1815system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
1816system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses
1817system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
1818system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses
1819system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
1820system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5084500 # number of ReadReq MSHR miss cycles
1821system.cpu3.icache.ReadReq_mshr_miss_latency::total 5084500 # number of ReadReq MSHR miss cycles
1822system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5084500 # number of demand (read+write) MSHR miss cycles
1823system.cpu3.icache.demand_mshr_miss_latency::total 5084500 # number of demand (read+write) MSHR miss cycles
1824system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5084500 # number of overall MSHR miss cycles
1825system.cpu3.icache.overall_mshr_miss_latency::total 5084500 # number of overall MSHR miss cycles
1826system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for ReadReq accesses
1827system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022873 # mshr miss rate for ReadReq accesses
1828system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for demand accesses
1829system.cpu3.icache.demand_mshr_miss_rate::total 0.022873 # mshr miss rate for demand accesses
1830system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for overall accesses
1831system.cpu3.icache.overall_mshr_miss_rate::total 0.022873 # mshr miss rate for overall accesses
1832system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average ReadReq mshr miss latency
1833system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248 # average ReadReq mshr miss latency
1834system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency
1835system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency
1836system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency
1837system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency
| 1808system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 65 # number of ReadReq MSHR hits
1809system.cpu3.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
1810system.cpu3.icache.demand_mshr_hits::cpu3.inst 65 # number of demand (read+write) MSHR hits
1811system.cpu3.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits
1812system.cpu3.icache.overall_mshr_hits::cpu3.inst 65 # number of overall MSHR hits
1813system.cpu3.icache.overall_mshr_hits::total 65 # number of overall MSHR hits
1814system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses
1815system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses
1816system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses
1817system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses
1818system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses
1819system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses
1820system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5678000 # number of ReadReq MSHR miss cycles
1821system.cpu3.icache.ReadReq_mshr_miss_latency::total 5678000 # number of ReadReq MSHR miss cycles
1822system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5678000 # number of demand (read+write) MSHR miss cycles
1823system.cpu3.icache.demand_mshr_miss_latency::total 5678000 # number of demand (read+write) MSHR miss cycles
1824system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5678000 # number of overall MSHR miss cycles
1825system.cpu3.icache.overall_mshr_miss_latency::total 5678000 # number of overall MSHR miss cycles
1826system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for ReadReq accesses
1827system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses
1828system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for demand accesses
1829system.cpu3.icache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses
1830system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for overall accesses
1831system.cpu3.icache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses
1832system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average ReadReq mshr miss latency
1833system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12933.940774 # average ReadReq mshr miss latency
1834system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average overall mshr miss latency
1835system.cpu3.icache.demand_avg_mshr_miss_latency::total 12933.940774 # average overall mshr miss latency
1836system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average overall mshr miss latency
1837system.cpu3.icache.overall_avg_mshr_miss_latency::total 12933.940774 # average overall mshr miss latency
|
1838system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1839system.cpu3.dcache.replacements 0 # number of replacements
| 1838system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1839system.cpu3.dcache.replacements 0 # number of replacements
|
1840system.cpu3.dcache.tagsinuse 26.205436 # Cycle average of tags in use
1841system.cpu3.dcache.total_refs 49620 # Total number of references to valid blocks.
| 1840system.cpu3.dcache.tagsinuse 26.059158 # Cycle average of tags in use
1841system.cpu3.dcache.total_refs 42792 # Total number of references to valid blocks.
|
1842system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
| 1842system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
1843system.cpu3.dcache.avg_refs 1772.142857 # Average number of references to valid blocks.
| 1843system.cpu3.dcache.avg_refs 1528.285714 # Average number of references to valid blocks.
|
1844system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1844system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1845system.cpu3.dcache.occ_blocks::cpu3.data 26.205436 # Average occupied blocks per requestor
1846system.cpu3.dcache.occ_percent::cpu3.data 0.051182 # Average percentage of cache occupancy
1847system.cpu3.dcache.occ_percent::total 0.051182 # Average percentage of cache occupancy
1848system.cpu3.dcache.ReadReq_hits::cpu3.data 52477 # number of ReadReq hits
1849system.cpu3.dcache.ReadReq_hits::total 52477 # number of ReadReq hits
1850system.cpu3.dcache.WriteReq_hits::cpu3.data 43221 # number of WriteReq hits
1851system.cpu3.dcache.WriteReq_hits::total 43221 # number of WriteReq hits
1852system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
1853system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1854system.cpu3.dcache.demand_hits::cpu3.data 95698 # number of demand (read+write) hits
1855system.cpu3.dcache.demand_hits::total 95698 # number of demand (read+write) hits
1856system.cpu3.dcache.overall_hits::cpu3.data 95698 # number of overall hits
1857system.cpu3.dcache.overall_hits::total 95698 # number of overall hits
1858system.cpu3.dcache.ReadReq_misses::cpu3.data 424 # number of ReadReq misses
1859system.cpu3.dcache.ReadReq_misses::total 424 # number of ReadReq misses
1860system.cpu3.dcache.WriteReq_misses::cpu3.data 150 # number of WriteReq misses
1861system.cpu3.dcache.WriteReq_misses::total 150 # number of WriteReq misses
1862system.cpu3.dcache.SwapReq_misses::cpu3.data 61 # number of SwapReq misses
1863system.cpu3.dcache.SwapReq_misses::total 61 # number of SwapReq misses
1864system.cpu3.dcache.demand_misses::cpu3.data 574 # number of demand (read+write) misses
1865system.cpu3.dcache.demand_misses::total 574 # number of demand (read+write) misses
1866system.cpu3.dcache.overall_misses::cpu3.data 574 # number of overall misses
1867system.cpu3.dcache.overall_misses::total 574 # number of overall misses
1868system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8617000 # number of ReadReq miss cycles
1869system.cpu3.dcache.ReadReq_miss_latency::total 8617000 # number of ReadReq miss cycles
1870system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2850000 # number of WriteReq miss cycles
1871system.cpu3.dcache.WriteReq_miss_latency::total 2850000 # number of WriteReq miss cycles
1872system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1161500 # number of SwapReq miss cycles
1873system.cpu3.dcache.SwapReq_miss_latency::total 1161500 # number of SwapReq miss cycles
1874system.cpu3.dcache.demand_miss_latency::cpu3.data 11467000 # number of demand (read+write) miss cycles
1875system.cpu3.dcache.demand_miss_latency::total 11467000 # number of demand (read+write) miss cycles
1876system.cpu3.dcache.overall_miss_latency::cpu3.data 11467000 # number of overall miss cycles
1877system.cpu3.dcache.overall_miss_latency::total 11467000 # number of overall miss cycles
1878system.cpu3.dcache.ReadReq_accesses::cpu3.data 52901 # number of ReadReq accesses(hits+misses)
1879system.cpu3.dcache.ReadReq_accesses::total 52901 # number of ReadReq accesses(hits+misses)
1880system.cpu3.dcache.WriteReq_accesses::cpu3.data 43371 # number of WriteReq accesses(hits+misses)
1881system.cpu3.dcache.WriteReq_accesses::total 43371 # number of WriteReq accesses(hits+misses)
1882system.cpu3.dcache.SwapReq_accesses::cpu3.data 73 # number of SwapReq accesses(hits+misses)
1883system.cpu3.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses)
1884system.cpu3.dcache.demand_accesses::cpu3.data 96272 # number of demand (read+write) accesses
1885system.cpu3.dcache.demand_accesses::total 96272 # number of demand (read+write) accesses
1886system.cpu3.dcache.overall_accesses::cpu3.data 96272 # number of overall (read+write) accesses
1887system.cpu3.dcache.overall_accesses::total 96272 # number of overall (read+write) accesses
1888system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008015 # miss rate for ReadReq accesses
1889system.cpu3.dcache.ReadReq_miss_rate::total 0.008015 # miss rate for ReadReq accesses
1890system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003459 # miss rate for WriteReq accesses
1891system.cpu3.dcache.WriteReq_miss_rate::total 0.003459 # miss rate for WriteReq accesses
1892system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835616 # miss rate for SwapReq accesses
1893system.cpu3.dcache.SwapReq_miss_rate::total 0.835616 # miss rate for SwapReq accesses
1894system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005962 # miss rate for demand accesses
1895system.cpu3.dcache.demand_miss_rate::total 0.005962 # miss rate for demand accesses
1896system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005962 # miss rate for overall accesses
1897system.cpu3.dcache.overall_miss_rate::total 0.005962 # miss rate for overall accesses
1898system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208 # average ReadReq miss latency
1899system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208 # average ReadReq miss latency
1900system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19000 # average WriteReq miss latency
1901system.cpu3.dcache.WriteReq_avg_miss_latency::total 19000 # average WriteReq miss latency
1902system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607 # average SwapReq miss latency
1903system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607 # average SwapReq miss latency
1904system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency
1905system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916 # average overall miss latency
1906system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency
1907system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916 # average overall miss latency
| 1845system.cpu3.dcache.occ_blocks::cpu3.data 26.059158 # Average occupied blocks per requestor
1846system.cpu3.dcache.occ_percent::cpu3.data 0.050897 # Average percentage of cache occupancy
1847system.cpu3.dcache.occ_percent::total 0.050897 # Average percentage of cache occupancy
1848system.cpu3.dcache.ReadReq_hits::cpu3.data 47204 # number of ReadReq hits
1849system.cpu3.dcache.ReadReq_hits::total 47204 # number of ReadReq hits
1850system.cpu3.dcache.WriteReq_hits::cpu3.data 36453 # number of WriteReq hits
1851system.cpu3.dcache.WriteReq_hits::total 36453 # number of WriteReq hits
1852system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
1853system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1854system.cpu3.dcache.demand_hits::cpu3.data 83657 # number of demand (read+write) hits
1855system.cpu3.dcache.demand_hits::total 83657 # number of demand (read+write) hits
1856system.cpu3.dcache.overall_hits::cpu3.data 83657 # number of overall hits
1857system.cpu3.dcache.overall_hits::total 83657 # number of overall hits
1858system.cpu3.dcache.ReadReq_misses::cpu3.data 361 # number of ReadReq misses
1859system.cpu3.dcache.ReadReq_misses::total 361 # number of ReadReq misses
1860system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses
1861system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses
1862system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
1863system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
1864system.cpu3.dcache.demand_misses::cpu3.data 501 # number of demand (read+write) misses
1865system.cpu3.dcache.demand_misses::total 501 # number of demand (read+write) misses
1866system.cpu3.dcache.overall_misses::cpu3.data 501 # number of overall misses
1867system.cpu3.dcache.overall_misses::total 501 # number of overall misses
1868system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9450000 # number of ReadReq miss cycles
1869system.cpu3.dcache.ReadReq_miss_latency::total 9450000 # number of ReadReq miss cycles
1870system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3328500 # number of WriteReq miss cycles
1871system.cpu3.dcache.WriteReq_miss_latency::total 3328500 # number of WriteReq miss cycles
1872system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1305500 # number of SwapReq miss cycles
1873system.cpu3.dcache.SwapReq_miss_latency::total 1305500 # number of SwapReq miss cycles
1874system.cpu3.dcache.demand_miss_latency::cpu3.data 12778500 # number of demand (read+write) miss cycles
1875system.cpu3.dcache.demand_miss_latency::total 12778500 # number of demand (read+write) miss cycles
1876system.cpu3.dcache.overall_miss_latency::cpu3.data 12778500 # number of overall miss cycles
1877system.cpu3.dcache.overall_miss_latency::total 12778500 # number of overall miss cycles
1878system.cpu3.dcache.ReadReq_accesses::cpu3.data 47565 # number of ReadReq accesses(hits+misses)
1879system.cpu3.dcache.ReadReq_accesses::total 47565 # number of ReadReq accesses(hits+misses)
1880system.cpu3.dcache.WriteReq_accesses::cpu3.data 36593 # number of WriteReq accesses(hits+misses)
1881system.cpu3.dcache.WriteReq_accesses::total 36593 # number of WriteReq accesses(hits+misses)
1882system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses)
1883system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
1884system.cpu3.dcache.demand_accesses::cpu3.data 84158 # number of demand (read+write) accesses
1885system.cpu3.dcache.demand_accesses::total 84158 # number of demand (read+write) accesses
1886system.cpu3.dcache.overall_accesses::cpu3.data 84158 # number of overall (read+write) accesses
1887system.cpu3.dcache.overall_accesses::total 84158 # number of overall (read+write) accesses
1888system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007590 # miss rate for ReadReq accesses
1889system.cpu3.dcache.ReadReq_miss_rate::total 0.007590 # miss rate for ReadReq accesses
1890system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003826 # miss rate for WriteReq accesses
1891system.cpu3.dcache.WriteReq_miss_rate::total 0.003826 # miss rate for WriteReq accesses
1892system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses
1893system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses
1894system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005953 # miss rate for demand accesses
1895system.cpu3.dcache.demand_miss_rate::total 0.005953 # miss rate for demand accesses
1896system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005953 # miss rate for overall accesses
1897system.cpu3.dcache.overall_miss_rate::total 0.005953 # miss rate for overall accesses
1898system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319 # average ReadReq miss latency
1899system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319 # average ReadReq miss latency
1900system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23775 # average WriteReq miss latency
1901system.cpu3.dcache.WriteReq_avg_miss_latency::total 23775 # average WriteReq miss latency
1902system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636 # average SwapReq miss latency
1903system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636 # average SwapReq miss latency
1904system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency
1905system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024 # average overall miss latency
1906system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency
1907system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024 # average overall miss latency
|
1908system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1909system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1910system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1911system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1912system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1913system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1914system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1915system.cpu3.dcache.cache_copies 0 # number of cache copies performed
| 1908system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1909system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1910system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1911system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
1912system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1913system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1914system.cpu3.dcache.fast_writes 0 # number of fast writes performed
1915system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
1916system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 264 # number of ReadReq MSHR hits
1917system.cpu3.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits
1918system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits
1919system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits
1920system.cpu3.dcache.demand_mshr_hits::cpu3.data 310 # number of demand (read+write) MSHR hits
1921system.cpu3.dcache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
1922system.cpu3.dcache.overall_mshr_hits::cpu3.data 310 # number of overall MSHR hits
1923system.cpu3.dcache.overall_mshr_hits::total 310 # number of overall MSHR hits
1924system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
1925system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
1926system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
1927system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1928system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 61 # number of SwapReq MSHR misses
1929system.cpu3.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses
1930system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses
1931system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses
1932system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses
1933system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
1934system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1797000 # number of ReadReq MSHR miss cycles
1935system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1797000 # number of ReadReq MSHR miss cycles
1936system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1508500 # number of WriteReq MSHR miss cycles
1937system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1508500 # number of WriteReq MSHR miss cycles
1938system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 978500 # number of SwapReq MSHR miss cycles
1939system.cpu3.dcache.SwapReq_mshr_miss_latency::total 978500 # number of SwapReq MSHR miss cycles
1940system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3305500 # number of demand (read+write) MSHR miss cycles
1941system.cpu3.dcache.demand_mshr_miss_latency::total 3305500 # number of demand (read+write) MSHR miss cycles
1942system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3305500 # number of overall MSHR miss cycles
1943system.cpu3.dcache.overall_mshr_miss_latency::total 3305500 # number of overall MSHR miss cycles
1944system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003025 # mshr miss rate for ReadReq accesses
1945system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003025 # mshr miss rate for ReadReq accesses
1946system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002398 # mshr miss rate for WriteReq accesses
1947system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002398 # mshr miss rate for WriteReq accesses
1948system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835616 # mshr miss rate for SwapReq accesses
1949system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835616 # mshr miss rate for SwapReq accesses
1950system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for demand accesses
1951system.cpu3.dcache.demand_mshr_miss_rate::total 0.002742 # mshr miss rate for demand accesses
1952system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for overall accesses
1953system.cpu3.dcache.overall_mshr_miss_rate::total 0.002742 # mshr miss rate for overall accesses
1954system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000 # average ReadReq mshr miss latency
1955system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000 # average ReadReq mshr miss latency
1956system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692 # average WriteReq mshr miss latency
1957system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692 # average WriteReq mshr miss latency
1958system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607 # average SwapReq mshr miss latency
1959system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607 # average SwapReq mshr miss latency
1960system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency
1961system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency
1962system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency
1963system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency
| 1916system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 206 # number of ReadReq MSHR hits
1917system.cpu3.dcache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits
1918system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits
1919system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
1920system.cpu3.dcache.demand_mshr_hits::cpu3.data 239 # number of demand (read+write) MSHR hits
1921system.cpu3.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits
1922system.cpu3.dcache.overall_mshr_hits::cpu3.data 239 # number of overall MSHR hits
1923system.cpu3.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits
1924system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses
1925system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
1926system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
1927system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
1928system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses
1929system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
1930system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses
1931system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
1932system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses
1933system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
1934system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2585504 # number of ReadReq MSHR miss cycles
1935system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2585504 # number of ReadReq MSHR miss cycles
1936system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1735000 # number of WriteReq MSHR miss cycles
1937system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1735000 # number of WriteReq MSHR miss cycles
1938system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1134500 # number of SwapReq MSHR miss cycles
1939system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1134500 # number of SwapReq MSHR miss cycles
1940system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4320504 # number of demand (read+write) MSHR miss cycles
1941system.cpu3.dcache.demand_mshr_miss_latency::total 4320504 # number of demand (read+write) MSHR miss cycles
1942system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4320504 # number of overall MSHR miss cycles
1943system.cpu3.dcache.overall_mshr_miss_latency::total 4320504 # number of overall MSHR miss cycles
1944system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003259 # mshr miss rate for ReadReq accesses
1945system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003259 # mshr miss rate for ReadReq accesses
1946system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002924 # mshr miss rate for WriteReq accesses
1947system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002924 # mshr miss rate for WriteReq accesses
1948system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses
1949system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses
1950system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for demand accesses
1951system.cpu3.dcache.demand_mshr_miss_rate::total 0.003113 # mshr miss rate for demand accesses
1952system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for overall accesses
1953system.cpu3.dcache.overall_mshr_miss_rate::total 0.003113 # mshr miss rate for overall accesses
1954system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968 # average ReadReq mshr miss latency
1955system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968 # average ReadReq mshr miss latency
1956system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271 # average WriteReq mshr miss latency
1957system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271 # average WriteReq mshr miss latency
1958system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727 # average SwapReq mshr miss latency
1959system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727 # average SwapReq mshr miss latency
1960system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency
1961system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency
1962system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency
1963system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency
|
1964system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1965system.l2c.replacements 0 # number of replacements
| 1964system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1965system.l2c.replacements 0 # number of replacements
|
1966system.l2c.tagsinuse 436.530480 # Cycle average of tags in use
1967system.l2c.total_refs 1479 # Total number of references to valid blocks.
1968system.l2c.sampled_refs 536 # Sample count of references to valid blocks.
1969system.l2c.avg_refs 2.759328 # Average number of references to valid blocks.
| 1966system.l2c.tagsinuse 436.890326 # Cycle average of tags in use
1967system.l2c.total_refs 1480 # Total number of references to valid blocks.
1968system.l2c.sampled_refs 538 # Sample count of references to valid blocks.
1969system.l2c.avg_refs 2.750929 # Average number of references to valid blocks.
|
1970system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1970system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1971system.l2c.occ_blocks::writebacks 0.840422 # Average occupied blocks per requestor
1972system.l2c.occ_blocks::cpu0.inst 294.533073 # Average occupied blocks per requestor
1973system.l2c.occ_blocks::cpu0.data 59.606311 # Average occupied blocks per requestor
1974system.l2c.occ_blocks::cpu1.inst 70.480803 # Average occupied blocks per requestor
1975system.l2c.occ_blocks::cpu1.data 5.728880 # Average occupied blocks per requestor
1976system.l2c.occ_blocks::cpu2.inst 1.673039 # Average occupied blocks per requestor
1977system.l2c.occ_blocks::cpu2.data 0.734409 # Average occupied blocks per requestor
1978system.l2c.occ_blocks::cpu3.inst 2.156423 # Average occupied blocks per requestor
1979system.l2c.occ_blocks::cpu3.data 0.777117 # Average occupied blocks per requestor
| 1971system.l2c.occ_blocks::writebacks 0.838452 # Average occupied blocks per requestor
1972system.l2c.occ_blocks::cpu0.inst 294.676580 # Average occupied blocks per requestor
1973system.l2c.occ_blocks::cpu0.data 59.534459 # Average occupied blocks per requestor
1974system.l2c.occ_blocks::cpu1.inst 68.181124 # Average occupied blocks per requestor
1975system.l2c.occ_blocks::cpu1.data 5.702984 # Average occupied blocks per requestor
1976system.l2c.occ_blocks::cpu2.inst 2.344879 # Average occupied blocks per requestor
1977system.l2c.occ_blocks::cpu2.data 0.730463 # Average occupied blocks per requestor
1978system.l2c.occ_blocks::cpu3.inst 4.107761 # Average occupied blocks per requestor
1979system.l2c.occ_blocks::cpu3.data 0.773625 # Average occupied blocks per requestor
|
1980system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
| 1980system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
|
1981system.l2c.occ_percent::cpu0.inst 0.004494 # Average percentage of cache occupancy
1982system.l2c.occ_percent::cpu0.data 0.000910 # Average percentage of cache occupancy
1983system.l2c.occ_percent::cpu1.inst 0.001075 # Average percentage of cache occupancy
| 1981system.l2c.occ_percent::cpu0.inst 0.004496 # Average percentage of cache occupancy
1982system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy
1983system.l2c.occ_percent::cpu1.inst 0.001040 # Average percentage of cache occupancy
|
1984system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy
| 1984system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy
|
1985system.l2c.occ_percent::cpu2.inst 0.000026 # Average percentage of cache occupancy
| 1985system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
|
1986system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
| 1986system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
|
1987system.l2c.occ_percent::cpu3.inst 0.000033 # Average percentage of cache occupancy
| 1987system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy
|
1988system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
| 1988system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
|
1989system.l2c.occ_percent::total 0.006661 # Average percentage of cache occupancy
1990system.l2c.ReadReq_hits::cpu0.inst 238 # number of ReadReq hits
| 1989system.l2c.occ_percent::total 0.006666 # Average percentage of cache occupancy
1990system.l2c.ReadReq_hits::cpu0.inst 239 # number of ReadReq hits
|
1991system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
| 1991system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
1992system.l2c.ReadReq_hits::cpu1.inst 347 # number of ReadReq hits
| 1992system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits
|
1993system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
| 1993system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
|
1994system.l2c.ReadReq_hits::cpu2.inst 431 # number of ReadReq hits
| 1994system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits
|
1995system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
1996system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits
1997system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
| 1995system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
1996system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits
1997system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
1998system.l2c.ReadReq_hits::total 1479 # number of ReadReq hits
| 1998system.l2c.ReadReq_hits::total 1480 # number of ReadReq hits
|
1999system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
2000system.l2c.Writeback_hits::total 1 # number of Writeback hits
2001system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2002system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
| 1999system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
2000system.l2c.Writeback_hits::total 1 # number of Writeback hits
2001system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2002system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
2003system.l2c.demand_hits::cpu0.inst 238 # number of demand (read+write) hits
| 2003system.l2c.demand_hits::cpu0.inst 239 # number of demand (read+write) hits
|
2004system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
| 2004system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
2005system.l2c.demand_hits::cpu1.inst 347 # number of demand (read+write) hits
| 2005system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits
|
2006system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
| 2006system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
2007system.l2c.demand_hits::cpu2.inst 431 # number of demand (read+write) hits
| 2007system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits
|
2008system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
2009system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits
2010system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
| 2008system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
2009system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits
2010system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
2011system.l2c.demand_hits::total 1479 # number of demand (read+write) hits
2012system.l2c.overall_hits::cpu0.inst 238 # number of overall hits
| 2011system.l2c.demand_hits::total 1480 # number of demand (read+write) hits
2012system.l2c.overall_hits::cpu0.inst 239 # number of overall hits
|
2013system.l2c.overall_hits::cpu0.data 5 # number of overall hits
| 2013system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
2014system.l2c.overall_hits::cpu1.inst 347 # number of overall hits
| 2014system.l2c.overall_hits::cpu1.inst 350 # number of overall hits
|
2015system.l2c.overall_hits::cpu1.data 5 # number of overall hits
| 2015system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
2016system.l2c.overall_hits::cpu2.inst 431 # number of overall hits
| 2016system.l2c.overall_hits::cpu2.inst 428 # number of overall hits
|
2017system.l2c.overall_hits::cpu2.data 11 # number of overall hits
2018system.l2c.overall_hits::cpu3.inst 431 # number of overall hits
2019system.l2c.overall_hits::cpu3.data 11 # number of overall hits
| 2017system.l2c.overall_hits::cpu2.data 11 # number of overall hits
2018system.l2c.overall_hits::cpu3.inst 431 # number of overall hits
2019system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
2020system.l2c.overall_hits::total 1479 # number of overall hits
2021system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses
2022system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
2023system.l2c.ReadReq_misses::cpu1.inst 89 # number of ReadReq misses
| 2020system.l2c.overall_hits::total 1480 # number of overall hits
2021system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses
2022system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
2023system.l2c.ReadReq_misses::cpu1.inst 86 # number of ReadReq misses
|
2024system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
| 2024system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
|
2025system.l2c.ReadReq_misses::cpu2.inst 7 # number of ReadReq misses
| 2025system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses
|
2026system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
| 2026system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
|
2027system.l2c.ReadReq_misses::cpu3.inst 5 # number of ReadReq misses
| 2027system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses
|
2028system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
| 2028system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
2029system.l2c.ReadReq_misses::total 546 # number of ReadReq misses
2030system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses
2031system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses
2032system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
| 2029system.l2c.ReadReq_misses::total 550 # number of ReadReq misses
2030system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses
2031system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
2032system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses
|
2033system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
| 2033system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
2034system.l2c.UpgradeReq_misses::total 81 # number of UpgradeReq misses
| 2034system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses
|
2035system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2036system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2037system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2038system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2039system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
| 2035system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2036system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2037system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2038system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2039system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
2040system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses
2041system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
2042system.l2c.demand_misses::cpu1.inst 89 # number of demand (read+write) misses
| 2040system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses
2041system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
2042system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
|
2043system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
| 2043system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
2044system.l2c.demand_misses::cpu2.inst 7 # number of demand (read+write) misses
| 2044system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses
|
2045system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
| 2045system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
2046system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
| 2046system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses
|
2047system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
| 2047system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
2048system.l2c.demand_misses::total 677 # number of demand (read+write) misses
2049system.l2c.overall_misses::cpu0.inst 361 # number of overall misses
2050system.l2c.overall_misses::cpu0.data 169 # number of overall misses
2051system.l2c.overall_misses::cpu1.inst 89 # number of overall misses
| 2048system.l2c.demand_misses::total 681 # number of demand (read+write) misses
2049system.l2c.overall_misses::cpu0.inst 363 # number of overall misses
2050system.l2c.overall_misses::cpu0.data 168 # number of overall misses
2051system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
|
2052system.l2c.overall_misses::cpu1.data 20 # number of overall misses
| 2052system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
2053system.l2c.overall_misses::cpu2.inst 7 # number of overall misses
| 2053system.l2c.overall_misses::cpu2.inst 10 # number of overall misses
|
2054system.l2c.overall_misses::cpu2.data 13 # number of overall misses
| 2054system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
2055system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
| 2055system.l2c.overall_misses::cpu3.inst 8 # number of overall misses
|
2056system.l2c.overall_misses::cpu3.data 13 # number of overall misses
| 2056system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
2057system.l2c.overall_misses::total 677 # number of overall misses
2058system.l2c.ReadReq_miss_latency::cpu0.inst 18817000 # number of ReadReq miss cycles
2059system.l2c.ReadReq_miss_latency::cpu0.data 3930500 # number of ReadReq miss cycles
2060system.l2c.ReadReq_miss_latency::cpu1.inst 4612000 # number of ReadReq miss cycles
2061system.l2c.ReadReq_miss_latency::cpu1.data 366000 # number of ReadReq miss cycles
2062system.l2c.ReadReq_miss_latency::cpu2.inst 304000 # number of ReadReq miss cycles
| 2057system.l2c.overall_misses::total 681 # number of overall misses
2058system.l2c.ReadReq_miss_latency::cpu0.inst 19255500 # number of ReadReq miss cycles
2059system.l2c.ReadReq_miss_latency::cpu0.data 4177000 # number of ReadReq miss cycles
2060system.l2c.ReadReq_miss_latency::cpu1.inst 4495500 # number of ReadReq miss cycles
2061system.l2c.ReadReq_miss_latency::cpu1.data 377500 # number of ReadReq miss cycles
2062system.l2c.ReadReq_miss_latency::cpu2.inst 449500 # number of ReadReq miss cycles
|
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2064system.l2c.ReadReq_miss_latency::cpu3.inst 254000 # number of ReadReq miss cycles
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|
2065system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles
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|
2066system.l2c.ReadReq_miss_latency::total 28388500 # number of ReadReq miss cycles
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2089system.l2c.overall_miss_latency::total 36483999 # number of overall miss cycles
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|
2092system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses)
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2095system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
| 2092system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses)
2093system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
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2095system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
|
2096system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses)
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|
2097system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
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|
2098system.l2c.ReadReq_accesses::total 2025 # number of ReadReq accesses(hits+misses)
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|
2099system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
2100system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
| 2099system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
2100system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
2101system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses)
2102system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses)
2103system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
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2102system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses)
2103system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
|
2104system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
| 2104system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
|
2105system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses)
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|
2106system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
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2109system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2110system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
| 2106system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2107system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2108system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2109system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2110system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
2111system.l2c.demand_accesses::cpu0.inst 599 # number of demand (read+write) accesses
2112system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
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2112system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
|
2113system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses
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2114system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
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2116system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
|
2117system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses
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|
2118system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
| 2118system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
2119system.l2c.demand_accesses::total 2156 # number of demand (read+write) accesses
2120system.l2c.overall_accesses::cpu0.inst 599 # number of overall (read+write) accesses
2121system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
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2120system.l2c.overall_accesses::cpu0.inst 602 # number of overall (read+write) accesses
2121system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
|
2122system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses
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2125system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
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2123system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
2124system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses
2125system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
|
2126system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses
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|
2127system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
| 2127system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
2128system.l2c.overall_accesses::total 2156 # number of overall (read+write) accesses
2129system.l2c.ReadReq_miss_rate::cpu0.inst 0.602671 # miss rate for ReadReq accesses
2130system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
2131system.l2c.ReadReq_miss_rate::cpu1.inst 0.204128 # miss rate for ReadReq accesses
| 2128system.l2c.overall_accesses::total 2161 # number of overall (read+write) accesses
2129system.l2c.ReadReq_miss_rate::cpu0.inst 0.602990 # miss rate for ReadReq accesses
2130system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
2131system.l2c.ReadReq_miss_rate::cpu1.inst 0.197248 # miss rate for ReadReq accesses
|
2132system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
| 2132system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
|
2133system.l2c.ReadReq_miss_rate::cpu2.inst 0.015982 # miss rate for ReadReq accesses
| 2133system.l2c.ReadReq_miss_rate::cpu2.inst 0.022831 # miss rate for ReadReq accesses
|
2134system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
| 2134system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
|
2135system.l2c.ReadReq_miss_rate::cpu3.inst 0.011468 # miss rate for ReadReq accesses
| 2135system.l2c.ReadReq_miss_rate::cpu3.inst 0.018223 # miss rate for ReadReq accesses
|
2136system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
| 2136system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
|
2137system.l2c.ReadReq_miss_rate::total 0.269630 # miss rate for ReadReq accesses
2138system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses
| 2137system.l2c.ReadReq_miss_rate::total 0.270936 # miss rate for ReadReq accesses
2138system.l2c.UpgradeReq_miss_rate::cpu0.data 0.869565 # miss rate for UpgradeReq accesses
|
2139system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2140system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2141system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
| 2139system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2140system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2141system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
2142system.l2c.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses
| 2142system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses
|
2143system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2144system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2145system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2146system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2147system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
| 2143system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2144system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2145system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2146system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2147system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2148system.l2c.demand_miss_rate::cpu0.inst 0.602671 # miss rate for demand accesses
2149system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
2150system.l2c.demand_miss_rate::cpu1.inst 0.204128 # miss rate for demand accesses
| 2148system.l2c.demand_miss_rate::cpu0.inst 0.602990 # miss rate for demand accesses
2149system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
2150system.l2c.demand_miss_rate::cpu1.inst 0.197248 # miss rate for demand accesses
|
2151system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
| 2151system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
|
2152system.l2c.demand_miss_rate::cpu2.inst 0.015982 # miss rate for demand accesses
| 2152system.l2c.demand_miss_rate::cpu2.inst 0.022831 # miss rate for demand accesses
|
2153system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
| 2153system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
|
2154system.l2c.demand_miss_rate::cpu3.inst 0.011468 # miss rate for demand accesses
| 2154system.l2c.demand_miss_rate::cpu3.inst 0.018223 # miss rate for demand accesses
|
2155system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
| 2155system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
|
2156system.l2c.demand_miss_rate::total 0.314007 # miss rate for demand accesses
2157system.l2c.overall_miss_rate::cpu0.inst 0.602671 # miss rate for overall accesses
2158system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2159system.l2c.overall_miss_rate::cpu1.inst 0.204128 # miss rate for overall accesses
| 2156system.l2c.demand_miss_rate::total 0.315132 # miss rate for demand accesses
2157system.l2c.overall_miss_rate::cpu0.inst 0.602990 # miss rate for overall accesses
2158system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
2159system.l2c.overall_miss_rate::cpu1.inst 0.197248 # miss rate for overall accesses
|
2160system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
| 2160system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
|
2161system.l2c.overall_miss_rate::cpu2.inst 0.015982 # miss rate for overall accesses
| 2161system.l2c.overall_miss_rate::cpu2.inst 0.022831 # miss rate for overall accesses
|
2162system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
| 2162system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
|
2163system.l2c.overall_miss_rate::cpu3.inst 0.011468 # miss rate for overall accesses
| 2163system.l2c.overall_miss_rate::cpu3.inst 0.018223 # miss rate for overall accesses
|
2164system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
| 2164system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
|
2165system.l2c.overall_miss_rate::total 0.314007 # miss rate for overall accesses
2166system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52124.653740 # average ReadReq miss latency
2167system.l2c.ReadReq_avg_miss_latency::cpu0.data 52406.666667 # average ReadReq miss latency
2168system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51820.224719 # average ReadReq miss latency
2169system.l2c.ReadReq_avg_miss_latency::cpu1.data 52285.714286 # average ReadReq miss latency
2170system.l2c.ReadReq_avg_miss_latency::cpu2.inst 43428.571429 # average ReadReq miss latency
| 2165system.l2c.overall_miss_rate::total 0.315132 # miss rate for overall accesses
2166system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.454545 # average ReadReq miss latency
2167system.l2c.ReadReq_avg_miss_latency::cpu0.data 56445.945946 # average ReadReq miss latency
2168system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.255814 # average ReadReq miss latency
2169system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429 # average ReadReq miss latency
2170system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44950 # average ReadReq miss latency
|
2171system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency
| 2171system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency
|
2172system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50800 # average ReadReq miss latency
| 2172system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48500 # average ReadReq miss latency
|
2173system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
| 2173system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
|
2174system.l2c.ReadReq_avg_miss_latency::total 51993.589744 # average ReadReq miss latency
2175system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52537.234043 # average ReadExReq miss latency
2176system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52423.076923 # average ReadExReq miss latency
2177system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52458.333333 # average ReadExReq miss latency
2178system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52333.333333 # average ReadExReq miss latency
2179system.l2c.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
2180system.l2c.demand_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency
2181system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2182system.l2c.demand_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency
2183system.l2c.demand_avg_miss_latency::cpu1.data 52375 # average overall miss latency
2184system.l2c.demand_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency
2185system.l2c.demand_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency
2186system.l2c.demand_avg_miss_latency::cpu3.inst 50800 # average overall miss latency
2187system.l2c.demand_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency
2188system.l2c.demand_avg_miss_latency::total 52091.580502 # average overall miss latency
2189system.l2c.overall_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency
2190system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency
2191system.l2c.overall_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency
2192system.l2c.overall_avg_miss_latency::cpu1.data 52375 # average overall miss latency
2193system.l2c.overall_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency
2194system.l2c.overall_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency
2195system.l2c.overall_avg_miss_latency::cpu3.inst 50800 # average overall miss latency
2196system.l2c.overall_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency
2197system.l2c.overall_avg_miss_latency::total 52091.580502 # average overall miss latency
| 2174system.l2c.ReadReq_avg_miss_latency::total 53178.181818 # average ReadReq miss latency
2175system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54930.851064 # average ReadExReq miss latency
2176system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769 # average ReadExReq miss latency
2177system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55250 # average ReadExReq miss latency
2178system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667 # average ReadExReq miss latency
2179system.l2c.ReadExReq_avg_miss_latency::total 55236.633588 # average ReadExReq miss latency
2180system.l2c.demand_avg_miss_latency::cpu0.inst 53045.454545 # average overall miss latency
2181system.l2c.demand_avg_miss_latency::cpu0.data 55598.214286 # average overall miss latency
2182system.l2c.demand_avg_miss_latency::cpu1.inst 52273.255814 # average overall miss latency
2183system.l2c.demand_avg_miss_latency::cpu1.data 56425 # average overall miss latency
2184system.l2c.demand_avg_miss_latency::cpu2.inst 44950 # average overall miss latency
2185system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency
2186system.l2c.demand_avg_miss_latency::cpu3.inst 48500 # average overall miss latency
2187system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency
2188system.l2c.demand_avg_miss_latency::total 53574.154185 # average overall miss latency
2189system.l2c.overall_avg_miss_latency::cpu0.inst 53045.454545 # average overall miss latency
2190system.l2c.overall_avg_miss_latency::cpu0.data 55598.214286 # average overall miss latency
2191system.l2c.overall_avg_miss_latency::cpu1.inst 52273.255814 # average overall miss latency
2192system.l2c.overall_avg_miss_latency::cpu1.data 56425 # average overall miss latency
2193system.l2c.overall_avg_miss_latency::cpu2.inst 44950 # average overall miss latency
2194system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency
2195system.l2c.overall_avg_miss_latency::cpu3.inst 48500 # average overall miss latency
2196system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency
2197system.l2c.overall_avg_miss_latency::total 53574.154185 # average overall miss latency
|
2198system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2199system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2200system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2201system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2202system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2203system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2204system.l2c.fast_writes 0 # number of fast writes performed
2205system.l2c.cache_copies 0 # number of cache copies performed
| 2198system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2199system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2200system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2201system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2202system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2203system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2204system.l2c.fast_writes 0 # number of fast writes performed
2205system.l2c.cache_copies 0 # number of cache copies performed
|
2206system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
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|
2207system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits
| 2207system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits
|
2208system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits
2209system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
2210system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
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2209system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
2210system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
|
2211system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
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|
2212system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
2213system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
2214system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
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2213system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
2214system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
|
2215system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
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|
2216system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
2217system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
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2219system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses
2220system.l2c.ReadReq_mshr_misses::cpu1.inst 88 # number of ReadReq MSHR misses
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2217system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
2218system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses
2219system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
2220system.l2c.ReadReq_mshr_misses::cpu1.inst 84 # number of ReadReq MSHR misses
|
2221system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
| 2221system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
|
2222system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses
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|
2223system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
| 2223system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
|
2224system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses
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|
2225system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
| 2225system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
|
2226system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses
2227system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses
2228system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses
2229system.l2c.UpgradeReq_mshr_misses::cpu2.data 19 # number of UpgradeReq MSHR misses
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2227system.l2c.UpgradeReq_mshr_misses::cpu0.data 20 # number of UpgradeReq MSHR misses
2228system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses
2229system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
|
2230system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
| 2230system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
|
2231system.l2c.UpgradeReq_mshr_misses::total 81 # number of UpgradeReq MSHR misses
| 2231system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses
|
2232system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2233system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
2234system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2235system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2236system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
| 2232system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2233system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
2234system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2235system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2236system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
|
2237system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses
2238system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
2239system.l2c.demand_mshr_misses::cpu1.inst 88 # number of demand (read+write) MSHR misses
| 2237system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses
2238system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
2239system.l2c.demand_mshr_misses::cpu1.inst 84 # number of demand (read+write) MSHR misses
|
2240system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
| 2240system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
|
2241system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses
| 2241system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses
|
2242system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
| 2242system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
|
2243system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses
| 2243system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses
|
2244system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
| 2244system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
|
2245system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses
2246system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses
2247system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
2248system.l2c.overall_mshr_misses::cpu1.inst 88 # number of overall MSHR misses
| 2245system.l2c.demand_mshr_misses::total 672 # number of demand (read+write) MSHR misses
2246system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses
2247system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
2248system.l2c.overall_mshr_misses::cpu1.inst 84 # number of overall MSHR misses
|
2249system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
| 2249system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
|
2250system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses
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|
2251system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
| 2251system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
|
2252system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses
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|
2253system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
| 2253system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
2254system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses
2255system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14412000 # number of ReadReq MSHR miss cycles
2256system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3017000 # number of ReadReq MSHR miss cycles
2257system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3521000 # number of ReadReq MSHR miss cycles
2258system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles
2259system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles
| 2254system.l2c.overall_mshr_misses::total 672 # number of overall MSHR misses
2255system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14840000 # number of ReadReq MSHR miss cycles
2256system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3282500 # number of ReadReq MSHR miss cycles
2257system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420000 # number of ReadReq MSHR miss cycles
2258system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291500 # number of ReadReq MSHR miss cycles
2259system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles
|
2260system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
| 2260system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
|
2261system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 160000 # number of ReadReq MSHR miss cycles
| 2261system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles
|
2262system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
| 2262system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
|
2263system.l2c.ReadReq_mshr_miss_latency::total 21550000 # number of ReadReq MSHR miss cycles
2264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 920000 # number of UpgradeReq MSHR miss cycles
2265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 800000 # number of UpgradeReq MSHR miss cycles
2266system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 760000 # number of UpgradeReq MSHR miss cycles
2267system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 760500 # number of UpgradeReq MSHR miss cycles
2268system.l2c.UpgradeReq_mshr_miss_latency::total 3240500 # number of UpgradeReq MSHR miss cycles
2269system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3791500 # number of ReadExReq MSHR miss cycles
2270system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 522500 # number of ReadExReq MSHR miss cycles
2271system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 483500 # number of ReadExReq MSHR miss cycles
2272system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles
2273system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles
2274system.l2c.demand_mshr_miss_latency::cpu0.inst 14412000 # number of demand (read+write) MSHR miss cycles
2275system.l2c.demand_mshr_miss_latency::cpu0.data 6808500 # number of demand (read+write) MSHR miss cycles
2276system.l2c.demand_mshr_miss_latency::cpu1.inst 3521000 # number of demand (read+write) MSHR miss cycles
2277system.l2c.demand_mshr_miss_latency::cpu1.data 802500 # number of demand (read+write) MSHR miss cycles
2278system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles
2279system.l2c.demand_mshr_miss_latency::cpu2.data 523500 # number of demand (read+write) MSHR miss cycles
2280system.l2c.demand_mshr_miss_latency::cpu3.inst 160000 # number of demand (read+write) MSHR miss cycles
2281system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles
2282system.l2c.demand_mshr_miss_latency::total 26829000 # number of demand (read+write) MSHR miss cycles
2283system.l2c.overall_mshr_miss_latency::cpu0.inst 14412000 # number of overall MSHR miss cycles
2284system.l2c.overall_mshr_miss_latency::cpu0.data 6808500 # number of overall MSHR miss cycles
2285system.l2c.overall_mshr_miss_latency::cpu1.inst 3521000 # number of overall MSHR miss cycles
2286system.l2c.overall_mshr_miss_latency::cpu1.data 802500 # number of overall MSHR miss cycles
2287system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles
2288system.l2c.overall_mshr_miss_latency::cpu2.data 523500 # number of overall MSHR miss cycles
2289system.l2c.overall_mshr_miss_latency::cpu3.inst 160000 # number of overall MSHR miss cycles
2290system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles
2291system.l2c.overall_mshr_miss_latency::total 26829000 # number of overall MSHR miss cycles
2292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for ReadReq accesses
2293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for ReadReq accesses
| 2263system.l2c.ReadReq_mshr_miss_latency::total 22354000 # number of ReadReq MSHR miss cycles
2264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles
2265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600000 # number of UpgradeReq MSHR miss cycles
2266system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles
2267system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 765000 # number of UpgradeReq MSHR miss cycles
2268system.l2c.UpgradeReq_mshr_miss_latency::total 3009000 # number of UpgradeReq MSHR miss cycles
2269system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4019000 # number of ReadExReq MSHR miss cycles
2270system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles
2271system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles
2272system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles
2273system.l2c.ReadExReq_mshr_miss_latency::total 5640500 # number of ReadExReq MSHR miss cycles
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2275system.l2c.demand_mshr_miss_latency::cpu0.data 7301500 # number of demand (read+write) MSHR miss cycles
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2277system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles
2278system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles
2279system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles
2280system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles
2281system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles
2282system.l2c.demand_mshr_miss_latency::total 27994500 # number of demand (read+write) MSHR miss cycles
2283system.l2c.overall_mshr_miss_latency::cpu0.inst 14840000 # number of overall MSHR miss cycles
2284system.l2c.overall_mshr_miss_latency::cpu0.data 7301500 # number of overall MSHR miss cycles
2285system.l2c.overall_mshr_miss_latency::cpu1.inst 3420000 # number of overall MSHR miss cycles
2286system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles
2287system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles
2288system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles
2289system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles
2290system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles
2291system.l2c.overall_mshr_miss_latency::total 27994500 # number of overall MSHR miss cycles
2292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for ReadReq accesses
2293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
2294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses
|
2295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
| 2295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
|
2296system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for ReadReq accesses
| 2296system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for ReadReq accesses
|
2297system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
| 2297system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
|
2298system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for ReadReq accesses
| 2298system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses
|
2299system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
| 2299system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
|
2300system.l2c.ReadReq_mshr_miss_rate::total 0.266173 # mshr miss rate for ReadReq accesses
2301system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses
| 2300system.l2c.ReadReq_mshr_miss_rate::total 0.266502 # mshr miss rate for ReadReq accesses
2301system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses
|
2302system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2303system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2304system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
| 2302system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2303system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2304system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
2305system.l2c.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses
| 2305system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses
|
2306system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2307system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2308system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2309system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2310system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
| 2306system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2307system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2308system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2309system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2310system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2311system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for demand accesses
2312system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2313system.l2c.demand_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for demand accesses
| 2311system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for demand accesses
2312system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
2313system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses
|
2314system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
| 2314system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
2315system.l2c.demand_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for demand accesses
| 2315system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for demand accesses
|
2316system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
| 2316system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
2317system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses
| 2317system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses
|
2318system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
| 2318system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
2319system.l2c.demand_mshr_miss_rate::total 0.310761 # mshr miss rate for demand accesses
2320system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for overall accesses
2321system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2322system.l2c.overall_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for overall accesses
| 2319system.l2c.demand_mshr_miss_rate::total 0.310967 # mshr miss rate for demand accesses
2320system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for overall accesses
2321system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
2322system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses
|
2323system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
| 2323system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
2324system.l2c.overall_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for overall accesses
| 2324system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses
|
2325system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
| 2325system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
2326system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses
| 2326system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses
|
2327system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
| 2327system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
2328system.l2c.overall_mshr_miss_rate::total 0.310761 # mshr miss rate for overall accesses
2329system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average ReadReq mshr miss latency
2330system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667 # average ReadReq mshr miss latency
2331system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average ReadReq mshr miss latency
2332system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
| 2328system.l2c.overall_mshr_miss_rate::total 0.310967 # mshr miss rate for overall accesses
2329system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average ReadReq mshr miss latency
2330system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108 # average ReadReq mshr miss latency
2331system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average ReadReq mshr miss latency
2332system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency
|
2333system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2334system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2335system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2336system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
| 2333system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
2334system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
2335system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
2336system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
2337system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency
| 2337system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189 # average ReadReq mshr miss latency
|
2338system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2339system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
| 2338system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
2339system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
|
2340system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
2341system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency
2342system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency
2343system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency
2344system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency
2345system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency
2346system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
2347system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency
2348system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency
2349system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency
2350system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency
2351system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency
| 2340system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency
2341system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895 # average UpgradeReq mshr miss latency
2342system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40120 # average UpgradeReq mshr miss latency
2343system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149 # average ReadExReq mshr miss latency
2344system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency
2345system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency
2346system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency
2347system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908 # average ReadExReq mshr miss latency
2348system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency
2349system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency
2350system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency
2351system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
|
2352system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
| 2352system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
2353system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency
| 2353system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
|
2354system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
| 2354system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
2355system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2356system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency
2357system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency
2358system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency
2359system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency
2360system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency
| 2355system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
2356system.l2c.demand_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency
2357system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency
2358system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency
2359system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency
2360system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
|
2361system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
| 2361system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
2362system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency
| 2362system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
|
2363system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
| 2363system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
2364system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
2365system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency
| 2364system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
2365system.l2c.overall_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency
|
2366system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2367
2368---------- End Simulation Statistics ----------
| 2366system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2367
2368---------- End Simulation Statistics ----------
|