| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 111402500 # Number of ticks simulated 5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 111402500 # Number of ticks simulated 5final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 189621 # Simulator instruction rate (inst/s) 8host_op_rate 189621 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19396106 # Simulator tick rate (ticks/s) 10host_mem_usage 226052 # Number of bytes of host memory used 11host_seconds 5.74 # Real time elapsed on the host | 7host_inst_rate 79928 # Simulator instruction rate (inst/s) 8host_op_rate 79928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8175729 # Simulator tick rate (ticks/s) 10host_mem_usage 236248 # Number of bytes of host memory used 11host_seconds 13.63 # Real time elapsed on the host |
| 12sim_insts 1089093 # Number of instructions simulated 13sim_ops 1089093 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 43072 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 673 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 304 unchanged lines hidden (view full) --- 324system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency 325system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency 326system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency 327system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked 328system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 329system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 330system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 331system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked | 12sim_insts 1089093 # Number of instructions simulated 13sim_ops 1089093 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 43072 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 673 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 304 unchanged lines hidden (view full) --- 324system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency 325system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency 326system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency 327system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked 328system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 329system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 330system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 331system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked |
| 332system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 332system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 333system.cpu0.icache.fast_writes 0 # number of fast writes performed 334system.cpu0.icache.cache_copies 0 # number of cache copies performed 335system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits 336system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits 337system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits 338system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 339system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits 340system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits --- 75 unchanged lines hidden (view full) --- 416system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency 417system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency 418system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency 419system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked 420system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 422system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked | 333system.cpu0.icache.fast_writes 0 # number of fast writes performed 334system.cpu0.icache.cache_copies 0 # number of cache copies performed 335system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits 336system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits 337system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits 338system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 339system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits 340system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits --- 75 unchanged lines hidden (view full) --- 416system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency 417system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency 418system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency 419system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked 420system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 422system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked |
| 424system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 424system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 425system.cpu0.dcache.fast_writes 0 # number of fast writes performed 426system.cpu0.dcache.cache_copies 0 # number of cache copies performed 427system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 428system.cpu0.dcache.writebacks::total 6 # number of writebacks 429system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits 430system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits 431system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 432system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits --- 336 unchanged lines hidden (view full) --- 769system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses 770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency 771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency 772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency 773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 425system.cpu0.dcache.fast_writes 0 # number of fast writes performed 426system.cpu0.dcache.cache_copies 0 # number of cache copies performed 427system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 428system.cpu0.dcache.writebacks::total 6 # number of writebacks 429system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits 430system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits 431system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 432system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits --- 336 unchanged lines hidden (view full) --- 769system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses 770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency 771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency 772system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency 773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 777system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 778system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 779system.cpu1.icache.fast_writes 0 # number of fast writes performed 780system.cpu1.icache.cache_copies 0 # number of cache copies performed 781system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits 782system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 783system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits 784system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 785system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits 786system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 861system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency 862system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency 863system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency 864system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency 865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 779system.cpu1.icache.fast_writes 0 # number of fast writes performed 780system.cpu1.icache.cache_copies 0 # number of cache copies performed 781system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits 782system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 783system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits 784system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 785system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits 786system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 861system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency 862system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency 863system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency 864system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency 865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 869system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 870system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 871system.cpu1.dcache.fast_writes 0 # number of fast writes performed 872system.cpu1.dcache.cache_copies 0 # number of cache copies performed 873system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 874system.cpu1.dcache.writebacks::total 1 # number of writebacks 875system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits 876system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits 877system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits 878system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 337 unchanged lines hidden (view full) --- 1216system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency 1217system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency 1218system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency 1219system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked 1220system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1221system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1222system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1223system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked | 871system.cpu1.dcache.fast_writes 0 # number of fast writes performed 872system.cpu1.dcache.cache_copies 0 # number of cache copies performed 873system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 874system.cpu1.dcache.writebacks::total 1 # number of writebacks 875system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits 876system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits 877system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits 878system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 337 unchanged lines hidden (view full) --- 1216system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency 1217system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency 1218system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency 1219system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked 1220system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1221system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1222system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1223system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked |
| 1224system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1224system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1225system.cpu2.icache.fast_writes 0 # number of fast writes performed 1226system.cpu2.icache.cache_copies 0 # number of cache copies performed 1227system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits 1228system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 1229system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits 1230system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 1231system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits 1232system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 1307system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency 1308system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency 1309system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency 1310system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency 1311system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1312system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1313system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1314system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1225system.cpu2.icache.fast_writes 0 # number of fast writes performed 1226system.cpu2.icache.cache_copies 0 # number of cache copies performed 1227system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits 1228system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 1229system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits 1230system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 1231system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits 1232system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 1307system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency 1308system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency 1309system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency 1310system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency 1311system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1312system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1313system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1314system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1315system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1316system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1315system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1316system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1317system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1318system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1319system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 1320system.cpu2.dcache.writebacks::total 1 # number of writebacks 1321system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits 1322system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 1323system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits 1324system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 336 unchanged lines hidden (view full) --- 1661system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses 1662system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency 1663system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency 1664system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency 1665system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1666system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1667system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1668system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked | 1317system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1318system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1319system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 1320system.cpu2.dcache.writebacks::total 1 # number of writebacks 1321system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits 1322system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 1323system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits 1324system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 336 unchanged lines hidden (view full) --- 1661system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses 1662system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency 1663system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency 1664system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency 1665system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1666system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1667system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1668system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1669system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1670system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1669system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1670system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1671system.cpu3.icache.fast_writes 0 # number of fast writes performed 1672system.cpu3.icache.cache_copies 0 # number of cache copies performed 1673system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits 1674system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 1675system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits 1676system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 1677system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits 1678system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 1753system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency 1754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency 1755system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency 1756system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency 1757system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1758system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1759system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1760system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1671system.cpu3.icache.fast_writes 0 # number of fast writes performed 1672system.cpu3.icache.cache_copies 0 # number of cache copies performed 1673system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits 1674system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 1675system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits 1676system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 1677system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits 1678system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits --- 74 unchanged lines hidden (view full) --- 1753system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency 1754system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency 1755system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency 1756system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency 1757system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1758system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1759system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1760system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1761system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1762system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1761system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1762system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1763system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1764system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1765system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 1766system.cpu3.dcache.writebacks::total 1 # number of writebacks 1767system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits 1768system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits 1769system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits 1770system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 262 unchanged lines hidden (view full) --- 2033system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency 2034system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency 2035system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency 2036system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency 2037system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2038system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2039system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2040system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 1763system.cpu3.dcache.fast_writes 0 # number of fast writes performed 1764system.cpu3.dcache.cache_copies 0 # number of cache copies performed 1765system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 1766system.cpu3.dcache.writebacks::total 1 # number of writebacks 1767system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits 1768system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits 1769system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits 1770system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits --- 262 unchanged lines hidden (view full) --- 2033system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency 2034system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency 2035system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency 2036system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency 2037system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2038system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2039system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2040system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2041system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 2042system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 2041system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2042system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2043system.l2c.fast_writes 0 # number of fast writes performed 2044system.l2c.cache_copies 0 # number of cache copies performed 2045system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 2046system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits 2047system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits 2048system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 2049system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2050system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits --- 147 unchanged lines hidden --- | 2043system.l2c.fast_writes 0 # number of fast writes performed 2044system.l2c.cache_copies 0 # number of cache copies performed 2045system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 2046system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits 2047system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits 2048system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 2049system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2050system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits --- 147 unchanged lines hidden --- |