3sim_seconds 0.000124 # Number of seconds simulated
4sim_ticks 123756000 # Number of ticks simulated
5final_tick 123756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 286843 # Simulator instruction rate (inst/s)
8host_op_rate 286842 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31050897 # Simulator tick rate (ticks/s)
10host_mem_usage 266468 # Number of bytes of host memory used
11host_seconds 3.99 # Real time elapsed on the host
12sim_insts 1143228 # Number of instructions simulated
13sim_ops 1143228 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 23616 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 6016 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.inst 768 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu2.data 896 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.inst 832 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory
25system.physmem.bytes_read::total 45248 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 23616 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 6016 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu2.inst 768 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu3.inst 832 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 31232 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 369 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.inst 94 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.inst 12 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu2.data 14 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.inst 13 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory
39system.physmem.num_reads::total 707 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 190827111 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 87397783 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 48611784 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 11377226 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 6205760 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 7240053 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 6722906 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 7240053 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 365622677 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 190827111 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 48611784 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 6205760 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 6722906 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 252367562 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 190827111 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 87397783 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 48611784 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 11377226 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 6205760 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 7240053 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 6722906 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 7240053 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 365622677 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.readReqs 707 # Number of read requests accepted
64system.physmem.writeReqs 0 # Number of write requests accepted
65system.physmem.readBursts 707 # Number of DRAM read bursts, including those serviced by the write queue
66system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
67system.physmem.bytesReadDRAM 45248 # Total number of bytes read from DRAM
68system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
69system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
70system.physmem.bytesReadSys 45248 # Total read bytes from the system interface side
71system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
72system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
73system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
74system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
75system.physmem.perBankRdBursts::0 118 # Per bank write bursts
76system.physmem.perBankRdBursts::1 45 # Per bank write bursts
77system.physmem.perBankRdBursts::2 32 # Per bank write bursts
78system.physmem.perBankRdBursts::3 63 # Per bank write bursts
79system.physmem.perBankRdBursts::4 69 # Per bank write bursts
80system.physmem.perBankRdBursts::5 27 # Per bank write bursts
81system.physmem.perBankRdBursts::6 19 # Per bank write bursts
82system.physmem.perBankRdBursts::7 27 # Per bank write bursts
83system.physmem.perBankRdBursts::8 7 # Per bank write bursts
84system.physmem.perBankRdBursts::9 29 # Per bank write bursts
85system.physmem.perBankRdBursts::10 23 # Per bank write bursts
86system.physmem.perBankRdBursts::11 13 # Per bank write bursts
87system.physmem.perBankRdBursts::12 70 # Per bank write bursts
88system.physmem.perBankRdBursts::13 47 # Per bank write bursts
89system.physmem.perBankRdBursts::14 18 # Per bank write bursts
90system.physmem.perBankRdBursts::15 100 # Per bank write bursts
91system.physmem.perBankWrBursts::0 0 # Per bank write bursts
92system.physmem.perBankWrBursts::1 0 # Per bank write bursts
93system.physmem.perBankWrBursts::2 0 # Per bank write bursts
94system.physmem.perBankWrBursts::3 0 # Per bank write bursts
95system.physmem.perBankWrBursts::4 0 # Per bank write bursts
96system.physmem.perBankWrBursts::5 0 # Per bank write bursts
97system.physmem.perBankWrBursts::6 0 # Per bank write bursts
98system.physmem.perBankWrBursts::7 0 # Per bank write bursts
99system.physmem.perBankWrBursts::8 0 # Per bank write bursts
100system.physmem.perBankWrBursts::9 0 # Per bank write bursts
101system.physmem.perBankWrBursts::10 0 # Per bank write bursts
102system.physmem.perBankWrBursts::11 0 # Per bank write bursts
103system.physmem.perBankWrBursts::12 0 # Per bank write bursts
104system.physmem.perBankWrBursts::13 0 # Per bank write bursts
105system.physmem.perBankWrBursts::14 0 # Per bank write bursts
106system.physmem.perBankWrBursts::15 0 # Per bank write bursts
107system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
108system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
109system.physmem.totGap 123516000 # Total gap between requests
110system.physmem.readPktSize::0 0 # Read request sizes (log2)
111system.physmem.readPktSize::1 0 # Read request sizes (log2)
112system.physmem.readPktSize::2 0 # Read request sizes (log2)
113system.physmem.readPktSize::3 0 # Read request sizes (log2)
114system.physmem.readPktSize::4 0 # Read request sizes (log2)
115system.physmem.readPktSize::5 0 # Read request sizes (log2)
116system.physmem.readPktSize::6 707 # Read request sizes (log2)
117system.physmem.writePktSize::0 0 # Write request sizes (log2)
118system.physmem.writePktSize::1 0 # Write request sizes (log2)
119system.physmem.writePktSize::2 0 # Write request sizes (log2)
120system.physmem.writePktSize::3 0 # Write request sizes (log2)
121system.physmem.writePktSize::4 0 # Write request sizes (log2)
122system.physmem.writePktSize::5 0 # Write request sizes (log2)
123system.physmem.writePktSize::6 0 # Write request sizes (log2)
124system.physmem.rdQLenPdf::0 412 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::1 215 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
156system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
220system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation
221system.physmem.bytesPerActivate::mean 251.834320 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::gmean 169.411435 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::stdev 244.318432 # Bytes accessed per row activation
224system.physmem.bytesPerActivate::0-127 58 34.32% 34.32% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::128-255 48 28.40% 62.72% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::256-383 26 15.38% 78.11% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::384-511 12 7.10% 85.21% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::512-639 7 4.14% 89.35% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::640-767 7 4.14% 93.49% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::768-895 4 2.37% 95.86% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation
234system.physmem.totQLat 11450750 # Total ticks spent queuing
235system.physmem.totMemAccLat 24707000 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 3535000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 16196.25 # Average queueing delay per DRAM burst
238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
239system.physmem.avgMemAccLat 34946.25 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 365.62 # Average DRAM read bandwidth in MiByte/s
241system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
242system.physmem.avgRdBWSys 365.62 # Average system read bandwidth in MiByte/s
243system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
245system.physmem.busUtil 2.86 # Data bus utilization in percentage
246system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads
247system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
248system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
249system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
250system.physmem.readRowHits 529 # Number of row buffer hits during reads
251system.physmem.writeRowHits 0 # Number of row buffer hits during writes
252system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads
253system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
254system.physmem.avgGap 174704.38 # Average gap between requests
255system.physmem.pageHitRate 74.82 # Row buffer hit rate, read and write combined
256system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ)
257system.physmem_0.preEnergy 428835 # Energy for precharge commands per rank (pJ)
258system.physmem_0.readEnergy 2856000 # Energy for read commands per rank (pJ)
259system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
260system.physmem_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ)
261system.physmem_0.actBackEnergy 6260880 # Energy for active background per rank (pJ)
262system.physmem_0.preBackEnergy 309600 # Energy for precharge background per rank (pJ)
263system.physmem_0.actPowerDownEnergy 30851820 # Energy for active power-down per rank (pJ)
264system.physmem_0.prePowerDownEnergy 11364960 # Energy for precharge power-down per rank (pJ)
265system.physmem_0.selfRefreshEnergy 3424140 # Energy for self refresh per rank (pJ)
266system.physmem_0.totalEnergy 65551215 # Total energy per rank (pJ)
267system.physmem_0.averagePower 529.680036 # Core power per rank (mW)
268system.physmem_0.totalIdleTime 108655750 # Total Idle time Per DRAM Rank
269system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states
270system.physmem_0.memoryStateTime::REF 3906000 # Time in different power states
271system.physmem_0.memoryStateTime::SREF 11965500 # Time in different power states
272system.physmem_0.memoryStateTime::PRE_PDN 29593750 # Time in different power states
273system.physmem_0.memoryStateTime::ACT 10265500 # Time in different power states
274system.physmem_0.memoryStateTime::ACT_PDN 67666750 # Time in different power states
275system.physmem_1.actEnergy 435540 # Energy for activate commands per rank (pJ)
276system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ)
277system.physmem_1.readEnergy 2191980 # Energy for read commands per rank (pJ)
278system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
279system.physmem_1.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ)
280system.physmem_1.actBackEnergy 4628970 # Energy for active background per rank (pJ)
281system.physmem_1.preBackEnergy 469440 # Energy for precharge background per rank (pJ)
282system.physmem_1.actPowerDownEnergy 25813590 # Energy for active power-down per rank (pJ)
283system.physmem_1.prePowerDownEnergy 8390400 # Energy for precharge power-down per rank (pJ)
284system.physmem_1.selfRefreshEnergy 8693940 # Energy for self refresh per rank (pJ)
285system.physmem_1.totalEnergy 58212060 # Total energy per rank (pJ)
286system.physmem_1.averagePower 470.376728 # Core power per rank (mW)
287system.physmem_1.totalIdleTime 112190500 # Total Idle time Per DRAM Rank
288system.physmem_1.memoryStateTime::IDLE 843500 # Time in different power states
289system.physmem_1.memoryStateTime::REF 3126000 # Time in different power states
290system.physmem_1.memoryStateTime::SREF 33923000 # Time in different power states
291system.physmem_1.memoryStateTime::PRE_PDN 21849000 # Time in different power states
292system.physmem_1.memoryStateTime::ACT 7402250 # Time in different power states
293system.physmem_1.memoryStateTime::ACT_PDN 56612250 # Time in different power states
294system.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
295system.cpu0.branchPred.lookups 96945 # Number of BP lookups
296system.cpu0.branchPred.condPredicted 92664 # Number of conditional branches predicted
297system.cpu0.branchPred.condIncorrect 1460 # Number of conditional branches incorrect
298system.cpu0.branchPred.BTBLookups 94281 # Number of BTB lookups
299system.cpu0.branchPred.BTBHits 0 # Number of BTB hits
300system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
301system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
302system.cpu0.branchPred.usedRAS 1072 # Number of times the RAS was used to get a target.
303system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
304system.cpu0.branchPred.indirectLookups 94281 # Number of indirect predictor lookups.
305system.cpu0.branchPred.indirectHits 87442 # Number of indirect target hits.
306system.cpu0.branchPred.indirectMisses 6839 # Number of indirect misses.
307system.cpu0.branchPredindirectMispredicted 944 # Number of mispredicted indirect branches.
308system.cpu_clk_domain.clock 500 # Clock period in ticks
309system.cpu0.workload.numSyscalls 89 # Number of system calls
310system.cpu0.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states
311system.cpu0.numCycles 247513 # number of cpu cycles simulated
312system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
313system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
314system.cpu0.fetch.icacheStallCycles 22810 # Number of cycles fetch is stalled on an Icache miss
315system.cpu0.fetch.Insts 572402 # Number of instructions fetch has processed
316system.cpu0.fetch.Branches 96945 # Number of branches that fetch encountered
317system.cpu0.fetch.predictedBranches 88514 # Number of branches that fetch has predicted taken
318system.cpu0.fetch.Cycles 191239 # Number of cycles fetch has run and was not squashing or blocked
319system.cpu0.fetch.SquashCycles 3219 # Number of cycles fetch has spent squashing
320system.cpu0.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
321system.cpu0.fetch.PendingTrapStallCycles 2152 # Number of stall cycles due to pending traps
322system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
323system.cpu0.fetch.CacheLines 7601 # Number of cache lines fetched
324system.cpu0.fetch.IcacheSquashes 796 # Number of outstanding Icache misses that were squashed
325system.cpu0.fetch.rateDist::samples 217827 # Number of instructions fetched each cycle (Total)
326system.cpu0.fetch.rateDist::mean 2.627783 # Number of instructions fetched each cycle (Total)
327system.cpu0.fetch.rateDist::stdev 2.257744 # Number of instructions fetched each cycle (Total)
328system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
329system.cpu0.fetch.rateDist::0 33416 15.34% 15.34% # Number of instructions fetched each cycle (Total)
330system.cpu0.fetch.rateDist::1 90280 41.45% 56.79% # Number of instructions fetched each cycle (Total)
331system.cpu0.fetch.rateDist::2 662 0.30% 57.09% # Number of instructions fetched each cycle (Total)
332system.cpu0.fetch.rateDist::3 1022 0.47% 57.56% # Number of instructions fetched each cycle (Total)
333system.cpu0.fetch.rateDist::4 476 0.22% 57.78% # Number of instructions fetched each cycle (Total)
334system.cpu0.fetch.rateDist::5 86076 39.52% 97.29% # Number of instructions fetched each cycle (Total)
335system.cpu0.fetch.rateDist::6 627 0.29% 97.58% # Number of instructions fetched each cycle (Total)
336system.cpu0.fetch.rateDist::7 458 0.21% 97.79% # Number of instructions fetched each cycle (Total)
337system.cpu0.fetch.rateDist::8 4810 2.21% 100.00% # Number of instructions fetched each cycle (Total)
338system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
339system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
340system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
341system.cpu0.fetch.rateDist::total 217827 # Number of instructions fetched each cycle (Total)
342system.cpu0.fetch.branchRate 0.391676 # Number of branch fetches per cycle
343system.cpu0.fetch.rate 2.312614 # Number of inst fetches per cycle
344system.cpu0.decode.IdleCycles 17128 # Number of cycles decode is idle
345system.cpu0.decode.BlockedCycles 19348 # Number of cycles decode is blocked
346system.cpu0.decode.RunCycles 178981 # Number of cycles decode is running
347system.cpu0.decode.UnblockCycles 761 # Number of cycles decode is unblocking
348system.cpu0.decode.SquashCycles 1609 # Number of cycles decode is squashing
349system.cpu0.decode.DecodedInsts 555305 # Number of instructions handled by decode
350system.cpu0.rename.SquashCycles 1609 # Number of cycles rename is squashing
351system.cpu0.rename.IdleCycles 17781 # Number of cycles rename is idle
352system.cpu0.rename.BlockCycles 1772 # Number of cycles rename is blocking
353system.cpu0.rename.serializeStallCycles 16195 # count of cycles rename stalled for serializing inst
354system.cpu0.rename.RunCycles 179089 # Number of cycles rename is running
355system.cpu0.rename.UnblockCycles 1381 # Number of cycles rename is unblocking
356system.cpu0.rename.RenamedInsts 550438 # Number of instructions processed by rename
357system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
358system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
359system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full
360system.cpu0.rename.RenamedOperands 376177 # Number of destination operands rename has renamed
361system.cpu0.rename.RenameLookups 1097223 # Number of register rename lookups that rename has made
362system.cpu0.rename.int_rename_lookups 828510 # Number of integer rename lookups
363system.cpu0.rename.CommittedMaps 359139 # Number of HB maps that are committed
364system.cpu0.rename.UndoneMaps 17038 # Number of HB maps that are undone due to squashing
365system.cpu0.rename.serializingInsts 1047 # count of serializing insts renamed
366system.cpu0.rename.tempSerializingInsts 1085 # count of temporary serializing insts renamed
367system.cpu0.rename.skidInsts 5185 # count of insts added to the skid buffer
368system.cpu0.memDep0.insertedLoads 175971 # Number of loads inserted to the mem dependence unit.
369system.cpu0.memDep0.insertedStores 88955 # Number of stores inserted to the mem dependence unit.
370system.cpu0.memDep0.conflictingLoads 85967 # Number of conflicting loads.
371system.cpu0.memDep0.conflictingStores 85657 # Number of conflicting stores.
372system.cpu0.iq.iqInstsAdded 459427 # Number of instructions added to the IQ (excludes non-spec)
373system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ
374system.cpu0.iq.iqInstsIssued 455664 # Number of instructions issued
375system.cpu0.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued
376system.cpu0.iq.iqSquashedInstsExamined 15166 # Number of squashed instructions iterated over during squash; mainly for profiling
377system.cpu0.iq.iqSquashedOperandsExamined 12611 # Number of squashed operands that are examined and possibly removed from graph
378system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed
379system.cpu0.iq.issued_per_cycle::samples 217827 # Number of insts issued each cycle
380system.cpu0.iq.issued_per_cycle::mean 2.091862 # Number of insts issued each cycle
381system.cpu0.iq.issued_per_cycle::stdev 1.108022 # Number of insts issued each cycle
382system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
383system.cpu0.iq.issued_per_cycle::0 36217 16.63% 16.63% # Number of insts issued each cycle
384system.cpu0.iq.issued_per_cycle::1 4343 1.99% 18.62% # Number of insts issued each cycle
385system.cpu0.iq.issued_per_cycle::2 87095 39.98% 58.60% # Number of insts issued each cycle
386system.cpu0.iq.issued_per_cycle::3 86709 39.81% 98.41% # Number of insts issued each cycle
387system.cpu0.iq.issued_per_cycle::4 1627 0.75% 99.16% # Number of insts issued each cycle
388system.cpu0.iq.issued_per_cycle::5 960 0.44% 99.60% # Number of insts issued each cycle
389system.cpu0.iq.issued_per_cycle::6 547 0.25% 99.85% # Number of insts issued each cycle
390system.cpu0.iq.issued_per_cycle::7 218 0.10% 99.95% # Number of insts issued each cycle
391system.cpu0.iq.issued_per_cycle::8 111 0.05% 100.00% # Number of insts issued each cycle
392system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
393system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
394system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
395system.cpu0.iq.issued_per_cycle::total 217827 # Number of insts issued each cycle
396system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
397system.cpu0.iq.fu_full::IntAlu 123 36.94% 36.94% # attempts to use FU when none available
398system.cpu0.iq.fu_full::IntMult 0 0.00% 36.94% # attempts to use FU when none available
399system.cpu0.iq.fu_full::IntDiv 0 0.00% 36.94% # attempts to use FU when none available
400system.cpu0.iq.fu_full::FloatAdd 0 0.00% 36.94% # attempts to use FU when none available
401system.cpu0.iq.fu_full::FloatCmp 0 0.00% 36.94% # attempts to use FU when none available
402system.cpu0.iq.fu_full::FloatCvt 0 0.00% 36.94% # attempts to use FU when none available
403system.cpu0.iq.fu_full::FloatMult 0 0.00% 36.94% # attempts to use FU when none available
404system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available
405system.cpu0.iq.fu_full::FloatDiv 0 0.00% 36.94% # attempts to use FU when none available
406system.cpu0.iq.fu_full::FloatMisc 0 0.00% 36.94% # attempts to use FU when none available
407system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 36.94% # attempts to use FU when none available
408system.cpu0.iq.fu_full::SimdAdd 0 0.00% 36.94% # attempts to use FU when none available
409system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 36.94% # attempts to use FU when none available
410system.cpu0.iq.fu_full::SimdAlu 0 0.00% 36.94% # attempts to use FU when none available
411system.cpu0.iq.fu_full::SimdCmp 0 0.00% 36.94% # attempts to use FU when none available
412system.cpu0.iq.fu_full::SimdCvt 0 0.00% 36.94% # attempts to use FU when none available
413system.cpu0.iq.fu_full::SimdMisc 0 0.00% 36.94% # attempts to use FU when none available
414system.cpu0.iq.fu_full::SimdMult 0 0.00% 36.94% # attempts to use FU when none available
415system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 36.94% # attempts to use FU when none available
416system.cpu0.iq.fu_full::SimdShift 0 0.00% 36.94% # attempts to use FU when none available
417system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 36.94% # attempts to use FU when none available
418system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 36.94% # attempts to use FU when none available
419system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 36.94% # attempts to use FU when none available
420system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 36.94% # attempts to use FU when none available
421system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 36.94% # attempts to use FU when none available
422system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 36.94% # attempts to use FU when none available
423system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 36.94% # attempts to use FU when none available
424system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 36.94% # attempts to use FU when none available
425system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 36.94% # attempts to use FU when none available
426system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available
427system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 36.94% # attempts to use FU when none available
428system.cpu0.iq.fu_full::MemRead 85 25.53% 62.46% # attempts to use FU when none available
429system.cpu0.iq.fu_full::MemWrite 125 37.54% 100.00% # attempts to use FU when none available
430system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
431system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
432system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
433system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
434system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
435system.cpu0.iq.FU_type_0::IntAlu 192140 42.17% 42.17% # Type of FU issued
436system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.17% # Type of FU issued
437system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.17% # Type of FU issued
438system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.17% # Type of FU issued
439system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.17% # Type of FU issued
440system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.17% # Type of FU issued
441system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.17% # Type of FU issued
442system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.17% # Type of FU issued
443system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.17% # Type of FU issued
444system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.17% # Type of FU issued
445system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.17% # Type of FU issued
446system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.17% # Type of FU issued
447system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.17% # Type of FU issued
448system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.17% # Type of FU issued
449system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.17% # Type of FU issued
450system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.17% # Type of FU issued
451system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.17% # Type of FU issued
452system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.17% # Type of FU issued
453system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.17% # Type of FU issued
454system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.17% # Type of FU issued
455system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.17% # Type of FU issued
456system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.17% # Type of FU issued
457system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.17% # Type of FU issued
458system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.17% # Type of FU issued
459system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.17% # Type of FU issued
460system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.17% # Type of FU issued
461system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.17% # Type of FU issued
462system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.17% # Type of FU issued
463system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.17% # Type of FU issued
464system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.17% # Type of FU issued
465system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.17% # Type of FU issued
466system.cpu0.iq.FU_type_0::MemRead 175355 38.48% 80.65% # Type of FU issued
467system.cpu0.iq.FU_type_0::MemWrite 88169 19.35% 100.00% # Type of FU issued
468system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
469system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
470system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
471system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
472system.cpu0.iq.FU_type_0::total 455664 # Type of FU issued
473system.cpu0.iq.rate 1.840970 # Inst issue rate
474system.cpu0.iq.fu_busy_cnt 333 # FU busy when requested
475system.cpu0.iq.fu_busy_rate 0.000731 # FU busy rate (busy events/executed inst)
476system.cpu0.iq.int_inst_queue_reads 1129583 # Number of integer instruction queue reads
477system.cpu0.iq.int_inst_queue_writes 475739 # Number of integer instruction queue writes
478system.cpu0.iq.int_inst_queue_wakeup_accesses 453318 # Number of integer instruction queue wakeup accesses
479system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
480system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
481system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
482system.cpu0.iq.int_alu_accesses 455997 # Number of integer alu accesses
483system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
484system.cpu0.iew.lsq.thread0.forwLoads 85314 # Number of loads that had data forwarded from stores
485system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
486system.cpu0.iew.lsq.thread0.squashedLoads 2812 # Number of loads squashed
487system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
488system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
489system.cpu0.iew.lsq.thread0.squashedStores 1869 # Number of stores squashed
490system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
491system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
492system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
493system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
494system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
495system.cpu0.iew.iewSquashCycles 1609 # Number of cycles IEW is squashing
496system.cpu0.iew.iewBlockCycles 1760 # Number of cycles IEW is blocking
497system.cpu0.iew.iewUnblockCycles 31 # Number of cycles IEW is unblocking
498system.cpu0.iew.iewDispatchedInsts 547045 # Number of instructions dispatched to IQ
499system.cpu0.iew.iewDispSquashedInsts 114 # Number of squashed instructions skipped by dispatch
500system.cpu0.iew.iewDispLoadInsts 175971 # Number of dispatched load instructions
501system.cpu0.iew.iewDispStoreInsts 88955 # Number of dispatched store instructions
502system.cpu0.iew.iewDispNonSpecInsts 969 # Number of dispatched non-speculative instructions
503system.cpu0.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
504system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
505system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
506system.cpu0.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly
507system.cpu0.iew.predictedNotTakenIncorrect 1555 # Number of branches that were predicted not taken incorrectly
508system.cpu0.iew.branchMispredicts 1766 # Number of branch mispredicts detected at execute
509system.cpu0.iew.iewExecutedInsts 454327 # Number of executed instructions
510system.cpu0.iew.iewExecLoadInsts 175012 # Number of load instructions executed
511system.cpu0.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute
512system.cpu0.iew.exec_swp 0 # number of swp insts executed
513system.cpu0.iew.exec_nop 86524 # number of nop insts executed
514system.cpu0.iew.exec_refs 262985 # number of memory reference insts executed
515system.cpu0.iew.exec_branches 90247 # Number of branches executed
516system.cpu0.iew.exec_stores 87973 # Number of stores executed
517system.cpu0.iew.exec_rate 1.835568 # Inst execution rate
518system.cpu0.iew.wb_sent 453748 # cumulative count of insts sent to commit
519system.cpu0.iew.wb_count 453318 # cumulative count of insts written-back
520system.cpu0.iew.wb_producers 268984 # num instructions producing a value
521system.cpu0.iew.wb_consumers 272473 # num instructions consuming a value
522system.cpu0.iew.wb_rate 1.831492 # insts written-back per cycle
523system.cpu0.iew.wb_fanout 0.987195 # average fanout of values written-back
524system.cpu0.commit.commitSquashedInsts 15911 # The number of squashed insts skipped by commit
525system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
526system.cpu0.commit.branchMispredicts 1460 # The number of times a branch was mispredicted
527system.cpu0.commit.committed_per_cycle::samples 214699 # Number of insts commited each cycle
528system.cpu0.commit.committed_per_cycle::mean 2.473509 # Number of insts commited each cycle
529system.cpu0.commit.committed_per_cycle::stdev 2.143772 # Number of insts commited each cycle
530system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
531system.cpu0.commit.committed_per_cycle::0 36174 16.85% 16.85% # Number of insts commited each cycle
532system.cpu0.commit.committed_per_cycle::1 89113 41.51% 58.35% # Number of insts commited each cycle
533system.cpu0.commit.committed_per_cycle::2 1996 0.93% 59.28% # Number of insts commited each cycle
534system.cpu0.commit.committed_per_cycle::3 609 0.28% 59.57% # Number of insts commited each cycle
535system.cpu0.commit.committed_per_cycle::4 464 0.22% 59.78% # Number of insts commited each cycle
536system.cpu0.commit.committed_per_cycle::5 85076 39.63% 99.41% # Number of insts commited each cycle
537system.cpu0.commit.committed_per_cycle::6 476 0.22% 99.63% # Number of insts commited each cycle
538system.cpu0.commit.committed_per_cycle::7 292 0.14% 99.77% # Number of insts commited each cycle
539system.cpu0.commit.committed_per_cycle::8 499 0.23% 100.00% # Number of insts commited each cycle
540system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
541system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
542system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
543system.cpu0.commit.committed_per_cycle::total 214699 # Number of insts commited each cycle
544system.cpu0.commit.committedInsts 531060 # Number of instructions committed
545system.cpu0.commit.committedOps 531060 # Number of ops (including micro ops) committed
546system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
547system.cpu0.commit.refs 260245 # Number of memory references committed
548system.cpu0.commit.loads 173159 # Number of loads committed
549system.cpu0.commit.membars 84 # Number of memory barriers committed
550system.cpu0.commit.branches 88973 # Number of branches committed
551system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
552system.cpu0.commit.int_insts 357470 # Number of committed integer instructions.
553system.cpu0.commit.function_calls 223 # Number of function calls committed.
554system.cpu0.commit.op_class_0::No_OpClass 85705 16.14% 16.14% # Class of committed instruction
555system.cpu0.commit.op_class_0::IntAlu 185026 34.84% 50.98% # Class of committed instruction
556system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.98% # Class of committed instruction
557system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.98% # Class of committed instruction
558system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.98% # Class of committed instruction
559system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.98% # Class of committed instruction
560system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.98% # Class of committed instruction
561system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.98% # Class of committed instruction
562system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.98% # Class of committed instruction
563system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.98% # Class of committed instruction
564system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.98% # Class of committed instruction
565system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.98% # Class of committed instruction
566system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.98% # Class of committed instruction
567system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.98% # Class of committed instruction
568system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.98% # Class of committed instruction
569system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.98% # Class of committed instruction
570system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.98% # Class of committed instruction
571system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.98% # Class of committed instruction
572system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.98% # Class of committed instruction
573system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.98% # Class of committed instruction
574system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.98% # Class of committed instruction
575system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.98% # Class of committed instruction
576system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.98% # Class of committed instruction
577system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.98% # Class of committed instruction
578system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.98% # Class of committed instruction
579system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.98% # Class of committed instruction
580system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.98% # Class of committed instruction
581system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.98% # Class of committed instruction
582system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.98% # Class of committed instruction
583system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.98% # Class of committed instruction
584system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.98% # Class of committed instruction
585system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.98% # Class of committed instruction
586system.cpu0.commit.op_class_0::MemRead 173243 32.62% 83.60% # Class of committed instruction
587system.cpu0.commit.op_class_0::MemWrite 87086 16.40% 100.00% # Class of committed instruction
588system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
589system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
590system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
591system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
592system.cpu0.commit.op_class_0::total 531060 # Class of committed instruction
593system.cpu0.commit.bw_lim_events 499 # number cycles where commit BW limit reached
594system.cpu0.rob.rob_reads 760010 # The number of ROB reads
595system.cpu0.rob.rob_writes 1097116 # The number of ROB writes
596system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
597system.cpu0.idleCycles 29686 # Total number of cycles that the CPU has spent unscheduled due to idling
598system.cpu0.committedInsts 445271 # Number of Instructions Simulated
599system.cpu0.committedOps 445271 # Number of Ops (including micro ops) Simulated
600system.cpu0.cpi 0.555870 # CPI: Cycles Per Instruction
601system.cpu0.cpi_total 0.555870 # CPI: Total CPI of All Threads
602system.cpu0.ipc 1.798980 # IPC: Instructions Per Cycle
603system.cpu0.ipc_total 1.798980 # IPC: Total IPC of All Threads
604system.cpu0.int_regfile_reads 812559 # number of integer regfile reads
605system.cpu0.int_regfile_writes 366073 # number of integer regfile writes
606system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
607system.cpu0.misc_regfile_reads 265038 # number of misc regfile reads
608system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
609system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
610system.cpu0.dcache.tags.replacements 2 # number of replacements
611system.cpu0.dcache.tags.tagsinuse 142.111163 # Cycle average of tags in use
612system.cpu0.dcache.tags.total_refs 175455 # Total number of references to valid blocks.
613system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
614system.cpu0.dcache.tags.avg_refs 1026.052632 # Average number of references to valid blocks.
615system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
616system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.111163 # Average occupied blocks per requestor
617system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277561 # Average percentage of cache occupancy
618system.cpu0.dcache.tags.occ_percent::total 0.277561 # Average percentage of cache occupancy
619system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
620system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
621system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
622system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
623system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
624system.cpu0.dcache.tags.tag_accesses 707079 # Number of tag accesses
625system.cpu0.dcache.tags.data_accesses 707079 # Number of data accesses
626system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
627system.cpu0.dcache.ReadReq_hits::cpu0.data 89048 # number of ReadReq hits
628system.cpu0.dcache.ReadReq_hits::total 89048 # number of ReadReq hits
629system.cpu0.dcache.WriteReq_hits::cpu0.data 86492 # number of WriteReq hits
630system.cpu0.dcache.WriteReq_hits::total 86492 # number of WriteReq hits
631system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits
632system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits
633system.cpu0.dcache.demand_hits::cpu0.data 175540 # number of demand (read+write) hits
634system.cpu0.dcache.demand_hits::total 175540 # number of demand (read+write) hits
635system.cpu0.dcache.overall_hits::cpu0.data 175540 # number of overall hits
636system.cpu0.dcache.overall_hits::total 175540 # number of overall hits
637system.cpu0.dcache.ReadReq_misses::cpu0.data 556 # number of ReadReq misses
638system.cpu0.dcache.ReadReq_misses::total 556 # number of ReadReq misses
639system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses
640system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses
641system.cpu0.dcache.SwapReq_misses::cpu0.data 24 # number of SwapReq misses
642system.cpu0.dcache.SwapReq_misses::total 24 # number of SwapReq misses
643system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses
644system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses
645system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses
646system.cpu0.dcache.overall_misses::total 1108 # number of overall misses
647system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15680500 # number of ReadReq miss cycles
648system.cpu0.dcache.ReadReq_miss_latency::total 15680500 # number of ReadReq miss cycles
649system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35675489 # number of WriteReq miss cycles
650system.cpu0.dcache.WriteReq_miss_latency::total 35675489 # number of WriteReq miss cycles
651system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 524500 # number of SwapReq miss cycles
652system.cpu0.dcache.SwapReq_miss_latency::total 524500 # number of SwapReq miss cycles
653system.cpu0.dcache.demand_miss_latency::cpu0.data 51355989 # number of demand (read+write) miss cycles
654system.cpu0.dcache.demand_miss_latency::total 51355989 # number of demand (read+write) miss cycles
655system.cpu0.dcache.overall_miss_latency::cpu0.data 51355989 # number of overall miss cycles
656system.cpu0.dcache.overall_miss_latency::total 51355989 # number of overall miss cycles
657system.cpu0.dcache.ReadReq_accesses::cpu0.data 89604 # number of ReadReq accesses(hits+misses)
658system.cpu0.dcache.ReadReq_accesses::total 89604 # number of ReadReq accesses(hits+misses)
659system.cpu0.dcache.WriteReq_accesses::cpu0.data 87044 # number of WriteReq accesses(hits+misses)
660system.cpu0.dcache.WriteReq_accesses::total 87044 # number of WriteReq accesses(hits+misses)
661system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
662system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
663system.cpu0.dcache.demand_accesses::cpu0.data 176648 # number of demand (read+write) accesses
664system.cpu0.dcache.demand_accesses::total 176648 # number of demand (read+write) accesses
665system.cpu0.dcache.overall_accesses::cpu0.data 176648 # number of overall (read+write) accesses
666system.cpu0.dcache.overall_accesses::total 176648 # number of overall (read+write) accesses
667system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006205 # miss rate for ReadReq accesses
668system.cpu0.dcache.ReadReq_miss_rate::total 0.006205 # miss rate for ReadReq accesses
669system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006342 # miss rate for WriteReq accesses
670system.cpu0.dcache.WriteReq_miss_rate::total 0.006342 # miss rate for WriteReq accesses
671system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses
672system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses
673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006272 # miss rate for demand accesses
674system.cpu0.dcache.demand_miss_rate::total 0.006272 # miss rate for demand accesses
675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006272 # miss rate for overall accesses
676system.cpu0.dcache.overall_miss_rate::total 0.006272 # miss rate for overall accesses
677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28202.338129 # average ReadReq miss latency
678system.cpu0.dcache.ReadReq_avg_miss_latency::total 28202.338129 # average ReadReq miss latency
679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64629.509058 # average WriteReq miss latency
680system.cpu0.dcache.WriteReq_avg_miss_latency::total 64629.509058 # average WriteReq miss latency
681system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21854.166667 # average SwapReq miss latency
682system.cpu0.dcache.SwapReq_avg_miss_latency::total 21854.166667 # average SwapReq miss latency
683system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency
684system.cpu0.dcache.demand_avg_miss_latency::total 46350.170578 # average overall miss latency
685system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency
686system.cpu0.dcache.overall_avg_miss_latency::total 46350.170578 # average overall miss latency
687system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked
688system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
689system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
690system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
691system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked
692system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
693system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
694system.cpu0.dcache.writebacks::total 1 # number of writebacks
695system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 364 # number of ReadReq MSHR hits
696system.cpu0.dcache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits
697system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits
698system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits
699system.cpu0.dcache.demand_mshr_hits::cpu0.data 743 # number of demand (read+write) MSHR hits
700system.cpu0.dcache.demand_mshr_hits::total 743 # number of demand (read+write) MSHR hits
701system.cpu0.dcache.overall_mshr_hits::cpu0.data 743 # number of overall MSHR hits
702system.cpu0.dcache.overall_mshr_hits::total 743 # number of overall MSHR hits
703system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192 # number of ReadReq MSHR misses
704system.cpu0.dcache.ReadReq_mshr_misses::total 192 # number of ReadReq MSHR misses
705system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 173 # number of WriteReq MSHR misses
706system.cpu0.dcache.WriteReq_mshr_misses::total 173 # number of WriteReq MSHR misses
707system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses
708system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses
709system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses
710system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
711system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses
712system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses
713system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7301500 # number of ReadReq MSHR miss cycles
714system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7301500 # number of ReadReq MSHR miss cycles
715system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8155500 # number of WriteReq MSHR miss cycles
716system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8155500 # number of WriteReq MSHR miss cycles
717system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 500500 # number of SwapReq MSHR miss cycles
718system.cpu0.dcache.SwapReq_mshr_miss_latency::total 500500 # number of SwapReq MSHR miss cycles
719system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15457000 # number of demand (read+write) MSHR miss cycles
720system.cpu0.dcache.demand_mshr_miss_latency::total 15457000 # number of demand (read+write) MSHR miss cycles
721system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15457000 # number of overall MSHR miss cycles
722system.cpu0.dcache.overall_mshr_miss_latency::total 15457000 # number of overall MSHR miss cycles
723system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses
724system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses
725system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001988 # mshr miss rate for WriteReq accesses
726system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001988 # mshr miss rate for WriteReq accesses
727system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses
728system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses
729system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for demand accesses
730system.cpu0.dcache.demand_mshr_miss_rate::total 0.002066 # mshr miss rate for demand accesses
731system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for overall accesses
732system.cpu0.dcache.overall_mshr_miss_rate::total 0.002066 # mshr miss rate for overall accesses
733system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38028.645833 # average ReadReq mshr miss latency
734system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38028.645833 # average ReadReq mshr miss latency
735system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47141.618497 # average WriteReq mshr miss latency
736system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47141.618497 # average WriteReq mshr miss latency
737system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20854.166667 # average SwapReq mshr miss latency
738system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20854.166667 # average SwapReq mshr miss latency
739system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency
740system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency
741system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency
742system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency
743system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
744system.cpu0.icache.tags.replacements 381 # number of replacements
745system.cpu0.icache.tags.tagsinuse 247.076486 # Cycle average of tags in use
746system.cpu0.icache.tags.total_refs 6698 # Total number of references to valid blocks.
747system.cpu0.icache.tags.sampled_refs 681 # Sample count of references to valid blocks.
748system.cpu0.icache.tags.avg_refs 9.835536 # Average number of references to valid blocks.
749system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
750system.cpu0.icache.tags.occ_blocks::cpu0.inst 247.076486 # Average occupied blocks per requestor
751system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482571 # Average percentage of cache occupancy
752system.cpu0.icache.tags.occ_percent::total 0.482571 # Average percentage of cache occupancy
753system.cpu0.icache.tags.occ_task_id_blocks::1024 300 # Occupied blocks per task id
754system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
755system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
756system.cpu0.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id
757system.cpu0.icache.tags.occ_task_id_percent::1024 0.585938 # Percentage of cache occupancy per task id
758system.cpu0.icache.tags.tag_accesses 8282 # Number of tag accesses
759system.cpu0.icache.tags.data_accesses 8282 # Number of data accesses
760system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
761system.cpu0.icache.ReadReq_hits::cpu0.inst 6698 # number of ReadReq hits
762system.cpu0.icache.ReadReq_hits::total 6698 # number of ReadReq hits
763system.cpu0.icache.demand_hits::cpu0.inst 6698 # number of demand (read+write) hits
764system.cpu0.icache.demand_hits::total 6698 # number of demand (read+write) hits
765system.cpu0.icache.overall_hits::cpu0.inst 6698 # number of overall hits
766system.cpu0.icache.overall_hits::total 6698 # number of overall hits
767system.cpu0.icache.ReadReq_misses::cpu0.inst 903 # number of ReadReq misses
768system.cpu0.icache.ReadReq_misses::total 903 # number of ReadReq misses
769system.cpu0.icache.demand_misses::cpu0.inst 903 # number of demand (read+write) misses
770system.cpu0.icache.demand_misses::total 903 # number of demand (read+write) misses
771system.cpu0.icache.overall_misses::cpu0.inst 903 # number of overall misses
772system.cpu0.icache.overall_misses::total 903 # number of overall misses
773system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 46390500 # number of ReadReq miss cycles
774system.cpu0.icache.ReadReq_miss_latency::total 46390500 # number of ReadReq miss cycles
775system.cpu0.icache.demand_miss_latency::cpu0.inst 46390500 # number of demand (read+write) miss cycles
776system.cpu0.icache.demand_miss_latency::total 46390500 # number of demand (read+write) miss cycles
777system.cpu0.icache.overall_miss_latency::cpu0.inst 46390500 # number of overall miss cycles
778system.cpu0.icache.overall_miss_latency::total 46390500 # number of overall miss cycles
779system.cpu0.icache.ReadReq_accesses::cpu0.inst 7601 # number of ReadReq accesses(hits+misses)
780system.cpu0.icache.ReadReq_accesses::total 7601 # number of ReadReq accesses(hits+misses)
781system.cpu0.icache.demand_accesses::cpu0.inst 7601 # number of demand (read+write) accesses
782system.cpu0.icache.demand_accesses::total 7601 # number of demand (read+write) accesses
783system.cpu0.icache.overall_accesses::cpu0.inst 7601 # number of overall (read+write) accesses
784system.cpu0.icache.overall_accesses::total 7601 # number of overall (read+write) accesses
785system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118800 # miss rate for ReadReq accesses
786system.cpu0.icache.ReadReq_miss_rate::total 0.118800 # miss rate for ReadReq accesses
787system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118800 # miss rate for demand accesses
788system.cpu0.icache.demand_miss_rate::total 0.118800 # miss rate for demand accesses
789system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118800 # miss rate for overall accesses
790system.cpu0.icache.overall_miss_rate::total 0.118800 # miss rate for overall accesses
791system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51373.754153 # average ReadReq miss latency
792system.cpu0.icache.ReadReq_avg_miss_latency::total 51373.754153 # average ReadReq miss latency
793system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency
794system.cpu0.icache.demand_avg_miss_latency::total 51373.754153 # average overall miss latency
795system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency
796system.cpu0.icache.overall_avg_miss_latency::total 51373.754153 # average overall miss latency
797system.cpu0.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked
798system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
799system.cpu0.icache.blocked::no_mshrs 3 # number of cycles access was blocked
800system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
801system.cpu0.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked
802system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
803system.cpu0.icache.writebacks::writebacks 381 # number of writebacks
804system.cpu0.icache.writebacks::total 381 # number of writebacks
805system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits
806system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits
807system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits
808system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
809system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits
810system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits
811system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 682 # number of ReadReq MSHR misses
812system.cpu0.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses
813system.cpu0.icache.demand_mshr_misses::cpu0.inst 682 # number of demand (read+write) MSHR misses
814system.cpu0.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses
815system.cpu0.icache.overall_mshr_misses::cpu0.inst 682 # number of overall MSHR misses
816system.cpu0.icache.overall_mshr_misses::total 682 # number of overall MSHR misses
817system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 35207000 # number of ReadReq MSHR miss cycles
818system.cpu0.icache.ReadReq_mshr_miss_latency::total 35207000 # number of ReadReq MSHR miss cycles
819system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 35207000 # number of demand (read+write) MSHR miss cycles
820system.cpu0.icache.demand_mshr_miss_latency::total 35207000 # number of demand (read+write) MSHR miss cycles
821system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 35207000 # number of overall MSHR miss cycles
822system.cpu0.icache.overall_mshr_miss_latency::total 35207000 # number of overall MSHR miss cycles
823system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for ReadReq accesses
824system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089725 # mshr miss rate for ReadReq accesses
825system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for demand accesses
826system.cpu0.icache.demand_mshr_miss_rate::total 0.089725 # mshr miss rate for demand accesses
827system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for overall accesses
828system.cpu0.icache.overall_mshr_miss_rate::total 0.089725 # mshr miss rate for overall accesses
829system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average ReadReq mshr miss latency
830system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51623.167155 # average ReadReq mshr miss latency
831system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency
832system.cpu0.icache.demand_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency
833system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency
834system.cpu0.icache.overall_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency
835system.cpu1.branchPred.lookups 61334 # Number of BP lookups
836system.cpu1.branchPred.condPredicted 54401 # Number of conditional branches predicted
837system.cpu1.branchPred.condIncorrect 2004 # Number of conditional branches incorrect
838system.cpu1.branchPred.BTBLookups 54412 # Number of BTB lookups
839system.cpu1.branchPred.BTBHits 0 # Number of BTB hits
840system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
841system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
842system.cpu1.branchPred.usedRAS 1793 # Number of times the RAS was used to get a target.
843system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
844system.cpu1.branchPred.indirectLookups 54412 # Number of indirect predictor lookups.
845system.cpu1.branchPred.indirectHits 44729 # Number of indirect target hits.
846system.cpu1.branchPred.indirectMisses 9683 # Number of indirect misses.
847system.cpu1.branchPredindirectMispredicted 984 # Number of mispredicted indirect branches.
848system.cpu1.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states
849system.cpu1.numCycles 189559 # number of cpu cycles simulated
850system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
851system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
852system.cpu1.fetch.icacheStallCycles 38670 # Number of cycles fetch is stalled on an Icache miss
853system.cpu1.fetch.Insts 332272 # Number of instructions fetch has processed
854system.cpu1.fetch.Branches 61334 # Number of branches that fetch encountered
855system.cpu1.fetch.predictedBranches 46522 # Number of branches that fetch has predicted taken
856system.cpu1.fetch.Cycles 140422 # Number of cycles fetch has run and was not squashing or blocked
857system.cpu1.fetch.SquashCycles 4165 # Number of cycles fetch has spent squashing
858system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
859system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
860system.cpu1.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps
861system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
862system.cpu1.fetch.CacheLines 27652 # Number of cache lines fetched
863system.cpu1.fetch.IcacheSquashes 879 # Number of outstanding Icache misses that were squashed
864system.cpu1.fetch.rateDist::samples 182684 # Number of instructions fetched each cycle (Total)
865system.cpu1.fetch.rateDist::mean 1.818835 # Number of instructions fetched each cycle (Total)
866system.cpu1.fetch.rateDist::stdev 2.303785 # Number of instructions fetched each cycle (Total)
867system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
868system.cpu1.fetch.rateDist::0 70336 38.50% 38.50% # Number of instructions fetched each cycle (Total)
869system.cpu1.fetch.rateDist::1 55803 30.55% 69.05% # Number of instructions fetched each cycle (Total)
870system.cpu1.fetch.rateDist::2 8540 4.67% 73.72% # Number of instructions fetched each cycle (Total)
871system.cpu1.fetch.rateDist::3 3408 1.87% 75.59% # Number of instructions fetched each cycle (Total)
872system.cpu1.fetch.rateDist::4 651 0.36% 75.94% # Number of instructions fetched each cycle (Total)
873system.cpu1.fetch.rateDist::5 33906 18.56% 94.50% # Number of instructions fetched each cycle (Total)
874system.cpu1.fetch.rateDist::6 999 0.55% 95.05% # Number of instructions fetched each cycle (Total)
875system.cpu1.fetch.rateDist::7 1291 0.71% 95.76% # Number of instructions fetched each cycle (Total)
876system.cpu1.fetch.rateDist::8 7750 4.24% 100.00% # Number of instructions fetched each cycle (Total)
877system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
878system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
879system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
880system.cpu1.fetch.rateDist::total 182684 # Number of instructions fetched each cycle (Total)
881system.cpu1.fetch.branchRate 0.323562 # Number of branch fetches per cycle
882system.cpu1.fetch.rate 1.752869 # Number of inst fetches per cycle
883system.cpu1.decode.IdleCycles 21125 # Number of cycles decode is idle
884system.cpu1.decode.BlockedCycles 71097 # Number of cycles decode is blocked
885system.cpu1.decode.RunCycles 83834 # Number of cycles decode is running
886system.cpu1.decode.UnblockCycles 4536 # Number of cycles decode is unblocking
887system.cpu1.decode.SquashCycles 2082 # Number of cycles decode is squashing
888system.cpu1.decode.DecodedInsts 303611 # Number of instructions handled by decode
889system.cpu1.rename.SquashCycles 2082 # Number of cycles rename is squashing
890system.cpu1.rename.IdleCycles 22030 # Number of cycles rename is idle
891system.cpu1.rename.BlockCycles 34668 # Number of cycles rename is blocking
892system.cpu1.rename.serializeStallCycles 13321 # count of cycles rename stalled for serializing inst
893system.cpu1.rename.RunCycles 84450 # Number of cycles rename is running
894system.cpu1.rename.UnblockCycles 26123 # Number of cycles rename is unblocking
895system.cpu1.rename.RenamedInsts 298128 # Number of instructions processed by rename
896system.cpu1.rename.IQFullEvents 22342 # Number of times rename has blocked due to IQ full
897system.cpu1.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
898system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers
899system.cpu1.rename.RenamedOperands 207771 # Number of destination operands rename has renamed
900system.cpu1.rename.RenameLookups 563979 # Number of register rename lookups that rename has made
901system.cpu1.rename.int_rename_lookups 439786 # Number of integer rename lookups
902system.cpu1.rename.fp_rename_lookups 36 # Number of floating rename lookups
903system.cpu1.rename.CommittedMaps 183614 # Number of HB maps that are committed
904system.cpu1.rename.UndoneMaps 24157 # Number of HB maps that are undone due to squashing
905system.cpu1.rename.serializingInsts 1533 # count of serializing insts renamed
906system.cpu1.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed
907system.cpu1.rename.skidInsts 31315 # count of insts added to the skid buffer
908system.cpu1.memDep0.insertedLoads 81609 # Number of loads inserted to the mem dependence unit.
909system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit.
910system.cpu1.memDep0.conflictingLoads 39208 # Number of conflicting loads.
911system.cpu1.memDep0.conflictingStores 31953 # Number of conflicting stores.
912system.cpu1.iq.iqInstsAdded 243349 # Number of instructions added to the IQ (excludes non-spec)
913system.cpu1.iq.iqNonSpecInstsAdded 8714 # Number of non-speculative instructions added to the IQ
914system.cpu1.iq.iqInstsIssued 245236 # Number of instructions issued
915system.cpu1.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued
916system.cpu1.iq.iqSquashedInstsExamined 21657 # Number of squashed instructions iterated over during squash; mainly for profiling
917system.cpu1.iq.iqSquashedOperandsExamined 16615 # Number of squashed operands that are examined and possibly removed from graph
918system.cpu1.iq.iqSquashedNonSpecRemoved 1128 # Number of squashed non-spec instructions that were removed
919system.cpu1.iq.issued_per_cycle::samples 182684 # Number of insts issued each cycle
920system.cpu1.iq.issued_per_cycle::mean 1.342405 # Number of insts issued each cycle
921system.cpu1.iq.issued_per_cycle::stdev 1.387446 # Number of insts issued each cycle
922system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
923system.cpu1.iq.issued_per_cycle::0 74656 40.87% 40.87% # Number of insts issued each cycle
924system.cpu1.iq.issued_per_cycle::1 27751 15.19% 56.06% # Number of insts issued each cycle
925system.cpu1.iq.issued_per_cycle::2 36635 20.05% 76.11% # Number of insts issued each cycle
926system.cpu1.iq.issued_per_cycle::3 36634 20.05% 96.16% # Number of insts issued each cycle
927system.cpu1.iq.issued_per_cycle::4 3526 1.93% 98.09% # Number of insts issued each cycle
928system.cpu1.iq.issued_per_cycle::5 1704 0.93% 99.03% # Number of insts issued each cycle
929system.cpu1.iq.issued_per_cycle::6 1046 0.57% 99.60% # Number of insts issued each cycle
930system.cpu1.iq.issued_per_cycle::7 443 0.24% 99.84% # Number of insts issued each cycle
931system.cpu1.iq.issued_per_cycle::8 289 0.16% 100.00% # Number of insts issued each cycle
932system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
933system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
934system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
935system.cpu1.iq.issued_per_cycle::total 182684 # Number of insts issued each cycle
936system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
937system.cpu1.iq.fu_full::IntAlu 163 36.88% 36.88% # attempts to use FU when none available
938system.cpu1.iq.fu_full::IntMult 0 0.00% 36.88% # attempts to use FU when none available
939system.cpu1.iq.fu_full::IntDiv 0 0.00% 36.88% # attempts to use FU when none available
940system.cpu1.iq.fu_full::FloatAdd 0 0.00% 36.88% # attempts to use FU when none available
941system.cpu1.iq.fu_full::FloatCmp 0 0.00% 36.88% # attempts to use FU when none available
942system.cpu1.iq.fu_full::FloatCvt 0 0.00% 36.88% # attempts to use FU when none available
943system.cpu1.iq.fu_full::FloatMult 0 0.00% 36.88% # attempts to use FU when none available
944system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available
945system.cpu1.iq.fu_full::FloatDiv 0 0.00% 36.88% # attempts to use FU when none available
946system.cpu1.iq.fu_full::FloatMisc 0 0.00% 36.88% # attempts to use FU when none available
947system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 36.88% # attempts to use FU when none available
948system.cpu1.iq.fu_full::SimdAdd 0 0.00% 36.88% # attempts to use FU when none available
949system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 36.88% # attempts to use FU when none available
950system.cpu1.iq.fu_full::SimdAlu 0 0.00% 36.88% # attempts to use FU when none available
951system.cpu1.iq.fu_full::SimdCmp 0 0.00% 36.88% # attempts to use FU when none available
952system.cpu1.iq.fu_full::SimdCvt 0 0.00% 36.88% # attempts to use FU when none available
953system.cpu1.iq.fu_full::SimdMisc 0 0.00% 36.88% # attempts to use FU when none available
954system.cpu1.iq.fu_full::SimdMult 0 0.00% 36.88% # attempts to use FU when none available
955system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 36.88% # attempts to use FU when none available
956system.cpu1.iq.fu_full::SimdShift 0 0.00% 36.88% # attempts to use FU when none available
957system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 36.88% # attempts to use FU when none available
958system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 36.88% # attempts to use FU when none available
959system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 36.88% # attempts to use FU when none available
960system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 36.88% # attempts to use FU when none available
961system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 36.88% # attempts to use FU when none available
962system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 36.88% # attempts to use FU when none available
963system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 36.88% # attempts to use FU when none available
964system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 36.88% # attempts to use FU when none available
965system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 36.88% # attempts to use FU when none available
966system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available
967system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 36.88% # attempts to use FU when none available
968system.cpu1.iq.fu_full::MemRead 52 11.76% 48.64% # attempts to use FU when none available
969system.cpu1.iq.fu_full::MemWrite 227 51.36% 100.00% # attempts to use FU when none available
970system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
971system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
972system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
973system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
974system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
975system.cpu1.iq.FU_type_0::IntAlu 120474 49.13% 49.13% # Type of FU issued
976system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.13% # Type of FU issued
977system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.13% # Type of FU issued
978system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.13% # Type of FU issued
979system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.13% # Type of FU issued
980system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.13% # Type of FU issued
981system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.13% # Type of FU issued
982system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 49.13% # Type of FU issued
983system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.13% # Type of FU issued
984system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 49.13% # Type of FU issued
985system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.13% # Type of FU issued
986system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.13% # Type of FU issued
987system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.13% # Type of FU issued
988system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.13% # Type of FU issued
989system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.13% # Type of FU issued
990system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.13% # Type of FU issued
991system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.13% # Type of FU issued
992system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.13% # Type of FU issued
993system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.13% # Type of FU issued
994system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.13% # Type of FU issued
995system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.13% # Type of FU issued
996system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.13% # Type of FU issued
997system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.13% # Type of FU issued
998system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.13% # Type of FU issued
999system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.13% # Type of FU issued
1000system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.13% # Type of FU issued
1001system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.13% # Type of FU issued
1002system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.13% # Type of FU issued
1003system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.13% # Type of FU issued
1004system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.13% # Type of FU issued
1005system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.13% # Type of FU issued
1006system.cpu1.iq.FU_type_0::MemRead 87542 35.70% 84.82% # Type of FU issued
1007system.cpu1.iq.FU_type_0::MemWrite 37220 15.18% 100.00% # Type of FU issued
1008system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
1009system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
1010system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1011system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1012system.cpu1.iq.FU_type_0::total 245236 # Type of FU issued
1013system.cpu1.iq.rate 1.293719 # Inst issue rate
1014system.cpu1.iq.fu_busy_cnt 442 # FU busy when requested
1015system.cpu1.iq.fu_busy_rate 0.001802 # FU busy rate (busy events/executed inst)
1016system.cpu1.iq.int_inst_queue_reads 673674 # Number of integer instruction queue reads
1017system.cpu1.iq.int_inst_queue_writes 273687 # Number of integer instruction queue writes
1018system.cpu1.iq.int_inst_queue_wakeup_accesses 241932 # Number of integer instruction queue wakeup accesses
1019system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1020system.cpu1.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes
1021system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1022system.cpu1.iq.int_alu_accesses 245678 # Number of integer alu accesses
1023system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1024system.cpu1.iew.lsq.thread0.forwLoads 31875 # Number of loads that had data forwarded from stores
1025system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1026system.cpu1.iew.lsq.thread0.squashedLoads 3921 # Number of loads squashed
1027system.cpu1.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed
1028system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
1029system.cpu1.iew.lsq.thread0.squashedStores 2368 # Number of stores squashed
1030system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1031system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1032system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1033system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1034system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1035system.cpu1.iew.iewSquashCycles 2082 # Number of cycles IEW is squashing
1036system.cpu1.iew.iewBlockCycles 9074 # Number of cycles IEW is blocking
1037system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
1038system.cpu1.iew.iewDispatchedInsts 292335 # Number of instructions dispatched to IQ
1039system.cpu1.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
1040system.cpu1.iew.iewDispLoadInsts 81609 # Number of dispatched load instructions
1041system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions
1042system.cpu1.iew.iewDispNonSpecInsts 1451 # Number of dispatched non-speculative instructions
1043system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall
1044system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1045system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
1046system.cpu1.iew.predictedTakenIncorrect 411 # Number of branches that were predicted taken incorrectly
1047system.cpu1.iew.predictedNotTakenIncorrect 2165 # Number of branches that were predicted not taken incorrectly
1048system.cpu1.iew.branchMispredicts 2576 # Number of branch mispredicts detected at execute
1049system.cpu1.iew.iewExecutedInsts 243135 # Number of executed instructions
1050system.cpu1.iew.iewExecLoadInsts 80226 # Number of load instructions executed
1051system.cpu1.iew.iewExecSquashedInsts 2101 # Number of squashed instructions skipped in execute
1052system.cpu1.iew.exec_swp 0 # number of swp insts executed
1053system.cpu1.iew.exec_nop 40272 # number of nop insts executed
1054system.cpu1.iew.exec_refs 117151 # number of memory reference insts executed
1055system.cpu1.iew.exec_branches 50431 # Number of branches executed
1056system.cpu1.iew.exec_stores 36925 # Number of stores executed
1057system.cpu1.iew.exec_rate 1.282635 # Inst execution rate
1058system.cpu1.iew.wb_sent 242358 # cumulative count of insts sent to commit
1059system.cpu1.iew.wb_count 241932 # cumulative count of insts written-back
1060system.cpu1.iew.wb_producers 135113 # num instructions producing a value
1061system.cpu1.iew.wb_consumers 142615 # num instructions consuming a value
1062system.cpu1.iew.wb_rate 1.276289 # insts written-back per cycle
1063system.cpu1.iew.wb_fanout 0.947397 # average fanout of values written-back
1064system.cpu1.commit.commitSquashedInsts 22606 # The number of squashed insts skipped by commit
1065system.cpu1.commit.commitNonSpecStalls 7586 # The number of times commit has been forced to stall to communicate backwards
1066system.cpu1.commit.branchMispredicts 2004 # The number of times a branch was mispredicted
1067system.cpu1.commit.committed_per_cycle::samples 178491 # Number of insts commited each cycle
1068system.cpu1.commit.committed_per_cycle::mean 1.510961 # Number of insts commited each cycle
1069system.cpu1.commit.committed_per_cycle::stdev 2.003537 # Number of insts commited each cycle
1070system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1071system.cpu1.commit.committed_per_cycle::0 81773 45.81% 45.81% # Number of insts commited each cycle
1072system.cpu1.commit.committed_per_cycle::1 46692 26.16% 71.97% # Number of insts commited each cycle
1073system.cpu1.commit.committed_per_cycle::2 5286 2.96% 74.93% # Number of insts commited each cycle
1074system.cpu1.commit.committed_per_cycle::3 8258 4.63% 79.56% # Number of insts commited each cycle
1075system.cpu1.commit.committed_per_cycle::4 1311 0.73% 80.30% # Number of insts commited each cycle
1076system.cpu1.commit.committed_per_cycle::5 32106 17.99% 98.28% # Number of insts commited each cycle
1077system.cpu1.commit.committed_per_cycle::6 812 0.45% 98.74% # Number of insts commited each cycle
1078system.cpu1.commit.committed_per_cycle::7 1015 0.57% 99.31% # Number of insts commited each cycle
1079system.cpu1.commit.committed_per_cycle::8 1238 0.69% 100.00% # Number of insts commited each cycle
1080system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1081system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1082system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1083system.cpu1.commit.committed_per_cycle::total 178491 # Number of insts commited each cycle
1084system.cpu1.commit.committedInsts 269693 # Number of instructions committed
1085system.cpu1.commit.committedOps 269693 # Number of ops (including micro ops) committed
1086system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1087system.cpu1.commit.refs 113352 # Number of memory references committed
1088system.cpu1.commit.loads 77688 # Number of loads committed
1089system.cpu1.commit.membars 6874 # Number of memory barriers committed
1090system.cpu1.commit.branches 48495 # Number of branches committed
1091system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
1092system.cpu1.commit.int_insts 183974 # Number of committed integer instructions.
1093system.cpu1.commit.function_calls 322 # Number of function calls committed.
1094system.cpu1.commit.op_class_0::No_OpClass 39287 14.57% 14.57% # Class of committed instruction
1095system.cpu1.commit.op_class_0::IntAlu 110180 40.85% 55.42% # Class of committed instruction
1096system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.42% # Class of committed instruction
1097system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.42% # Class of committed instruction
1098system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.42% # Class of committed instruction
1099system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.42% # Class of committed instruction
1100system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.42% # Class of committed instruction
1101system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.42% # Class of committed instruction
1102system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 55.42% # Class of committed instruction
1103system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.42% # Class of committed instruction
1104system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 55.42% # Class of committed instruction
1105system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.42% # Class of committed instruction
1106system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.42% # Class of committed instruction
1107system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.42% # Class of committed instruction
1108system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.42% # Class of committed instruction
1109system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.42% # Class of committed instruction
1110system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.42% # Class of committed instruction
1111system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.42% # Class of committed instruction
1112system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.42% # Class of committed instruction
1113system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.42% # Class of committed instruction
1114system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.42% # Class of committed instruction
1115system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.42% # Class of committed instruction
1116system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.42% # Class of committed instruction
1117system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.42% # Class of committed instruction
1118system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.42% # Class of committed instruction
1119system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.42% # Class of committed instruction
1120system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.42% # Class of committed instruction
1121system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.42% # Class of committed instruction
1122system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.42% # Class of committed instruction
1123system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.42% # Class of committed instruction
1124system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.42% # Class of committed instruction
1125system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.42% # Class of committed instruction
1126system.cpu1.commit.op_class_0::MemRead 84562 31.35% 86.78% # Class of committed instruction
1127system.cpu1.commit.op_class_0::MemWrite 35664 13.22% 100.00% # Class of committed instruction
1128system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
1129system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
1130system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1131system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1132system.cpu1.commit.op_class_0::total 269693 # Class of committed instruction
1133system.cpu1.commit.bw_lim_events 1238 # number cycles where commit BW limit reached
1134system.cpu1.rob.rob_reads 468966 # The number of ROB reads
1135system.cpu1.rob.rob_writes 588835 # The number of ROB writes
1136system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself
1137system.cpu1.idleCycles 6875 # Total number of cycles that the CPU has spent unscheduled due to idling
1138system.cpu1.quiesceCycles 49435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1139system.cpu1.committedInsts 223532 # Number of Instructions Simulated
1140system.cpu1.committedOps 223532 # Number of Ops (including micro ops) Simulated
1141system.cpu1.cpi 0.848017 # CPI: Cycles Per Instruction
1142system.cpu1.cpi_total 0.848017 # CPI: Total CPI of All Threads
1143system.cpu1.ipc 1.179221 # IPC: Instructions Per Cycle
1144system.cpu1.ipc_total 1.179221 # IPC: Total IPC of All Threads
1145system.cpu1.int_regfile_reads 414823 # number of integer regfile reads
1146system.cpu1.int_regfile_writes 193738 # number of integer regfile writes
1147system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
1148system.cpu1.misc_regfile_reads 118957 # number of misc regfile reads
1149system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
1150system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1151system.cpu1.dcache.tags.replacements 0 # number of replacements
1152system.cpu1.dcache.tags.tagsinuse 26.585143 # Cycle average of tags in use
1153system.cpu1.dcache.tags.total_refs 42712 # Total number of references to valid blocks.
1154system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
1155system.cpu1.dcache.tags.avg_refs 1377.806452 # Average number of references to valid blocks.
1156system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1157system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.585143 # Average occupied blocks per requestor
1158system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051924 # Average percentage of cache occupancy
1159system.cpu1.dcache.tags.occ_percent::total 0.051924 # Average percentage of cache occupancy
1160system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
1161system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
1162system.cpu1.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
1163system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
1164system.cpu1.dcache.tags.tag_accesses 336213 # Number of tag accesses
1165system.cpu1.dcache.tags.data_accesses 336213 # Number of data accesses
1166system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1167system.cpu1.dcache.ReadReq_hits::cpu1.data 47868 # number of ReadReq hits
1168system.cpu1.dcache.ReadReq_hits::total 47868 # number of ReadReq hits
1169system.cpu1.dcache.WriteReq_hits::cpu1.data 35447 # number of WriteReq hits
1170system.cpu1.dcache.WriteReq_hits::total 35447 # number of WriteReq hits
1171system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
1172system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
1173system.cpu1.dcache.demand_hits::cpu1.data 83315 # number of demand (read+write) hits
1174system.cpu1.dcache.demand_hits::total 83315 # number of demand (read+write) hits
1175system.cpu1.dcache.overall_hits::cpu1.data 83315 # number of overall hits
1176system.cpu1.dcache.overall_hits::total 83315 # number of overall hits
1177system.cpu1.dcache.ReadReq_misses::cpu1.data 458 # number of ReadReq misses
1178system.cpu1.dcache.ReadReq_misses::total 458 # number of ReadReq misses
1179system.cpu1.dcache.WriteReq_misses::cpu1.data 151 # number of WriteReq misses
1180system.cpu1.dcache.WriteReq_misses::total 151 # number of WriteReq misses
1181system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses
1182system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses
1183system.cpu1.dcache.demand_misses::cpu1.data 609 # number of demand (read+write) misses
1184system.cpu1.dcache.demand_misses::total 609 # number of demand (read+write) misses
1185system.cpu1.dcache.overall_misses::cpu1.data 609 # number of overall misses
1186system.cpu1.dcache.overall_misses::total 609 # number of overall misses
1187system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4693000 # number of ReadReq miss cycles
1188system.cpu1.dcache.ReadReq_miss_latency::total 4693000 # number of ReadReq miss cycles
1189system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3635500 # number of WriteReq miss cycles
1190system.cpu1.dcache.WriteReq_miss_latency::total 3635500 # number of WriteReq miss cycles
1191system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 328500 # number of SwapReq miss cycles
1192system.cpu1.dcache.SwapReq_miss_latency::total 328500 # number of SwapReq miss cycles
1193system.cpu1.dcache.demand_miss_latency::cpu1.data 8328500 # number of demand (read+write) miss cycles
1194system.cpu1.dcache.demand_miss_latency::total 8328500 # number of demand (read+write) miss cycles
1195system.cpu1.dcache.overall_miss_latency::cpu1.data 8328500 # number of overall miss cycles
1196system.cpu1.dcache.overall_miss_latency::total 8328500 # number of overall miss cycles
1197system.cpu1.dcache.ReadReq_accesses::cpu1.data 48326 # number of ReadReq accesses(hits+misses)
1198system.cpu1.dcache.ReadReq_accesses::total 48326 # number of ReadReq accesses(hits+misses)
1199system.cpu1.dcache.WriteReq_accesses::cpu1.data 35598 # number of WriteReq accesses(hits+misses)
1200system.cpu1.dcache.WriteReq_accesses::total 35598 # number of WriteReq accesses(hits+misses)
1201system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
1202system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
1203system.cpu1.dcache.demand_accesses::cpu1.data 83924 # number of demand (read+write) accesses
1204system.cpu1.dcache.demand_accesses::total 83924 # number of demand (read+write) accesses
1205system.cpu1.dcache.overall_accesses::cpu1.data 83924 # number of overall (read+write) accesses
1206system.cpu1.dcache.overall_accesses::total 83924 # number of overall (read+write) accesses
1207system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009477 # miss rate for ReadReq accesses
1208system.cpu1.dcache.ReadReq_miss_rate::total 0.009477 # miss rate for ReadReq accesses
1209system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004242 # miss rate for WriteReq accesses
1210system.cpu1.dcache.WriteReq_miss_rate::total 0.004242 # miss rate for WriteReq accesses
1211system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.757576 # miss rate for SwapReq accesses
1212system.cpu1.dcache.SwapReq_miss_rate::total 0.757576 # miss rate for SwapReq accesses
1213system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007257 # miss rate for demand accesses
1214system.cpu1.dcache.demand_miss_rate::total 0.007257 # miss rate for demand accesses
1215system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007257 # miss rate for overall accesses
1216system.cpu1.dcache.overall_miss_rate::total 0.007257 # miss rate for overall accesses
1217system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10246.724891 # average ReadReq miss latency
1218system.cpu1.dcache.ReadReq_avg_miss_latency::total 10246.724891 # average ReadReq miss latency
1219system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24076.158940 # average WriteReq miss latency
1220system.cpu1.dcache.WriteReq_avg_miss_latency::total 24076.158940 # average WriteReq miss latency
1221system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6570 # average SwapReq miss latency
1222system.cpu1.dcache.SwapReq_avg_miss_latency::total 6570 # average SwapReq miss latency
1223system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency
1224system.cpu1.dcache.demand_avg_miss_latency::total 13675.697865 # average overall miss latency
1225system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency
1226system.cpu1.dcache.overall_avg_miss_latency::total 13675.697865 # average overall miss latency
1227system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1228system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1229system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1230system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1231system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1232system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1233system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 292 # number of ReadReq MSHR hits
1234system.cpu1.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits
1235system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits
1236system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits
1237system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 4 # number of SwapReq MSHR hits
1238system.cpu1.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits
1239system.cpu1.dcache.demand_mshr_hits::cpu1.data 339 # number of demand (read+write) MSHR hits
1240system.cpu1.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
1241system.cpu1.dcache.overall_mshr_hits::cpu1.data 339 # number of overall MSHR hits
1242system.cpu1.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
1243system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses
1244system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
1245system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses
1246system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1247system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 46 # number of SwapReq MSHR misses
1248system.cpu1.dcache.SwapReq_mshr_misses::total 46 # number of SwapReq MSHR misses
1249system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
1250system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
1251system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
1252system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
1253system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1641000 # number of ReadReq MSHR miss cycles
1254system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1641000 # number of ReadReq MSHR miss cycles
1255system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1541000 # number of WriteReq MSHR miss cycles
1256system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1541000 # number of WriteReq MSHR miss cycles
1257system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 278500 # number of SwapReq MSHR miss cycles
1258system.cpu1.dcache.SwapReq_mshr_miss_latency::total 278500 # number of SwapReq MSHR miss cycles
1259system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3182000 # number of demand (read+write) MSHR miss cycles
1260system.cpu1.dcache.demand_mshr_miss_latency::total 3182000 # number of demand (read+write) MSHR miss cycles
1261system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3182000 # number of overall MSHR miss cycles
1262system.cpu1.dcache.overall_mshr_miss_latency::total 3182000 # number of overall MSHR miss cycles
1263system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003435 # mshr miss rate for ReadReq accesses
1264system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003435 # mshr miss rate for ReadReq accesses
1265system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002922 # mshr miss rate for WriteReq accesses
1266system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002922 # mshr miss rate for WriteReq accesses
1267system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.696970 # mshr miss rate for SwapReq accesses
1268system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.696970 # mshr miss rate for SwapReq accesses
1269system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for demand accesses
1270system.cpu1.dcache.demand_mshr_miss_rate::total 0.003217 # mshr miss rate for demand accesses
1271system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for overall accesses
1272system.cpu1.dcache.overall_mshr_miss_rate::total 0.003217 # mshr miss rate for overall accesses
1273system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9885.542169 # average ReadReq mshr miss latency
1274system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9885.542169 # average ReadReq mshr miss latency
1275system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14817.307692 # average WriteReq mshr miss latency
1276system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14817.307692 # average WriteReq mshr miss latency
1277system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6054.347826 # average SwapReq mshr miss latency
1278system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6054.347826 # average SwapReq mshr miss latency
1279system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11785.185185 # average overall mshr miss latency
1280system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11785.185185 # average overall mshr miss latency
1281system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11785.185185 # average overall mshr miss latency
1282system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11785.185185 # average overall mshr miss latency
1283system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1284system.cpu1.icache.tags.replacements 507 # number of replacements
1285system.cpu1.icache.tags.tagsinuse 97.467355 # Cycle average of tags in use
1286system.cpu1.icache.tags.total_refs 26848 # Total number of references to valid blocks.
1287system.cpu1.icache.tags.sampled_refs 643 # Sample count of references to valid blocks.
1288system.cpu1.icache.tags.avg_refs 41.754277 # Average number of references to valid blocks.
1289system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1290system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.467355 # Average occupied blocks per requestor
1291system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190366 # Average percentage of cache occupancy
1292system.cpu1.icache.tags.occ_percent::total 0.190366 # Average percentage of cache occupancy
1293system.cpu1.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id
1294system.cpu1.icache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
1295system.cpu1.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id
1296system.cpu1.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id
1297system.cpu1.icache.tags.tag_accesses 28295 # Number of tag accesses
1298system.cpu1.icache.tags.data_accesses 28295 # Number of data accesses
1299system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1300system.cpu1.icache.ReadReq_hits::cpu1.inst 26848 # number of ReadReq hits
1301system.cpu1.icache.ReadReq_hits::total 26848 # number of ReadReq hits
1302system.cpu1.icache.demand_hits::cpu1.inst 26848 # number of demand (read+write) hits
1303system.cpu1.icache.demand_hits::total 26848 # number of demand (read+write) hits
1304system.cpu1.icache.overall_hits::cpu1.inst 26848 # number of overall hits
1305system.cpu1.icache.overall_hits::total 26848 # number of overall hits
1306system.cpu1.icache.ReadReq_misses::cpu1.inst 804 # number of ReadReq misses
1307system.cpu1.icache.ReadReq_misses::total 804 # number of ReadReq misses
1308system.cpu1.icache.demand_misses::cpu1.inst 804 # number of demand (read+write) misses
1309system.cpu1.icache.demand_misses::total 804 # number of demand (read+write) misses
1310system.cpu1.icache.overall_misses::cpu1.inst 804 # number of overall misses
1311system.cpu1.icache.overall_misses::total 804 # number of overall misses
1312system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19785000 # number of ReadReq miss cycles
1313system.cpu1.icache.ReadReq_miss_latency::total 19785000 # number of ReadReq miss cycles
1314system.cpu1.icache.demand_miss_latency::cpu1.inst 19785000 # number of demand (read+write) miss cycles
1315system.cpu1.icache.demand_miss_latency::total 19785000 # number of demand (read+write) miss cycles
1316system.cpu1.icache.overall_miss_latency::cpu1.inst 19785000 # number of overall miss cycles
1317system.cpu1.icache.overall_miss_latency::total 19785000 # number of overall miss cycles
1318system.cpu1.icache.ReadReq_accesses::cpu1.inst 27652 # number of ReadReq accesses(hits+misses)
1319system.cpu1.icache.ReadReq_accesses::total 27652 # number of ReadReq accesses(hits+misses)
1320system.cpu1.icache.demand_accesses::cpu1.inst 27652 # number of demand (read+write) accesses
1321system.cpu1.icache.demand_accesses::total 27652 # number of demand (read+write) accesses
1322system.cpu1.icache.overall_accesses::cpu1.inst 27652 # number of overall (read+write) accesses
1323system.cpu1.icache.overall_accesses::total 27652 # number of overall (read+write) accesses
1324system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029076 # miss rate for ReadReq accesses
1325system.cpu1.icache.ReadReq_miss_rate::total 0.029076 # miss rate for ReadReq accesses
1326system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029076 # miss rate for demand accesses
1327system.cpu1.icache.demand_miss_rate::total 0.029076 # miss rate for demand accesses
1328system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029076 # miss rate for overall accesses
1329system.cpu1.icache.overall_miss_rate::total 0.029076 # miss rate for overall accesses
1330system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24608.208955 # average ReadReq miss latency
1331system.cpu1.icache.ReadReq_avg_miss_latency::total 24608.208955 # average ReadReq miss latency
1332system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency
1333system.cpu1.icache.demand_avg_miss_latency::total 24608.208955 # average overall miss latency
1334system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency
1335system.cpu1.icache.overall_avg_miss_latency::total 24608.208955 # average overall miss latency
1336system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked
1337system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1338system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked
1339system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1340system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked
1341system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1342system.cpu1.icache.writebacks::writebacks 507 # number of writebacks
1343system.cpu1.icache.writebacks::total 507 # number of writebacks
1344system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 161 # number of ReadReq MSHR hits
1345system.cpu1.icache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits
1346system.cpu1.icache.demand_mshr_hits::cpu1.inst 161 # number of demand (read+write) MSHR hits
1347system.cpu1.icache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits
1348system.cpu1.icache.overall_mshr_hits::cpu1.inst 161 # number of overall MSHR hits
1349system.cpu1.icache.overall_mshr_hits::total 161 # number of overall MSHR hits
1350system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 643 # number of ReadReq MSHR misses
1351system.cpu1.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
1352system.cpu1.icache.demand_mshr_misses::cpu1.inst 643 # number of demand (read+write) MSHR misses
1353system.cpu1.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
1354system.cpu1.icache.overall_mshr_misses::cpu1.inst 643 # number of overall MSHR misses
1355system.cpu1.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
1356system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15397000 # number of ReadReq MSHR miss cycles
1357system.cpu1.icache.ReadReq_mshr_miss_latency::total 15397000 # number of ReadReq MSHR miss cycles
1358system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15397000 # number of demand (read+write) MSHR miss cycles
1359system.cpu1.icache.demand_mshr_miss_latency::total 15397000 # number of demand (read+write) MSHR miss cycles
1360system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15397000 # number of overall MSHR miss cycles
1361system.cpu1.icache.overall_mshr_miss_latency::total 15397000 # number of overall MSHR miss cycles
1362system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for ReadReq accesses
1363system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023253 # mshr miss rate for ReadReq accesses
1364system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for demand accesses
1365system.cpu1.icache.demand_mshr_miss_rate::total 0.023253 # mshr miss rate for demand accesses
1366system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for overall accesses
1367system.cpu1.icache.overall_mshr_miss_rate::total 0.023253 # mshr miss rate for overall accesses
1368system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average ReadReq mshr miss latency
1369system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23945.567652 # average ReadReq mshr miss latency
1370system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency
1371system.cpu1.icache.demand_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency
1372system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency
1373system.cpu1.icache.overall_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency
1374system.cpu2.branchPred.lookups 68293 # Number of BP lookups
1375system.cpu2.branchPred.condPredicted 60753 # Number of conditional branches predicted
1376system.cpu2.branchPred.condIncorrect 2314 # Number of conditional branches incorrect
1377system.cpu2.branchPred.BTBLookups 60518 # Number of BTB lookups
1378system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
1379system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1380system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
1381system.cpu2.branchPred.usedRAS 1899 # Number of times the RAS was used to get a target.
1382system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
1383system.cpu2.branchPred.indirectLookups 60518 # Number of indirect predictor lookups.
1384system.cpu2.branchPred.indirectHits 50086 # Number of indirect target hits.
1385system.cpu2.branchPred.indirectMisses 10432 # Number of indirect misses.
1386system.cpu2.branchPredindirectMispredicted 1220 # Number of mispredicted indirect branches.
1387system.cpu2.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states
1388system.cpu2.numCycles 189148 # number of cpu cycles simulated
1389system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1390system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1391system.cpu2.fetch.icacheStallCycles 37019 # Number of cycles fetch is stalled on an Icache miss
1392system.cpu2.fetch.Insts 374433 # Number of instructions fetch has processed
1393system.cpu2.fetch.Branches 68293 # Number of branches that fetch encountered
1394system.cpu2.fetch.predictedBranches 51985 # Number of branches that fetch has predicted taken
1395system.cpu2.fetch.Cycles 146261 # Number of cycles fetch has run and was not squashing or blocked
1396system.cpu2.fetch.SquashCycles 4785 # Number of cycles fetch has spent squashing
1397system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1398system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
1399system.cpu2.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps
1400system.cpu2.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
1401system.cpu2.fetch.CacheLines 25650 # Number of cache lines fetched
1402system.cpu2.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed
1403system.cpu2.fetch.rateDist::samples 187354 # Number of instructions fetched each cycle (Total)
1404system.cpu2.fetch.rateDist::mean 1.998532 # Number of instructions fetched each cycle (Total)
1405system.cpu2.fetch.rateDist::stdev 2.363195 # Number of instructions fetched each cycle (Total)
1406system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1407system.cpu2.fetch.rateDist::0 64471 34.41% 34.41% # Number of instructions fetched each cycle (Total)
1408system.cpu2.fetch.rateDist::1 60026 32.04% 66.45% # Number of instructions fetched each cycle (Total)
1409system.cpu2.fetch.rateDist::2 7128 3.80% 70.25% # Number of instructions fetched each cycle (Total)
1410system.cpu2.fetch.rateDist::3 3545 1.89% 72.15% # Number of instructions fetched each cycle (Total)
1411system.cpu2.fetch.rateDist::4 670 0.36% 72.50% # Number of instructions fetched each cycle (Total)
1412system.cpu2.fetch.rateDist::5 40604 21.67% 94.18% # Number of instructions fetched each cycle (Total)
1413system.cpu2.fetch.rateDist::6 1041 0.56% 94.73% # Number of instructions fetched each cycle (Total)
1414system.cpu2.fetch.rateDist::7 1382 0.74% 95.47% # Number of instructions fetched each cycle (Total)
1415system.cpu2.fetch.rateDist::8 8487 4.53% 100.00% # Number of instructions fetched each cycle (Total)
1416system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1417system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1418system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1419system.cpu2.fetch.rateDist::total 187354 # Number of instructions fetched each cycle (Total)
1420system.cpu2.fetch.branchRate 0.361056 # Number of branch fetches per cycle
1421system.cpu2.fetch.rate 1.979577 # Number of inst fetches per cycle
1422system.cpu2.decode.IdleCycles 21923 # Number of cycles decode is idle
1423system.cpu2.decode.BlockedCycles 61377 # Number of cycles decode is blocked
1424system.cpu2.decode.RunCycles 97674 # Number of cycles decode is running
1425system.cpu2.decode.UnblockCycles 3978 # Number of cycles decode is unblocking
1426system.cpu2.decode.SquashCycles 2392 # Number of cycles decode is squashing
1427system.cpu2.decode.DecodedInsts 343665 # Number of instructions handled by decode
1428system.cpu2.rename.SquashCycles 2392 # Number of cycles rename is squashing
1429system.cpu2.rename.IdleCycles 22954 # Number of cycles rename is idle
1430system.cpu2.rename.BlockCycles 28666 # Number of cycles rename is blocking
1431system.cpu2.rename.serializeStallCycles 13829 # count of cycles rename stalled for serializing inst
1432system.cpu2.rename.RunCycles 98633 # Number of cycles rename is running
1433system.cpu2.rename.UnblockCycles 20870 # Number of cycles rename is unblocking
1434system.cpu2.rename.RenamedInsts 337053 # Number of instructions processed by rename
1435system.cpu2.rename.IQFullEvents 18126 # Number of times rename has blocked due to IQ full
1436system.cpu2.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full
1437system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
1438system.cpu2.rename.RenamedOperands 236414 # Number of destination operands rename has renamed
1439system.cpu2.rename.RenameLookups 645955 # Number of register rename lookups that rename has made
1440system.cpu2.rename.int_rename_lookups 501894 # Number of integer rename lookups
1441system.cpu2.rename.fp_rename_lookups 22 # Number of floating rename lookups
1442system.cpu2.rename.CommittedMaps 208648 # Number of HB maps that are committed
1443system.cpu2.rename.UndoneMaps 27766 # Number of HB maps that are undone due to squashing
1444system.cpu2.rename.serializingInsts 1626 # count of serializing insts renamed
1445system.cpu2.rename.tempSerializingInsts 1738 # count of temporary serializing insts renamed
1446system.cpu2.rename.skidInsts 26523 # count of insts added to the skid buffer
1447system.cpu2.memDep0.insertedLoads 93867 # Number of loads inserted to the mem dependence unit.
1448system.cpu2.memDep0.insertedStores 44893 # Number of stores inserted to the mem dependence unit.
1449system.cpu2.memDep0.conflictingLoads 44587 # Number of conflicting loads.
1450system.cpu2.memDep0.conflictingStores 38578 # Number of conflicting stores.
1451system.cpu2.iq.iqInstsAdded 275945 # Number of instructions added to the IQ (excludes non-spec)
1452system.cpu2.iq.iqNonSpecInstsAdded 7527 # Number of non-speculative instructions added to the IQ
1453system.cpu2.iq.iqInstsIssued 275850 # Number of instructions issued
1454system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued
1455system.cpu2.iq.iqSquashedInstsExamined 23937 # Number of squashed instructions iterated over during squash; mainly for profiling
1456system.cpu2.iq.iqSquashedOperandsExamined 18592 # Number of squashed operands that are examined and possibly removed from graph
1457system.cpu2.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed
1458system.cpu2.iq.issued_per_cycle::samples 187354 # Number of insts issued each cycle
1459system.cpu2.iq.issued_per_cycle::mean 1.472346 # Number of insts issued each cycle
1460system.cpu2.iq.issued_per_cycle::stdev 1.381832 # Number of insts issued each cycle
1461system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1462system.cpu2.iq.issued_per_cycle::0 68951 36.80% 36.80% # Number of insts issued each cycle
1463system.cpu2.iq.issued_per_cycle::1 24397 13.02% 49.82% # Number of insts issued each cycle
1464system.cpu2.iq.issued_per_cycle::2 43633 23.29% 73.11% # Number of insts issued each cycle
1465system.cpu2.iq.issued_per_cycle::3 43435 23.18% 96.30% # Number of insts issued each cycle
1466system.cpu2.iq.issued_per_cycle::4 3472 1.85% 98.15% # Number of insts issued each cycle
1467system.cpu2.iq.issued_per_cycle::5 1779 0.95% 99.10% # Number of insts issued each cycle
1468system.cpu2.iq.issued_per_cycle::6 1003 0.54% 99.63% # Number of insts issued each cycle
1469system.cpu2.iq.issued_per_cycle::7 391 0.21% 99.84% # Number of insts issued each cycle
1470system.cpu2.iq.issued_per_cycle::8 293 0.16% 100.00% # Number of insts issued each cycle
1471system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1472system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1473system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1474system.cpu2.iq.issued_per_cycle::total 187354 # Number of insts issued each cycle
1475system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1476system.cpu2.iq.fu_full::IntAlu 191 39.71% 39.71% # attempts to use FU when none available
1477system.cpu2.iq.fu_full::IntMult 0 0.00% 39.71% # attempts to use FU when none available
1478system.cpu2.iq.fu_full::IntDiv 0 0.00% 39.71% # attempts to use FU when none available
1479system.cpu2.iq.fu_full::FloatAdd 0 0.00% 39.71% # attempts to use FU when none available
1480system.cpu2.iq.fu_full::FloatCmp 0 0.00% 39.71% # attempts to use FU when none available
1481system.cpu2.iq.fu_full::FloatCvt 0 0.00% 39.71% # attempts to use FU when none available
1482system.cpu2.iq.fu_full::FloatMult 0 0.00% 39.71% # attempts to use FU when none available
1483system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available
1484system.cpu2.iq.fu_full::FloatDiv 0 0.00% 39.71% # attempts to use FU when none available
1485system.cpu2.iq.fu_full::FloatMisc 0 0.00% 39.71% # attempts to use FU when none available
1486system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 39.71% # attempts to use FU when none available
1487system.cpu2.iq.fu_full::SimdAdd 0 0.00% 39.71% # attempts to use FU when none available
1488system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 39.71% # attempts to use FU when none available
1489system.cpu2.iq.fu_full::SimdAlu 0 0.00% 39.71% # attempts to use FU when none available
1490system.cpu2.iq.fu_full::SimdCmp 0 0.00% 39.71% # attempts to use FU when none available
1491system.cpu2.iq.fu_full::SimdCvt 0 0.00% 39.71% # attempts to use FU when none available
1492system.cpu2.iq.fu_full::SimdMisc 0 0.00% 39.71% # attempts to use FU when none available
1493system.cpu2.iq.fu_full::SimdMult 0 0.00% 39.71% # attempts to use FU when none available
1494system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 39.71% # attempts to use FU when none available
1495system.cpu2.iq.fu_full::SimdShift 0 0.00% 39.71% # attempts to use FU when none available
1496system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 39.71% # attempts to use FU when none available
1497system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 39.71% # attempts to use FU when none available
1498system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 39.71% # attempts to use FU when none available
1499system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 39.71% # attempts to use FU when none available
1500system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 39.71% # attempts to use FU when none available
1501system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 39.71% # attempts to use FU when none available
1502system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 39.71% # attempts to use FU when none available
1503system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 39.71% # attempts to use FU when none available
1504system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 39.71% # attempts to use FU when none available
1505system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available
1506system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 39.71% # attempts to use FU when none available
1507system.cpu2.iq.fu_full::MemRead 64 13.31% 53.01% # attempts to use FU when none available
1508system.cpu2.iq.fu_full::MemWrite 226 46.99% 100.00% # attempts to use FU when none available
1509system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
1510system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
1511system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1512system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1513system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
1514system.cpu2.iq.FU_type_0::IntAlu 133523 48.40% 48.40% # Type of FU issued
1515system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.40% # Type of FU issued
1516system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.40% # Type of FU issued
1517system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.40% # Type of FU issued
1518system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.40% # Type of FU issued
1519system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.40% # Type of FU issued
1520system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.40% # Type of FU issued
1521system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.40% # Type of FU issued
1522system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.40% # Type of FU issued
1523system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.40% # Type of FU issued
1524system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.40% # Type of FU issued
1525system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.40% # Type of FU issued
1526system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.40% # Type of FU issued
1527system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.40% # Type of FU issued
1528system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.40% # Type of FU issued
1529system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.40% # Type of FU issued
1530system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.40% # Type of FU issued
1531system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.40% # Type of FU issued
1532system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.40% # Type of FU issued
1533system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.40% # Type of FU issued
1534system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.40% # Type of FU issued
1535system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.40% # Type of FU issued
1536system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.40% # Type of FU issued
1537system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.40% # Type of FU issued
1538system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.40% # Type of FU issued
1539system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.40% # Type of FU issued
1540system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.40% # Type of FU issued
1541system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.40% # Type of FU issued
1542system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.40% # Type of FU issued
1543system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.40% # Type of FU issued
1544system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.40% # Type of FU issued
1545system.cpu2.iq.FU_type_0::MemRead 98433 35.68% 84.09% # Type of FU issued
1546system.cpu2.iq.FU_type_0::MemWrite 43894 15.91% 100.00% # Type of FU issued
1547system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
1548system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
1549system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1550system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1551system.cpu2.iq.FU_type_0::total 275850 # Type of FU issued
1552system.cpu2.iq.rate 1.458382 # Inst issue rate
1553system.cpu2.iq.fu_busy_cnt 481 # FU busy when requested
1554system.cpu2.iq.fu_busy_rate 0.001744 # FU busy rate (busy events/executed inst)
1555system.cpu2.iq.int_inst_queue_reads 739606 # Number of integer instruction queue reads
1556system.cpu2.iq.int_inst_queue_writes 307404 # Number of integer instruction queue writes
1557system.cpu2.iq.int_inst_queue_wakeup_accesses 272120 # Number of integer instruction queue wakeup accesses
1558system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1559system.cpu2.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes
1560system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1561system.cpu2.iq.int_alu_accesses 276331 # Number of integer alu accesses
1562system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
1563system.cpu2.iew.lsq.thread0.forwLoads 38492 # Number of loads that had data forwarded from stores
1564system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1565system.cpu2.iew.lsq.thread0.squashedLoads 4293 # Number of loads squashed
1566system.cpu2.iew.lsq.thread0.ignoredResponses 47 # Number of memory responses ignored because the instruction is squashed
1567system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
1568system.cpu2.iew.lsq.thread0.squashedStores 2655 # Number of stores squashed
1569system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1570system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1571system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1572system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1573system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1574system.cpu2.iew.iewSquashCycles 2392 # Number of cycles IEW is squashing
1575system.cpu2.iew.iewBlockCycles 7918 # Number of cycles IEW is blocking
1576system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
1577system.cpu2.iew.iewDispatchedInsts 329268 # Number of instructions dispatched to IQ
1578system.cpu2.iew.iewDispSquashedInsts 414 # Number of squashed instructions skipped by dispatch
1579system.cpu2.iew.iewDispLoadInsts 93867 # Number of dispatched load instructions
1580system.cpu2.iew.iewDispStoreInsts 44893 # Number of dispatched store instructions
1581system.cpu2.iew.iewDispNonSpecInsts 1518 # Number of dispatched non-speculative instructions
1582system.cpu2.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
1583system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1584system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
1585system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
1586system.cpu2.iew.predictedNotTakenIncorrect 2459 # Number of branches that were predicted not taken incorrectly
1587system.cpu2.iew.branchMispredicts 2902 # Number of branch mispredicts detected at execute
1588system.cpu2.iew.iewExecutedInsts 273426 # Number of executed instructions
1589system.cpu2.iew.iewExecLoadInsts 92301 # Number of load instructions executed
1590system.cpu2.iew.iewExecSquashedInsts 2424 # Number of squashed instructions skipped in execute
1591system.cpu2.iew.exec_swp 0 # number of swp insts executed
1592system.cpu2.iew.exec_nop 45796 # number of nop insts executed
1593system.cpu2.iew.exec_refs 135892 # number of memory reference insts executed
1594system.cpu2.iew.exec_branches 56020 # Number of branches executed
1595system.cpu2.iew.exec_stores 43591 # Number of stores executed
1596system.cpu2.iew.exec_rate 1.445566 # Inst execution rate
1597system.cpu2.iew.wb_sent 272582 # cumulative count of insts sent to commit
1598system.cpu2.iew.wb_count 272120 # cumulative count of insts written-back
1599system.cpu2.iew.wb_producers 153730 # num instructions producing a value
1600system.cpu2.iew.wb_consumers 161299 # num instructions consuming a value
1601system.cpu2.iew.wb_rate 1.438662 # insts written-back per cycle
1602system.cpu2.iew.wb_fanout 0.953075 # average fanout of values written-back
1603system.cpu2.commit.commitSquashedInsts 25088 # The number of squashed insts skipped by commit
1604system.cpu2.commit.commitNonSpecStalls 6354 # The number of times commit has been forced to stall to communicate backwards
1605system.cpu2.commit.branchMispredicts 2314 # The number of times a branch was mispredicted
1606system.cpu2.commit.committed_per_cycle::samples 182587 # Number of insts commited each cycle
1607system.cpu2.commit.committed_per_cycle::mean 1.665803 # Number of insts commited each cycle
1608system.cpu2.commit.committed_per_cycle::stdev 2.057645 # Number of insts commited each cycle
1609system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1610system.cpu2.commit.committed_per_cycle::0 74839 40.99% 40.99% # Number of insts commited each cycle
1611system.cpu2.commit.committed_per_cycle::1 52317 28.65% 69.64% # Number of insts commited each cycle
1612system.cpu2.commit.committed_per_cycle::2 5497 3.01% 72.65% # Number of insts commited each cycle
1613system.cpu2.commit.committed_per_cycle::3 6991 3.83% 76.48% # Number of insts commited each cycle
1614system.cpu2.commit.committed_per_cycle::4 1341 0.73% 77.22% # Number of insts commited each cycle
1615system.cpu2.commit.committed_per_cycle::5 38632 21.16% 98.37% # Number of insts commited each cycle
1616system.cpu2.commit.committed_per_cycle::6 681 0.37% 98.75% # Number of insts commited each cycle
1617system.cpu2.commit.committed_per_cycle::7 1052 0.58% 99.32% # Number of insts commited each cycle
1618system.cpu2.commit.committed_per_cycle::8 1237 0.68% 100.00% # Number of insts commited each cycle
1619system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1620system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1621system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1622system.cpu2.commit.committed_per_cycle::total 182587 # Number of insts commited each cycle
1623system.cpu2.commit.committedInsts 304154 # Number of instructions committed
1624system.cpu2.commit.committedOps 304154 # Number of ops (including micro ops) committed
1625system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1626system.cpu2.commit.refs 131812 # Number of memory references committed
1627system.cpu2.commit.loads 89574 # Number of loads committed
1628system.cpu2.commit.membars 5632 # Number of memory barriers committed
1629system.cpu2.commit.branches 53837 # Number of branches committed
1630system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1631system.cpu2.commit.int_insts 207761 # Number of committed integer instructions.
1632system.cpu2.commit.function_calls 322 # Number of function calls committed.
1633system.cpu2.commit.op_class_0::No_OpClass 44619 14.67% 14.67% # Class of committed instruction
1634system.cpu2.commit.op_class_0::IntAlu 122091 40.14% 54.81% # Class of committed instruction
1635system.cpu2.commit.op_class_0::IntMult 0 0.00% 54.81% # Class of committed instruction
1636system.cpu2.commit.op_class_0::IntDiv 0 0.00% 54.81% # Class of committed instruction
1637system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 54.81% # Class of committed instruction
1638system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 54.81% # Class of committed instruction
1639system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 54.81% # Class of committed instruction
1640system.cpu2.commit.op_class_0::FloatMult 0 0.00% 54.81% # Class of committed instruction
1641system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 54.81% # Class of committed instruction
1642system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 54.81% # Class of committed instruction
1643system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 54.81% # Class of committed instruction
1644system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 54.81% # Class of committed instruction
1645system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 54.81% # Class of committed instruction
1646system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 54.81% # Class of committed instruction
1647system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 54.81% # Class of committed instruction
1648system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 54.81% # Class of committed instruction
1649system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 54.81% # Class of committed instruction
1650system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 54.81% # Class of committed instruction
1651system.cpu2.commit.op_class_0::SimdMult 0 0.00% 54.81% # Class of committed instruction
1652system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 54.81% # Class of committed instruction
1653system.cpu2.commit.op_class_0::SimdShift 0 0.00% 54.81% # Class of committed instruction
1654system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 54.81% # Class of committed instruction
1655system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 54.81% # Class of committed instruction
1656system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 54.81% # Class of committed instruction
1657system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 54.81% # Class of committed instruction
1658system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 54.81% # Class of committed instruction
1659system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 54.81% # Class of committed instruction
1660system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 54.81% # Class of committed instruction
1661system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 54.81% # Class of committed instruction
1662system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 54.81% # Class of committed instruction
1663system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.81% # Class of committed instruction
1664system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.81% # Class of committed instruction
1665system.cpu2.commit.op_class_0::MemRead 95206 31.30% 86.11% # Class of committed instruction
1666system.cpu2.commit.op_class_0::MemWrite 42238 13.89% 100.00% # Class of committed instruction
1667system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
1668system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
1669system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1670system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1671system.cpu2.commit.op_class_0::total 304154 # Class of committed instruction
1672system.cpu2.commit.bw_lim_events 1237 # number cycles where commit BW limit reached
1673system.cpu2.rob.rob_reads 510006 # The number of ROB reads
1674system.cpu2.rob.rob_writes 663292 # The number of ROB writes
1675system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
1676system.cpu2.idleCycles 1794 # Total number of cycles that the CPU has spent unscheduled due to idling
1677system.cpu2.quiesceCycles 49847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1678system.cpu2.committedInsts 253903 # Number of Instructions Simulated
1679system.cpu2.committedOps 253903 # Number of Ops (including micro ops) Simulated
1680system.cpu2.cpi 0.744962 # CPI: Cycles Per Instruction
1681system.cpu2.cpi_total 0.744962 # CPI: Total CPI of All Threads
1682system.cpu2.ipc 1.342351 # IPC: Instructions Per Cycle
1683system.cpu2.ipc_total 1.342351 # IPC: Total IPC of All Threads
1684system.cpu2.int_regfile_reads 471960 # number of integer regfile reads
1685system.cpu2.int_regfile_writes 219741 # number of integer regfile writes
1686system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
1687system.cpu2.misc_regfile_reads 137767 # number of misc regfile reads
1688system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
1689system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1690system.cpu2.dcache.tags.replacements 0 # number of replacements
1691system.cpu2.dcache.tags.tagsinuse 25.074061 # Cycle average of tags in use
1692system.cpu2.dcache.tags.total_refs 49166 # Total number of references to valid blocks.
1693system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1694system.cpu2.dcache.tags.avg_refs 1695.379310 # Average number of references to valid blocks.
1695system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1696system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.074061 # Average occupied blocks per requestor
1697system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048973 # Average percentage of cache occupancy
1698system.cpu2.dcache.tags.occ_percent::total 0.048973 # Average percentage of cache occupancy
1699system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1700system.cpu2.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
1701system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1702system.cpu2.dcache.tags.tag_accesses 384293 # Number of tag accesses
1703system.cpu2.dcache.tags.data_accesses 384293 # Number of data accesses
1704system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1705system.cpu2.dcache.ReadReq_hits::cpu2.data 53240 # number of ReadReq hits
1706system.cpu2.dcache.ReadReq_hits::total 53240 # number of ReadReq hits
1707system.cpu2.dcache.WriteReq_hits::cpu2.data 42018 # number of WriteReq hits
1708system.cpu2.dcache.WriteReq_hits::total 42018 # number of WriteReq hits
1709system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
1710system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
1711system.cpu2.dcache.demand_hits::cpu2.data 95258 # number of demand (read+write) hits
1712system.cpu2.dcache.demand_hits::total 95258 # number of demand (read+write) hits
1713system.cpu2.dcache.overall_hits::cpu2.data 95258 # number of overall hits
1714system.cpu2.dcache.overall_hits::total 95258 # number of overall hits
1715system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses
1716system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses
1717system.cpu2.dcache.WriteReq_misses::cpu2.data 144 # number of WriteReq misses
1718system.cpu2.dcache.WriteReq_misses::total 144 # number of WriteReq misses
1719system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses
1720system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses
1721system.cpu2.dcache.demand_misses::cpu2.data 673 # number of demand (read+write) misses
1722system.cpu2.dcache.demand_misses::total 673 # number of demand (read+write) misses
1723system.cpu2.dcache.overall_misses::cpu2.data 673 # number of overall misses
1724system.cpu2.dcache.overall_misses::total 673 # number of overall misses
1725system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 4007500 # number of ReadReq miss cycles
1726system.cpu2.dcache.ReadReq_miss_latency::total 4007500 # number of ReadReq miss cycles
1727system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3035500 # number of WriteReq miss cycles
1728system.cpu2.dcache.WriteReq_miss_latency::total 3035500 # number of WriteReq miss cycles
1729system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 419500 # number of SwapReq miss cycles
1730system.cpu2.dcache.SwapReq_miss_latency::total 419500 # number of SwapReq miss cycles
1731system.cpu2.dcache.demand_miss_latency::cpu2.data 7043000 # number of demand (read+write) miss cycles
1732system.cpu2.dcache.demand_miss_latency::total 7043000 # number of demand (read+write) miss cycles
1733system.cpu2.dcache.overall_miss_latency::cpu2.data 7043000 # number of overall miss cycles
1734system.cpu2.dcache.overall_miss_latency::total 7043000 # number of overall miss cycles
1735system.cpu2.dcache.ReadReq_accesses::cpu2.data 53769 # number of ReadReq accesses(hits+misses)
1736system.cpu2.dcache.ReadReq_accesses::total 53769 # number of ReadReq accesses(hits+misses)
1737system.cpu2.dcache.WriteReq_accesses::cpu2.data 42162 # number of WriteReq accesses(hits+misses)
1738system.cpu2.dcache.WriteReq_accesses::total 42162 # number of WriteReq accesses(hits+misses)
1739system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses)
1740system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
1741system.cpu2.dcache.demand_accesses::cpu2.data 95931 # number of demand (read+write) accesses
1742system.cpu2.dcache.demand_accesses::total 95931 # number of demand (read+write) accesses
1743system.cpu2.dcache.overall_accesses::cpu2.data 95931 # number of overall (read+write) accesses
1744system.cpu2.dcache.overall_accesses::total 95931 # number of overall (read+write) accesses
1745system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009838 # miss rate for ReadReq accesses
1746system.cpu2.dcache.ReadReq_miss_rate::total 0.009838 # miss rate for ReadReq accesses
1747system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003415 # miss rate for WriteReq accesses
1748system.cpu2.dcache.WriteReq_miss_rate::total 0.003415 # miss rate for WriteReq accesses
1749system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.855263 # miss rate for SwapReq accesses
1750system.cpu2.dcache.SwapReq_miss_rate::total 0.855263 # miss rate for SwapReq accesses
1751system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007015 # miss rate for demand accesses
1752system.cpu2.dcache.demand_miss_rate::total 0.007015 # miss rate for demand accesses
1753system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007015 # miss rate for overall accesses
1754system.cpu2.dcache.overall_miss_rate::total 0.007015 # miss rate for overall accesses
1755system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7575.614367 # average ReadReq miss latency
1756system.cpu2.dcache.ReadReq_avg_miss_latency::total 7575.614367 # average ReadReq miss latency
1757system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21079.861111 # average WriteReq miss latency
1758system.cpu2.dcache.WriteReq_avg_miss_latency::total 21079.861111 # average WriteReq miss latency
1759system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6453.846154 # average SwapReq miss latency
1760system.cpu2.dcache.SwapReq_avg_miss_latency::total 6453.846154 # average SwapReq miss latency
1761system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency
1762system.cpu2.dcache.demand_avg_miss_latency::total 10465.081724 # average overall miss latency
1763system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency
1764system.cpu2.dcache.overall_avg_miss_latency::total 10465.081724 # average overall miss latency
1765system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1766system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1767system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1768system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1769system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1770system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1771system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 358 # number of ReadReq MSHR hits
1772system.cpu2.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
1773system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits
1774system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits
1775system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 1 # number of SwapReq MSHR hits
1776system.cpu2.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits
1777system.cpu2.dcache.demand_mshr_hits::cpu2.data 399 # number of demand (read+write) MSHR hits
1778system.cpu2.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits
1779system.cpu2.dcache.overall_mshr_hits::cpu2.data 399 # number of overall MSHR hits
1780system.cpu2.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits
1781system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses
1782system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses
1783system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses
1784system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
1785system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 64 # number of SwapReq MSHR misses
1786system.cpu2.dcache.SwapReq_mshr_misses::total 64 # number of SwapReq MSHR misses
1787system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses
1788system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
1789system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses
1790system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses
1791system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1122000 # number of ReadReq MSHR miss cycles
1792system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1122000 # number of ReadReq MSHR miss cycles
1793system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1473000 # number of WriteReq MSHR miss cycles
1794system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1473000 # number of WriteReq MSHR miss cycles
1795system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 354500 # number of SwapReq MSHR miss cycles
1796system.cpu2.dcache.SwapReq_mshr_miss_latency::total 354500 # number of SwapReq MSHR miss cycles
1797system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2595000 # number of demand (read+write) MSHR miss cycles
1798system.cpu2.dcache.demand_mshr_miss_latency::total 2595000 # number of demand (read+write) MSHR miss cycles
1799system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2595000 # number of overall MSHR miss cycles
1800system.cpu2.dcache.overall_mshr_miss_latency::total 2595000 # number of overall MSHR miss cycles
1801system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003180 # mshr miss rate for ReadReq accesses
1802system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003180 # mshr miss rate for ReadReq accesses
1803system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002443 # mshr miss rate for WriteReq accesses
1804system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002443 # mshr miss rate for WriteReq accesses
1805system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.842105 # mshr miss rate for SwapReq accesses
1806system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.842105 # mshr miss rate for SwapReq accesses
1807system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002856 # mshr miss rate for demand accesses
1808system.cpu2.dcache.demand_mshr_miss_rate::total 0.002856 # mshr miss rate for demand accesses
1809system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002856 # mshr miss rate for overall accesses
1810system.cpu2.dcache.overall_mshr_miss_rate::total 0.002856 # mshr miss rate for overall accesses
1811system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6561.403509 # average ReadReq mshr miss latency
1812system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6561.403509 # average ReadReq mshr miss latency
1813system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14300.970874 # average WriteReq mshr miss latency
1814system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14300.970874 # average WriteReq mshr miss latency
1815system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5539.062500 # average SwapReq mshr miss latency
1816system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5539.062500 # average SwapReq mshr miss latency
1817system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency
1818system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency
1819system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency
1820system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency
1821system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1822system.cpu2.icache.tags.replacements 575 # number of replacements
1823system.cpu2.icache.tags.tagsinuse 93.413944 # Cycle average of tags in use
1824system.cpu2.icache.tags.total_refs 24822 # Total number of references to valid blocks.
1825system.cpu2.icache.tags.sampled_refs 707 # Sample count of references to valid blocks.
1826system.cpu2.icache.tags.avg_refs 35.108911 # Average number of references to valid blocks.
1827system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1828system.cpu2.icache.tags.occ_blocks::cpu2.inst 93.413944 # Average occupied blocks per requestor
1829system.cpu2.icache.tags.occ_percent::cpu2.inst 0.182449 # Average percentage of cache occupancy
1830system.cpu2.icache.tags.occ_percent::total 0.182449 # Average percentage of cache occupancy
1831system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id
1832system.cpu2.icache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
1833system.cpu2.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
1834system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id
1835system.cpu2.icache.tags.tag_accesses 26357 # Number of tag accesses
1836system.cpu2.icache.tags.data_accesses 26357 # Number of data accesses
1837system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
1838system.cpu2.icache.ReadReq_hits::cpu2.inst 24822 # number of ReadReq hits
1839system.cpu2.icache.ReadReq_hits::total 24822 # number of ReadReq hits
1840system.cpu2.icache.demand_hits::cpu2.inst 24822 # number of demand (read+write) hits
1841system.cpu2.icache.demand_hits::total 24822 # number of demand (read+write) hits
1842system.cpu2.icache.overall_hits::cpu2.inst 24822 # number of overall hits
1843system.cpu2.icache.overall_hits::total 24822 # number of overall hits
1844system.cpu2.icache.ReadReq_misses::cpu2.inst 828 # number of ReadReq misses
1845system.cpu2.icache.ReadReq_misses::total 828 # number of ReadReq misses
1846system.cpu2.icache.demand_misses::cpu2.inst 828 # number of demand (read+write) misses
1847system.cpu2.icache.demand_misses::total 828 # number of demand (read+write) misses
1848system.cpu2.icache.overall_misses::cpu2.inst 828 # number of overall misses
1849system.cpu2.icache.overall_misses::total 828 # number of overall misses
1850system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12872000 # number of ReadReq miss cycles
1851system.cpu2.icache.ReadReq_miss_latency::total 12872000 # number of ReadReq miss cycles
1852system.cpu2.icache.demand_miss_latency::cpu2.inst 12872000 # number of demand (read+write) miss cycles
1853system.cpu2.icache.demand_miss_latency::total 12872000 # number of demand (read+write) miss cycles
1854system.cpu2.icache.overall_miss_latency::cpu2.inst 12872000 # number of overall miss cycles
1855system.cpu2.icache.overall_miss_latency::total 12872000 # number of overall miss cycles
1856system.cpu2.icache.ReadReq_accesses::cpu2.inst 25650 # number of ReadReq accesses(hits+misses)
1857system.cpu2.icache.ReadReq_accesses::total 25650 # number of ReadReq accesses(hits+misses)
1858system.cpu2.icache.demand_accesses::cpu2.inst 25650 # number of demand (read+write) accesses
1859system.cpu2.icache.demand_accesses::total 25650 # number of demand (read+write) accesses
1860system.cpu2.icache.overall_accesses::cpu2.inst 25650 # number of overall (read+write) accesses
1861system.cpu2.icache.overall_accesses::total 25650 # number of overall (read+write) accesses
1862system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.032281 # miss rate for ReadReq accesses
1863system.cpu2.icache.ReadReq_miss_rate::total 0.032281 # miss rate for ReadReq accesses
1864system.cpu2.icache.demand_miss_rate::cpu2.inst 0.032281 # miss rate for demand accesses
1865system.cpu2.icache.demand_miss_rate::total 0.032281 # miss rate for demand accesses
1866system.cpu2.icache.overall_miss_rate::cpu2.inst 0.032281 # miss rate for overall accesses
1867system.cpu2.icache.overall_miss_rate::total 0.032281 # miss rate for overall accesses
1868system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15545.893720 # average ReadReq miss latency
1869system.cpu2.icache.ReadReq_avg_miss_latency::total 15545.893720 # average ReadReq miss latency
1870system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency
1871system.cpu2.icache.demand_avg_miss_latency::total 15545.893720 # average overall miss latency
1872system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency
1873system.cpu2.icache.overall_avg_miss_latency::total 15545.893720 # average overall miss latency
1874system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked
1875system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1876system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked
1877system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1878system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked
1879system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1880system.cpu2.icache.writebacks::writebacks 575 # number of writebacks
1881system.cpu2.icache.writebacks::total 575 # number of writebacks
1882system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 121 # number of ReadReq MSHR hits
1883system.cpu2.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits
1884system.cpu2.icache.demand_mshr_hits::cpu2.inst 121 # number of demand (read+write) MSHR hits
1885system.cpu2.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits
1886system.cpu2.icache.overall_mshr_hits::cpu2.inst 121 # number of overall MSHR hits
1887system.cpu2.icache.overall_mshr_hits::total 121 # number of overall MSHR hits
1888system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 707 # number of ReadReq MSHR misses
1889system.cpu2.icache.ReadReq_mshr_misses::total 707 # number of ReadReq MSHR misses
1890system.cpu2.icache.demand_mshr_misses::cpu2.inst 707 # number of demand (read+write) MSHR misses
1891system.cpu2.icache.demand_mshr_misses::total 707 # number of demand (read+write) MSHR misses
1892system.cpu2.icache.overall_mshr_misses::cpu2.inst 707 # number of overall MSHR misses
1893system.cpu2.icache.overall_mshr_misses::total 707 # number of overall MSHR misses
1894system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 11018000 # number of ReadReq MSHR miss cycles
1895system.cpu2.icache.ReadReq_mshr_miss_latency::total 11018000 # number of ReadReq MSHR miss cycles
1896system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 11018000 # number of demand (read+write) MSHR miss cycles
1897system.cpu2.icache.demand_mshr_miss_latency::total 11018000 # number of demand (read+write) MSHR miss cycles
1898system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 11018000 # number of overall MSHR miss cycles
1899system.cpu2.icache.overall_mshr_miss_latency::total 11018000 # number of overall MSHR miss cycles
1900system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for ReadReq accesses
1901system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.027563 # mshr miss rate for ReadReq accesses
1902system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for demand accesses
1903system.cpu2.icache.demand_mshr_miss_rate::total 0.027563 # mshr miss rate for demand accesses
1904system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for overall accesses
1905system.cpu2.icache.overall_mshr_miss_rate::total 0.027563 # mshr miss rate for overall accesses
1906system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average ReadReq mshr miss latency
1907system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15584.158416 # average ReadReq mshr miss latency
1908system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency
1909system.cpu2.icache.demand_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency
1910system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency
1911system.cpu2.icache.overall_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency
1912system.cpu3.branchPred.lookups 62938 # Number of BP lookups
1913system.cpu3.branchPred.condPredicted 55062 # Number of conditional branches predicted
1914system.cpu3.branchPred.condIncorrect 2421 # Number of conditional branches incorrect
1915system.cpu3.branchPred.BTBLookups 53856 # Number of BTB lookups
1916system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
1917system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1918system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
1919system.cpu3.branchPred.usedRAS 2064 # Number of times the RAS was used to get a target.
1920system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
1921system.cpu3.branchPred.indirectLookups 53856 # Number of indirect predictor lookups.
1922system.cpu3.branchPred.indirectHits 44056 # Number of indirect target hits.
1923system.cpu3.branchPred.indirectMisses 9800 # Number of indirect misses.
1924system.cpu3.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches.
1925system.cpu3.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states
1926system.cpu3.numCycles 188742 # number of cpu cycles simulated
1927system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1928system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1929system.cpu3.fetch.icacheStallCycles 40214 # Number of cycles fetch is stalled on an Icache miss
1930system.cpu3.fetch.Insts 338441 # Number of instructions fetch has processed
1931system.cpu3.fetch.Branches 62938 # Number of branches that fetch encountered
1932system.cpu3.fetch.predictedBranches 46120 # Number of branches that fetch has predicted taken
1933system.cpu3.fetch.Cycles 142180 # Number of cycles fetch has run and was not squashing or blocked
1934system.cpu3.fetch.SquashCycles 4995 # Number of cycles fetch has spent squashing
1935system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1936system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
1937system.cpu3.fetch.PendingTrapStallCycles 1755 # Number of stall cycles due to pending traps
1938system.cpu3.fetch.CacheLines 28914 # Number of cache lines fetched
1939system.cpu3.fetch.IcacheSquashes 967 # Number of outstanding Icache misses that were squashed
1940system.cpu3.fetch.rateDist::samples 186659 # Number of instructions fetched each cycle (Total)
1941system.cpu3.fetch.rateDist::mean 1.813151 # Number of instructions fetched each cycle (Total)
1942system.cpu3.fetch.rateDist::stdev 2.333247 # Number of instructions fetched each cycle (Total)
1943system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1944system.cpu3.fetch.rateDist::0 73605 39.43% 39.43% # Number of instructions fetched each cycle (Total)
1945system.cpu3.fetch.rateDist::1 55869 29.93% 69.36% # Number of instructions fetched each cycle (Total)
1946system.cpu3.fetch.rateDist::2 8647 4.63% 74.00% # Number of instructions fetched each cycle (Total)
1947system.cpu3.fetch.rateDist::3 3452 1.85% 75.85% # Number of instructions fetched each cycle (Total)
1948system.cpu3.fetch.rateDist::4 624 0.33% 76.18% # Number of instructions fetched each cycle (Total)
1949system.cpu3.fetch.rateDist::5 33274 17.83% 94.01% # Number of instructions fetched each cycle (Total)
1950system.cpu3.fetch.rateDist::6 1074 0.58% 94.58% # Number of instructions fetched each cycle (Total)
1951system.cpu3.fetch.rateDist::7 1300 0.70% 95.28% # Number of instructions fetched each cycle (Total)
1952system.cpu3.fetch.rateDist::8 8814 4.72% 100.00% # Number of instructions fetched each cycle (Total)
1953system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1954system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1955system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1956system.cpu3.fetch.rateDist::total 186659 # Number of instructions fetched each cycle (Total)
1957system.cpu3.fetch.branchRate 0.333460 # Number of branch fetches per cycle
1958system.cpu3.fetch.rate 1.793141 # Number of inst fetches per cycle
1959system.cpu3.decode.IdleCycles 22716 # Number of cycles decode is idle
1960system.cpu3.decode.BlockedCycles 73421 # Number of cycles decode is blocked
1961system.cpu3.decode.RunCycles 83265 # Number of cycles decode is running
1962system.cpu3.decode.UnblockCycles 4750 # Number of cycles decode is unblocking
1963system.cpu3.decode.SquashCycles 2497 # Number of cycles decode is squashing
1964system.cpu3.decode.DecodedInsts 307410 # Number of instructions handled by decode
1965system.cpu3.rename.SquashCycles 2497 # Number of cycles rename is squashing
1966system.cpu3.rename.IdleCycles 23704 # Number of cycles rename is idle
1967system.cpu3.rename.BlockCycles 36346 # Number of cycles rename is blocking
1968system.cpu3.rename.serializeStallCycles 12933 # count of cycles rename stalled for serializing inst
1969system.cpu3.rename.RunCycles 84283 # Number of cycles rename is running
1970system.cpu3.rename.UnblockCycles 26886 # Number of cycles rename is unblocking
1971system.cpu3.rename.RenamedInsts 301080 # Number of instructions processed by rename
1972system.cpu3.rename.IQFullEvents 23387 # Number of times rename has blocked due to IQ full
1973system.cpu3.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
1974system.cpu3.rename.RenamedOperands 210366 # Number of destination operands rename has renamed
1975system.cpu3.rename.RenameLookups 567874 # Number of register rename lookups that rename has made
1976system.cpu3.rename.int_rename_lookups 443450 # Number of integer rename lookups
1977system.cpu3.rename.fp_rename_lookups 24 # Number of floating rename lookups
1978system.cpu3.rename.CommittedMaps 181055 # Number of HB maps that are committed
1979system.cpu3.rename.UndoneMaps 29311 # Number of HB maps that are undone due to squashing
1980system.cpu3.rename.serializingInsts 1630 # count of serializing insts renamed
1981system.cpu3.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed
1982system.cpu3.rename.skidInsts 32120 # count of insts added to the skid buffer
1983system.cpu3.memDep0.insertedLoads 81178 # Number of loads inserted to the mem dependence unit.
1984system.cpu3.memDep0.insertedStores 37704 # Number of stores inserted to the mem dependence unit.
1985system.cpu3.memDep0.conflictingLoads 38749 # Number of conflicting loads.
1986system.cpu3.memDep0.conflictingStores 31258 # Number of conflicting stores.
1987system.cpu3.iq.iqInstsAdded 243640 # Number of instructions added to the IQ (excludes non-spec)
1988system.cpu3.iq.iqNonSpecInstsAdded 9008 # Number of non-speculative instructions added to the IQ
1989system.cpu3.iq.iqInstsIssued 244569 # Number of instructions issued
1990system.cpu3.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued
1991system.cpu3.iq.iqSquashedInstsExamined 25003 # Number of squashed instructions iterated over during squash; mainly for profiling
1992system.cpu3.iq.iqSquashedOperandsExamined 20491 # Number of squashed operands that are examined and possibly removed from graph
1993system.cpu3.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed
1994system.cpu3.iq.issued_per_cycle::samples 186659 # Number of insts issued each cycle
1995system.cpu3.iq.issued_per_cycle::mean 1.310245 # Number of insts issued each cycle
1996system.cpu3.iq.issued_per_cycle::stdev 1.388449 # Number of insts issued each cycle
1997system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1998system.cpu3.iq.issued_per_cycle::0 78461 42.03% 42.03% # Number of insts issued each cycle
1999system.cpu3.iq.issued_per_cycle::1 28833 15.45% 57.48% # Number of insts issued each cycle
2000system.cpu3.iq.issued_per_cycle::2 36126 19.35% 76.84% # Number of insts issued each cycle
2001system.cpu3.iq.issued_per_cycle::3 35957 19.26% 96.10% # Number of insts issued each cycle
2002system.cpu3.iq.issued_per_cycle::4 3664 1.96% 98.06% # Number of insts issued each cycle
2003system.cpu3.iq.issued_per_cycle::5 1804 0.97% 99.03% # Number of insts issued each cycle
2004system.cpu3.iq.issued_per_cycle::6 1069 0.57% 99.60% # Number of insts issued each cycle
2005system.cpu3.iq.issued_per_cycle::7 437 0.23% 99.83% # Number of insts issued each cycle
2006system.cpu3.iq.issued_per_cycle::8 308 0.17% 100.00% # Number of insts issued each cycle
2007system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2008system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2009system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2010system.cpu3.iq.issued_per_cycle::total 186659 # Number of insts issued each cycle
2011system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2012system.cpu3.iq.fu_full::IntAlu 212 43.80% 43.80% # attempts to use FU when none available
2013system.cpu3.iq.fu_full::IntMult 0 0.00% 43.80% # attempts to use FU when none available
2014system.cpu3.iq.fu_full::IntDiv 0 0.00% 43.80% # attempts to use FU when none available
2015system.cpu3.iq.fu_full::FloatAdd 0 0.00% 43.80% # attempts to use FU when none available
2016system.cpu3.iq.fu_full::FloatCmp 0 0.00% 43.80% # attempts to use FU when none available
2017system.cpu3.iq.fu_full::FloatCvt 0 0.00% 43.80% # attempts to use FU when none available
2018system.cpu3.iq.fu_full::FloatMult 0 0.00% 43.80% # attempts to use FU when none available
2019system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available
2020system.cpu3.iq.fu_full::FloatDiv 0 0.00% 43.80% # attempts to use FU when none available
2021system.cpu3.iq.fu_full::FloatMisc 0 0.00% 43.80% # attempts to use FU when none available
2022system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 43.80% # attempts to use FU when none available
2023system.cpu3.iq.fu_full::SimdAdd 0 0.00% 43.80% # attempts to use FU when none available
2024system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 43.80% # attempts to use FU when none available
2025system.cpu3.iq.fu_full::SimdAlu 0 0.00% 43.80% # attempts to use FU when none available
2026system.cpu3.iq.fu_full::SimdCmp 0 0.00% 43.80% # attempts to use FU when none available
2027system.cpu3.iq.fu_full::SimdCvt 0 0.00% 43.80% # attempts to use FU when none available
2028system.cpu3.iq.fu_full::SimdMisc 0 0.00% 43.80% # attempts to use FU when none available
2029system.cpu3.iq.fu_full::SimdMult 0 0.00% 43.80% # attempts to use FU when none available
2030system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 43.80% # attempts to use FU when none available
2031system.cpu3.iq.fu_full::SimdShift 0 0.00% 43.80% # attempts to use FU when none available
2032system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 43.80% # attempts to use FU when none available
2033system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 43.80% # attempts to use FU when none available
2034system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 43.80% # attempts to use FU when none available
2035system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 43.80% # attempts to use FU when none available
2036system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 43.80% # attempts to use FU when none available
2037system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 43.80% # attempts to use FU when none available
2038system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 43.80% # attempts to use FU when none available
2039system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 43.80% # attempts to use FU when none available
2040system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 43.80% # attempts to use FU when none available
2041system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available
2042system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 43.80% # attempts to use FU when none available
2043system.cpu3.iq.fu_full::MemRead 41 8.47% 52.27% # attempts to use FU when none available
2044system.cpu3.iq.fu_full::MemWrite 231 47.73% 100.00% # attempts to use FU when none available
2045system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
2046system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
2047system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2048system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2049system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2050system.cpu3.iq.FU_type_0::IntAlu 120712 49.36% 49.36% # Type of FU issued
2051system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.36% # Type of FU issued
2052system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.36% # Type of FU issued
2053system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.36% # Type of FU issued
2054system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.36% # Type of FU issued
2055system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.36% # Type of FU issued
2056system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.36% # Type of FU issued
2057system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 49.36% # Type of FU issued
2058system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.36% # Type of FU issued
2059system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 49.36% # Type of FU issued
2060system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.36% # Type of FU issued
2061system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.36% # Type of FU issued
2062system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.36% # Type of FU issued
2063system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.36% # Type of FU issued
2064system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.36% # Type of FU issued
2065system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.36% # Type of FU issued
2066system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.36% # Type of FU issued
2067system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.36% # Type of FU issued
2068system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.36% # Type of FU issued
2069system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.36% # Type of FU issued
2070system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.36% # Type of FU issued
2071system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.36% # Type of FU issued
2072system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.36% # Type of FU issued
2073system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.36% # Type of FU issued
2074system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.36% # Type of FU issued
2075system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.36% # Type of FU issued
2076system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.36% # Type of FU issued
2077system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.36% # Type of FU issued
2078system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.36% # Type of FU issued
2079system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.36% # Type of FU issued
2080system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.36% # Type of FU issued
2081system.cpu3.iq.FU_type_0::MemRead 87244 35.67% 85.03% # Type of FU issued
2082system.cpu3.iq.FU_type_0::MemWrite 36613 14.97% 100.00% # Type of FU issued
2083system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
2084system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
2085system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2086system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2087system.cpu3.iq.FU_type_0::total 244569 # Type of FU issued
2088system.cpu3.iq.rate 1.295785 # Inst issue rate
2089system.cpu3.iq.fu_busy_cnt 484 # FU busy when requested
2090system.cpu3.iq.fu_busy_rate 0.001979 # FU busy rate (busy events/executed inst)
2091system.cpu3.iq.int_inst_queue_reads 676366 # Number of integer instruction queue reads
2092system.cpu3.iq.int_inst_queue_writes 277636 # Number of integer instruction queue writes
2093system.cpu3.iq.int_inst_queue_wakeup_accesses 240444 # Number of integer instruction queue wakeup accesses
2094system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
2095system.cpu3.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
2096system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
2097system.cpu3.iq.int_alu_accesses 245053 # Number of integer alu accesses
2098system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2099system.cpu3.iew.lsq.thread0.forwLoads 31180 # Number of loads that had data forwarded from stores
2100system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2101system.cpu3.iew.lsq.thread0.squashedLoads 4645 # Number of loads squashed
2102system.cpu3.iew.lsq.thread0.ignoredResponses 43 # Number of memory responses ignored because the instruction is squashed
2103system.cpu3.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations
2104system.cpu3.iew.lsq.thread0.squashedStores 2744 # Number of stores squashed
2105system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2106system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2107system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2108system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2109system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2110system.cpu3.iew.iewSquashCycles 2497 # Number of cycles IEW is squashing
2111system.cpu3.iew.iewBlockCycles 9575 # Number of cycles IEW is blocking
2112system.cpu3.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking
2113system.cpu3.iew.iewDispatchedInsts 292625 # Number of instructions dispatched to IQ
2114system.cpu3.iew.iewDispSquashedInsts 421 # Number of squashed instructions skipped by dispatch
2115system.cpu3.iew.iewDispLoadInsts 81178 # Number of dispatched load instructions
2116system.cpu3.iew.iewDispStoreInsts 37704 # Number of dispatched store instructions
2117system.cpu3.iew.iewDispNonSpecInsts 1504 # Number of dispatched non-speculative instructions
2118system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall
2119system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
2120system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations
2121system.cpu3.iew.predictedTakenIncorrect 434 # Number of branches that were predicted taken incorrectly
2122system.cpu3.iew.predictedNotTakenIncorrect 2602 # Number of branches that were predicted not taken incorrectly
2123system.cpu3.iew.branchMispredicts 3036 # Number of branch mispredicts detected at execute
2124system.cpu3.iew.iewExecutedInsts 241934 # Number of executed instructions
2125system.cpu3.iew.iewExecLoadInsts 79457 # Number of load instructions executed
2126system.cpu3.iew.iewExecSquashedInsts 2635 # Number of squashed instructions skipped in execute
2127system.cpu3.iew.exec_swp 0 # number of swp insts executed
2128system.cpu3.iew.exec_nop 39977 # number of nop insts executed
2129system.cpu3.iew.exec_refs 115781 # number of memory reference insts executed
2130system.cpu3.iew.exec_branches 50244 # Number of branches executed
2131system.cpu3.iew.exec_stores 36324 # Number of stores executed
2132system.cpu3.iew.exec_rate 1.281824 # Inst execution rate
2133system.cpu3.iew.wb_sent 241008 # cumulative count of insts sent to commit
2134system.cpu3.iew.wb_count 240444 # cumulative count of insts written-back
2135system.cpu3.iew.wb_producers 133441 # num instructions producing a value
2136system.cpu3.iew.wb_consumers 140864 # num instructions consuming a value
2137system.cpu3.iew.wb_rate 1.273929 # insts written-back per cycle
2138system.cpu3.iew.wb_fanout 0.947304 # average fanout of values written-back
2139system.cpu3.commit.commitSquashedInsts 26116 # The number of squashed insts skipped by commit
2140system.cpu3.commit.commitNonSpecStalls 7835 # The number of times commit has been forced to stall to communicate backwards
2141system.cpu3.commit.branchMispredicts 2421 # The number of times a branch was mispredicted
2142system.cpu3.commit.committed_per_cycle::samples 181669 # Number of insts commited each cycle
2143system.cpu3.commit.committed_per_cycle::mean 1.466860 # Number of insts commited each cycle
2144system.cpu3.commit.committed_per_cycle::stdev 1.985223 # Number of insts commited each cycle
2145system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2146system.cpu3.commit.committed_per_cycle::0 85663 47.15% 47.15% # Number of insts commited each cycle
2147system.cpu3.commit.committed_per_cycle::1 46447 25.57% 72.72% # Number of insts commited each cycle
2148system.cpu3.commit.committed_per_cycle::2 5344 2.94% 75.66% # Number of insts commited each cycle
2149system.cpu3.commit.committed_per_cycle::3 8472 4.66% 80.33% # Number of insts commited each cycle
2150system.cpu3.commit.committed_per_cycle::4 1289 0.71% 81.03% # Number of insts commited each cycle
2151system.cpu3.commit.committed_per_cycle::5 31374 17.27% 98.30% # Number of insts commited each cycle
2152system.cpu3.commit.committed_per_cycle::6 856 0.47% 98.78% # Number of insts commited each cycle
2153system.cpu3.commit.committed_per_cycle::7 1022 0.56% 99.34% # Number of insts commited each cycle
2154system.cpu3.commit.committed_per_cycle::8 1202 0.66% 100.00% # Number of insts commited each cycle
2155system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2156system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2157system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2158system.cpu3.commit.committed_per_cycle::total 181669 # Number of insts commited each cycle
2159system.cpu3.commit.committedInsts 266483 # Number of instructions committed
2160system.cpu3.commit.committedOps 266483 # Number of ops (including micro ops) committed
2161system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2162system.cpu3.commit.refs 111493 # Number of memory references committed
2163system.cpu3.commit.loads 76533 # Number of loads committed
2164system.cpu3.commit.membars 7123 # Number of memory barriers committed
2165system.cpu3.commit.branches 48046 # Number of branches committed
2166system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
2167system.cpu3.commit.int_insts 181662 # Number of committed integer instructions.
2168system.cpu3.commit.function_calls 322 # Number of function calls committed.
2169system.cpu3.commit.op_class_0::No_OpClass 38838 14.57% 14.57% # Class of committed instruction
2170system.cpu3.commit.op_class_0::IntAlu 109029 40.91% 55.49% # Class of committed instruction
2171system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.49% # Class of committed instruction
2172system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.49% # Class of committed instruction
2173system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.49% # Class of committed instruction
2174system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.49% # Class of committed instruction
2175system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.49% # Class of committed instruction
2176system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.49% # Class of committed instruction
2177system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.49% # Class of committed instruction
2178system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.49% # Class of committed instruction
2179system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.49% # Class of committed instruction
2180system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.49% # Class of committed instruction
2181system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.49% # Class of committed instruction
2182system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.49% # Class of committed instruction
2183system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.49% # Class of committed instruction
2184system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.49% # Class of committed instruction
2185system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.49% # Class of committed instruction
2186system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.49% # Class of committed instruction
2187system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.49% # Class of committed instruction
2188system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.49% # Class of committed instruction
2189system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.49% # Class of committed instruction
2190system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.49% # Class of committed instruction
2191system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.49% # Class of committed instruction
2192system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.49% # Class of committed instruction
2193system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.49% # Class of committed instruction
2194system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.49% # Class of committed instruction
2195system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.49% # Class of committed instruction
2196system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.49% # Class of committed instruction
2197system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.49% # Class of committed instruction
2198system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.49% # Class of committed instruction
2199system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.49% # Class of committed instruction
2200system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.49% # Class of committed instruction
2201system.cpu3.commit.op_class_0::MemRead 83656 31.39% 86.88% # Class of committed instruction
2202system.cpu3.commit.op_class_0::MemWrite 34960 13.12% 100.00% # Class of committed instruction
2203system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
2204system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
2205system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2206system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2207system.cpu3.commit.op_class_0::total 266483 # Class of committed instruction
2208system.cpu3.commit.bw_lim_events 1202 # number cycles where commit BW limit reached
2209system.cpu3.rob.rob_reads 472480 # The number of ROB reads
2210system.cpu3.rob.rob_writes 590253 # The number of ROB writes
2211system.cpu3.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
2212system.cpu3.idleCycles 2083 # Total number of cycles that the CPU has spent unscheduled due to idling
2213system.cpu3.quiesceCycles 50253 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2214system.cpu3.committedInsts 220522 # Number of Instructions Simulated
2215system.cpu3.committedOps 220522 # Number of Ops (including micro ops) Simulated
2216system.cpu3.cpi 0.855887 # CPI: Cycles Per Instruction
2217system.cpu3.cpi_total 0.855887 # CPI: Total CPI of All Threads
2218system.cpu3.ipc 1.168378 # IPC: Instructions Per Cycle
2219system.cpu3.ipc_total 1.168378 # IPC: Total IPC of All Threads
2220system.cpu3.int_regfile_reads 411294 # number of integer regfile reads
2221system.cpu3.int_regfile_writes 192402 # number of integer regfile writes
2222system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
2223system.cpu3.misc_regfile_reads 117678 # number of misc regfile reads
2224system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
2225system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2226system.cpu3.dcache.tags.replacements 0 # number of replacements
2227system.cpu3.dcache.tags.tagsinuse 24.245200 # Cycle average of tags in use
2228system.cpu3.dcache.tags.total_refs 42083 # Total number of references to valid blocks.
2229system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
2230system.cpu3.dcache.tags.avg_refs 1451.137931 # Average number of references to valid blocks.
2231system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2232system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.245200 # Average occupied blocks per requestor
2233system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047354 # Average percentage of cache occupancy
2234system.cpu3.dcache.tags.occ_percent::total 0.047354 # Average percentage of cache occupancy
2235system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
2236system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
2237system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
2238system.cpu3.dcache.tags.tag_accesses 333051 # Number of tag accesses
2239system.cpu3.dcache.tags.data_accesses 333051 # Number of data accesses
2240system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2241system.cpu3.dcache.ReadReq_hits::cpu3.data 47761 # number of ReadReq hits
2242system.cpu3.dcache.ReadReq_hits::total 47761 # number of ReadReq hits
2243system.cpu3.dcache.WriteReq_hits::cpu3.data 34756 # number of WriteReq hits
2244system.cpu3.dcache.WriteReq_hits::total 34756 # number of WriteReq hits
2245system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
2246system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
2247system.cpu3.dcache.demand_hits::cpu3.data 82517 # number of demand (read+write) hits
2248system.cpu3.dcache.demand_hits::total 82517 # number of demand (read+write) hits
2249system.cpu3.dcache.overall_hits::cpu3.data 82517 # number of overall hits
2250system.cpu3.dcache.overall_hits::total 82517 # number of overall hits
2251system.cpu3.dcache.ReadReq_misses::cpu3.data 480 # number of ReadReq misses
2252system.cpu3.dcache.ReadReq_misses::total 480 # number of ReadReq misses
2253system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
2254system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
2255system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses
2256system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses
2257system.cpu3.dcache.demand_misses::cpu3.data 618 # number of demand (read+write) misses
2258system.cpu3.dcache.demand_misses::total 618 # number of demand (read+write) misses
2259system.cpu3.dcache.overall_misses::cpu3.data 618 # number of overall misses
2260system.cpu3.dcache.overall_misses::total 618 # number of overall misses
2261system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4264500 # number of ReadReq miss cycles
2262system.cpu3.dcache.ReadReq_miss_latency::total 4264500 # number of ReadReq miss cycles
2263system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3342000 # number of WriteReq miss cycles
2264system.cpu3.dcache.WriteReq_miss_latency::total 3342000 # number of WriteReq miss cycles
2265system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 357000 # number of SwapReq miss cycles
2266system.cpu3.dcache.SwapReq_miss_latency::total 357000 # number of SwapReq miss cycles
2267system.cpu3.dcache.demand_miss_latency::cpu3.data 7606500 # number of demand (read+write) miss cycles
2268system.cpu3.dcache.demand_miss_latency::total 7606500 # number of demand (read+write) miss cycles
2269system.cpu3.dcache.overall_miss_latency::cpu3.data 7606500 # number of overall miss cycles
2270system.cpu3.dcache.overall_miss_latency::total 7606500 # number of overall miss cycles
2271system.cpu3.dcache.ReadReq_accesses::cpu3.data 48241 # number of ReadReq accesses(hits+misses)
2272system.cpu3.dcache.ReadReq_accesses::total 48241 # number of ReadReq accesses(hits+misses)
2273system.cpu3.dcache.WriteReq_accesses::cpu3.data 34894 # number of WriteReq accesses(hits+misses)
2274system.cpu3.dcache.WriteReq_accesses::total 34894 # number of WriteReq accesses(hits+misses)
2275system.cpu3.dcache.SwapReq_accesses::cpu3.data 66 # number of SwapReq accesses(hits+misses)
2276system.cpu3.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
2277system.cpu3.dcache.demand_accesses::cpu3.data 83135 # number of demand (read+write) accesses
2278system.cpu3.dcache.demand_accesses::total 83135 # number of demand (read+write) accesses
2279system.cpu3.dcache.overall_accesses::cpu3.data 83135 # number of overall (read+write) accesses
2280system.cpu3.dcache.overall_accesses::total 83135 # number of overall (read+write) accesses
2281system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009950 # miss rate for ReadReq accesses
2282system.cpu3.dcache.ReadReq_miss_rate::total 0.009950 # miss rate for ReadReq accesses
2283system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003955 # miss rate for WriteReq accesses
2284system.cpu3.dcache.WriteReq_miss_rate::total 0.003955 # miss rate for WriteReq accesses
2285system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.803030 # miss rate for SwapReq accesses
2286system.cpu3.dcache.SwapReq_miss_rate::total 0.803030 # miss rate for SwapReq accesses
2287system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007434 # miss rate for demand accesses
2288system.cpu3.dcache.demand_miss_rate::total 0.007434 # miss rate for demand accesses
2289system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007434 # miss rate for overall accesses
2290system.cpu3.dcache.overall_miss_rate::total 0.007434 # miss rate for overall accesses
2291system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 8884.375000 # average ReadReq miss latency
2292system.cpu3.dcache.ReadReq_avg_miss_latency::total 8884.375000 # average ReadReq miss latency
2293system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 24217.391304 # average WriteReq miss latency
2294system.cpu3.dcache.WriteReq_avg_miss_latency::total 24217.391304 # average WriteReq miss latency
2295system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6735.849057 # average SwapReq miss latency
2296system.cpu3.dcache.SwapReq_avg_miss_latency::total 6735.849057 # average SwapReq miss latency
2297system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12308.252427 # average overall miss latency
2298system.cpu3.dcache.demand_avg_miss_latency::total 12308.252427 # average overall miss latency
2299system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12308.252427 # average overall miss latency
2300system.cpu3.dcache.overall_avg_miss_latency::total 12308.252427 # average overall miss latency
2301system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2302system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2303system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2304system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2305system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2306system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2307system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 324 # number of ReadReq MSHR hits
2308system.cpu3.dcache.ReadReq_mshr_hits::total 324 # number of ReadReq MSHR hits
2309system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits
2310system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
2311system.cpu3.dcache.demand_mshr_hits::cpu3.data 355 # number of demand (read+write) MSHR hits
2312system.cpu3.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
2313system.cpu3.dcache.overall_mshr_hits::cpu3.data 355 # number of overall MSHR hits
2314system.cpu3.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
2315system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 156 # number of ReadReq MSHR misses
2316system.cpu3.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses
2317system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
2318system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
2319system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses
2320system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
2321system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses
2322system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
2323system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses
2324system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
2325system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1092500 # number of ReadReq MSHR miss cycles
2326system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1092500 # number of ReadReq MSHR miss cycles
2327system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1676500 # number of WriteReq MSHR miss cycles
2328system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1676500 # number of WriteReq MSHR miss cycles
2329system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 304000 # number of SwapReq MSHR miss cycles
2330system.cpu3.dcache.SwapReq_mshr_miss_latency::total 304000 # number of SwapReq MSHR miss cycles
2331system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2769000 # number of demand (read+write) MSHR miss cycles
2332system.cpu3.dcache.demand_mshr_miss_latency::total 2769000 # number of demand (read+write) MSHR miss cycles
2333system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2769000 # number of overall MSHR miss cycles
2334system.cpu3.dcache.overall_mshr_miss_latency::total 2769000 # number of overall MSHR miss cycles
2335system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003234 # mshr miss rate for ReadReq accesses
2336system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003234 # mshr miss rate for ReadReq accesses
2337system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003066 # mshr miss rate for WriteReq accesses
2338system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003066 # mshr miss rate for WriteReq accesses
2339system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.803030 # mshr miss rate for SwapReq accesses
2340system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.803030 # mshr miss rate for SwapReq accesses
2341system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for demand accesses
2342system.cpu3.dcache.demand_mshr_miss_rate::total 0.003164 # mshr miss rate for demand accesses
2343system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for overall accesses
2344system.cpu3.dcache.overall_mshr_miss_rate::total 0.003164 # mshr miss rate for overall accesses
2345system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7003.205128 # average ReadReq mshr miss latency
2346system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7003.205128 # average ReadReq mshr miss latency
2347system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15668.224299 # average WriteReq mshr miss latency
2348system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15668.224299 # average WriteReq mshr miss latency
2349system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5735.849057 # average SwapReq mshr miss latency
2350system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5735.849057 # average SwapReq mshr miss latency
2351system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency
2352system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency
2353system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency
2354system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency
2355system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2356system.cpu3.icache.tags.replacements 578 # number of replacements
2357system.cpu3.icache.tags.tagsinuse 92.244162 # Cycle average of tags in use
2358system.cpu3.icache.tags.total_refs 28072 # Total number of references to valid blocks.
2359system.cpu3.icache.tags.sampled_refs 714 # Sample count of references to valid blocks.
2360system.cpu3.icache.tags.avg_refs 39.316527 # Average number of references to valid blocks.
2361system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2362system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.244162 # Average occupied blocks per requestor
2363system.cpu3.icache.tags.occ_percent::cpu3.inst 0.180164 # Average percentage of cache occupancy
2364system.cpu3.icache.tags.occ_percent::total 0.180164 # Average percentage of cache occupancy
2365system.cpu3.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id
2366system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
2367system.cpu3.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
2368system.cpu3.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id
2369system.cpu3.icache.tags.tag_accesses 29628 # Number of tag accesses
2370system.cpu3.icache.tags.data_accesses 29628 # Number of data accesses
2371system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2372system.cpu3.icache.ReadReq_hits::cpu3.inst 28072 # number of ReadReq hits
2373system.cpu3.icache.ReadReq_hits::total 28072 # number of ReadReq hits
2374system.cpu3.icache.demand_hits::cpu3.inst 28072 # number of demand (read+write) hits
2375system.cpu3.icache.demand_hits::total 28072 # number of demand (read+write) hits
2376system.cpu3.icache.overall_hits::cpu3.inst 28072 # number of overall hits
2377system.cpu3.icache.overall_hits::total 28072 # number of overall hits
2378system.cpu3.icache.ReadReq_misses::cpu3.inst 842 # number of ReadReq misses
2379system.cpu3.icache.ReadReq_misses::total 842 # number of ReadReq misses
2380system.cpu3.icache.demand_misses::cpu3.inst 842 # number of demand (read+write) misses
2381system.cpu3.icache.demand_misses::total 842 # number of demand (read+write) misses
2382system.cpu3.icache.overall_misses::cpu3.inst 842 # number of overall misses
2383system.cpu3.icache.overall_misses::total 842 # number of overall misses
2384system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 12413000 # number of ReadReq miss cycles
2385system.cpu3.icache.ReadReq_miss_latency::total 12413000 # number of ReadReq miss cycles
2386system.cpu3.icache.demand_miss_latency::cpu3.inst 12413000 # number of demand (read+write) miss cycles
2387system.cpu3.icache.demand_miss_latency::total 12413000 # number of demand (read+write) miss cycles
2388system.cpu3.icache.overall_miss_latency::cpu3.inst 12413000 # number of overall miss cycles
2389system.cpu3.icache.overall_miss_latency::total 12413000 # number of overall miss cycles
2390system.cpu3.icache.ReadReq_accesses::cpu3.inst 28914 # number of ReadReq accesses(hits+misses)
2391system.cpu3.icache.ReadReq_accesses::total 28914 # number of ReadReq accesses(hits+misses)
2392system.cpu3.icache.demand_accesses::cpu3.inst 28914 # number of demand (read+write) accesses
2393system.cpu3.icache.demand_accesses::total 28914 # number of demand (read+write) accesses
2394system.cpu3.icache.overall_accesses::cpu3.inst 28914 # number of overall (read+write) accesses
2395system.cpu3.icache.overall_accesses::total 28914 # number of overall (read+write) accesses
2396system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.029121 # miss rate for ReadReq accesses
2397system.cpu3.icache.ReadReq_miss_rate::total 0.029121 # miss rate for ReadReq accesses
2398system.cpu3.icache.demand_miss_rate::cpu3.inst 0.029121 # miss rate for demand accesses
2399system.cpu3.icache.demand_miss_rate::total 0.029121 # miss rate for demand accesses
2400system.cpu3.icache.overall_miss_rate::cpu3.inst 0.029121 # miss rate for overall accesses
2401system.cpu3.icache.overall_miss_rate::total 0.029121 # miss rate for overall accesses
2402system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14742.280285 # average ReadReq miss latency
2403system.cpu3.icache.ReadReq_avg_miss_latency::total 14742.280285 # average ReadReq miss latency
2404system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14742.280285 # average overall miss latency
2405system.cpu3.icache.demand_avg_miss_latency::total 14742.280285 # average overall miss latency
2406system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14742.280285 # average overall miss latency
2407system.cpu3.icache.overall_avg_miss_latency::total 14742.280285 # average overall miss latency
2408system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2409system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2410system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2411system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2412system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2413system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2414system.cpu3.icache.writebacks::writebacks 578 # number of writebacks
2415system.cpu3.icache.writebacks::total 578 # number of writebacks
2416system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits
2417system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits
2418system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits
2419system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits
2420system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits
2421system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits
2422system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 714 # number of ReadReq MSHR misses
2423system.cpu3.icache.ReadReq_mshr_misses::total 714 # number of ReadReq MSHR misses
2424system.cpu3.icache.demand_mshr_misses::cpu3.inst 714 # number of demand (read+write) MSHR misses
2425system.cpu3.icache.demand_mshr_misses::total 714 # number of demand (read+write) MSHR misses
2426system.cpu3.icache.overall_mshr_misses::cpu3.inst 714 # number of overall MSHR misses
2427system.cpu3.icache.overall_mshr_misses::total 714 # number of overall MSHR misses
2428system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10783500 # number of ReadReq MSHR miss cycles
2429system.cpu3.icache.ReadReq_mshr_miss_latency::total 10783500 # number of ReadReq MSHR miss cycles
2430system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10783500 # number of demand (read+write) MSHR miss cycles
2431system.cpu3.icache.demand_mshr_miss_latency::total 10783500 # number of demand (read+write) MSHR miss cycles
2432system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10783500 # number of overall MSHR miss cycles
2433system.cpu3.icache.overall_mshr_miss_latency::total 10783500 # number of overall MSHR miss cycles
2434system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.024694 # mshr miss rate for ReadReq accesses
2435system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.024694 # mshr miss rate for ReadReq accesses
2436system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.024694 # mshr miss rate for demand accesses
2437system.cpu3.icache.demand_mshr_miss_rate::total 0.024694 # mshr miss rate for demand accesses
2438system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.024694 # mshr miss rate for overall accesses
2439system.cpu3.icache.overall_mshr_miss_rate::total 0.024694 # mshr miss rate for overall accesses
2440system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15102.941176 # average ReadReq mshr miss latency
2441system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15102.941176 # average ReadReq mshr miss latency
2442system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15102.941176 # average overall mshr miss latency
2443system.cpu3.icache.demand_avg_mshr_miss_latency::total 15102.941176 # average overall mshr miss latency
2444system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15102.941176 # average overall mshr miss latency
2445system.cpu3.icache.overall_avg_mshr_miss_latency::total 15102.941176 # average overall mshr miss latency
2446system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2447system.l2c.tags.replacements 0 # number of replacements
2448system.l2c.tags.tagsinuse 560.431051 # Cycle average of tags in use
2449system.l2c.tags.total_refs 3109 # Total number of references to valid blocks.
2450system.l2c.tags.sampled_refs 707 # Sample count of references to valid blocks.
2451system.l2c.tags.avg_refs 4.397454 # Average number of references to valid blocks.
2452system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2453system.l2c.tags.occ_blocks::cpu0.inst 296.754574 # Average occupied blocks per requestor
2454system.l2c.tags.occ_blocks::cpu0.data 144.555076 # Average occupied blocks per requestor
2455system.l2c.tags.occ_blocks::cpu1.inst 69.060046 # Average occupied blocks per requestor
2456system.l2c.tags.occ_blocks::cpu1.data 16.007345 # Average occupied blocks per requestor
2457system.l2c.tags.occ_blocks::cpu2.inst 7.444463 # Average occupied blocks per requestor
2458system.l2c.tags.occ_blocks::cpu2.data 9.891084 # Average occupied blocks per requestor
2459system.l2c.tags.occ_blocks::cpu3.inst 6.988316 # Average occupied blocks per requestor
2460system.l2c.tags.occ_blocks::cpu3.data 9.730146 # Average occupied blocks per requestor
2461system.l2c.tags.occ_percent::cpu0.inst 0.004528 # Average percentage of cache occupancy
2462system.l2c.tags.occ_percent::cpu0.data 0.002206 # Average percentage of cache occupancy
2463system.l2c.tags.occ_percent::cpu1.inst 0.001054 # Average percentage of cache occupancy
2464system.l2c.tags.occ_percent::cpu1.data 0.000244 # Average percentage of cache occupancy
2465system.l2c.tags.occ_percent::cpu2.inst 0.000114 # Average percentage of cache occupancy
2466system.l2c.tags.occ_percent::cpu2.data 0.000151 # Average percentage of cache occupancy
2467system.l2c.tags.occ_percent::cpu3.inst 0.000107 # Average percentage of cache occupancy
2468system.l2c.tags.occ_percent::cpu3.data 0.000148 # Average percentage of cache occupancy
2469system.l2c.tags.occ_percent::total 0.008551 # Average percentage of cache occupancy
2470system.l2c.tags.occ_task_id_blocks::1024 707 # Occupied blocks per task id
2471system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
2472system.l2c.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
2473system.l2c.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
2474system.l2c.tags.occ_task_id_percent::1024 0.010788 # Percentage of cache occupancy per task id
2475system.l2c.tags.tag_accesses 31411 # Number of tag accesses
2476system.l2c.tags.data_accesses 31411 # Number of data accesses
2477system.l2c.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2478system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
2479system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
2480system.l2c.WritebackClean_hits::writebacks 752 # number of WritebackClean hits
2481system.l2c.WritebackClean_hits::total 752 # number of WritebackClean hits
2482system.l2c.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits
2483system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits
2484system.l2c.UpgradeReq_hits::cpu2.data 20 # number of UpgradeReq hits
2485system.l2c.UpgradeReq_hits::cpu3.data 22 # number of UpgradeReq hits
2486system.l2c.UpgradeReq_hits::total 87 # number of UpgradeReq hits
2487system.l2c.ReadCleanReq_hits::cpu0.inst 309 # number of ReadCleanReq hits
2488system.l2c.ReadCleanReq_hits::cpu1.inst 544 # number of ReadCleanReq hits
2489system.l2c.ReadCleanReq_hits::cpu2.inst 685 # number of ReadCleanReq hits
2490system.l2c.ReadCleanReq_hits::cpu3.inst 698 # number of ReadCleanReq hits
2491system.l2c.ReadCleanReq_hits::total 2236 # number of ReadCleanReq hits
2492system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
2493system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
2494system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
2495system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
2496system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits
2497system.l2c.demand_hits::cpu0.inst 309 # number of demand (read+write) hits
2498system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
2499system.l2c.demand_hits::cpu1.inst 544 # number of demand (read+write) hits
2500system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
2501system.l2c.demand_hits::cpu2.inst 685 # number of demand (read+write) hits
2502system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
2503system.l2c.demand_hits::cpu3.inst 698 # number of demand (read+write) hits
2504system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
2505system.l2c.demand_hits::total 2268 # number of demand (read+write) hits
2506system.l2c.overall_hits::cpu0.inst 309 # number of overall hits
2507system.l2c.overall_hits::cpu0.data 5 # number of overall hits
2508system.l2c.overall_hits::cpu1.inst 544 # number of overall hits
2509system.l2c.overall_hits::cpu1.data 5 # number of overall hits
2510system.l2c.overall_hits::cpu2.inst 685 # number of overall hits
2511system.l2c.overall_hits::cpu2.data 11 # number of overall hits
2512system.l2c.overall_hits::cpu3.inst 698 # number of overall hits
2513system.l2c.overall_hits::cpu3.data 11 # number of overall hits
2514system.l2c.overall_hits::total 2268 # number of overall hits
2515system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2516system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2517system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2518system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2519system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
2520system.l2c.ReadCleanReq_misses::cpu0.inst 373 # number of ReadCleanReq misses
2521system.l2c.ReadCleanReq_misses::cpu1.inst 99 # number of ReadCleanReq misses
2522system.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses
2523system.l2c.ReadCleanReq_misses::cpu3.inst 16 # number of ReadCleanReq misses
2524system.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses
2525system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses
2526system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses
2527system.l2c.ReadSharedReq_misses::cpu2.data 2 # number of ReadSharedReq misses
2528system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
2529system.l2c.ReadSharedReq_misses::total 88 # number of ReadSharedReq misses
2530system.l2c.demand_misses::cpu0.inst 373 # number of demand (read+write) misses
2531system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
2532system.l2c.demand_misses::cpu1.inst 99 # number of demand (read+write) misses
2533system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses
2534system.l2c.demand_misses::cpu2.inst 22 # number of demand (read+write) misses
2535system.l2c.demand_misses::cpu2.data 14 # number of demand (read+write) misses
2536system.l2c.demand_misses::cpu3.inst 16 # number of demand (read+write) misses
2537system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses
2538system.l2c.demand_misses::total 729 # number of demand (read+write) misses
2539system.l2c.overall_misses::cpu0.inst 373 # number of overall misses
2540system.l2c.overall_misses::cpu0.data 169 # number of overall misses
2541system.l2c.overall_misses::cpu1.inst 99 # number of overall misses
2542system.l2c.overall_misses::cpu1.data 22 # number of overall misses
2543system.l2c.overall_misses::cpu2.inst 22 # number of overall misses
2544system.l2c.overall_misses::cpu2.data 14 # number of overall misses
2545system.l2c.overall_misses::cpu3.inst 16 # number of overall misses
2546system.l2c.overall_misses::cpu3.data 14 # number of overall misses
2547system.l2c.overall_misses::total 729 # number of overall misses
2548system.l2c.ReadExReq_miss_latency::cpu0.data 7939000 # number of ReadExReq miss cycles
2549system.l2c.ReadExReq_miss_latency::cpu1.data 1091000 # number of ReadExReq miss cycles
2550system.l2c.ReadExReq_miss_latency::cpu2.data 1053000 # number of ReadExReq miss cycles
2551system.l2c.ReadExReq_miss_latency::cpu3.data 1225000 # number of ReadExReq miss cycles
2552system.l2c.ReadExReq_miss_latency::total 11308000 # number of ReadExReq miss cycles
2553system.l2c.ReadCleanReq_miss_latency::cpu0.inst 30754500 # number of ReadCleanReq miss cycles
2554system.l2c.ReadCleanReq_miss_latency::cpu1.inst 8285500 # number of ReadCleanReq miss cycles
2555system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2209000 # number of ReadCleanReq miss cycles
2556system.l2c.ReadCleanReq_miss_latency::cpu3.inst 1811500 # number of ReadCleanReq miss cycles
2557system.l2c.ReadCleanReq_miss_latency::total 43060500 # number of ReadCleanReq miss cycles
2558system.l2c.ReadSharedReq_miss_latency::cpu0.data 6607500 # number of ReadSharedReq miss cycles
2559system.l2c.ReadSharedReq_miss_latency::cpu1.data 768000 # number of ReadSharedReq miss cycles
2560system.l2c.ReadSharedReq_miss_latency::cpu2.data 179500 # number of ReadSharedReq miss cycles
2561system.l2c.ReadSharedReq_miss_latency::cpu3.data 199500 # number of ReadSharedReq miss cycles
2562system.l2c.ReadSharedReq_miss_latency::total 7754500 # number of ReadSharedReq miss cycles
2563system.l2c.demand_miss_latency::cpu0.inst 30754500 # number of demand (read+write) miss cycles
2564system.l2c.demand_miss_latency::cpu0.data 14546500 # number of demand (read+write) miss cycles
2565system.l2c.demand_miss_latency::cpu1.inst 8285500 # number of demand (read+write) miss cycles
2566system.l2c.demand_miss_latency::cpu1.data 1859000 # number of demand (read+write) miss cycles
2567system.l2c.demand_miss_latency::cpu2.inst 2209000 # number of demand (read+write) miss cycles
2568system.l2c.demand_miss_latency::cpu2.data 1232500 # number of demand (read+write) miss cycles
2569system.l2c.demand_miss_latency::cpu3.inst 1811500 # number of demand (read+write) miss cycles
2570system.l2c.demand_miss_latency::cpu3.data 1424500 # number of demand (read+write) miss cycles
2571system.l2c.demand_miss_latency::total 62123000 # number of demand (read+write) miss cycles
2572system.l2c.overall_miss_latency::cpu0.inst 30754500 # number of overall miss cycles
2573system.l2c.overall_miss_latency::cpu0.data 14546500 # number of overall miss cycles
2574system.l2c.overall_miss_latency::cpu1.inst 8285500 # number of overall miss cycles
2575system.l2c.overall_miss_latency::cpu1.data 1859000 # number of overall miss cycles
2576system.l2c.overall_miss_latency::cpu2.inst 2209000 # number of overall miss cycles
2577system.l2c.overall_miss_latency::cpu2.data 1232500 # number of overall miss cycles
2578system.l2c.overall_miss_latency::cpu3.inst 1811500 # number of overall miss cycles
2579system.l2c.overall_miss_latency::cpu3.data 1424500 # number of overall miss cycles
2580system.l2c.overall_miss_latency::total 62123000 # number of overall miss cycles
2581system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
2582system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
2583system.l2c.WritebackClean_accesses::writebacks 752 # number of WritebackClean accesses(hits+misses)
2584system.l2c.WritebackClean_accesses::total 752 # number of WritebackClean accesses(hits+misses)
2585system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses)
2586system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses)
2587system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
2588system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses)
2589system.l2c.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses)
2590system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2591system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2592system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2593system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2594system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
2595system.l2c.ReadCleanReq_accesses::cpu0.inst 682 # number of ReadCleanReq accesses(hits+misses)
2596system.l2c.ReadCleanReq_accesses::cpu1.inst 643 # number of ReadCleanReq accesses(hits+misses)
2597system.l2c.ReadCleanReq_accesses::cpu2.inst 707 # number of ReadCleanReq accesses(hits+misses)
2598system.l2c.ReadCleanReq_accesses::cpu3.inst 714 # number of ReadCleanReq accesses(hits+misses)
2599system.l2c.ReadCleanReq_accesses::total 2746 # number of ReadCleanReq accesses(hits+misses)
2600system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses)
2601system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses)
2602system.l2c.ReadSharedReq_accesses::cpu2.data 13 # number of ReadSharedReq accesses(hits+misses)
2603system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses)
2604system.l2c.ReadSharedReq_accesses::total 120 # number of ReadSharedReq accesses(hits+misses)
2605system.l2c.demand_accesses::cpu0.inst 682 # number of demand (read+write) accesses
2606system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
2607system.l2c.demand_accesses::cpu1.inst 643 # number of demand (read+write) accesses
2608system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses
2609system.l2c.demand_accesses::cpu2.inst 707 # number of demand (read+write) accesses
2610system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
2611system.l2c.demand_accesses::cpu3.inst 714 # number of demand (read+write) accesses
2612system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
2613system.l2c.demand_accesses::total 2997 # number of demand (read+write) accesses
2614system.l2c.overall_accesses::cpu0.inst 682 # number of overall (read+write) accesses
2615system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
2616system.l2c.overall_accesses::cpu1.inst 643 # number of overall (read+write) accesses
2617system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses
2618system.l2c.overall_accesses::cpu2.inst 707 # number of overall (read+write) accesses
2619system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
2620system.l2c.overall_accesses::cpu3.inst 714 # number of overall (read+write) accesses
2621system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
2622system.l2c.overall_accesses::total 2997 # number of overall (read+write) accesses
2623system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2624system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2625system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2626system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2627system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2628system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.546921 # miss rate for ReadCleanReq accesses
2629system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.153966 # miss rate for ReadCleanReq accesses
2630system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.031117 # miss rate for ReadCleanReq accesses
2631system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.022409 # miss rate for ReadCleanReq accesses
2632system.l2c.ReadCleanReq_miss_rate::total 0.185725 # miss rate for ReadCleanReq accesses
2633system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses
2634system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses
2635system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadSharedReq accesses
2636system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses
2637system.l2c.ReadSharedReq_miss_rate::total 0.733333 # miss rate for ReadSharedReq accesses
2638system.l2c.demand_miss_rate::cpu0.inst 0.546921 # miss rate for demand accesses
2639system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
2640system.l2c.demand_miss_rate::cpu1.inst 0.153966 # miss rate for demand accesses
2641system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses
2642system.l2c.demand_miss_rate::cpu2.inst 0.031117 # miss rate for demand accesses
2643system.l2c.demand_miss_rate::cpu2.data 0.560000 # miss rate for demand accesses
2644system.l2c.demand_miss_rate::cpu3.inst 0.022409 # miss rate for demand accesses
2645system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses
2646system.l2c.demand_miss_rate::total 0.243243 # miss rate for demand accesses
2647system.l2c.overall_miss_rate::cpu0.inst 0.546921 # miss rate for overall accesses
2648system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
2649system.l2c.overall_miss_rate::cpu1.inst 0.153966 # miss rate for overall accesses
2650system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses
2651system.l2c.overall_miss_rate::cpu2.inst 0.031117 # miss rate for overall accesses
2652system.l2c.overall_miss_rate::cpu2.data 0.560000 # miss rate for overall accesses
2653system.l2c.overall_miss_rate::cpu3.inst 0.022409 # miss rate for overall accesses
2654system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses
2655system.l2c.overall_miss_rate::total 0.243243 # miss rate for overall accesses
2656system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84457.446809 # average ReadExReq miss latency
2657system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83923.076923 # average ReadExReq miss latency
2658system.l2c.ReadExReq_avg_miss_latency::cpu2.data 87750 # average ReadExReq miss latency
2659system.l2c.ReadExReq_avg_miss_latency::cpu3.data 102083.333333 # average ReadExReq miss latency
2660system.l2c.ReadExReq_avg_miss_latency::total 86320.610687 # average ReadExReq miss latency
2661system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82451.742627 # average ReadCleanReq miss latency
2662system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83691.919192 # average ReadCleanReq miss latency
2663system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 100409.090909 # average ReadCleanReq miss latency
2664system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 113218.750000 # average ReadCleanReq miss latency
2665system.l2c.ReadCleanReq_avg_miss_latency::total 84432.352941 # average ReadCleanReq miss latency
2666system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88100 # average ReadSharedReq miss latency
2667system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85333.333333 # average ReadSharedReq miss latency
2668system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 89750 # average ReadSharedReq miss latency
2669system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 99750 # average ReadSharedReq miss latency
2670system.l2c.ReadSharedReq_avg_miss_latency::total 88119.318182 # average ReadSharedReq miss latency
2671system.l2c.demand_avg_miss_latency::cpu0.inst 82451.742627 # average overall miss latency
2672system.l2c.demand_avg_miss_latency::cpu0.data 86073.964497 # average overall miss latency
2673system.l2c.demand_avg_miss_latency::cpu1.inst 83691.919192 # average overall miss latency
2674system.l2c.demand_avg_miss_latency::cpu1.data 84500 # average overall miss latency
2675system.l2c.demand_avg_miss_latency::cpu2.inst 100409.090909 # average overall miss latency
2676system.l2c.demand_avg_miss_latency::cpu2.data 88035.714286 # average overall miss latency
2677system.l2c.demand_avg_miss_latency::cpu3.inst 113218.750000 # average overall miss latency
2678system.l2c.demand_avg_miss_latency::cpu3.data 101750 # average overall miss latency
2679system.l2c.demand_avg_miss_latency::total 85216.735254 # average overall miss latency
2680system.l2c.overall_avg_miss_latency::cpu0.inst 82451.742627 # average overall miss latency
2681system.l2c.overall_avg_miss_latency::cpu0.data 86073.964497 # average overall miss latency
2682system.l2c.overall_avg_miss_latency::cpu1.inst 83691.919192 # average overall miss latency
2683system.l2c.overall_avg_miss_latency::cpu1.data 84500 # average overall miss latency
2684system.l2c.overall_avg_miss_latency::cpu2.inst 100409.090909 # average overall miss latency
2685system.l2c.overall_avg_miss_latency::cpu2.data 88035.714286 # average overall miss latency
2686system.l2c.overall_avg_miss_latency::cpu3.inst 113218.750000 # average overall miss latency
2687system.l2c.overall_avg_miss_latency::cpu3.data 101750 # average overall miss latency
2688system.l2c.overall_avg_miss_latency::total 85216.735254 # average overall miss latency
2689system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2690system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2691system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2692system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2693system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2694system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2695system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits
2696system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits
2697system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits
2698system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
2699system.l2c.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits
2700system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
2701system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
2702system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits
2703system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
2704system.l2c.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
2705system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
2706system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
2707system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits
2708system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2709system.l2c.overall_mshr_hits::total 21 # number of overall MSHR hits
2710system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2711system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
2712system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2713system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2714system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
2715system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 370 # number of ReadCleanReq MSHR misses
2716system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 94 # number of ReadCleanReq MSHR misses
2717system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 12 # number of ReadCleanReq MSHR misses
2718system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 13 # number of ReadCleanReq MSHR misses
2719system.l2c.ReadCleanReq_mshr_misses::total 489 # number of ReadCleanReq MSHR misses
2720system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses
2721system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses
2722system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2 # number of ReadSharedReq MSHR misses
2723system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses
2724system.l2c.ReadSharedReq_mshr_misses::total 88 # number of ReadSharedReq MSHR misses
2725system.l2c.demand_mshr_misses::cpu0.inst 370 # number of demand (read+write) MSHR misses
2726system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
2727system.l2c.demand_mshr_misses::cpu1.inst 94 # number of demand (read+write) MSHR misses
2728system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
2729system.l2c.demand_mshr_misses::cpu2.inst 12 # number of demand (read+write) MSHR misses
2730system.l2c.demand_mshr_misses::cpu2.data 14 # number of demand (read+write) MSHR misses
2731system.l2c.demand_mshr_misses::cpu3.inst 13 # number of demand (read+write) MSHR misses
2732system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses
2733system.l2c.demand_mshr_misses::total 708 # number of demand (read+write) MSHR misses
2734system.l2c.overall_mshr_misses::cpu0.inst 370 # number of overall MSHR misses
2735system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
2736system.l2c.overall_mshr_misses::cpu1.inst 94 # number of overall MSHR misses
2737system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
2738system.l2c.overall_mshr_misses::cpu2.inst 12 # number of overall MSHR misses
2739system.l2c.overall_mshr_misses::cpu2.data 14 # number of overall MSHR misses
2740system.l2c.overall_mshr_misses::cpu3.inst 13 # number of overall MSHR misses
2741system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses
2742system.l2c.overall_mshr_misses::total 708 # number of overall MSHR misses
2743system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6999000 # number of ReadExReq MSHR miss cycles
2744system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 961000 # number of ReadExReq MSHR miss cycles
2745system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 933000 # number of ReadExReq MSHR miss cycles
2746system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1105000 # number of ReadExReq MSHR miss cycles
2747system.l2c.ReadExReq_mshr_miss_latency::total 9998000 # number of ReadExReq MSHR miss cycles
2748system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 26936000 # number of ReadCleanReq MSHR miss cycles
2749system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 7072000 # number of ReadCleanReq MSHR miss cycles
2750system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1460500 # number of ReadCleanReq MSHR miss cycles
2751system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1496500 # number of ReadCleanReq MSHR miss cycles
2752system.l2c.ReadCleanReq_mshr_miss_latency::total 36965000 # number of ReadCleanReq MSHR miss cycles
2753system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5857500 # number of ReadSharedReq MSHR miss cycles
2754system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 678000 # number of ReadSharedReq MSHR miss cycles
2755system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 159500 # number of ReadSharedReq MSHR miss cycles
2756system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 179500 # number of ReadSharedReq MSHR miss cycles
2757system.l2c.ReadSharedReq_mshr_miss_latency::total 6874500 # number of ReadSharedReq MSHR miss cycles
2758system.l2c.demand_mshr_miss_latency::cpu0.inst 26936000 # number of demand (read+write) MSHR miss cycles
2759system.l2c.demand_mshr_miss_latency::cpu0.data 12856500 # number of demand (read+write) MSHR miss cycles
2760system.l2c.demand_mshr_miss_latency::cpu1.inst 7072000 # number of demand (read+write) MSHR miss cycles
2761system.l2c.demand_mshr_miss_latency::cpu1.data 1639000 # number of demand (read+write) MSHR miss cycles
2762system.l2c.demand_mshr_miss_latency::cpu2.inst 1460500 # number of demand (read+write) MSHR miss cycles
2763system.l2c.demand_mshr_miss_latency::cpu2.data 1092500 # number of demand (read+write) MSHR miss cycles
2764system.l2c.demand_mshr_miss_latency::cpu3.inst 1496500 # number of demand (read+write) MSHR miss cycles
2765system.l2c.demand_mshr_miss_latency::cpu3.data 1284500 # number of demand (read+write) MSHR miss cycles
2766system.l2c.demand_mshr_miss_latency::total 53837500 # number of demand (read+write) MSHR miss cycles
2767system.l2c.overall_mshr_miss_latency::cpu0.inst 26936000 # number of overall MSHR miss cycles
2768system.l2c.overall_mshr_miss_latency::cpu0.data 12856500 # number of overall MSHR miss cycles
2769system.l2c.overall_mshr_miss_latency::cpu1.inst 7072000 # number of overall MSHR miss cycles
2770system.l2c.overall_mshr_miss_latency::cpu1.data 1639000 # number of overall MSHR miss cycles
2771system.l2c.overall_mshr_miss_latency::cpu2.inst 1460500 # number of overall MSHR miss cycles
2772system.l2c.overall_mshr_miss_latency::cpu2.data 1092500 # number of overall MSHR miss cycles
2773system.l2c.overall_mshr_miss_latency::cpu3.inst 1496500 # number of overall MSHR miss cycles
2774system.l2c.overall_mshr_miss_latency::cpu3.data 1284500 # number of overall MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::total 53837500 # number of overall MSHR miss cycles
2776system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2777system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2778system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2779system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2780system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2781system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.542522 # mshr miss rate for ReadCleanReq accesses
2782system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.146190 # mshr miss rate for ReadCleanReq accesses
2783system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.016973 # mshr miss rate for ReadCleanReq accesses
2784system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for ReadCleanReq accesses
2785system.l2c.ReadCleanReq_mshr_miss_rate::total 0.178077 # mshr miss rate for ReadCleanReq accesses
2786system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses
2787system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses
2788system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadSharedReq accesses
2789system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses
2790system.l2c.ReadSharedReq_mshr_miss_rate::total 0.733333 # mshr miss rate for ReadSharedReq accesses
2791system.l2c.demand_mshr_miss_rate::cpu0.inst 0.542522 # mshr miss rate for demand accesses
2792system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2793system.l2c.demand_mshr_miss_rate::cpu1.inst 0.146190 # mshr miss rate for demand accesses
2794system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses
2795system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016973 # mshr miss rate for demand accesses
2796system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for demand accesses
2797system.l2c.demand_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for demand accesses
2798system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses
2799system.l2c.demand_mshr_miss_rate::total 0.236236 # mshr miss rate for demand accesses
2800system.l2c.overall_mshr_miss_rate::cpu0.inst 0.542522 # mshr miss rate for overall accesses
2801system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2802system.l2c.overall_mshr_miss_rate::cpu1.inst 0.146190 # mshr miss rate for overall accesses
2803system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses
2804system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016973 # mshr miss rate for overall accesses
2805system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for overall accesses
2806system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for overall accesses
2807system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses
2808system.l2c.overall_mshr_miss_rate::total 0.236236 # mshr miss rate for overall accesses
2809system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74457.446809 # average ReadExReq mshr miss latency
2810system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73923.076923 # average ReadExReq mshr miss latency
2811system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 77750 # average ReadExReq mshr miss latency
2812system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 92083.333333 # average ReadExReq mshr miss latency
2813system.l2c.ReadExReq_avg_mshr_miss_latency::total 76320.610687 # average ReadExReq mshr miss latency
2814system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72800 # average ReadCleanReq mshr miss latency
2815system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average ReadCleanReq mshr miss latency
2816system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average ReadCleanReq mshr miss latency
2817system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average ReadCleanReq mshr miss latency
2818system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75593.047035 # average ReadCleanReq mshr miss latency
2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78100 # average ReadSharedReq mshr miss latency
2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75333.333333 # average ReadSharedReq mshr miss latency
2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79750 # average ReadSharedReq mshr miss latency
2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 89750 # average ReadSharedReq mshr miss latency
2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78119.318182 # average ReadSharedReq mshr miss latency
2824system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency
2825system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency
2826system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency
2827system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency
2828system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency
2829system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency
2830system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency
2831system.l2c.demand_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency
2832system.l2c.demand_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency
2833system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency
2834system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency
2835system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency
2836system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency
2837system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency
2838system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency
2839system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency
2840system.l2c.overall_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency
2841system.l2c.overall_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency
2842system.membus.snoop_filter.tot_requests 958 # Total number of requests made to the snoop filter.
2843system.membus.snoop_filter.hit_single_requests 251 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2844system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2845system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2846system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2847system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2848system.membus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2849system.membus.trans_dist::ReadResp 576 # Transaction distribution
2850system.membus.trans_dist::UpgradeReq 200 # Transaction distribution
2851system.membus.trans_dist::ReadExReq 182 # Transaction distribution
2852system.membus.trans_dist::ReadExResp 131 # Transaction distribution
2853system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution
2854system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1665 # Packet count per connected master and slave (bytes)
2855system.membus.pkt_count::total 1665 # Packet count per connected master and slave (bytes)
2856system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45248 # Cumulative packet size per connected master and slave (bytes)
2857system.membus.pkt_size::total 45248 # Cumulative packet size per connected master and slave (bytes)
2858system.membus.snoops 251 # Total snoops (count)
2859system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2860system.membus.snoop_fanout::samples 958 # Request fanout histogram
2861system.membus.snoop_fanout::mean 0 # Request fanout histogram
2862system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2863system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2864system.membus.snoop_fanout::0 958 100.00% 100.00% # Request fanout histogram
2865system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2866system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2867system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2868system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2869system.membus.snoop_fanout::total 958 # Request fanout histogram
2870system.membus.reqLayer0.occupancy 881500 # Layer occupancy (ticks)
2871system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
2872system.membus.respLayer1.occupancy 3759250 # Layer occupancy (ticks)
2873system.membus.respLayer1.utilization 3.0 # Layer utilization (%)
2874system.toL2Bus.snoop_filter.tot_requests 6160 # Total number of requests made to the snoop filter.
2875system.toL2Bus.snoop_filter.hit_single_requests 1652 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2876system.toL2Bus.snoop_filter.hit_multi_requests 3166 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2877system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2878system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2879system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2880system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states
2881system.toL2Bus.trans_dist::ReadResp 3429 # Transaction distribution
2882system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
2883system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
2884system.toL2Bus.trans_dist::WritebackClean 2041 # Transaction distribution
2885system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
2886system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution
2887system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution
2888system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution
2889system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution
2890system.toL2Bus.trans_dist::ReadCleanReq 2746 # Transaction distribution
2891system.toL2Bus.trans_dist::ReadSharedReq 686 # Transaction distribution
2892system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1744 # Packet count per connected master and slave (bytes)
2893system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes)
2894system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1793 # Packet count per connected master and slave (bytes)
2895system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
2896system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1989 # Packet count per connected master and slave (bytes)
2897system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 384 # Packet count per connected master and slave (bytes)
2898system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2006 # Packet count per connected master and slave (bytes)
2899system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
2900system.toL2Bus.pkt_count::total 9243 # Packet count per connected master and slave (bytes)
2901system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 67968 # Cumulative packet size per connected master and slave (bytes)
2902system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
2903system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 73600 # Cumulative packet size per connected master and slave (bytes)
2904system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes)
2905system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82048 # Cumulative packet size per connected master and slave (bytes)
2906system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2907system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes)
2908system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2909system.toL2Bus.pkt_size::total 322432 # Cumulative packet size per connected master and slave (bytes)
2910system.toL2Bus.snoops 1033 # Total snoops (count)
2911system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes)
2912system.toL2Bus.snoop_fanout::samples 4117 # Request fanout histogram
2913system.toL2Bus.snoop_fanout::mean 1.305805 # Request fanout histogram
2914system.toL2Bus.snoop_fanout::stdev 1.138383 # Request fanout histogram
2915system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2916system.toL2Bus.snoop_fanout::0 1342 32.60% 32.60% # Request fanout histogram
2917system.toL2Bus.snoop_fanout::1 1062 25.80% 58.39% # Request fanout histogram
2918system.toL2Bus.snoop_fanout::2 825 20.04% 78.43% # Request fanout histogram
2919system.toL2Bus.snoop_fanout::3 888 21.57% 100.00% # Request fanout histogram
2920system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2921system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
2922system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
2923system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2924system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2925system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2926system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2927system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
2928system.toL2Bus.snoop_fanout::total 4117 # Request fanout histogram
2929system.toL2Bus.reqLayer0.occupancy 5135473 # Layer occupancy (ticks)
2930system.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%)
2931system.toL2Bus.respLayer0.occupancy 1023494 # Layer occupancy (ticks)
2932system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
2933system.toL2Bus.respLayer1.occupancy 524487 # Layer occupancy (ticks)
2934system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
2935system.toL2Bus.respLayer2.occupancy 967494 # Layer occupancy (ticks)
2936system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%)
2937system.toL2Bus.respLayer3.occupancy 424479 # Layer occupancy (ticks)
2938system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)
2939system.toL2Bus.respLayer4.occupancy 1065487 # Layer occupancy (ticks)
2940system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%)
2941system.toL2Bus.respLayer5.occupancy 451954 # Layer occupancy (ticks)
2942system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
2943system.toL2Bus.respLayer6.occupancy 1072994 # Layer occupancy (ticks)
2944system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%)
2945system.toL2Bus.respLayer7.occupancy 419968 # Layer occupancy (ticks)
2946system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)
| 3sim_seconds 0.000127
4sim_ticks 126524000
5final_tick 126524000
6sim_freq 1000000000000
7host_inst_rate 214440
8host_op_rate 214440
9host_tick_rate 23217304
10host_mem_usage 280860
11host_seconds 5.45
12sim_insts 1168600
13sim_ops 1168600
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 126524000
17system.physmem.bytes_read::cpu0.inst 23616
18system.physmem.bytes_read::cpu0.data 10816
19system.physmem.bytes_read::cpu1.inst 5888
20system.physmem.bytes_read::cpu1.data 1344
21system.physmem.bytes_read::cpu2.inst 896
22system.physmem.bytes_read::cpu2.data 896
23system.physmem.bytes_read::cpu3.inst 768
24system.physmem.bytes_read::cpu3.data 960
25system.physmem.bytes_read::total 45184
26system.physmem.bytes_inst_read::cpu0.inst 23616
27system.physmem.bytes_inst_read::cpu1.inst 5888
28system.physmem.bytes_inst_read::cpu2.inst 896
29system.physmem.bytes_inst_read::cpu3.inst 768
30system.physmem.bytes_inst_read::total 31168
31system.physmem.num_reads::cpu0.inst 369
32system.physmem.num_reads::cpu0.data 169
33system.physmem.num_reads::cpu1.inst 92
34system.physmem.num_reads::cpu1.data 21
35system.physmem.num_reads::cpu2.inst 14
36system.physmem.num_reads::cpu2.data 14
37system.physmem.num_reads::cpu3.inst 12
38system.physmem.num_reads::cpu3.data 15
39system.physmem.num_reads::total 706
40system.physmem.bw_read::cpu0.inst 186652335
41system.physmem.bw_read::cpu0.data 85485758
42system.physmem.bw_read::cpu1.inst 46536625
43system.physmem.bw_read::cpu1.data 10622491
44system.physmem.bw_read::cpu2.inst 7081660
45system.physmem.bw_read::cpu2.data 7081660
46system.physmem.bw_read::cpu3.inst 6069995
47system.physmem.bw_read::cpu3.data 7587493
48system.physmem.bw_read::total 357118017
49system.physmem.bw_inst_read::cpu0.inst 186652335
50system.physmem.bw_inst_read::cpu1.inst 46536625
51system.physmem.bw_inst_read::cpu2.inst 7081660
52system.physmem.bw_inst_read::cpu3.inst 6069995
53system.physmem.bw_inst_read::total 246340615
54system.physmem.bw_total::cpu0.inst 186652335
55system.physmem.bw_total::cpu0.data 85485758
56system.physmem.bw_total::cpu1.inst 46536625
57system.physmem.bw_total::cpu1.data 10622491
58system.physmem.bw_total::cpu2.inst 7081660
59system.physmem.bw_total::cpu2.data 7081660
60system.physmem.bw_total::cpu3.inst 6069995
61system.physmem.bw_total::cpu3.data 7587493
62system.physmem.bw_total::total 357118017
63system.physmem.readReqs 706
64system.physmem.writeReqs 0
65system.physmem.readBursts 706
66system.physmem.writeBursts 0
67system.physmem.bytesReadDRAM 45184
68system.physmem.bytesReadWrQ 0
69system.physmem.bytesWritten 0
70system.physmem.bytesReadSys 45184
71system.physmem.bytesWrittenSys 0
72system.physmem.servicedByWrQ 0
73system.physmem.mergedWrBursts 0
74system.physmem.neitherReadNorWriteReqs 0
75system.physmem.perBankRdBursts::0 118
76system.physmem.perBankRdBursts::1 44
77system.physmem.perBankRdBursts::2 34
78system.physmem.perBankRdBursts::3 38
79system.physmem.perBankRdBursts::4 62
80system.physmem.perBankRdBursts::5 39
81system.physmem.perBankRdBursts::6 22
82system.physmem.perBankRdBursts::7 39
83system.physmem.perBankRdBursts::8 11
84system.physmem.perBankRdBursts::9 29
85system.physmem.perBankRdBursts::10 23
86system.physmem.perBankRdBursts::11 13
87system.physmem.perBankRdBursts::12 69
88system.physmem.perBankRdBursts::13 46
89system.physmem.perBankRdBursts::14 19
90system.physmem.perBankRdBursts::15 100
91system.physmem.perBankWrBursts::0 0
92system.physmem.perBankWrBursts::1 0
93system.physmem.perBankWrBursts::2 0
94system.physmem.perBankWrBursts::3 0
95system.physmem.perBankWrBursts::4 0
96system.physmem.perBankWrBursts::5 0
97system.physmem.perBankWrBursts::6 0
98system.physmem.perBankWrBursts::7 0
99system.physmem.perBankWrBursts::8 0
100system.physmem.perBankWrBursts::9 0
101system.physmem.perBankWrBursts::10 0
102system.physmem.perBankWrBursts::11 0
103system.physmem.perBankWrBursts::12 0
104system.physmem.perBankWrBursts::13 0
105system.physmem.perBankWrBursts::14 0
106system.physmem.perBankWrBursts::15 0
107system.physmem.numRdRetry 0
108system.physmem.numWrRetry 0
109system.physmem.totGap 126284000
110system.physmem.readPktSize::0 0
111system.physmem.readPktSize::1 0
112system.physmem.readPktSize::2 0
113system.physmem.readPktSize::3 0
114system.physmem.readPktSize::4 0
115system.physmem.readPktSize::5 0
116system.physmem.readPktSize::6 706
117system.physmem.writePktSize::0 0
118system.physmem.writePktSize::1 0
119system.physmem.writePktSize::2 0
120system.physmem.writePktSize::3 0
121system.physmem.writePktSize::4 0
122system.physmem.writePktSize::5 0
123system.physmem.writePktSize::6 0
124system.physmem.rdQLenPdf::0 414
125system.physmem.rdQLenPdf::1 215
126system.physmem.rdQLenPdf::2 55
127system.physmem.rdQLenPdf::3 17
128system.physmem.rdQLenPdf::4 4
129system.physmem.rdQLenPdf::5 1
130system.physmem.rdQLenPdf::6 0
131system.physmem.rdQLenPdf::7 0
132system.physmem.rdQLenPdf::8 0
133system.physmem.rdQLenPdf::9 0
134system.physmem.rdQLenPdf::10 0
135system.physmem.rdQLenPdf::11 0
136system.physmem.rdQLenPdf::12 0
137system.physmem.rdQLenPdf::13 0
138system.physmem.rdQLenPdf::14 0
139system.physmem.rdQLenPdf::15 0
140system.physmem.rdQLenPdf::16 0
141system.physmem.rdQLenPdf::17 0
142system.physmem.rdQLenPdf::18 0
143system.physmem.rdQLenPdf::19 0
144system.physmem.rdQLenPdf::20 0
145system.physmem.rdQLenPdf::21 0
146system.physmem.rdQLenPdf::22 0
147system.physmem.rdQLenPdf::23 0
148system.physmem.rdQLenPdf::24 0
149system.physmem.rdQLenPdf::25 0
150system.physmem.rdQLenPdf::26 0
151system.physmem.rdQLenPdf::27 0
152system.physmem.rdQLenPdf::28 0
153system.physmem.rdQLenPdf::29 0
154system.physmem.rdQLenPdf::30 0
155system.physmem.rdQLenPdf::31 0
156system.physmem.wrQLenPdf::0 0
157system.physmem.wrQLenPdf::1 0
158system.physmem.wrQLenPdf::2 0
159system.physmem.wrQLenPdf::3 0
160system.physmem.wrQLenPdf::4 0
161system.physmem.wrQLenPdf::5 0
162system.physmem.wrQLenPdf::6 0
163system.physmem.wrQLenPdf::7 0
164system.physmem.wrQLenPdf::8 0
165system.physmem.wrQLenPdf::9 0
166system.physmem.wrQLenPdf::10 0
167system.physmem.wrQLenPdf::11 0
168system.physmem.wrQLenPdf::12 0
169system.physmem.wrQLenPdf::13 0
170system.physmem.wrQLenPdf::14 0
171system.physmem.wrQLenPdf::15 0
172system.physmem.wrQLenPdf::16 0
173system.physmem.wrQLenPdf::17 0
174system.physmem.wrQLenPdf::18 0
175system.physmem.wrQLenPdf::19 0
176system.physmem.wrQLenPdf::20 0
177system.physmem.wrQLenPdf::21 0
178system.physmem.wrQLenPdf::22 0
179system.physmem.wrQLenPdf::23 0
180system.physmem.wrQLenPdf::24 0
181system.physmem.wrQLenPdf::25 0
182system.physmem.wrQLenPdf::26 0
183system.physmem.wrQLenPdf::27 0
184system.physmem.wrQLenPdf::28 0
185system.physmem.wrQLenPdf::29 0
186system.physmem.wrQLenPdf::30 0
187system.physmem.wrQLenPdf::31 0
188system.physmem.wrQLenPdf::32 0
189system.physmem.wrQLenPdf::33 0
190system.physmem.wrQLenPdf::34 0
191system.physmem.wrQLenPdf::35 0
192system.physmem.wrQLenPdf::36 0
193system.physmem.wrQLenPdf::37 0
194system.physmem.wrQLenPdf::38 0
195system.physmem.wrQLenPdf::39 0
196system.physmem.wrQLenPdf::40 0
197system.physmem.wrQLenPdf::41 0
198system.physmem.wrQLenPdf::42 0
199system.physmem.wrQLenPdf::43 0
200system.physmem.wrQLenPdf::44 0
201system.physmem.wrQLenPdf::45 0
202system.physmem.wrQLenPdf::46 0
203system.physmem.wrQLenPdf::47 0
204system.physmem.wrQLenPdf::48 0
205system.physmem.wrQLenPdf::49 0
206system.physmem.wrQLenPdf::50 0
207system.physmem.wrQLenPdf::51 0
208system.physmem.wrQLenPdf::52 0
209system.physmem.wrQLenPdf::53 0
210system.physmem.wrQLenPdf::54 0
211system.physmem.wrQLenPdf::55 0
212system.physmem.wrQLenPdf::56 0
213system.physmem.wrQLenPdf::57 0
214system.physmem.wrQLenPdf::58 0
215system.physmem.wrQLenPdf::59 0
216system.physmem.wrQLenPdf::60 0
217system.physmem.wrQLenPdf::61 0
218system.physmem.wrQLenPdf::62 0
219system.physmem.wrQLenPdf::63 0
220system.physmem.bytesPerActivate::samples 171
221system.physmem.bytesPerActivate::mean 248.140351
222system.physmem.bytesPerActivate::gmean 165.969670
223system.physmem.bytesPerActivate::stdev 244.268664
224system.physmem.bytesPerActivate::0-127 61 35.67% 35.67%
225system.physmem.bytesPerActivate::128-255 47 27.49% 63.16%
226system.physmem.bytesPerActivate::256-383 27 15.79% 78.95%
227system.physmem.bytesPerActivate::384-511 11 6.43% 85.38%
228system.physmem.bytesPerActivate::512-639 7 4.09% 89.47%
229system.physmem.bytesPerActivate::640-767 7 4.09% 93.57%
230system.physmem.bytesPerActivate::768-895 4 2.34% 95.91%
231system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49%
232system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00%
233system.physmem.bytesPerActivate::total 171
234system.physmem.totQLat 12887500
235system.physmem.totMemAccLat 26125000
236system.physmem.totBusLat 3530000
237system.physmem.avgQLat 18254.25
238system.physmem.avgBusLat 5000.00
239system.physmem.avgMemAccLat 37004.25
240system.physmem.avgRdBW 357.12
241system.physmem.avgWrBW 0.00
242system.physmem.avgRdBWSys 357.12
243system.physmem.avgWrBWSys 0.00
244system.physmem.peakBW 12800.00
245system.physmem.busUtil 2.79
246system.physmem.busUtilRead 2.79
247system.physmem.busUtilWrite 0.00
248system.physmem.avgRdQLen 1.22
249system.physmem.avgWrQLen 0.00
250system.physmem.readRowHits 525
251system.physmem.writeRowHits 0
252system.physmem.readRowHitRate 74.36
253system.physmem.writeRowHitRate nan
254system.physmem.avgGap 178872.52
255system.physmem.pageHitRate 74.36
256system.physmem_0.actEnergy 813960
257system.physmem_0.preEnergy 417450
258system.physmem_0.readEnergy 2827440
259system.physmem_0.writeEnergy 0
260system.physmem_0.refreshEnergy 9834240.000000
261system.physmem_0.actBackEnergy 6303630
262system.physmem_0.preBackEnergy 322080
263system.physmem_0.actPowerDownEnergy 38492100
264system.physmem_0.prePowerDownEnergy 7873440
265system.physmem_0.selfRefreshEnergy 2219340
266system.physmem_0.totalEnergy 69103680
267system.physmem_0.averagePower 546.166212
268system.physmem_0.totalIdleTime 111290750
269system.physmem_0.memoryStateTime::IDLE 364500
270system.physmem_0.memoryStateTime::REF 4166000
271system.physmem_0.memoryStateTime::SREF 6945750
272system.physmem_0.memoryStateTime::PRE_PDN 20504750
273system.physmem_0.memoryStateTime::ACT 10132500
274system.physmem_0.memoryStateTime::ACT_PDN 84410500
275system.physmem_1.actEnergy 478380
276system.physmem_1.preEnergy 231495
277system.physmem_1.readEnergy 2213400
278system.physmem_1.writeEnergy 0
279system.physmem_1.refreshEnergy 11063520.000000
280system.physmem_1.actBackEnergy 5380230
281system.physmem_1.preBackEnergy 811200
282system.physmem_1.actPowerDownEnergy 30383280
283system.physmem_1.prePowerDownEnergy 13088160
284system.physmem_1.selfRefreshEnergy 5064960
285system.physmem_1.totalEnergy 68714625
286system.physmem_1.averagePower 543.091286
287system.physmem_1.totalIdleTime 112417500
288system.physmem_1.memoryStateTime::IDLE 1635500
289system.physmem_1.memoryStateTime::REF 4704000
290system.physmem_1.memoryStateTime::SREF 11899500
291system.physmem_1.memoryStateTime::PRE_PDN 34081750
292system.physmem_1.memoryStateTime::ACT 7573250
293system.physmem_1.memoryStateTime::ACT_PDN 66630000
294system.pwrStateResidencyTicks::UNDEFINED 126524000
295system.cpu0.branchPred.lookups 99156
296system.cpu0.branchPred.condPredicted 94556
297system.cpu0.branchPred.condIncorrect 1594
298system.cpu0.branchPred.BTBLookups 96162
299system.cpu0.branchPred.BTBHits 0
300system.cpu0.branchPred.BTBCorrect 0
301system.cpu0.branchPred.BTBHitPct 0.000000
302system.cpu0.branchPred.usedRAS 1175
303system.cpu0.branchPred.RASInCorrect 128
304system.cpu0.branchPred.indirectLookups 96162
305system.cpu0.branchPred.indirectHits 88867
306system.cpu0.branchPred.indirectMisses 7295
307system.cpu0.branchPredindirectMispredicted 1040
308system.cpu_clk_domain.clock 500
309system.cpu0.workload.numSyscalls 26
310system.cpu0.pwrStateResidencyTicks::ON 126524000
311system.cpu0.numCycles 253049
312system.cpu0.numWorkItemsStarted 0
313system.cpu0.numWorkItemsCompleted 0
314system.cpu0.fetch.icacheStallCycles 23270
315system.cpu0.fetch.Insts 585438
316system.cpu0.fetch.Branches 99156
317system.cpu0.fetch.predictedBranches 90042
318system.cpu0.fetch.Cycles 194902
319system.cpu0.fetch.SquashCycles 3487
320system.cpu0.fetch.MiscStallCycles 9
321system.cpu0.fetch.PendingTrapStallCycles 2371
322system.cpu0.fetch.IcacheWaitRetryStallCycles 8
323system.cpu0.fetch.CacheLines 8150
324system.cpu0.fetch.IcacheSquashes 854
325system.cpu0.fetch.rateDist::samples 222303
326system.cpu0.fetch.rateDist::mean 2.633514
327system.cpu0.fetch.rateDist::stdev 2.266765
328system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00%
329system.cpu0.fetch.rateDist::0 34223 15.39% 15.39%
330system.cpu0.fetch.rateDist::1 91924 41.35% 56.75%
331system.cpu0.fetch.rateDist::2 702 0.32% 57.06%
332system.cpu0.fetch.rateDist::3 1052 0.47% 57.53%
333system.cpu0.fetch.rateDist::4 464 0.21% 57.74%
334system.cpu0.fetch.rateDist::5 87528 39.37% 97.12%
335system.cpu0.fetch.rateDist::6 631 0.28% 97.40%
336system.cpu0.fetch.rateDist::7 560 0.25% 97.65%
337system.cpu0.fetch.rateDist::8 5219 2.35% 100.00%
338system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00%
339system.cpu0.fetch.rateDist::min_value 0
340system.cpu0.fetch.rateDist::max_value 8
341system.cpu0.fetch.rateDist::total 222303
342system.cpu0.fetch.branchRate 0.391845
343system.cpu0.fetch.rate 2.313536
344system.cpu0.decode.IdleCycles 17878
345system.cpu0.decode.BlockedCycles 19403
346system.cpu0.decode.RunCycles 182453
347system.cpu0.decode.UnblockCycles 826
348system.cpu0.decode.SquashCycles 1743
349system.cpu0.decode.DecodedInsts 566849
350system.cpu0.rename.SquashCycles 1743
351system.cpu0.rename.IdleCycles 18557
352system.cpu0.rename.BlockCycles 1896
353system.cpu0.rename.serializeStallCycles 16116
354system.cpu0.rename.RunCycles 182592
355system.cpu0.rename.UnblockCycles 1399
356system.cpu0.rename.RenamedInsts 561565
357system.cpu0.rename.IQFullEvents 11
358system.cpu0.rename.LQFullEvents 11
359system.cpu0.rename.SQFullEvents 925
360system.cpu0.rename.RenamedOperands 384271
361system.cpu0.rename.RenameLookups 1119475
362system.cpu0.rename.int_rename_lookups 845599
363system.cpu0.rename.CommittedMaps 365219
364system.cpu0.rename.UndoneMaps 19052
365system.cpu0.rename.serializingInsts 1117
366system.cpu0.rename.tempSerializingInsts 1148
367system.cpu0.rename.skidInsts 5501
368system.cpu0.memDep0.insertedLoads 179238
369system.cpu0.memDep0.insertedStores 90554
370system.cpu0.memDep0.conflictingLoads 87434
371system.cpu0.memDep0.conflictingStores 87111
372system.cpu0.iq.iqInstsAdded 468496
373system.cpu0.iq.iqNonSpecInstsAdded 1145
374system.cpu0.iq.iqInstsIssued 464441
375system.cpu0.iq.iqSquashedInstsIssued 106
376system.cpu0.iq.iqSquashedInstsExamined 16686
377system.cpu0.iq.iqSquashedOperandsExamined 13469
378system.cpu0.iq.iqSquashedNonSpecRemoved 586
379system.cpu0.iq.issued_per_cycle::samples 222303
380system.cpu0.iq.issued_per_cycle::mean 2.089225
381system.cpu0.iq.issued_per_cycle::stdev 1.109552
382system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00%
383system.cpu0.iq.issued_per_cycle::0 37150 16.71% 16.71%
384system.cpu0.iq.issued_per_cycle::1 4499 2.02% 18.74%
385system.cpu0.iq.issued_per_cycle::2 88751 39.92% 58.66%
386system.cpu0.iq.issued_per_cycle::3 88374 39.75% 98.41%
387system.cpu0.iq.issued_per_cycle::4 1681 0.76% 99.17%
388system.cpu0.iq.issued_per_cycle::5 953 0.43% 99.60%
389system.cpu0.iq.issued_per_cycle::6 547 0.25% 99.84%
390system.cpu0.iq.issued_per_cycle::7 237 0.11% 99.95%
391system.cpu0.iq.issued_per_cycle::8 111 0.05% 100.00%
392system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00%
393system.cpu0.iq.issued_per_cycle::min_value 0
394system.cpu0.iq.issued_per_cycle::max_value 8
395system.cpu0.iq.issued_per_cycle::total 222303
396system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00%
397system.cpu0.iq.fu_full::IntAlu 131 39.34% 39.34%
398system.cpu0.iq.fu_full::IntMult 0 0.00% 39.34%
399system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.34%
400system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.34%
401system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.34%
402system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.34%
403system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.34%
404system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 39.34%
405system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.34%
406system.cpu0.iq.fu_full::FloatMisc 0 0.00% 39.34%
407system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.34%
408system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.34%
409system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.34%
410system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.34%
411system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.34%
412system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.34%
413system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.34%
414system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.34%
415system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.34%
416system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.34%
417system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.34%
418system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.34%
419system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.34%
420system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.34%
421system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.34%
422system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.34%
423system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.34%
424system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.34%
425system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.34%
426system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.34%
427system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.34%
428system.cpu0.iq.fu_full::MemRead 78 23.42% 62.76%
429system.cpu0.iq.fu_full::MemWrite 124 37.24% 100.00%
430system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00%
431system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00%
432system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00%
433system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00%
434system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
435system.cpu0.iq.FU_type_0::IntAlu 196072 42.22% 42.22%
436system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22%
437system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22%
438system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22%
439system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22%
440system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22%
441system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22%
442system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.22%
443system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22%
444system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.22%
445system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22%
446system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22%
447system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22%
448system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22%
449system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22%
450system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22%
451system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22%
452system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22%
453system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22%
454system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22%
455system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22%
456system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22%
457system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22%
458system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22%
459system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22%
460system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22%
461system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22%
462system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22%
463system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22%
464system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22%
465system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22%
466system.cpu0.iq.FU_type_0::MemRead 178607 38.46% 80.67%
467system.cpu0.iq.FU_type_0::MemWrite 89762 19.33% 100.00%
468system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00%
469system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00%
470system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00%
471system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
472system.cpu0.iq.FU_type_0::total 464441
473system.cpu0.iq.rate 1.835380
474system.cpu0.iq.fu_busy_cnt 333
475system.cpu0.iq.fu_busy_rate 0.000717
476system.cpu0.iq.int_inst_queue_reads 1151624
477system.cpu0.iq.int_inst_queue_writes 486379
478system.cpu0.iq.int_inst_queue_wakeup_accesses 461879
479system.cpu0.iq.fp_inst_queue_reads 0
480system.cpu0.iq.fp_inst_queue_writes 0
481system.cpu0.iq.fp_inst_queue_wakeup_accesses 0
482system.cpu0.iq.int_alu_accesses 464774
483system.cpu0.iq.fp_alu_accesses 0
484system.cpu0.iew.lsq.thread0.forwLoads 86836
485system.cpu0.iew.lsq.thread0.invAddrLoads 0
486system.cpu0.iew.lsq.thread0.squashedLoads 3039
487system.cpu0.iew.lsq.thread0.ignoredResponses 10
488system.cpu0.iew.lsq.thread0.memOrderViolation 54
489system.cpu0.iew.lsq.thread0.squashedStores 1948
490system.cpu0.iew.lsq.thread0.invAddrSwpfs 0
491system.cpu0.iew.lsq.thread0.blockedLoads 0
492system.cpu0.iew.lsq.thread0.rescheduledLoads 0
493system.cpu0.iew.lsq.thread0.cacheBlocked 12
494system.cpu0.iew.iewIdleCycles 0
495system.cpu0.iew.iewSquashCycles 1743
496system.cpu0.iew.iewBlockCycles 1896
497system.cpu0.iew.iewUnblockCycles 25
498system.cpu0.iew.iewDispatchedInsts 557675
499system.cpu0.iew.iewDispSquashedInsts 154
500system.cpu0.iew.iewDispLoadInsts 179238
501system.cpu0.iew.iewDispStoreInsts 90554
502system.cpu0.iew.iewDispNonSpecInsts 1020
503system.cpu0.iew.iewIQFullEvents 25
504system.cpu0.iew.iewLSQFullEvents 0
505system.cpu0.iew.memOrderViolationEvents 54
506system.cpu0.iew.predictedTakenIncorrect 223
507system.cpu0.iew.predictedNotTakenIncorrect 1713
508system.cpu0.iew.branchMispredicts 1936
509system.cpu0.iew.iewExecutedInsts 462987
510system.cpu0.iew.iewExecLoadInsts 178230
511system.cpu0.iew.iewExecSquashedInsts 1454
512system.cpu0.iew.exec_swp 0
513system.cpu0.iew.exec_nop 88034
514system.cpu0.iew.exec_refs 267793
515system.cpu0.iew.exec_branches 91939
516system.cpu0.iew.exec_stores 89563
517system.cpu0.iew.exec_rate 1.829634
518system.cpu0.iew.wb_sent 462340
519system.cpu0.iew.wb_count 461879
520system.cpu0.iew.wb_producers 273734
521system.cpu0.iew.wb_consumers 277281
522system.cpu0.iew.wb_rate 1.825255
523system.cpu0.iew.wb_fanout 0.987208
524system.cpu0.commit.commitSquashedInsts 17412
525system.cpu0.commit.commitNonSpecStalls 559
526system.cpu0.commit.branchMispredicts 1594
527system.cpu0.commit.committed_per_cycle::samples 218890
528system.cpu0.commit.committed_per_cycle::mean 2.467815
529system.cpu0.commit.committed_per_cycle::stdev 2.142481
530system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00%
531system.cpu0.commit.committed_per_cycle::0 37135 16.97% 16.97%
532system.cpu0.commit.committed_per_cycle::1 90773 41.47% 58.43%
533system.cpu0.commit.committed_per_cycle::2 2099 0.96% 59.39%
534system.cpu0.commit.committed_per_cycle::3 598 0.27% 59.67%
535system.cpu0.commit.committed_per_cycle::4 457 0.21% 59.88%
536system.cpu0.commit.committed_per_cycle::5 86592 39.56% 99.44%
537system.cpu0.commit.committed_per_cycle::6 481 0.22% 99.66%
538system.cpu0.commit.committed_per_cycle::7 299 0.14% 99.79%
539system.cpu0.commit.committed_per_cycle::8 456 0.21% 100.00%
540system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00%
541system.cpu0.commit.committed_per_cycle::min_value 0
542system.cpu0.commit.committed_per_cycle::max_value 8
543system.cpu0.commit.committed_per_cycle::total 218890
544system.cpu0.commit.committedInsts 540180
545system.cpu0.commit.committedOps 540180
546system.cpu0.commit.swp_count 0
547system.cpu0.commit.refs 264805
548system.cpu0.commit.loads 176199
549system.cpu0.commit.membars 84
550system.cpu0.commit.branches 90493
551system.cpu0.commit.fp_insts 0
552system.cpu0.commit.int_insts 363550
553system.cpu0.commit.function_calls 223
554system.cpu0.commit.op_class_0::No_OpClass 87225 16.15% 16.15%
555system.cpu0.commit.op_class_0::IntAlu 188066 34.82% 50.96%
556system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96%
557system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96%
558system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96%
559system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96%
560system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96%
561system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96%
562system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96%
563system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96%
564system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96%
565system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96%
566system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96%
567system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96%
568system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96%
569system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96%
570system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96%
571system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96%
572system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96%
573system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96%
574system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96%
575system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96%
576system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96%
577system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96%
578system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96%
579system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96%
580system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96%
581system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96%
582system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96%
583system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96%
584system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96%
585system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96%
586system.cpu0.commit.op_class_0::MemRead 176283 32.63% 83.60%
587system.cpu0.commit.op_class_0::MemWrite 88606 16.40% 100.00%
588system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00%
589system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00%
590system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00%
591system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
592system.cpu0.commit.op_class_0::total 540180
593system.cpu0.commit.bw_lim_events 456
594system.cpu0.rob.rob_reads 774865
595system.cpu0.rob.rob_writes 1118644
596system.cpu0.timesIdled 329
597system.cpu0.idleCycles 30746
598system.cpu0.committedInsts 452871
599system.cpu0.committedOps 452871
600system.cpu0.cpi 0.558766
601system.cpu0.cpi_total 0.558766
602system.cpu0.ipc 1.789657
603system.cpu0.ipc_total 1.789657
604system.cpu0.int_regfile_reads 827809
605system.cpu0.int_regfile_writes 373052
606system.cpu0.fp_regfile_reads 192
607system.cpu0.misc_regfile_reads 269916
608system.cpu0.misc_regfile_writes 564
609system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
610system.cpu0.dcache.tags.replacements 2
611system.cpu0.dcache.tags.tagsinuse 142.437972
612system.cpu0.dcache.tags.total_refs 178652
613system.cpu0.dcache.tags.sampled_refs 171
614system.cpu0.dcache.tags.avg_refs 1044.748538
615system.cpu0.dcache.tags.warmup_cycle 0
616system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.437972
617system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278199
618system.cpu0.dcache.tags.occ_percent::total 0.278199
619system.cpu0.dcache.tags.occ_task_id_blocks::1024 169
620system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18
621system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8
622system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143
623system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078
624system.cpu0.dcache.tags.tag_accesses 719933
625system.cpu0.dcache.tags.data_accesses 719933
626system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 126524000
627system.cpu0.dcache.ReadReq_hits::cpu0.data 90725
628system.cpu0.dcache.ReadReq_hits::total 90725
629system.cpu0.dcache.WriteReq_hits::cpu0.data 88017
630system.cpu0.dcache.WriteReq_hits::total 88017
631system.cpu0.dcache.SwapReq_hits::cpu0.data 17
632system.cpu0.dcache.SwapReq_hits::total 17
633system.cpu0.dcache.demand_hits::cpu0.data 178742
634system.cpu0.dcache.demand_hits::total 178742
635system.cpu0.dcache.overall_hits::cpu0.data 178742
636system.cpu0.dcache.overall_hits::total 178742
637system.cpu0.dcache.ReadReq_misses::cpu0.data 571
638system.cpu0.dcache.ReadReq_misses::total 571
639system.cpu0.dcache.WriteReq_misses::cpu0.data 547
640system.cpu0.dcache.WriteReq_misses::total 547
641system.cpu0.dcache.SwapReq_misses::cpu0.data 25
642system.cpu0.dcache.SwapReq_misses::total 25
643system.cpu0.dcache.demand_misses::cpu0.data 1118
644system.cpu0.dcache.demand_misses::total 1118
645system.cpu0.dcache.overall_misses::cpu0.data 1118
646system.cpu0.dcache.overall_misses::total 1118
647system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15765500
648system.cpu0.dcache.ReadReq_miss_latency::total 15765500
649system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35483989
650system.cpu0.dcache.WriteReq_miss_latency::total 35483989
651system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 519500
652system.cpu0.dcache.SwapReq_miss_latency::total 519500
653system.cpu0.dcache.demand_miss_latency::cpu0.data 51249489
654system.cpu0.dcache.demand_miss_latency::total 51249489
655system.cpu0.dcache.overall_miss_latency::cpu0.data 51249489
656system.cpu0.dcache.overall_miss_latency::total 51249489
657system.cpu0.dcache.ReadReq_accesses::cpu0.data 91296
658system.cpu0.dcache.ReadReq_accesses::total 91296
659system.cpu0.dcache.WriteReq_accesses::cpu0.data 88564
660system.cpu0.dcache.WriteReq_accesses::total 88564
661system.cpu0.dcache.SwapReq_accesses::cpu0.data 42
662system.cpu0.dcache.SwapReq_accesses::total 42
663system.cpu0.dcache.demand_accesses::cpu0.data 179860
664system.cpu0.dcache.demand_accesses::total 179860
665system.cpu0.dcache.overall_accesses::cpu0.data 179860
666system.cpu0.dcache.overall_accesses::total 179860
667system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006254
668system.cpu0.dcache.ReadReq_miss_rate::total 0.006254
669system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006176
670system.cpu0.dcache.WriteReq_miss_rate::total 0.006176
671system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238
672system.cpu0.dcache.SwapReq_miss_rate::total 0.595238
673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006216
674system.cpu0.dcache.demand_miss_rate::total 0.006216
675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006216
676system.cpu0.dcache.overall_miss_rate::total 0.006216
677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27610.332750
678system.cpu0.dcache.ReadReq_avg_miss_latency::total 27610.332750
679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64870.180987
680system.cpu0.dcache.WriteReq_avg_miss_latency::total 64870.180987
681system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20780
682system.cpu0.dcache.SwapReq_avg_miss_latency::total 20780
683system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45840.330054
684system.cpu0.dcache.demand_avg_miss_latency::total 45840.330054
685system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45840.330054
686system.cpu0.dcache.overall_avg_miss_latency::total 45840.330054
687system.cpu0.dcache.blocked_cycles::no_mshrs 885
688system.cpu0.dcache.blocked_cycles::no_targets 0
689system.cpu0.dcache.blocked::no_mshrs 21
690system.cpu0.dcache.blocked::no_targets 0
691system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857
692system.cpu0.dcache.avg_blocked_cycles::no_targets nan
693system.cpu0.dcache.writebacks::writebacks 1
694system.cpu0.dcache.writebacks::total 1
695system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 371
696system.cpu0.dcache.ReadReq_mshr_hits::total 371
697system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380
698system.cpu0.dcache.WriteReq_mshr_hits::total 380
699system.cpu0.dcache.demand_mshr_hits::cpu0.data 751
700system.cpu0.dcache.demand_mshr_hits::total 751
701system.cpu0.dcache.overall_mshr_hits::cpu0.data 751
702system.cpu0.dcache.overall_mshr_hits::total 751
703system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 200
704system.cpu0.dcache.ReadReq_mshr_misses::total 200
705system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167
706system.cpu0.dcache.WriteReq_mshr_misses::total 167
707system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25
708system.cpu0.dcache.SwapReq_mshr_misses::total 25
709system.cpu0.dcache.demand_mshr_misses::cpu0.data 367
710system.cpu0.dcache.demand_mshr_misses::total 367
711system.cpu0.dcache.overall_mshr_misses::cpu0.data 367
712system.cpu0.dcache.overall_mshr_misses::total 367
713system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7360500
714system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7360500
715system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8143000
716system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8143000
717system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 494500
718system.cpu0.dcache.SwapReq_mshr_miss_latency::total 494500
719system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15503500
720system.cpu0.dcache.demand_mshr_miss_latency::total 15503500
721system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15503500
722system.cpu0.dcache.overall_mshr_miss_latency::total 15503500
723system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002191
724system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002191
725system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001886
726system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001886
727system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238
728system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238
729system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002040
730system.cpu0.dcache.demand_mshr_miss_rate::total 0.002040
731system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002040
732system.cpu0.dcache.overall_mshr_miss_rate::total 0.002040
733system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36802.500000
734system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36802.500000
735system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48760.479042
736system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48760.479042
737system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 19780
738system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 19780
739system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42243.869210
740system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42243.869210
741system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42243.869210
742system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42243.869210
743system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
744system.cpu0.icache.tags.replacements 389
745system.cpu0.icache.tags.tagsinuse 247.660025
746system.cpu0.icache.tags.total_refs 7239
747system.cpu0.icache.tags.sampled_refs 689
748system.cpu0.icache.tags.avg_refs 10.506531
749system.cpu0.icache.tags.warmup_cycle 0
750system.cpu0.icache.tags.occ_blocks::cpu0.inst 247.660025
751system.cpu0.icache.tags.occ_percent::cpu0.inst 0.483711
752system.cpu0.icache.tags.occ_percent::total 0.483711
753system.cpu0.icache.tags.occ_task_id_blocks::1024 300
754system.cpu0.icache.tags.age_task_id_blocks_1024::0 67
755system.cpu0.icache.tags.age_task_id_blocks_1024::1 40
756system.cpu0.icache.tags.age_task_id_blocks_1024::2 193
757system.cpu0.icache.tags.occ_task_id_percent::1024 0.585938
758system.cpu0.icache.tags.tag_accesses 8839
759system.cpu0.icache.tags.data_accesses 8839
760system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 126524000
761system.cpu0.icache.ReadReq_hits::cpu0.inst 7239
762system.cpu0.icache.ReadReq_hits::total 7239
763system.cpu0.icache.demand_hits::cpu0.inst 7239
764system.cpu0.icache.demand_hits::total 7239
765system.cpu0.icache.overall_hits::cpu0.inst 7239
766system.cpu0.icache.overall_hits::total 7239
767system.cpu0.icache.ReadReq_misses::cpu0.inst 911
768system.cpu0.icache.ReadReq_misses::total 911
769system.cpu0.icache.demand_misses::cpu0.inst 911
770system.cpu0.icache.demand_misses::total 911
771system.cpu0.icache.overall_misses::cpu0.inst 911
772system.cpu0.icache.overall_misses::total 911
773system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 46831000
774system.cpu0.icache.ReadReq_miss_latency::total 46831000
775system.cpu0.icache.demand_miss_latency::cpu0.inst 46831000
776system.cpu0.icache.demand_miss_latency::total 46831000
777system.cpu0.icache.overall_miss_latency::cpu0.inst 46831000
778system.cpu0.icache.overall_miss_latency::total 46831000
779system.cpu0.icache.ReadReq_accesses::cpu0.inst 8150
780system.cpu0.icache.ReadReq_accesses::total 8150
781system.cpu0.icache.demand_accesses::cpu0.inst 8150
782system.cpu0.icache.demand_accesses::total 8150
783system.cpu0.icache.overall_accesses::cpu0.inst 8150
784system.cpu0.icache.overall_accesses::total 8150
785system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111779
786system.cpu0.icache.ReadReq_miss_rate::total 0.111779
787system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111779
788system.cpu0.icache.demand_miss_rate::total 0.111779
789system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111779
790system.cpu0.icache.overall_miss_rate::total 0.111779
791system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51406.147091
792system.cpu0.icache.ReadReq_avg_miss_latency::total 51406.147091
793system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51406.147091
794system.cpu0.icache.demand_avg_miss_latency::total 51406.147091
795system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51406.147091
796system.cpu0.icache.overall_avg_miss_latency::total 51406.147091
797system.cpu0.icache.blocked_cycles::no_mshrs 84
798system.cpu0.icache.blocked_cycles::no_targets 0
799system.cpu0.icache.blocked::no_mshrs 3
800system.cpu0.icache.blocked::no_targets 0
801system.cpu0.icache.avg_blocked_cycles::no_mshrs 28
802system.cpu0.icache.avg_blocked_cycles::no_targets nan
803system.cpu0.icache.writebacks::writebacks 389
804system.cpu0.icache.writebacks::total 389
805system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221
806system.cpu0.icache.ReadReq_mshr_hits::total 221
807system.cpu0.icache.demand_mshr_hits::cpu0.inst 221
808system.cpu0.icache.demand_mshr_hits::total 221
809system.cpu0.icache.overall_mshr_hits::cpu0.inst 221
810system.cpu0.icache.overall_mshr_hits::total 221
811system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 690
812system.cpu0.icache.ReadReq_mshr_misses::total 690
813system.cpu0.icache.demand_mshr_misses::cpu0.inst 690
814system.cpu0.icache.demand_mshr_misses::total 690
815system.cpu0.icache.overall_mshr_misses::cpu0.inst 690
816system.cpu0.icache.overall_mshr_misses::total 690
817system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 35682500
818system.cpu0.icache.ReadReq_mshr_miss_latency::total 35682500
819system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 35682500
820system.cpu0.icache.demand_mshr_miss_latency::total 35682500
821system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 35682500
822system.cpu0.icache.overall_mshr_miss_latency::total 35682500
823system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084663
824system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084663
825system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084663
826system.cpu0.icache.demand_mshr_miss_rate::total 0.084663
827system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084663
828system.cpu0.icache.overall_mshr_miss_rate::total 0.084663
829system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51713.768116
830system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51713.768116
831system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51713.768116
832system.cpu0.icache.demand_avg_mshr_miss_latency::total 51713.768116
833system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51713.768116
834system.cpu0.icache.overall_avg_mshr_miss_latency::total 51713.768116
835system.cpu1.branchPred.lookups 63294
836system.cpu1.branchPred.condPredicted 55557
837system.cpu1.branchPred.condIncorrect 2283
838system.cpu1.branchPred.BTBLookups 55348
839system.cpu1.branchPred.BTBHits 0
840system.cpu1.branchPred.BTBCorrect 0
841system.cpu1.branchPred.BTBHitPct 0.000000
842system.cpu1.branchPred.usedRAS 1956
843system.cpu1.branchPred.RASInCorrect 231
844system.cpu1.branchPred.indirectLookups 55348
845system.cpu1.branchPred.indirectHits 45091
846system.cpu1.branchPred.indirectMisses 10257
847system.cpu1.branchPredindirectMispredicted 1210
848system.cpu1.pwrStateResidencyTicks::ON 126524000
849system.cpu1.numCycles 193951
850system.cpu1.numWorkItemsStarted 0
851system.cpu1.numWorkItemsCompleted 0
852system.cpu1.fetch.icacheStallCycles 40389
853system.cpu1.fetch.Insts 341951
854system.cpu1.fetch.Branches 63294
855system.cpu1.fetch.predictedBranches 47047
856system.cpu1.fetch.Cycles 142781
857system.cpu1.fetch.SquashCycles 4723
858system.cpu1.fetch.MiscStallCycles 6
859system.cpu1.fetch.NoActiveThreadStallCycles 10
860system.cpu1.fetch.PendingTrapStallCycles 1381
861system.cpu1.fetch.IcacheWaitRetryStallCycles 38
862system.cpu1.fetch.CacheLines 28562
863system.cpu1.fetch.IcacheSquashes 991
864system.cpu1.fetch.rateDist::samples 186966
865system.cpu1.fetch.rateDist::mean 1.828948
866system.cpu1.fetch.rateDist::stdev 2.328595
867system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00%
868system.cpu1.fetch.rateDist::0 72547 38.80% 38.80%
869system.cpu1.fetch.rateDist::1 56594 30.27% 69.07%
870system.cpu1.fetch.rateDist::2 8597 4.60% 73.67%
871system.cpu1.fetch.rateDist::3 3330 1.78% 75.45%
872system.cpu1.fetch.rateDist::4 695 0.37% 75.82%
873system.cpu1.fetch.rateDist::5 34236 18.31% 94.13%
874system.cpu1.fetch.rateDist::6 1093 0.58% 94.72%
875system.cpu1.fetch.rateDist::7 1337 0.72% 95.43%
876system.cpu1.fetch.rateDist::8 8537 4.57% 100.00%
877system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00%
878system.cpu1.fetch.rateDist::min_value 0
879system.cpu1.fetch.rateDist::max_value 8
880system.cpu1.fetch.rateDist::total 186966
881system.cpu1.fetch.branchRate 0.326340
882system.cpu1.fetch.rate 1.763079
883system.cpu1.decode.IdleCycles 22891
884system.cpu1.decode.BlockedCycles 71776
885system.cpu1.decode.RunCycles 85305
886system.cpu1.decode.UnblockCycles 4623
887system.cpu1.decode.SquashCycles 2361
888system.cpu1.decode.DecodedInsts 310456
889system.cpu1.rename.SquashCycles 2361
890system.cpu1.rename.IdleCycles 23853
891system.cpu1.rename.BlockCycles 35144
892system.cpu1.rename.serializeStallCycles 13312
893system.cpu1.rename.RunCycles 86491
894system.cpu1.rename.UnblockCycles 25795
895system.cpu1.rename.RenamedInsts 304191
896system.cpu1.rename.IQFullEvents 22567
897system.cpu1.rename.LQFullEvents 13
898system.cpu1.rename.FullRegisterEvents 3
899system.cpu1.rename.RenamedOperands 212285
900system.cpu1.rename.RenameLookups 574883
901system.cpu1.rename.int_rename_lookups 448400
902system.cpu1.rename.fp_rename_lookups 44
903system.cpu1.rename.CommittedMaps 185221
904system.cpu1.rename.UndoneMaps 27064
905system.cpu1.rename.serializingInsts 1647
906system.cpu1.rename.tempSerializingInsts 1783
907system.cpu1.rename.skidInsts 31202
908system.cpu1.memDep0.insertedLoads 82743
909system.cpu1.memDep0.insertedStores 38627
910system.cpu1.memDep0.conflictingLoads 39639
911system.cpu1.memDep0.conflictingStores 32322
912system.cpu1.iq.iqInstsAdded 247154
913system.cpu1.iq.iqNonSpecInstsAdded 8855
914system.cpu1.iq.iqInstsIssued 248497
915system.cpu1.iq.iqSquashedInstsIssued 91
916system.cpu1.iq.iqSquashedInstsExamined 23477
917system.cpu1.iq.iqSquashedOperandsExamined 18537
918system.cpu1.iq.iqSquashedNonSpecRemoved 1202
919system.cpu1.iq.issued_per_cycle::samples 186966
920system.cpu1.iq.issued_per_cycle::mean 1.329103
921system.cpu1.iq.issued_per_cycle::stdev 1.385649
922system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00%
923system.cpu1.iq.issued_per_cycle::0 77442 41.42% 41.42%
924system.cpu1.iq.issued_per_cycle::1 28211 15.09% 56.51%
925system.cpu1.iq.issued_per_cycle::2 37135 19.86% 76.37%
926system.cpu1.iq.issued_per_cycle::3 36997 19.79% 96.16%
927system.cpu1.iq.issued_per_cycle::4 3585 1.92% 98.08%
928system.cpu1.iq.issued_per_cycle::5 1867 1.00% 99.08%
929system.cpu1.iq.issued_per_cycle::6 1035 0.55% 99.63%
930system.cpu1.iq.issued_per_cycle::7 412 0.22% 99.85%
931system.cpu1.iq.issued_per_cycle::8 282 0.15% 100.00%
932system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00%
933system.cpu1.iq.issued_per_cycle::min_value 0
934system.cpu1.iq.issued_per_cycle::max_value 8
935system.cpu1.iq.issued_per_cycle::total 186966
936system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00%
937system.cpu1.iq.fu_full::IntAlu 182 38.56% 38.56%
938system.cpu1.iq.fu_full::IntMult 0 0.00% 38.56%
939system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.56%
940system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.56%
941system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.56%
942system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.56%
943system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.56%
944system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 38.56%
945system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.56%
946system.cpu1.iq.fu_full::FloatMisc 0 0.00% 38.56%
947system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.56%
948system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.56%
949system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.56%
950system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.56%
951system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.56%
952system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.56%
953system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.56%
954system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.56%
955system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.56%
956system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.56%
957system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.56%
958system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.56%
959system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.56%
960system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.56%
961system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.56%
962system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.56%
963system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.56%
964system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.56%
965system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.56%
966system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56%
967system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56%
968system.cpu1.iq.fu_full::MemRead 56 11.86% 50.42%
969system.cpu1.iq.fu_full::MemWrite 234 49.58% 100.00%
970system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00%
971system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00%
972system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00%
973system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00%
974system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
975system.cpu1.iq.FU_type_0::IntAlu 122183 49.17% 49.17%
976system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.17%
977system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.17%
978system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.17%
979system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.17%
980system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.17%
981system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.17%
982system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 49.17%
983system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.17%
984system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 49.17%
985system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.17%
986system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.17%
987system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.17%
988system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.17%
989system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.17%
990system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.17%
991system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.17%
992system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.17%
993system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.17%
994system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.17%
995system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.17%
996system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.17%
997system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.17%
998system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.17%
999system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.17%
1000system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.17%
1001system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.17%
1002system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.17%
1003system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.17%
1004system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.17%
1005system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.17%
1006system.cpu1.iq.FU_type_0::MemRead 88669 35.68% 84.85%
1007system.cpu1.iq.FU_type_0::MemWrite 37645 15.15% 100.00%
1008system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00%
1009system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00%
1010system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00%
1011system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
1012system.cpu1.iq.FU_type_0::total 248497
1013system.cpu1.iq.rate 1.281236
1014system.cpu1.iq.fu_busy_cnt 472
1015system.cpu1.iq.fu_busy_rate 0.001899
1016system.cpu1.iq.int_inst_queue_reads 684523
1017system.cpu1.iq.int_inst_queue_writes 279437
1018system.cpu1.iq.int_inst_queue_wakeup_accesses 244623
1019system.cpu1.iq.fp_inst_queue_reads 0
1020system.cpu1.iq.fp_inst_queue_writes 88
1021system.cpu1.iq.fp_inst_queue_wakeup_accesses 0
1022system.cpu1.iq.int_alu_accesses 248969
1023system.cpu1.iq.fp_alu_accesses 0
1024system.cpu1.iew.lsq.thread0.forwLoads 32276
1025system.cpu1.iew.lsq.thread0.invAddrLoads 0
1026system.cpu1.iew.lsq.thread0.squashedLoads 4218
1027system.cpu1.iew.lsq.thread0.ignoredResponses 48
1028system.cpu1.iew.lsq.thread0.memOrderViolation 39
1029system.cpu1.iew.lsq.thread0.squashedStores 2578
1030system.cpu1.iew.lsq.thread0.invAddrSwpfs 0
1031system.cpu1.iew.lsq.thread0.blockedLoads 0
1032system.cpu1.iew.lsq.thread0.rescheduledLoads 0
1033system.cpu1.iew.lsq.thread0.cacheBlocked 0
1034system.cpu1.iew.iewIdleCycles 0
1035system.cpu1.iew.iewSquashCycles 2361
1036system.cpu1.iew.iewBlockCycles 9309
1037system.cpu1.iew.iewUnblockCycles 53
1038system.cpu1.iew.iewDispatchedInsts 296855
1039system.cpu1.iew.iewDispSquashedInsts 287
1040system.cpu1.iew.iewDispLoadInsts 82743
1041system.cpu1.iew.iewDispStoreInsts 38627
1042system.cpu1.iew.iewDispNonSpecInsts 1515
1043system.cpu1.iew.iewIQFullEvents 28
1044system.cpu1.iew.iewLSQFullEvents 0
1045system.cpu1.iew.memOrderViolationEvents 39
1046system.cpu1.iew.predictedTakenIncorrect 446
1047system.cpu1.iew.predictedNotTakenIncorrect 2413
1048system.cpu1.iew.branchMispredicts 2859
1049system.cpu1.iew.iewExecutedInsts 245962
1050system.cpu1.iew.iewExecLoadInsts 81205
1051system.cpu1.iew.iewExecSquashedInsts 2535
1052system.cpu1.iew.exec_swp 0
1053system.cpu1.iew.exec_nop 40846
1054system.cpu1.iew.exec_refs 118541
1055system.cpu1.iew.exec_branches 51063
1056system.cpu1.iew.exec_stores 37336
1057system.cpu1.iew.exec_rate 1.268166
1058system.cpu1.iew.wb_sent 245120
1059system.cpu1.iew.wb_count 244623
1060system.cpu1.iew.wb_producers 136387
1061system.cpu1.iew.wb_consumers 143829
1062system.cpu1.iew.wb_rate 1.261262
1063system.cpu1.iew.wb_fanout 0.948258
1064system.cpu1.commit.commitSquashedInsts 24565
1065system.cpu1.commit.commitNonSpecStalls 7653
1066system.cpu1.commit.branchMispredicts 2283
1067system.cpu1.commit.committed_per_cycle::samples 182310
1068system.cpu1.commit.committed_per_cycle::mean 1.493451
1069system.cpu1.commit.committed_per_cycle::stdev 1.997873
1070system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00%
1071system.cpu1.commit.committed_per_cycle::0 84529 46.37% 46.37%
1072system.cpu1.commit.committed_per_cycle::1 47318 25.95% 72.32%
1073system.cpu1.commit.committed_per_cycle::2 5367 2.94% 75.26%
1074system.cpu1.commit.committed_per_cycle::3 8292 4.55% 79.81%
1075system.cpu1.commit.committed_per_cycle::4 1281 0.70% 80.52%
1076system.cpu1.commit.committed_per_cycle::5 32483 17.82% 98.33%
1077system.cpu1.commit.committed_per_cycle::6 752 0.41% 98.74%
1078system.cpu1.commit.committed_per_cycle::7 1012 0.56% 99.30%
1079system.cpu1.commit.committed_per_cycle::8 1276 0.70% 100.00%
1080system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00%
1081system.cpu1.commit.committed_per_cycle::min_value 0
1082system.cpu1.commit.committed_per_cycle::max_value 8
1083system.cpu1.commit.committed_per_cycle::total 182310
1084system.cpu1.commit.committedInsts 272271
1085system.cpu1.commit.committedOps 272271
1086system.cpu1.commit.swp_count 0
1087system.cpu1.commit.refs 114574
1088system.cpu1.commit.loads 78525
1089system.cpu1.commit.membars 6941
1090system.cpu1.commit.branches 48947
1091system.cpu1.commit.fp_insts 0
1092system.cpu1.commit.int_insts 185648
1093system.cpu1.commit.function_calls 322
1094system.cpu1.commit.op_class_0::No_OpClass 39739 14.60% 14.60%
1095system.cpu1.commit.op_class_0::IntAlu 111017 40.77% 55.37%
1096system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.37%
1097system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.37%
1098system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.37%
1099system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.37%
1100system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.37%
1101system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.37%
1102system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 55.37%
1103system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.37%
1104system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 55.37%
1105system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.37%
1106system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.37%
1107system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.37%
1108system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.37%
1109system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.37%
1110system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.37%
1111system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.37%
1112system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.37%
1113system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.37%
1114system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.37%
1115system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.37%
1116system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.37%
1117system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.37%
1118system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.37%
1119system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.37%
1120system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.37%
1121system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.37%
1122system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.37%
1123system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.37%
1124system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.37%
1125system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.37%
1126system.cpu1.commit.op_class_0::MemRead 85466 31.39% 86.76%
1127system.cpu1.commit.op_class_0::MemWrite 36049 13.24% 100.00%
1128system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00%
1129system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00%
1130system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00%
1131system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
1132system.cpu1.commit.op_class_0::total 272271
1133system.cpu1.commit.bw_lim_events 1276
1134system.cpu1.rob.rob_reads 477284
1135system.cpu1.rob.rob_writes 598384
1136system.cpu1.timesIdled 242
1137system.cpu1.idleCycles 6985
1138system.cpu1.quiesceCycles 49435
1139system.cpu1.committedInsts 225591
1140system.cpu1.committedOps 225591
1141system.cpu1.cpi 0.859746
1142system.cpu1.cpi_total 0.859746
1143system.cpu1.ipc 1.163134
1144system.cpu1.ipc_total 1.163134
1145system.cpu1.int_regfile_reads 419202
1146system.cpu1.int_regfile_writes 195886
1147system.cpu1.fp_regfile_writes 64
1148system.cpu1.misc_regfile_reads 120419
1149system.cpu1.misc_regfile_writes 652
1150system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
1151system.cpu1.dcache.tags.replacements 0
1152system.cpu1.dcache.tags.tagsinuse 26.619618
1153system.cpu1.dcache.tags.total_refs 43145
1154system.cpu1.dcache.tags.sampled_refs 30
1155system.cpu1.dcache.tags.avg_refs 1438.166667
1156system.cpu1.dcache.tags.warmup_cycle 0
1157system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.619618
1158system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051991
1159system.cpu1.dcache.tags.occ_percent::total 0.051991
1160system.cpu1.dcache.tags.occ_task_id_blocks::1024 30
1161system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1
1162system.cpu1.dcache.tags.age_task_id_blocks_1024::1 17
1163system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12
1164system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594
1165system.cpu1.dcache.tags.tag_accesses 340046
1166system.cpu1.dcache.tags.data_accesses 340046
1167system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 126524000
1168system.cpu1.dcache.ReadReq_hits::cpu1.data 48453
1169system.cpu1.dcache.ReadReq_hits::total 48453
1170system.cpu1.dcache.WriteReq_hits::cpu1.data 35830
1171system.cpu1.dcache.WriteReq_hits::total 35830
1172system.cpu1.dcache.SwapReq_hits::cpu1.data 16
1173system.cpu1.dcache.SwapReq_hits::total 16
1174system.cpu1.dcache.demand_hits::cpu1.data 84283
1175system.cpu1.dcache.demand_hits::total 84283
1176system.cpu1.dcache.overall_hits::cpu1.data 84283
1177system.cpu1.dcache.overall_hits::total 84283
1178system.cpu1.dcache.ReadReq_misses::cpu1.data 447
1179system.cpu1.dcache.ReadReq_misses::total 447
1180system.cpu1.dcache.WriteReq_misses::cpu1.data 153
1181system.cpu1.dcache.WriteReq_misses::total 153
1182system.cpu1.dcache.SwapReq_misses::cpu1.data 50
1183system.cpu1.dcache.SwapReq_misses::total 50
1184system.cpu1.dcache.demand_misses::cpu1.data 600
1185system.cpu1.dcache.demand_misses::total 600
1186system.cpu1.dcache.overall_misses::cpu1.data 600
1187system.cpu1.dcache.overall_misses::total 600
1188system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4515500
1189system.cpu1.dcache.ReadReq_miss_latency::total 4515500
1190system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3649500
1191system.cpu1.dcache.WriteReq_miss_latency::total 3649500
1192system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 328500
1193system.cpu1.dcache.SwapReq_miss_latency::total 328500
1194system.cpu1.dcache.demand_miss_latency::cpu1.data 8165000
1195system.cpu1.dcache.demand_miss_latency::total 8165000
1196system.cpu1.dcache.overall_miss_latency::cpu1.data 8165000
1197system.cpu1.dcache.overall_miss_latency::total 8165000
1198system.cpu1.dcache.ReadReq_accesses::cpu1.data 48900
1199system.cpu1.dcache.ReadReq_accesses::total 48900
1200system.cpu1.dcache.WriteReq_accesses::cpu1.data 35983
1201system.cpu1.dcache.WriteReq_accesses::total 35983
1202system.cpu1.dcache.SwapReq_accesses::cpu1.data 66
1203system.cpu1.dcache.SwapReq_accesses::total 66
1204system.cpu1.dcache.demand_accesses::cpu1.data 84883
1205system.cpu1.dcache.demand_accesses::total 84883
1206system.cpu1.dcache.overall_accesses::cpu1.data 84883
1207system.cpu1.dcache.overall_accesses::total 84883
1208system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009141
1209system.cpu1.dcache.ReadReq_miss_rate::total 0.009141
1210system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004252
1211system.cpu1.dcache.WriteReq_miss_rate::total 0.004252
1212system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.757576
1213system.cpu1.dcache.SwapReq_miss_rate::total 0.757576
1214system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007069
1215system.cpu1.dcache.demand_miss_rate::total 0.007069
1216system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007069
1217system.cpu1.dcache.overall_miss_rate::total 0.007069
1218system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10101.789709
1219system.cpu1.dcache.ReadReq_avg_miss_latency::total 10101.789709
1220system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23852.941176
1221system.cpu1.dcache.WriteReq_avg_miss_latency::total 23852.941176
1222system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6570
1223system.cpu1.dcache.SwapReq_avg_miss_latency::total 6570
1224system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13608.333333
1225system.cpu1.dcache.demand_avg_miss_latency::total 13608.333333
1226system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13608.333333
1227system.cpu1.dcache.overall_avg_miss_latency::total 13608.333333
1228system.cpu1.dcache.blocked_cycles::no_mshrs 0
1229system.cpu1.dcache.blocked_cycles::no_targets 0
1230system.cpu1.dcache.blocked::no_mshrs 0
1231system.cpu1.dcache.blocked::no_targets 0
1232system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
1233system.cpu1.dcache.avg_blocked_cycles::no_targets nan
1234system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 284
1235system.cpu1.dcache.ReadReq_mshr_hits::total 284
1236system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49
1237system.cpu1.dcache.WriteReq_mshr_hits::total 49
1238system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 4
1239system.cpu1.dcache.SwapReq_mshr_hits::total 4
1240system.cpu1.dcache.demand_mshr_hits::cpu1.data 333
1241system.cpu1.dcache.demand_mshr_hits::total 333
1242system.cpu1.dcache.overall_mshr_hits::cpu1.data 333
1243system.cpu1.dcache.overall_mshr_hits::total 333
1244system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163
1245system.cpu1.dcache.ReadReq_mshr_misses::total 163
1246system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104
1247system.cpu1.dcache.WriteReq_mshr_misses::total 104
1248system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 46
1249system.cpu1.dcache.SwapReq_mshr_misses::total 46
1250system.cpu1.dcache.demand_mshr_misses::cpu1.data 267
1251system.cpu1.dcache.demand_mshr_misses::total 267
1252system.cpu1.dcache.overall_mshr_misses::cpu1.data 267
1253system.cpu1.dcache.overall_mshr_misses::total 267
1254system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1545000
1255system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1545000
1256system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1530500
1257system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1530500
1258system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 278500
1259system.cpu1.dcache.SwapReq_mshr_miss_latency::total 278500
1260system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3075500
1261system.cpu1.dcache.demand_mshr_miss_latency::total 3075500
1262system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3075500
1263system.cpu1.dcache.overall_mshr_miss_latency::total 3075500
1264system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003333
1265system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003333
1266system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002890
1267system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002890
1268system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.696970
1269system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.696970
1270system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003146
1271system.cpu1.dcache.demand_mshr_miss_rate::total 0.003146
1272system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003146
1273system.cpu1.dcache.overall_mshr_miss_rate::total 0.003146
1274system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9478.527607
1275system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9478.527607
1276system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14716.346154
1277system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14716.346154
1278system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6054.347826
1279system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6054.347826
1280system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11518.726592
1281system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11518.726592
1282system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11518.726592
1283system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11518.726592
1284system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
1285system.cpu1.icache.tags.replacements 602
1286system.cpu1.icache.tags.tagsinuse 99.247443
1287system.cpu1.icache.tags.total_refs 27667
1288system.cpu1.icache.tags.sampled_refs 737
1289system.cpu1.icache.tags.avg_refs 37.540027
1290system.cpu1.icache.tags.warmup_cycle 0
1291system.cpu1.icache.tags.occ_blocks::cpu1.inst 99.247443
1292system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193843
1293system.cpu1.icache.tags.occ_percent::total 0.193843
1294system.cpu1.icache.tags.occ_task_id_blocks::1024 135
1295system.cpu1.icache.tags.age_task_id_blocks_1024::0 18
1296system.cpu1.icache.tags.age_task_id_blocks_1024::1 99
1297system.cpu1.icache.tags.age_task_id_blocks_1024::2 18
1298system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672
1299system.cpu1.icache.tags.tag_accesses 29299
1300system.cpu1.icache.tags.data_accesses 29299
1301system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 126524000
1302system.cpu1.icache.ReadReq_hits::cpu1.inst 27667
1303system.cpu1.icache.ReadReq_hits::total 27667
1304system.cpu1.icache.demand_hits::cpu1.inst 27667
1305system.cpu1.icache.demand_hits::total 27667
1306system.cpu1.icache.overall_hits::cpu1.inst 27667
1307system.cpu1.icache.overall_hits::total 27667
1308system.cpu1.icache.ReadReq_misses::cpu1.inst 895
1309system.cpu1.icache.ReadReq_misses::total 895
1310system.cpu1.icache.demand_misses::cpu1.inst 895
1311system.cpu1.icache.demand_misses::total 895
1312system.cpu1.icache.overall_misses::cpu1.inst 895
1313system.cpu1.icache.overall_misses::total 895
1314system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 22011500
1315system.cpu1.icache.ReadReq_miss_latency::total 22011500
1316system.cpu1.icache.demand_miss_latency::cpu1.inst 22011500
1317system.cpu1.icache.demand_miss_latency::total 22011500
1318system.cpu1.icache.overall_miss_latency::cpu1.inst 22011500
1319system.cpu1.icache.overall_miss_latency::total 22011500
1320system.cpu1.icache.ReadReq_accesses::cpu1.inst 28562
1321system.cpu1.icache.ReadReq_accesses::total 28562
1322system.cpu1.icache.demand_accesses::cpu1.inst 28562
1323system.cpu1.icache.demand_accesses::total 28562
1324system.cpu1.icache.overall_accesses::cpu1.inst 28562
1325system.cpu1.icache.overall_accesses::total 28562
1326system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031335
1327system.cpu1.icache.ReadReq_miss_rate::total 0.031335
1328system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031335
1329system.cpu1.icache.demand_miss_rate::total 0.031335
1330system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031335
1331system.cpu1.icache.overall_miss_rate::total 0.031335
1332system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24593.854749
1333system.cpu1.icache.ReadReq_avg_miss_latency::total 24593.854749
1334system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24593.854749
1335system.cpu1.icache.demand_avg_miss_latency::total 24593.854749
1336system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24593.854749
1337system.cpu1.icache.overall_avg_miss_latency::total 24593.854749
1338system.cpu1.icache.blocked_cycles::no_mshrs 240
1339system.cpu1.icache.blocked_cycles::no_targets 0
1340system.cpu1.icache.blocked::no_mshrs 8
1341system.cpu1.icache.blocked::no_targets 0
1342system.cpu1.icache.avg_blocked_cycles::no_mshrs 30
1343system.cpu1.icache.avg_blocked_cycles::no_targets nan
1344system.cpu1.icache.writebacks::writebacks 602
1345system.cpu1.icache.writebacks::total 602
1346system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158
1347system.cpu1.icache.ReadReq_mshr_hits::total 158
1348system.cpu1.icache.demand_mshr_hits::cpu1.inst 158
1349system.cpu1.icache.demand_mshr_hits::total 158
1350system.cpu1.icache.overall_mshr_hits::cpu1.inst 158
1351system.cpu1.icache.overall_mshr_hits::total 158
1352system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 737
1353system.cpu1.icache.ReadReq_mshr_misses::total 737
1354system.cpu1.icache.demand_mshr_misses::cpu1.inst 737
1355system.cpu1.icache.demand_mshr_misses::total 737
1356system.cpu1.icache.overall_mshr_misses::cpu1.inst 737
1357system.cpu1.icache.overall_mshr_misses::total 737
1358system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16836000
1359system.cpu1.icache.ReadReq_mshr_miss_latency::total 16836000
1360system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16836000
1361system.cpu1.icache.demand_mshr_miss_latency::total 16836000
1362system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16836000
1363system.cpu1.icache.overall_mshr_miss_latency::total 16836000
1364system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025804
1365system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025804
1366system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025804
1367system.cpu1.icache.demand_mshr_miss_rate::total 0.025804
1368system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025804
1369system.cpu1.icache.overall_mshr_miss_rate::total 0.025804
1370system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22843.962008
1371system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22843.962008
1372system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22843.962008
1373system.cpu1.icache.demand_avg_mshr_miss_latency::total 22843.962008
1374system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22843.962008
1375system.cpu1.icache.overall_avg_mshr_miss_latency::total 22843.962008
1376system.cpu2.branchPred.lookups 63005
1377system.cpu2.branchPred.condPredicted 54943
1378system.cpu2.branchPred.condIncorrect 2446
1379system.cpu2.branchPred.BTBLookups 54515
1380system.cpu2.branchPred.BTBHits 0
1381system.cpu2.branchPred.BTBCorrect 0
1382system.cpu2.branchPred.BTBHitPct 0.000000
1383system.cpu2.branchPred.usedRAS 2009
1384system.cpu2.branchPred.RASInCorrect 231
1385system.cpu2.branchPred.indirectLookups 54515
1386system.cpu2.branchPred.indirectHits 43815
1387system.cpu2.branchPred.indirectMisses 10700
1388system.cpu2.branchPredindirectMispredicted 1320
1389system.cpu2.pwrStateResidencyTicks::ON 126524000
1390system.cpu2.numCycles 193568
1391system.cpu2.numWorkItemsStarted 0
1392system.cpu2.numWorkItemsCompleted 0
1393system.cpu2.fetch.icacheStallCycles 41212
1394system.cpu2.fetch.Insts 337111
1395system.cpu2.fetch.Branches 63005
1396system.cpu2.fetch.predictedBranches 45824
1397system.cpu2.fetch.Cycles 146186
1398system.cpu2.fetch.SquashCycles 5049
1399system.cpu2.fetch.MiscStallCycles 3
1400system.cpu2.fetch.NoActiveThreadStallCycles 10
1401system.cpu2.fetch.PendingTrapStallCycles 1881
1402system.cpu2.fetch.CacheLines 30662
1403system.cpu2.fetch.IcacheSquashes 928
1404system.cpu2.fetch.rateDist::samples 191816
1405system.cpu2.fetch.rateDist::mean 1.757471
1406system.cpu2.fetch.rateDist::stdev 2.316309
1407system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00%
1408system.cpu2.fetch.rateDist::0 78288 40.81% 40.81%
1409system.cpu2.fetch.rateDist::1 56335 29.37% 70.18%
1410system.cpu2.fetch.rateDist::2 9442 4.92% 75.11%
1411system.cpu2.fetch.rateDist::3 3538 1.84% 76.95%
1412system.cpu2.fetch.rateDist::4 653 0.34% 77.29%
1413system.cpu2.fetch.rateDist::5 32047 16.71% 94.00%
1414system.cpu2.fetch.rateDist::6 1150 0.60% 94.60%
1415system.cpu2.fetch.rateDist::7 1373 0.72% 95.31%
1416system.cpu2.fetch.rateDist::8 8990 4.69% 100.00%
1417system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00%
1418system.cpu2.fetch.rateDist::min_value 0
1419system.cpu2.fetch.rateDist::max_value 8
1420system.cpu2.fetch.rateDist::total 191816
1421system.cpu2.fetch.branchRate 0.325493
1422system.cpu2.fetch.rate 1.741564
1423system.cpu2.decode.IdleCycles 22511
1424system.cpu2.decode.BlockedCycles 80270
1425system.cpu2.decode.RunCycles 81305
1426system.cpu2.decode.UnblockCycles 5196
1427system.cpu2.decode.SquashCycles 2524
1428system.cpu2.decode.DecodedInsts 304951
1429system.cpu2.rename.SquashCycles 2524
1430system.cpu2.rename.IdleCycles 23572
1431system.cpu2.rename.BlockCycles 39907
1432system.cpu2.rename.serializeStallCycles 13834
1433system.cpu2.rename.RunCycles 82651
1434system.cpu2.rename.UnblockCycles 29318
1435system.cpu2.rename.RenamedInsts 297990
1436system.cpu2.rename.IQFullEvents 25746
1437system.cpu2.rename.LQFullEvents 17
1438system.cpu2.rename.FullRegisterEvents 2
1439system.cpu2.rename.RenamedOperands 207037
1440system.cpu2.rename.RenameLookups 557824
1441system.cpu2.rename.int_rename_lookups 436197
1442system.cpu2.rename.fp_rename_lookups 20
1443system.cpu2.rename.CommittedMaps 176797
1444system.cpu2.rename.UndoneMaps 30240
1445system.cpu2.rename.serializingInsts 1683
1446system.cpu2.rename.tempSerializingInsts 1817
1447system.cpu2.rename.skidInsts 35305
1448system.cpu2.memDep0.insertedLoads 79616
1449system.cpu2.memDep0.insertedStores 36437
1450system.cpu2.memDep0.conflictingLoads 38372
1451system.cpu2.memDep0.conflictingStores 30080
1452system.cpu2.iq.iqInstsAdded 239894
1453system.cpu2.iq.iqNonSpecInstsAdded 9906
1454system.cpu2.iq.iqInstsIssued 241219
1455system.cpu2.iq.iqSquashedInstsIssued 120
1456system.cpu2.iq.iqSquashedInstsExamined 26152
1457system.cpu2.iq.iqSquashedOperandsExamined 21212
1458system.cpu2.iq.iqSquashedNonSpecRemoved 1309
1459system.cpu2.iq.issued_per_cycle::samples 191816
1460system.cpu2.iq.issued_per_cycle::mean 1.257554
1461system.cpu2.iq.issued_per_cycle::stdev 1.379653
1462system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00%
1463system.cpu2.iq.issued_per_cycle::0 83659 43.61% 43.61%
1464system.cpu2.iq.issued_per_cycle::1 31014 16.17% 59.78%
1465system.cpu2.iq.issued_per_cycle::2 35021 18.26% 78.04%
1466system.cpu2.iq.issued_per_cycle::3 34852 18.17% 96.21%
1467system.cpu2.iq.issued_per_cycle::4 3649 1.90% 98.11%
1468system.cpu2.iq.issued_per_cycle::5 1791 0.93% 99.05%
1469system.cpu2.iq.issued_per_cycle::6 1085 0.57% 99.61%
1470system.cpu2.iq.issued_per_cycle::7 414 0.22% 99.83%
1471system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00%
1472system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00%
1473system.cpu2.iq.issued_per_cycle::min_value 0
1474system.cpu2.iq.issued_per_cycle::max_value 8
1475system.cpu2.iq.issued_per_cycle::total 191816
1476system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00%
1477system.cpu2.iq.fu_full::IntAlu 208 41.52% 41.52%
1478system.cpu2.iq.fu_full::IntMult 0 0.00% 41.52%
1479system.cpu2.iq.fu_full::IntDiv 0 0.00% 41.52%
1480system.cpu2.iq.fu_full::FloatAdd 0 0.00% 41.52%
1481system.cpu2.iq.fu_full::FloatCmp 0 0.00% 41.52%
1482system.cpu2.iq.fu_full::FloatCvt 0 0.00% 41.52%
1483system.cpu2.iq.fu_full::FloatMult 0 0.00% 41.52%
1484system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 41.52%
1485system.cpu2.iq.fu_full::FloatDiv 0 0.00% 41.52%
1486system.cpu2.iq.fu_full::FloatMisc 0 0.00% 41.52%
1487system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 41.52%
1488system.cpu2.iq.fu_full::SimdAdd 0 0.00% 41.52%
1489system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 41.52%
1490system.cpu2.iq.fu_full::SimdAlu 0 0.00% 41.52%
1491system.cpu2.iq.fu_full::SimdCmp 0 0.00% 41.52%
1492system.cpu2.iq.fu_full::SimdCvt 0 0.00% 41.52%
1493system.cpu2.iq.fu_full::SimdMisc 0 0.00% 41.52%
1494system.cpu2.iq.fu_full::SimdMult 0 0.00% 41.52%
1495system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 41.52%
1496system.cpu2.iq.fu_full::SimdShift 0 0.00% 41.52%
1497system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 41.52%
1498system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 41.52%
1499system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 41.52%
1500system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 41.52%
1501system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 41.52%
1502system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 41.52%
1503system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 41.52%
1504system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 41.52%
1505system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 41.52%
1506system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.52%
1507system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 41.52%
1508system.cpu2.iq.fu_full::MemRead 64 12.77% 54.29%
1509system.cpu2.iq.fu_full::MemWrite 229 45.71% 100.00%
1510system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00%
1511system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00%
1512system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00%
1513system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00%
1514system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
1515system.cpu2.iq.FU_type_0::IntAlu 119551 49.56% 49.56%
1516system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.56%
1517system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.56%
1518system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.56%
1519system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.56%
1520system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.56%
1521system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.56%
1522system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 49.56%
1523system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.56%
1524system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 49.56%
1525system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.56%
1526system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.56%
1527system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.56%
1528system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.56%
1529system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.56%
1530system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.56%
1531system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.56%
1532system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.56%
1533system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.56%
1534system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.56%
1535system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.56%
1536system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.56%
1537system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.56%
1538system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.56%
1539system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.56%
1540system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.56%
1541system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.56%
1542system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.56%
1543system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.56%
1544system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.56%
1545system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.56%
1546system.cpu2.iq.FU_type_0::MemRead 86276 35.77% 85.33%
1547system.cpu2.iq.FU_type_0::MemWrite 35392 14.67% 100.00%
1548system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00%
1549system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00%
1550system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00%
1551system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
1552system.cpu2.iq.FU_type_0::total 241219
1553system.cpu2.iq.rate 1.246172
1554system.cpu2.iq.fu_busy_cnt 501
1555system.cpu2.iq.fu_busy_rate 0.002077
1556system.cpu2.iq.int_inst_queue_reads 674875
1557system.cpu2.iq.int_inst_queue_writes 275950
1558system.cpu2.iq.int_inst_queue_wakeup_accesses 237037
1559system.cpu2.iq.fp_inst_queue_reads 0
1560system.cpu2.iq.fp_inst_queue_writes 40
1561system.cpu2.iq.fp_inst_queue_wakeup_accesses 0
1562system.cpu2.iq.int_alu_accesses 241720
1563system.cpu2.iq.fp_alu_accesses 0
1564system.cpu2.iew.lsq.thread0.forwLoads 29936
1565system.cpu2.iew.lsq.thread0.invAddrLoads 0
1566system.cpu2.iew.lsq.thread0.squashedLoads 4843
1567system.cpu2.iew.lsq.thread0.ignoredResponses 35
1568system.cpu2.iew.lsq.thread0.memOrderViolation 38
1569system.cpu2.iew.lsq.thread0.squashedStores 2724
1570system.cpu2.iew.lsq.thread0.invAddrSwpfs 0
1571system.cpu2.iew.lsq.thread0.blockedLoads 0
1572system.cpu2.iew.lsq.thread0.rescheduledLoads 0
1573system.cpu2.iew.lsq.thread0.cacheBlocked 0
1574system.cpu2.iew.iewIdleCycles 0
1575system.cpu2.iew.iewSquashCycles 2524
1576system.cpu2.iew.iewBlockCycles 10427
1577system.cpu2.iew.iewUnblockCycles 59
1578system.cpu2.iew.iewDispatchedInsts 289447
1579system.cpu2.iew.iewDispSquashedInsts 340
1580system.cpu2.iew.iewDispLoadInsts 79616
1581system.cpu2.iew.iewDispStoreInsts 36437
1582system.cpu2.iew.iewDispNonSpecInsts 1558
1583system.cpu2.iew.iewIQFullEvents 36
1584system.cpu2.iew.iewLSQFullEvents 0
1585system.cpu2.iew.memOrderViolationEvents 38
1586system.cpu2.iew.predictedTakenIncorrect 449
1587system.cpu2.iew.predictedNotTakenIncorrect 2607
1588system.cpu2.iew.branchMispredicts 3056
1589system.cpu2.iew.iewExecutedInsts 238568
1590system.cpu2.iew.iewExecLoadInsts 77774
1591system.cpu2.iew.iewExecSquashedInsts 2651
1592system.cpu2.iew.exec_swp 0
1593system.cpu2.iew.exec_nop 39647
1594system.cpu2.iew.exec_refs 112834
1595system.cpu2.iew.exec_branches 49845
1596system.cpu2.iew.exec_stores 35060
1597system.cpu2.iew.exec_rate 1.232476
1598system.cpu2.iew.wb_sent 237626
1599system.cpu2.iew.wb_count 237037
1600system.cpu2.iew.wb_producers 130856
1601system.cpu2.iew.wb_consumers 138405
1602system.cpu2.iew.wb_rate 1.224567
1603system.cpu2.iew.wb_fanout 0.945457
1604system.cpu2.commit.commitSquashedInsts 27430
1605system.cpu2.commit.commitNonSpecStalls 8597
1606system.cpu2.commit.branchMispredicts 2446
1607system.cpu2.commit.committed_per_cycle::samples 186682
1608system.cpu2.commit.committed_per_cycle::mean 1.403387
1609system.cpu2.commit.committed_per_cycle::stdev 1.956532
1610system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00%
1611system.cpu2.commit.committed_per_cycle::0 91634 49.09% 49.09%
1612system.cpu2.commit.committed_per_cycle::1 46034 24.66% 73.74%
1613system.cpu2.commit.committed_per_cycle::2 5345 2.86% 76.61%
1614system.cpu2.commit.committed_per_cycle::3 9142 4.90% 81.50%
1615system.cpu2.commit.committed_per_cycle::4 1340 0.72% 82.22%
1616system.cpu2.commit.committed_per_cycle::5 30155 16.15% 98.38%
1617system.cpu2.commit.committed_per_cycle::6 771 0.41% 98.79%
1618system.cpu2.commit.committed_per_cycle::7 1012 0.54% 99.33%
1619system.cpu2.commit.committed_per_cycle::8 1249 0.67% 100.00%
1620system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00%
1621system.cpu2.commit.committed_per_cycle::min_value 0
1622system.cpu2.commit.committed_per_cycle::max_value 8
1623system.cpu2.commit.committed_per_cycle::total 186682
1624system.cpu2.commit.committedInsts 261987
1625system.cpu2.commit.committedOps 261987
1626system.cpu2.commit.swp_count 0
1627system.cpu2.commit.refs 108486
1628system.cpu2.commit.loads 74773
1629system.cpu2.commit.membars 7877
1630system.cpu2.commit.branches 47555
1631system.cpu2.commit.fp_insts 0
1632system.cpu2.commit.int_insts 178156
1633system.cpu2.commit.function_calls 322
1634system.cpu2.commit.op_class_0::No_OpClass 38339 14.63% 14.63%
1635system.cpu2.commit.op_class_0::IntAlu 107285 40.95% 55.58%
1636system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.58%
1637system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.58%
1638system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.58%
1639system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.58%
1640system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.58%
1641system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.58%
1642system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.58%
1643system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.58%
1644system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.58%
1645system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.58%
1646system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.58%
1647system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.58%
1648system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.58%
1649system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.58%
1650system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.58%
1651system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.58%
1652system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.58%
1653system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.58%
1654system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.58%
1655system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.58%
1656system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.58%
1657system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.58%
1658system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.58%
1659system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.58%
1660system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.58%
1661system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.58%
1662system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.58%
1663system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.58%
1664system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.58%
1665system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.58%
1666system.cpu2.commit.op_class_0::MemRead 82650 31.55% 87.13%
1667system.cpu2.commit.op_class_0::MemWrite 33713 12.87% 100.00%
1668system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00%
1669system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00%
1670system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00%
1671system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
1672system.cpu2.commit.op_class_0::total 261987
1673system.cpu2.commit.bw_lim_events 1249
1674system.cpu2.rob.rob_reads 474264
1675system.cpu2.rob.rob_writes 584030
1676system.cpu2.timesIdled 214
1677system.cpu2.idleCycles 1752
1678system.cpu2.quiesceCycles 49819
1679system.cpu2.committedInsts 215771
1680system.cpu2.committedOps 215771
1681system.cpu2.cpi 0.897099
1682system.cpu2.cpi_total 0.897099
1683system.cpu2.ipc 1.114704
1684system.cpu2.ipc_total 1.114704
1685system.cpu2.int_regfile_reads 403345
1686system.cpu2.int_regfile_writes 188790
1687system.cpu2.fp_regfile_writes 64
1688system.cpu2.misc_regfile_reads 114754
1689system.cpu2.misc_regfile_writes 652
1690system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
1691system.cpu2.dcache.tags.replacements 0
1692system.cpu2.dcache.tags.tagsinuse 24.506015
1693system.cpu2.dcache.tags.total_refs 40898
1694system.cpu2.dcache.tags.sampled_refs 29
1695system.cpu2.dcache.tags.avg_refs 1410.275862
1696system.cpu2.dcache.tags.warmup_cycle 0
1697system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.506015
1698system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047863
1699system.cpu2.dcache.tags.occ_percent::total 0.047863
1700system.cpu2.dcache.tags.occ_task_id_blocks::1024 29
1701system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25
1702system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4
1703system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641
1704system.cpu2.dcache.tags.tag_accesses 326280
1705system.cpu2.dcache.tags.data_accesses 326280
1706system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 126524000
1707system.cpu2.dcache.ReadReq_hits::cpu2.data 47272
1708system.cpu2.dcache.ReadReq_hits::total 47272
1709system.cpu2.dcache.WriteReq_hits::cpu2.data 33497
1710system.cpu2.dcache.WriteReq_hits::total 33497
1711system.cpu2.dcache.SwapReq_hits::cpu2.data 12
1712system.cpu2.dcache.SwapReq_hits::total 12
1713system.cpu2.dcache.demand_hits::cpu2.data 80769
1714system.cpu2.dcache.demand_hits::total 80769
1715system.cpu2.dcache.overall_hits::cpu2.data 80769
1716system.cpu2.dcache.overall_hits::total 80769
1717system.cpu2.dcache.ReadReq_misses::cpu2.data 517
1718system.cpu2.dcache.ReadReq_misses::total 517
1719system.cpu2.dcache.WriteReq_misses::cpu2.data 142
1720system.cpu2.dcache.WriteReq_misses::total 142
1721system.cpu2.dcache.SwapReq_misses::cpu2.data 62
1722system.cpu2.dcache.SwapReq_misses::total 62
1723system.cpu2.dcache.demand_misses::cpu2.data 659
1724system.cpu2.dcache.demand_misses::total 659
1725system.cpu2.dcache.overall_misses::cpu2.data 659
1726system.cpu2.dcache.overall_misses::total 659
1727system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 4039000
1728system.cpu2.dcache.ReadReq_miss_latency::total 4039000
1729system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3186000
1730system.cpu2.dcache.WriteReq_miss_latency::total 3186000
1731system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 386500
1732system.cpu2.dcache.SwapReq_miss_latency::total 386500
1733system.cpu2.dcache.demand_miss_latency::cpu2.data 7225000
1734system.cpu2.dcache.demand_miss_latency::total 7225000
1735system.cpu2.dcache.overall_miss_latency::cpu2.data 7225000
1736system.cpu2.dcache.overall_miss_latency::total 7225000
1737system.cpu2.dcache.ReadReq_accesses::cpu2.data 47789
1738system.cpu2.dcache.ReadReq_accesses::total 47789
1739system.cpu2.dcache.WriteReq_accesses::cpu2.data 33639
1740system.cpu2.dcache.WriteReq_accesses::total 33639
1741system.cpu2.dcache.SwapReq_accesses::cpu2.data 74
1742system.cpu2.dcache.SwapReq_accesses::total 74
1743system.cpu2.dcache.demand_accesses::cpu2.data 81428
1744system.cpu2.dcache.demand_accesses::total 81428
1745system.cpu2.dcache.overall_accesses::cpu2.data 81428
1746system.cpu2.dcache.overall_accesses::total 81428
1747system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010818
1748system.cpu2.dcache.ReadReq_miss_rate::total 0.010818
1749system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004221
1750system.cpu2.dcache.WriteReq_miss_rate::total 0.004221
1751system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838
1752system.cpu2.dcache.SwapReq_miss_rate::total 0.837838
1753system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008093
1754system.cpu2.dcache.demand_miss_rate::total 0.008093
1755system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008093
1756system.cpu2.dcache.overall_miss_rate::total 0.008093
1757system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7812.379110
1758system.cpu2.dcache.ReadReq_avg_miss_latency::total 7812.379110
1759system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22436.619718
1760system.cpu2.dcache.WriteReq_avg_miss_latency::total 22436.619718
1761system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6233.870968
1762system.cpu2.dcache.SwapReq_avg_miss_latency::total 6233.870968
1763system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10963.581184
1764system.cpu2.dcache.demand_avg_miss_latency::total 10963.581184
1765system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10963.581184
1766system.cpu2.dcache.overall_avg_miss_latency::total 10963.581184
1767system.cpu2.dcache.blocked_cycles::no_mshrs 0
1768system.cpu2.dcache.blocked_cycles::no_targets 0
1769system.cpu2.dcache.blocked::no_mshrs 0
1770system.cpu2.dcache.blocked::no_targets 0
1771system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
1772system.cpu2.dcache.avg_blocked_cycles::no_targets nan
1773system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 341
1774system.cpu2.dcache.ReadReq_mshr_hits::total 341
1775system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 36
1776system.cpu2.dcache.WriteReq_mshr_hits::total 36
1777system.cpu2.dcache.demand_mshr_hits::cpu2.data 377
1778system.cpu2.dcache.demand_mshr_hits::total 377
1779system.cpu2.dcache.overall_mshr_hits::cpu2.data 377
1780system.cpu2.dcache.overall_mshr_hits::total 377
1781system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 176
1782system.cpu2.dcache.ReadReq_mshr_misses::total 176
1783system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106
1784system.cpu2.dcache.WriteReq_mshr_misses::total 106
1785system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62
1786system.cpu2.dcache.SwapReq_mshr_misses::total 62
1787system.cpu2.dcache.demand_mshr_misses::cpu2.data 282
1788system.cpu2.dcache.demand_mshr_misses::total 282
1789system.cpu2.dcache.overall_mshr_misses::cpu2.data 282
1790system.cpu2.dcache.overall_mshr_misses::total 282
1791system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1172500
1792system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1172500
1793system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1650500
1794system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1650500
1795system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 324500
1796system.cpu2.dcache.SwapReq_mshr_miss_latency::total 324500
1797system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2823000
1798system.cpu2.dcache.demand_mshr_miss_latency::total 2823000
1799system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2823000
1800system.cpu2.dcache.overall_mshr_miss_latency::total 2823000
1801system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003683
1802system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003683
1803system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003151
1804system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003151
1805system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.837838
1806system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.837838
1807system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003463
1808system.cpu2.dcache.demand_mshr_miss_rate::total 0.003463
1809system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003463
1810system.cpu2.dcache.overall_mshr_miss_rate::total 0.003463
1811system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6661.931818
1812system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6661.931818
1813system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15570.754717
1814system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15570.754717
1815system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5233.870968
1816system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5233.870968
1817system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10010.638298
1818system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10010.638298
1819system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10010.638298
1820system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10010.638298
1821system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
1822system.cpu2.icache.tags.replacements 533
1823system.cpu2.icache.tags.tagsinuse 93.527122
1824system.cpu2.icache.tags.total_refs 29858
1825system.cpu2.icache.tags.sampled_refs 668
1826system.cpu2.icache.tags.avg_refs 44.697605
1827system.cpu2.icache.tags.warmup_cycle 0
1828system.cpu2.icache.tags.occ_blocks::cpu2.inst 93.527122
1829system.cpu2.icache.tags.occ_percent::cpu2.inst 0.182670
1830system.cpu2.icache.tags.occ_percent::total 0.182670
1831system.cpu2.icache.tags.occ_task_id_blocks::1024 135
1832system.cpu2.icache.tags.age_task_id_blocks_1024::0 16
1833system.cpu2.icache.tags.age_task_id_blocks_1024::1 107
1834system.cpu2.icache.tags.age_task_id_blocks_1024::2 12
1835system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672
1836system.cpu2.icache.tags.tag_accesses 31330
1837system.cpu2.icache.tags.data_accesses 31330
1838system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 126524000
1839system.cpu2.icache.ReadReq_hits::cpu2.inst 29858
1840system.cpu2.icache.ReadReq_hits::total 29858
1841system.cpu2.icache.demand_hits::cpu2.inst 29858
1842system.cpu2.icache.demand_hits::total 29858
1843system.cpu2.icache.overall_hits::cpu2.inst 29858
1844system.cpu2.icache.overall_hits::total 29858
1845system.cpu2.icache.ReadReq_misses::cpu2.inst 804
1846system.cpu2.icache.ReadReq_misses::total 804
1847system.cpu2.icache.demand_misses::cpu2.inst 804
1848system.cpu2.icache.demand_misses::total 804
1849system.cpu2.icache.overall_misses::cpu2.inst 804
1850system.cpu2.icache.overall_misses::total 804
1851system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12745500
1852system.cpu2.icache.ReadReq_miss_latency::total 12745500
1853system.cpu2.icache.demand_miss_latency::cpu2.inst 12745500
1854system.cpu2.icache.demand_miss_latency::total 12745500
1855system.cpu2.icache.overall_miss_latency::cpu2.inst 12745500
1856system.cpu2.icache.overall_miss_latency::total 12745500
1857system.cpu2.icache.ReadReq_accesses::cpu2.inst 30662
1858system.cpu2.icache.ReadReq_accesses::total 30662
1859system.cpu2.icache.demand_accesses::cpu2.inst 30662
1860system.cpu2.icache.demand_accesses::total 30662
1861system.cpu2.icache.overall_accesses::cpu2.inst 30662
1862system.cpu2.icache.overall_accesses::total 30662
1863system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.026221
1864system.cpu2.icache.ReadReq_miss_rate::total 0.026221
1865system.cpu2.icache.demand_miss_rate::cpu2.inst 0.026221
1866system.cpu2.icache.demand_miss_rate::total 0.026221
1867system.cpu2.icache.overall_miss_rate::cpu2.inst 0.026221
1868system.cpu2.icache.overall_miss_rate::total 0.026221
1869system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15852.611940
1870system.cpu2.icache.ReadReq_avg_miss_latency::total 15852.611940
1871system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15852.611940
1872system.cpu2.icache.demand_avg_miss_latency::total 15852.611940
1873system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15852.611940
1874system.cpu2.icache.overall_avg_miss_latency::total 15852.611940
1875system.cpu2.icache.blocked_cycles::no_mshrs 39
1876system.cpu2.icache.blocked_cycles::no_targets 0
1877system.cpu2.icache.blocked::no_mshrs 2
1878system.cpu2.icache.blocked::no_targets 0
1879system.cpu2.icache.avg_blocked_cycles::no_mshrs 19.500000
1880system.cpu2.icache.avg_blocked_cycles::no_targets nan
1881system.cpu2.icache.writebacks::writebacks 533
1882system.cpu2.icache.writebacks::total 533
1883system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 136
1884system.cpu2.icache.ReadReq_mshr_hits::total 136
1885system.cpu2.icache.demand_mshr_hits::cpu2.inst 136
1886system.cpu2.icache.demand_mshr_hits::total 136
1887system.cpu2.icache.overall_mshr_hits::cpu2.inst 136
1888system.cpu2.icache.overall_mshr_hits::total 136
1889system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 668
1890system.cpu2.icache.ReadReq_mshr_misses::total 668
1891system.cpu2.icache.demand_mshr_misses::cpu2.inst 668
1892system.cpu2.icache.demand_mshr_misses::total 668
1893system.cpu2.icache.overall_mshr_misses::cpu2.inst 668
1894system.cpu2.icache.overall_mshr_misses::total 668
1895system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10698000
1896system.cpu2.icache.ReadReq_mshr_miss_latency::total 10698000
1897system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10698000
1898system.cpu2.icache.demand_mshr_miss_latency::total 10698000
1899system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10698000
1900system.cpu2.icache.overall_mshr_miss_latency::total 10698000
1901system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021786
1902system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021786
1903system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021786
1904system.cpu2.icache.demand_mshr_miss_rate::total 0.021786
1905system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021786
1906system.cpu2.icache.overall_mshr_miss_rate::total 0.021786
1907system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 16014.970060
1908system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 16014.970060
1909system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 16014.970060
1910system.cpu2.icache.demand_avg_mshr_miss_latency::total 16014.970060
1911system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 16014.970060
1912system.cpu2.icache.overall_avg_mshr_miss_latency::total 16014.970060
1913system.cpu3.branchPred.lookups 72293
1914system.cpu3.branchPred.condPredicted 64508
1915system.cpu3.branchPred.condIncorrect 2352
1916system.cpu3.branchPred.BTBLookups 63427
1917system.cpu3.branchPred.BTBHits 0
1918system.cpu3.branchPred.BTBCorrect 0
1919system.cpu3.branchPred.BTBHitPct 0.000000
1920system.cpu3.branchPred.usedRAS 2060
1921system.cpu3.branchPred.RASInCorrect 231
1922system.cpu3.branchPred.indirectLookups 63427
1923system.cpu3.branchPred.indirectHits 53739
1924system.cpu3.branchPred.indirectMisses 9688
1925system.cpu3.branchPredindirectMispredicted 1247
1926system.cpu3.pwrStateResidencyTicks::ON 126524000
1927system.cpu3.numCycles 193192
1928system.cpu3.numWorkItemsStarted 0
1929system.cpu3.numWorkItemsCompleted 0
1930system.cpu3.fetch.icacheStallCycles 35761
1931system.cpu3.fetch.Insts 398740
1932system.cpu3.fetch.Branches 72293
1933system.cpu3.fetch.predictedBranches 55799
1934system.cpu3.fetch.Cycles 151769
1935system.cpu3.fetch.SquashCycles 4859
1936system.cpu3.fetch.MiscStallCycles 3
1937system.cpu3.fetch.NoActiveThreadStallCycles 10
1938system.cpu3.fetch.PendingTrapStallCycles 1574
1939system.cpu3.fetch.CacheLines 24631
1940system.cpu3.fetch.IcacheSquashes 962
1941system.cpu3.fetch.rateDist::samples 191546
1942system.cpu3.fetch.rateDist::mean 2.081693
1943system.cpu3.fetch.rateDist::stdev 2.372350
1944system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00%
1945system.cpu3.fetch.rateDist::0 61472 32.09% 32.09%
1946system.cpu3.fetch.rateDist::1 63433 33.12% 65.21%
1947system.cpu3.fetch.rateDist::2 6639 3.47% 68.67%
1948system.cpu3.fetch.rateDist::3 3404 1.78% 70.45%
1949system.cpu3.fetch.rateDist::4 665 0.35% 70.80%
1950system.cpu3.fetch.rateDist::5 44919 23.45% 94.25%
1951system.cpu3.fetch.rateDist::6 1096 0.57% 94.82%
1952system.cpu3.fetch.rateDist::7 1358 0.71% 95.53%
1953system.cpu3.fetch.rateDist::8 8560 4.47% 100.00%
1954system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00%
1955system.cpu3.fetch.rateDist::min_value 0
1956system.cpu3.fetch.rateDist::max_value 8
1957system.cpu3.fetch.rateDist::total 191546
1958system.cpu3.fetch.branchRate 0.374203
1959system.cpu3.fetch.rate 2.063957
1960system.cpu3.decode.IdleCycles 22177
1961system.cpu3.decode.BlockedCycles 57153
1962system.cpu3.decode.RunCycles 106023
1963system.cpu3.decode.UnblockCycles 3754
1964system.cpu3.decode.SquashCycles 2429
1965system.cpu3.decode.DecodedInsts 367896
1966system.cpu3.rename.SquashCycles 2429
1967system.cpu3.rename.IdleCycles 23211
1968system.cpu3.rename.BlockCycles 26609
1969system.cpu3.rename.serializeStallCycles 13121
1970system.cpu3.rename.RunCycles 106749
1971system.cpu3.rename.UnblockCycles 19417
1972system.cpu3.rename.RenamedInsts 361084
1973system.cpu3.rename.IQFullEvents 16689
1974system.cpu3.rename.LQFullEvents 17
1975system.cpu3.rename.RenamedOperands 253671
1976system.cpu3.rename.RenameLookups 696424
1977system.cpu3.rename.int_rename_lookups 539785
1978system.cpu3.rename.fp_rename_lookups 26
1979system.cpu3.rename.CommittedMaps 225321
1980system.cpu3.rename.UndoneMaps 28350
1981system.cpu3.rename.serializingInsts 1632
1982system.cpu3.rename.tempSerializingInsts 1767
1983system.cpu3.rename.skidInsts 25027
1984system.cpu3.memDep0.insertedLoads 102074
1985system.cpu3.memDep0.insertedStores 49198
1986system.cpu3.memDep0.conflictingLoads 48321
1987system.cpu3.memDep0.conflictingStores 42853
1988system.cpu3.iq.iqInstsAdded 296921
1989system.cpu3.iq.iqNonSpecInstsAdded 6960
1990system.cpu3.iq.iqInstsIssued 296157
1991system.cpu3.iq.iqSquashedInstsIssued 99
1992system.cpu3.iq.iqSquashedInstsExamined 24377
1993system.cpu3.iq.iqSquashedOperandsExamined 19466
1994system.cpu3.iq.iqSquashedNonSpecRemoved 1109
1995system.cpu3.iq.issued_per_cycle::samples 191546
1996system.cpu3.iq.issued_per_cycle::mean 1.546140
1997system.cpu3.iq.issued_per_cycle::stdev 1.378862
1998system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00%
1999system.cpu3.iq.issued_per_cycle::0 66138 34.53% 34.53%
2000system.cpu3.iq.issued_per_cycle::1 22907 11.96% 46.49%
2001system.cpu3.iq.issued_per_cycle::2 47792 24.95% 71.44%
2002system.cpu3.iq.issued_per_cycle::3 47510 24.80% 96.24%
2003system.cpu3.iq.issued_per_cycle::4 3644 1.90% 98.14%
2004system.cpu3.iq.issued_per_cycle::5 1780 0.93% 99.07%
2005system.cpu3.iq.issued_per_cycle::6 1054 0.55% 99.62%
2006system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.85%
2007system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00%
2008system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00%
2009system.cpu3.iq.issued_per_cycle::min_value 0
2010system.cpu3.iq.issued_per_cycle::max_value 8
2011system.cpu3.iq.issued_per_cycle::total 191546
2012system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00%
2013system.cpu3.iq.fu_full::IntAlu 185 40.13% 40.13%
2014system.cpu3.iq.fu_full::IntMult 0 0.00% 40.13%
2015system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.13%
2016system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.13%
2017system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.13%
2018system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.13%
2019system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.13%
2020system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.13%
2021system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.13%
2022system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.13%
2023system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.13%
2024system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.13%
2025system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.13%
2026system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.13%
2027system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.13%
2028system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.13%
2029system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.13%
2030system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.13%
2031system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.13%
2032system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.13%
2033system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.13%
2034system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.13%
2035system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.13%
2036system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.13%
2037system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.13%
2038system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.13%
2039system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.13%
2040system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.13%
2041system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.13%
2042system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.13%
2043system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.13%
2044system.cpu3.iq.fu_full::MemRead 47 10.20% 50.33%
2045system.cpu3.iq.fu_full::MemWrite 229 49.67% 100.00%
2046system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00%
2047system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00%
2048system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00%
2049system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00%
2050system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
2051system.cpu3.iq.FU_type_0::IntAlu 141800 47.88% 47.88%
2052system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.88%
2053system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.88%
2054system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.88%
2055system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.88%
2056system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.88%
2057system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.88%
2058system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 47.88%
2059system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.88%
2060system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 47.88%
2061system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.88%
2062system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.88%
2063system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88%
2064system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.88%
2065system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.88%
2066system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.88%
2067system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.88%
2068system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.88%
2069system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88%
2070system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.88%
2071system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.88%
2072system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.88%
2073system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88%
2074system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88%
2075system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88%
2076system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88%
2077system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88%
2078system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.88%
2079system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88%
2080system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.88%
2081system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88%
2082system.cpu3.iq.FU_type_0::MemRead 106215 35.86% 83.74%
2083system.cpu3.iq.FU_type_0::MemWrite 48142 16.26% 100.00%
2084system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00%
2085system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00%
2086system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00%
2087system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
2088system.cpu3.iq.FU_type_0::total 296157
2089system.cpu3.iq.rate 1.532967
2090system.cpu3.iq.fu_busy_cnt 461
2091system.cpu3.iq.fu_busy_rate 0.001557
2092system.cpu3.iq.int_inst_queue_reads 784420
2093system.cpu3.iq.int_inst_queue_writes 328242
2094system.cpu3.iq.int_inst_queue_wakeup_accesses 292189
2095system.cpu3.iq.fp_inst_queue_reads 0
2096system.cpu3.iq.fp_inst_queue_writes 52
2097system.cpu3.iq.fp_inst_queue_wakeup_accesses 0
2098system.cpu3.iq.int_alu_accesses 296618
2099system.cpu3.iq.fp_alu_accesses 0
2100system.cpu3.iew.lsq.thread0.forwLoads 42744
2101system.cpu3.iew.lsq.thread0.invAddrLoads 0
2102system.cpu3.iew.lsq.thread0.squashedLoads 4403
2103system.cpu3.iew.lsq.thread0.ignoredResponses 29
2104system.cpu3.iew.lsq.thread0.memOrderViolation 36
2105system.cpu3.iew.lsq.thread0.squashedStores 2674
2106system.cpu3.iew.lsq.thread0.invAddrSwpfs 0
2107system.cpu3.iew.lsq.thread0.blockedLoads 0
2108system.cpu3.iew.lsq.thread0.rescheduledLoads 0
2109system.cpu3.iew.lsq.thread0.cacheBlocked 0
2110system.cpu3.iew.iewIdleCycles 0
2111system.cpu3.iew.iewSquashCycles 2429
2112system.cpu3.iew.iewBlockCycles 7527
2113system.cpu3.iew.iewUnblockCycles 48
2114system.cpu3.iew.iewDispatchedInsts 353355
2115system.cpu3.iew.iewDispSquashedInsts 397
2116system.cpu3.iew.iewDispLoadInsts 102074
2117system.cpu3.iew.iewDispStoreInsts 49198
2118system.cpu3.iew.iewDispNonSpecInsts 1516
2119system.cpu3.iew.iewIQFullEvents 34
2120system.cpu3.iew.iewLSQFullEvents 0
2121system.cpu3.iew.memOrderViolationEvents 36
2122system.cpu3.iew.predictedTakenIncorrect 456
2123system.cpu3.iew.predictedNotTakenIncorrect 2533
2124system.cpu3.iew.branchMispredicts 2989
2125system.cpu3.iew.iewExecutedInsts 293543
2126system.cpu3.iew.iewExecLoadInsts 100466
2127system.cpu3.iew.iewExecSquashedInsts 2614
2128system.cpu3.iew.exec_swp 0
2129system.cpu3.iew.exec_nop 49474
2130system.cpu3.iew.exec_refs 148308
2131system.cpu3.iew.exec_branches 59826
2132system.cpu3.iew.exec_stores 47842
2133system.cpu3.iew.exec_rate 1.519437
2134system.cpu3.iew.wb_sent 292703
2135system.cpu3.iew.wb_count 292189
2136system.cpu3.iew.wb_producers 166184
2137system.cpu3.iew.wb_consumers 173731
2138system.cpu3.iew.wb_rate 1.512428
2139system.cpu3.iew.wb_fanout 0.956559
2140system.cpu3.commit.commitSquashedInsts 25409
2141system.cpu3.commit.commitNonSpecStalls 5851
2142system.cpu3.commit.branchMispredicts 2352
2143system.cpu3.commit.committed_per_cycle::samples 186670
2144system.cpu3.commit.committed_per_cycle::mean 1.756683
2145system.cpu3.commit.committed_per_cycle::stdev 2.084505
2146system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00%
2147system.cpu3.commit.committed_per_cycle::0 71411 38.26% 38.26%
2148system.cpu3.commit.committed_per_cycle::1 56079 30.04% 68.30%
2149system.cpu3.commit.committed_per_cycle::2 5419 2.90% 71.20%
2150system.cpu3.commit.committed_per_cycle::3 6543 3.51% 74.71%
2151system.cpu3.commit.committed_per_cycle::4 1250 0.67% 75.37%
2152system.cpu3.commit.committed_per_cycle::5 42928 23.00% 98.37%
2153system.cpu3.commit.committed_per_cycle::6 773 0.41% 98.79%
2154system.cpu3.commit.committed_per_cycle::7 1040 0.56% 99.34%
2155system.cpu3.commit.committed_per_cycle::8 1227 0.66% 100.00%
2156system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00%
2157system.cpu3.commit.committed_per_cycle::min_value 0
2158system.cpu3.commit.committed_per_cycle::max_value 8
2159system.cpu3.commit.committed_per_cycle::total 186670
2160system.cpu3.commit.committedInsts 327920
2161system.cpu3.commit.committedOps 327920
2162system.cpu3.commit.swp_count 0
2163system.cpu3.commit.refs 144195
2164system.cpu3.commit.loads 97671
2165system.cpu3.commit.membars 5137
2166system.cpu3.commit.branches 57626
2167system.cpu3.commit.fp_insts 0
2168system.cpu3.commit.int_insts 223941
2169system.cpu3.commit.function_calls 322
2170system.cpu3.commit.op_class_0::No_OpClass 48416 14.76% 14.76%
2171system.cpu3.commit.op_class_0::IntAlu 130172 39.70% 54.46%
2172system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.46%
2173system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.46%
2174system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.46%
2175system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.46%
2176system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.46%
2177system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.46%
2178system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 54.46%
2179system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.46%
2180system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 54.46%
2181system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.46%
2182system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.46%
2183system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.46%
2184system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.46%
2185system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.46%
2186system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.46%
2187system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.46%
2188system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.46%
2189system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.46%
2190system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.46%
2191system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.46%
2192system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.46%
2193system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.46%
2194system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.46%
2195system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.46%
2196system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.46%
2197system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.46%
2198system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.46%
2199system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.46%
2200system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.46%
2201system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.46%
2202system.cpu3.commit.op_class_0::MemRead 102808 31.35% 85.81%
2203system.cpu3.commit.op_class_0::MemWrite 46524 14.19% 100.00%
2204system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00%
2205system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00%
2206system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00%
2207system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
2208system.cpu3.commit.op_class_0::total 327920
2209system.cpu3.commit.bw_lim_events 1227
2210system.cpu3.rob.rob_reads 538186
2211system.cpu3.rob.rob_writes 711575
2212system.cpu3.timesIdled 229
2213system.cpu3.idleCycles 1646
2214system.cpu3.quiesceCycles 50195
2215system.cpu3.committedInsts 274367
2216system.cpu3.committedOps 274367
2217system.cpu3.cpi 0.704137
2218system.cpu3.cpi_total 0.704137
2219system.cpu3.ipc 1.420178
2220system.cpu3.ipc_total 1.420178
2221system.cpu3.int_regfile_reads 509137
2222system.cpu3.int_regfile_writes 236602
2223system.cpu3.fp_regfile_writes 64
2224system.cpu3.misc_regfile_reads 150205
2225system.cpu3.misc_regfile_writes 652
2226system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
2227system.cpu3.dcache.tags.replacements 0
2228system.cpu3.dcache.tags.tagsinuse 26.193054
2229system.cpu3.dcache.tags.total_refs 53586
2230system.cpu3.dcache.tags.sampled_refs 30
2231system.cpu3.dcache.tags.avg_refs 1786.200000
2232system.cpu3.dcache.tags.warmup_cycle 0
2233system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.193054
2234system.cpu3.dcache.tags.occ_percent::cpu3.data 0.051158
2235system.cpu3.dcache.tags.occ_percent::total 0.051158
2236system.cpu3.dcache.tags.occ_task_id_blocks::1024 30
2237system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26
2238system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4
2239system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594
2240system.cpu3.dcache.tags.tag_accesses 417128
2241system.cpu3.dcache.tags.data_accesses 417128
2242system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 126524000
2243system.cpu3.dcache.ReadReq_hits::cpu3.data 57193
2244system.cpu3.dcache.ReadReq_hits::total 57193
2245system.cpu3.dcache.WriteReq_hits::cpu3.data 46316
2246system.cpu3.dcache.WriteReq_hits::total 46316
2247system.cpu3.dcache.SwapReq_hits::cpu3.data 12
2248system.cpu3.dcache.SwapReq_hits::total 12
2249system.cpu3.dcache.demand_hits::cpu3.data 103509
2250system.cpu3.dcache.demand_hits::total 103509
2251system.cpu3.dcache.overall_hits::cpu3.data 103509
2252system.cpu3.dcache.overall_hits::total 103509
2253system.cpu3.dcache.ReadReq_misses::cpu3.data 502
2254system.cpu3.dcache.ReadReq_misses::total 502
2255system.cpu3.dcache.WriteReq_misses::cpu3.data 140
2256system.cpu3.dcache.WriteReq_misses::total 140
2257system.cpu3.dcache.SwapReq_misses::cpu3.data 56
2258system.cpu3.dcache.SwapReq_misses::total 56
2259system.cpu3.dcache.demand_misses::cpu3.data 642
2260system.cpu3.dcache.demand_misses::total 642
2261system.cpu3.dcache.overall_misses::cpu3.data 642
2262system.cpu3.dcache.overall_misses::total 642
2263system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3817000
2264system.cpu3.dcache.ReadReq_miss_latency::total 3817000
2265system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2858000
2266system.cpu3.dcache.WriteReq_miss_latency::total 2858000
2267system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 340000
2268system.cpu3.dcache.SwapReq_miss_latency::total 340000
2269system.cpu3.dcache.demand_miss_latency::cpu3.data 6675000
2270system.cpu3.dcache.demand_miss_latency::total 6675000
2271system.cpu3.dcache.overall_miss_latency::cpu3.data 6675000
2272system.cpu3.dcache.overall_miss_latency::total 6675000
2273system.cpu3.dcache.ReadReq_accesses::cpu3.data 57695
2274system.cpu3.dcache.ReadReq_accesses::total 57695
2275system.cpu3.dcache.WriteReq_accesses::cpu3.data 46456
2276system.cpu3.dcache.WriteReq_accesses::total 46456
2277system.cpu3.dcache.SwapReq_accesses::cpu3.data 68
2278system.cpu3.dcache.SwapReq_accesses::total 68
2279system.cpu3.dcache.demand_accesses::cpu3.data 104151
2280system.cpu3.dcache.demand_accesses::total 104151
2281system.cpu3.dcache.overall_accesses::cpu3.data 104151
2282system.cpu3.dcache.overall_accesses::total 104151
2283system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008701
2284system.cpu3.dcache.ReadReq_miss_rate::total 0.008701
2285system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003014
2286system.cpu3.dcache.WriteReq_miss_rate::total 0.003014
2287system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.823529
2288system.cpu3.dcache.SwapReq_miss_rate::total 0.823529
2289system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006164
2290system.cpu3.dcache.demand_miss_rate::total 0.006164
2291system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006164
2292system.cpu3.dcache.overall_miss_rate::total 0.006164
2293system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7603.585657
2294system.cpu3.dcache.ReadReq_avg_miss_latency::total 7603.585657
2295system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20414.285714
2296system.cpu3.dcache.WriteReq_avg_miss_latency::total 20414.285714
2297system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6071.428571
2298system.cpu3.dcache.SwapReq_avg_miss_latency::total 6071.428571
2299system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10397.196262
2300system.cpu3.dcache.demand_avg_miss_latency::total 10397.196262
2301system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10397.196262
2302system.cpu3.dcache.overall_avg_miss_latency::total 10397.196262
2303system.cpu3.dcache.blocked_cycles::no_mshrs 0
2304system.cpu3.dcache.blocked_cycles::no_targets 0
2305system.cpu3.dcache.blocked::no_mshrs 0
2306system.cpu3.dcache.blocked::no_targets 0
2307system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
2308system.cpu3.dcache.avg_blocked_cycles::no_targets nan
2309system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 340
2310system.cpu3.dcache.ReadReq_mshr_hits::total 340
2311system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34
2312system.cpu3.dcache.WriteReq_mshr_hits::total 34
2313system.cpu3.dcache.demand_mshr_hits::cpu3.data 374
2314system.cpu3.dcache.demand_mshr_hits::total 374
2315system.cpu3.dcache.overall_mshr_hits::cpu3.data 374
2316system.cpu3.dcache.overall_mshr_hits::total 374
2317system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162
2318system.cpu3.dcache.ReadReq_mshr_misses::total 162
2319system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106
2320system.cpu3.dcache.WriteReq_mshr_misses::total 106
2321system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56
2322system.cpu3.dcache.SwapReq_mshr_misses::total 56
2323system.cpu3.dcache.demand_mshr_misses::cpu3.data 268
2324system.cpu3.dcache.demand_mshr_misses::total 268
2325system.cpu3.dcache.overall_mshr_misses::cpu3.data 268
2326system.cpu3.dcache.overall_mshr_misses::total 268
2327system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1182500
2328system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1182500
2329system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1396000
2330system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1396000
2331system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 284000
2332system.cpu3.dcache.SwapReq_mshr_miss_latency::total 284000
2333system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2578500
2334system.cpu3.dcache.demand_mshr_miss_latency::total 2578500
2335system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2578500
2336system.cpu3.dcache.overall_mshr_miss_latency::total 2578500
2337system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002808
2338system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002808
2339system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002282
2340system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002282
2341system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.823529
2342system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.823529
2343system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002573
2344system.cpu3.dcache.demand_mshr_miss_rate::total 0.002573
2345system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002573
2346system.cpu3.dcache.overall_mshr_miss_rate::total 0.002573
2347system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7299.382716
2348system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7299.382716
2349system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13169.811321
2350system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13169.811321
2351system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5071.428571
2352system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5071.428571
2353system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9621.268657
2354system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9621.268657
2355system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9621.268657
2356system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9621.268657
2357system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000
2358system.cpu3.icache.tags.replacements 589
2359system.cpu3.icache.tags.tagsinuse 95.413384
2360system.cpu3.icache.tags.total_refs 23771
2361system.cpu3.icache.tags.sampled_refs 723
2362system.cpu3.icache.tags.avg_refs 32.878285
2363system.cpu3.icache.tags.warmup_cycle 0
2364system.cpu3.icache.tags.occ_blocks::cpu3.inst 95.413384
2365system.cpu3.icache.tags.occ_percent::cpu3.inst 0.186354
2366system.cpu3.icache.tags.occ_percent::total 0.186354
2367system.cpu3.icache.tags.occ_task_id_blocks::1024 134
2368system.cpu3.icache.tags.age_task_id_blocks_1024::0 2
2369system.cpu3.icache.tags.age_task_id_blocks_1024::1 120
2370system.cpu3.icache.tags.age_task_id_blocks_1024::2 12
2371system.cpu3.icache.tags.occ_task_id_percent::1024 0.261719
2372system.cpu3.icache.tags.tag_accesses 25354
2373system.cpu3.icache.tags.data_accesses 25354
2374system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 126524000
2375system.cpu3.icache.ReadReq_hits::cpu3.inst 23771
2376system.cpu3.icache.ReadReq_hits::total 23771
2377system.cpu3.icache.demand_hits::cpu3.inst 23771
2378system.cpu3.icache.demand_hits::total 23771
2379system.cpu3.icache.overall_hits::cpu3.inst 23771
2380system.cpu3.icache.overall_hits::total 23771
2381system.cpu3.icache.ReadReq_misses::cpu3.inst 860
2382system.cpu3.icache.ReadReq_misses::total 860
2383system.cpu3.icache.demand_misses::cpu3.inst 860
2384system.cpu3.icache.demand_misses::total 860
2385system.cpu3.icache.overall_misses::cpu3.inst 860
2386system.cpu3.icache.overall_misses::total 860
2387system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 13120500
2388system.cpu3.icache.ReadReq_miss_latency::total 13120500
2389system.cpu3.icache.demand_miss_latency::cpu3.inst 13120500
2390system.cpu3.icache.demand_miss_latency::total 13120500
2391system.cpu3.icache.overall_miss_latency::cpu3.inst 13120500
2392system.cpu3.icache.overall_miss_latency::total 13120500
2393system.cpu3.icache.ReadReq_accesses::cpu3.inst 24631
2394system.cpu3.icache.ReadReq_accesses::total 24631
2395system.cpu3.icache.demand_accesses::cpu3.inst 24631
2396system.cpu3.icache.demand_accesses::total 24631
2397system.cpu3.icache.overall_accesses::cpu3.inst 24631
2398system.cpu3.icache.overall_accesses::total 24631
2399system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.034915
2400system.cpu3.icache.ReadReq_miss_rate::total 0.034915
2401system.cpu3.icache.demand_miss_rate::cpu3.inst 0.034915
2402system.cpu3.icache.demand_miss_rate::total 0.034915
2403system.cpu3.icache.overall_miss_rate::cpu3.inst 0.034915
2404system.cpu3.icache.overall_miss_rate::total 0.034915
2405system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15256.395349
2406system.cpu3.icache.ReadReq_avg_miss_latency::total 15256.395349
2407system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15256.395349
2408system.cpu3.icache.demand_avg_miss_latency::total 15256.395349
2409system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15256.395349
2410system.cpu3.icache.overall_avg_miss_latency::total 15256.395349
2411system.cpu3.icache.blocked_cycles::no_mshrs 0
2412system.cpu3.icache.blocked_cycles::no_targets 0
2413system.cpu3.icache.blocked::no_mshrs 0
2414system.cpu3.icache.blocked::no_targets 0
2415system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
2416system.cpu3.icache.avg_blocked_cycles::no_targets nan
2417system.cpu3.icache.writebacks::writebacks 589
2418system.cpu3.icache.writebacks::total 589
2419system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 137
2420system.cpu3.icache.ReadReq_mshr_hits::total 137
2421system.cpu3.icache.demand_mshr_hits::cpu3.inst 137
2422system.cpu3.icache.demand_mshr_hits::total 137
2423system.cpu3.icache.overall_mshr_hits::cpu3.inst 137
2424system.cpu3.icache.overall_mshr_hits::total 137
2425system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 723
2426system.cpu3.icache.ReadReq_mshr_misses::total 723
2427system.cpu3.icache.demand_mshr_misses::cpu3.inst 723
2428system.cpu3.icache.demand_mshr_misses::total 723
2429system.cpu3.icache.overall_mshr_misses::cpu3.inst 723
2430system.cpu3.icache.overall_mshr_misses::total 723
2431system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11427500
2432system.cpu3.icache.ReadReq_mshr_miss_latency::total 11427500
2433system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11427500
2434system.cpu3.icache.demand_mshr_miss_latency::total 11427500
2435system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11427500
2436system.cpu3.icache.overall_mshr_miss_latency::total 11427500
2437system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.029353
2438system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.029353
2439system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.029353
2440system.cpu3.icache.demand_mshr_miss_rate::total 0.029353
2441system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.029353
2442system.cpu3.icache.overall_mshr_miss_rate::total 0.029353
2443system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15805.670816
2444system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15805.670816
2445system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15805.670816
2446system.cpu3.icache.demand_avg_mshr_miss_latency::total 15805.670816
2447system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15805.670816
2448system.cpu3.icache.overall_avg_mshr_miss_latency::total 15805.670816
2449system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 126524000
2450system.l2c.tags.replacements 0
2451system.l2c.tags.tagsinuse 563.321355
2452system.l2c.tags.total_refs 3204
2453system.l2c.tags.sampled_refs 706
2454system.l2c.tags.avg_refs 4.538244
2455system.l2c.tags.warmup_cycle 0
2456system.l2c.tags.occ_blocks::cpu0.inst 296.928117
2457system.l2c.tags.occ_blocks::cpu0.data 144.858983
2458system.l2c.tags.occ_blocks::cpu1.inst 69.416277
2459system.l2c.tags.occ_blocks::cpu1.data 15.941995
2460system.l2c.tags.occ_blocks::cpu2.inst 8.217801
2461system.l2c.tags.occ_blocks::cpu2.data 9.832103
2462system.l2c.tags.occ_blocks::cpu3.inst 7.210411
2463system.l2c.tags.occ_blocks::cpu3.data 10.915668
2464system.l2c.tags.occ_percent::cpu0.inst 0.004531
2465system.l2c.tags.occ_percent::cpu0.data 0.002210
2466system.l2c.tags.occ_percent::cpu1.inst 0.001059
2467system.l2c.tags.occ_percent::cpu1.data 0.000243
2468system.l2c.tags.occ_percent::cpu2.inst 0.000125
2469system.l2c.tags.occ_percent::cpu2.data 0.000150
2470system.l2c.tags.occ_percent::cpu3.inst 0.000110
2471system.l2c.tags.occ_percent::cpu3.data 0.000167
2472system.l2c.tags.occ_percent::total 0.008596
2473system.l2c.tags.occ_task_id_blocks::1024 706
2474system.l2c.tags.age_task_id_blocks_1024::0 52
2475system.l2c.tags.age_task_id_blocks_1024::1 137
2476system.l2c.tags.age_task_id_blocks_1024::2 517
2477system.l2c.tags.occ_task_id_percent::1024 0.010773
2478system.l2c.tags.tag_accesses 32122
2479system.l2c.tags.data_accesses 32122
2480system.l2c.pwrStateResidencyTicks::UNDEFINED 126524000
2481system.l2c.WritebackDirty_hits::writebacks 1
2482system.l2c.WritebackDirty_hits::total 1
2483system.l2c.WritebackClean_hits::writebacks 764
2484system.l2c.WritebackClean_hits::total 764
2485system.l2c.UpgradeReq_hits::cpu0.data 24
2486system.l2c.UpgradeReq_hits::cpu1.data 24
2487system.l2c.UpgradeReq_hits::cpu2.data 23
2488system.l2c.UpgradeReq_hits::cpu3.data 21
2489system.l2c.UpgradeReq_hits::total 92
2490system.l2c.ReadCleanReq_hits::cpu0.inst 318
2491system.l2c.ReadCleanReq_hits::cpu1.inst 642
2492system.l2c.ReadCleanReq_hits::cpu2.inst 646
2493system.l2c.ReadCleanReq_hits::cpu3.inst 708
2494system.l2c.ReadCleanReq_hits::total 2314
2495system.l2c.ReadSharedReq_hits::cpu0.data 5
2496system.l2c.ReadSharedReq_hits::cpu1.data 5
2497system.l2c.ReadSharedReq_hits::cpu2.data 11
2498system.l2c.ReadSharedReq_hits::cpu3.data 11
2499system.l2c.ReadSharedReq_hits::total 32
2500system.l2c.demand_hits::cpu0.inst 318
2501system.l2c.demand_hits::cpu0.data 5
2502system.l2c.demand_hits::cpu1.inst 642
2503system.l2c.demand_hits::cpu1.data 5
2504system.l2c.demand_hits::cpu2.inst 646
2505system.l2c.demand_hits::cpu2.data 11
2506system.l2c.demand_hits::cpu3.inst 708
2507system.l2c.demand_hits::cpu3.data 11
2508system.l2c.demand_hits::total 2346
2509system.l2c.overall_hits::cpu0.inst 318
2510system.l2c.overall_hits::cpu0.data 5
2511system.l2c.overall_hits::cpu1.inst 642
2512system.l2c.overall_hits::cpu1.data 5
2513system.l2c.overall_hits::cpu2.inst 646
2514system.l2c.overall_hits::cpu2.data 11
2515system.l2c.overall_hits::cpu3.inst 708
2516system.l2c.overall_hits::cpu3.data 11
2517system.l2c.overall_hits::total 2346
2518system.l2c.ReadExReq_misses::cpu0.data 94
2519system.l2c.ReadExReq_misses::cpu1.data 13
2520system.l2c.ReadExReq_misses::cpu2.data 12
2521system.l2c.ReadExReq_misses::cpu3.data 12
2522system.l2c.ReadExReq_misses::total 131
2523system.l2c.ReadCleanReq_misses::cpu0.inst 372
2524system.l2c.ReadCleanReq_misses::cpu1.inst 95
2525system.l2c.ReadCleanReq_misses::cpu2.inst 22
2526system.l2c.ReadCleanReq_misses::cpu3.inst 15
2527system.l2c.ReadCleanReq_misses::total 504
2528system.l2c.ReadSharedReq_misses::cpu0.data 75
2529system.l2c.ReadSharedReq_misses::cpu1.data 8
2530system.l2c.ReadSharedReq_misses::cpu2.data 2
2531system.l2c.ReadSharedReq_misses::cpu3.data 3
2532system.l2c.ReadSharedReq_misses::total 88
2533system.l2c.demand_misses::cpu0.inst 372
2534system.l2c.demand_misses::cpu0.data 169
2535system.l2c.demand_misses::cpu1.inst 95
2536system.l2c.demand_misses::cpu1.data 21
2537system.l2c.demand_misses::cpu2.inst 22
2538system.l2c.demand_misses::cpu2.data 14
2539system.l2c.demand_misses::cpu3.inst 15
2540system.l2c.demand_misses::cpu3.data 15
2541system.l2c.demand_misses::total 723
2542system.l2c.overall_misses::cpu0.inst 372
2543system.l2c.overall_misses::cpu0.data 169
2544system.l2c.overall_misses::cpu1.inst 95
2545system.l2c.overall_misses::cpu1.data 21
2546system.l2c.overall_misses::cpu2.inst 22
2547system.l2c.overall_misses::cpu2.data 14
2548system.l2c.overall_misses::cpu3.inst 15
2549system.l2c.overall_misses::cpu3.data 15
2550system.l2c.overall_misses::total 723
2551system.l2c.ReadExReq_miss_latency::cpu0.data 7911000
2552system.l2c.ReadExReq_miss_latency::cpu1.data 1069500
2553system.l2c.ReadExReq_miss_latency::cpu2.data 1214500
2554system.l2c.ReadExReq_miss_latency::cpu3.data 955500
2555system.l2c.ReadExReq_miss_latency::total 11150500
2556system.l2c.ReadCleanReq_miss_latency::cpu0.inst 31119000
2557system.l2c.ReadCleanReq_miss_latency::cpu1.inst 8458500
2558system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2352500
2559system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2347000
2560system.l2c.ReadCleanReq_miss_latency::total 44277000
2561system.l2c.ReadSharedReq_miss_latency::cpu0.data 6607000
2562system.l2c.ReadSharedReq_miss_latency::cpu1.data 681000
2563system.l2c.ReadSharedReq_miss_latency::cpu2.data 179500
2564system.l2c.ReadSharedReq_miss_latency::cpu3.data 296500
2565system.l2c.ReadSharedReq_miss_latency::total 7764000
2566system.l2c.demand_miss_latency::cpu0.inst 31119000
2567system.l2c.demand_miss_latency::cpu0.data 14518000
2568system.l2c.demand_miss_latency::cpu1.inst 8458500
2569system.l2c.demand_miss_latency::cpu1.data 1750500
2570system.l2c.demand_miss_latency::cpu2.inst 2352500
2571system.l2c.demand_miss_latency::cpu2.data 1394000
2572system.l2c.demand_miss_latency::cpu3.inst 2347000
2573system.l2c.demand_miss_latency::cpu3.data 1252000
2574system.l2c.demand_miss_latency::total 63191500
2575system.l2c.overall_miss_latency::cpu0.inst 31119000
2576system.l2c.overall_miss_latency::cpu0.data 14518000
2577system.l2c.overall_miss_latency::cpu1.inst 8458500
2578system.l2c.overall_miss_latency::cpu1.data 1750500
2579system.l2c.overall_miss_latency::cpu2.inst 2352500
2580system.l2c.overall_miss_latency::cpu2.data 1394000
2581system.l2c.overall_miss_latency::cpu3.inst 2347000
2582system.l2c.overall_miss_latency::cpu3.data 1252000
2583system.l2c.overall_miss_latency::total 63191500
2584system.l2c.WritebackDirty_accesses::writebacks 1
2585system.l2c.WritebackDirty_accesses::total 1
2586system.l2c.WritebackClean_accesses::writebacks 764
2587system.l2c.WritebackClean_accesses::total 764
2588system.l2c.UpgradeReq_accesses::cpu0.data 24
2589system.l2c.UpgradeReq_accesses::cpu1.data 24
2590system.l2c.UpgradeReq_accesses::cpu2.data 23
2591system.l2c.UpgradeReq_accesses::cpu3.data 21
2592system.l2c.UpgradeReq_accesses::total 92
2593system.l2c.ReadExReq_accesses::cpu0.data 94
2594system.l2c.ReadExReq_accesses::cpu1.data 13
2595system.l2c.ReadExReq_accesses::cpu2.data 12
2596system.l2c.ReadExReq_accesses::cpu3.data 12
2597system.l2c.ReadExReq_accesses::total 131
2598system.l2c.ReadCleanReq_accesses::cpu0.inst 690
2599system.l2c.ReadCleanReq_accesses::cpu1.inst 737
2600system.l2c.ReadCleanReq_accesses::cpu2.inst 668
2601system.l2c.ReadCleanReq_accesses::cpu3.inst 723
2602system.l2c.ReadCleanReq_accesses::total 2818
2603system.l2c.ReadSharedReq_accesses::cpu0.data 80
2604system.l2c.ReadSharedReq_accesses::cpu1.data 13
2605system.l2c.ReadSharedReq_accesses::cpu2.data 13
2606system.l2c.ReadSharedReq_accesses::cpu3.data 14
2607system.l2c.ReadSharedReq_accesses::total 120
2608system.l2c.demand_accesses::cpu0.inst 690
2609system.l2c.demand_accesses::cpu0.data 174
2610system.l2c.demand_accesses::cpu1.inst 737
2611system.l2c.demand_accesses::cpu1.data 26
2612system.l2c.demand_accesses::cpu2.inst 668
2613system.l2c.demand_accesses::cpu2.data 25
2614system.l2c.demand_accesses::cpu3.inst 723
2615system.l2c.demand_accesses::cpu3.data 26
2616system.l2c.demand_accesses::total 3069
2617system.l2c.overall_accesses::cpu0.inst 690
2618system.l2c.overall_accesses::cpu0.data 174
2619system.l2c.overall_accesses::cpu1.inst 737
2620system.l2c.overall_accesses::cpu1.data 26
2621system.l2c.overall_accesses::cpu2.inst 668
2622system.l2c.overall_accesses::cpu2.data 25
2623system.l2c.overall_accesses::cpu3.inst 723
2624system.l2c.overall_accesses::cpu3.data 26
2625system.l2c.overall_accesses::total 3069
2626system.l2c.ReadExReq_miss_rate::cpu0.data 1
2627system.l2c.ReadExReq_miss_rate::cpu1.data 1
2628system.l2c.ReadExReq_miss_rate::cpu2.data 1
2629system.l2c.ReadExReq_miss_rate::cpu3.data 1
2630system.l2c.ReadExReq_miss_rate::total 1
2631system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.539130
2632system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.128901
2633system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.032934
2634system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.020747
2635system.l2c.ReadCleanReq_miss_rate::total 0.178850
2636system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500
2637system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.615385
2638system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.153846
2639system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.214286
2640system.l2c.ReadSharedReq_miss_rate::total 0.733333
2641system.l2c.demand_miss_rate::cpu0.inst 0.539130
2642system.l2c.demand_miss_rate::cpu0.data 0.971264
2643system.l2c.demand_miss_rate::cpu1.inst 0.128901
2644system.l2c.demand_miss_rate::cpu1.data 0.807692
2645system.l2c.demand_miss_rate::cpu2.inst 0.032934
2646system.l2c.demand_miss_rate::cpu2.data 0.560000
2647system.l2c.demand_miss_rate::cpu3.inst 0.020747
2648system.l2c.demand_miss_rate::cpu3.data 0.576923
2649system.l2c.demand_miss_rate::total 0.235582
2650system.l2c.overall_miss_rate::cpu0.inst 0.539130
2651system.l2c.overall_miss_rate::cpu0.data 0.971264
2652system.l2c.overall_miss_rate::cpu1.inst 0.128901
2653system.l2c.overall_miss_rate::cpu1.data 0.807692
2654system.l2c.overall_miss_rate::cpu2.inst 0.032934
2655system.l2c.overall_miss_rate::cpu2.data 0.560000
2656system.l2c.overall_miss_rate::cpu3.inst 0.020747
2657system.l2c.overall_miss_rate::cpu3.data 0.576923
2658system.l2c.overall_miss_rate::total 0.235582
2659system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84159.574468
2660system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82269.230769
2661system.l2c.ReadExReq_avg_miss_latency::cpu2.data 101208.333333
2662system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79625
2663system.l2c.ReadExReq_avg_miss_latency::total 85118.320611
2664system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 83653.225806
2665system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 89036.842105
2666system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 106931.818182
2667system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 156466.666667
2668system.l2c.ReadCleanReq_avg_miss_latency::total 87851.190476
2669system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88093.333333
2670system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85125
2671system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 89750
2672system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 98833.333333
2673system.l2c.ReadSharedReq_avg_miss_latency::total 88227.272727
2674system.l2c.demand_avg_miss_latency::cpu0.inst 83653.225806
2675system.l2c.demand_avg_miss_latency::cpu0.data 85905.325444
2676system.l2c.demand_avg_miss_latency::cpu1.inst 89036.842105
2677system.l2c.demand_avg_miss_latency::cpu1.data 83357.142857
2678system.l2c.demand_avg_miss_latency::cpu2.inst 106931.818182
2679system.l2c.demand_avg_miss_latency::cpu2.data 99571.428571
2680system.l2c.demand_avg_miss_latency::cpu3.inst 156466.666667
2681system.l2c.demand_avg_miss_latency::cpu3.data 83466.666667
2682system.l2c.demand_avg_miss_latency::total 87401.798064
2683system.l2c.overall_avg_miss_latency::cpu0.inst 83653.225806
2684system.l2c.overall_avg_miss_latency::cpu0.data 85905.325444
2685system.l2c.overall_avg_miss_latency::cpu1.inst 89036.842105
2686system.l2c.overall_avg_miss_latency::cpu1.data 83357.142857
2687system.l2c.overall_avg_miss_latency::cpu2.inst 106931.818182
2688system.l2c.overall_avg_miss_latency::cpu2.data 99571.428571
2689system.l2c.overall_avg_miss_latency::cpu3.inst 156466.666667
2690system.l2c.overall_avg_miss_latency::cpu3.data 83466.666667
2691system.l2c.overall_avg_miss_latency::total 87401.798064
2692system.l2c.blocked_cycles::no_mshrs 0
2693system.l2c.blocked_cycles::no_targets 0
2694system.l2c.blocked::no_mshrs 0
2695system.l2c.blocked::no_targets 0
2696system.l2c.avg_blocked_cycles::no_mshrs nan
2697system.l2c.avg_blocked_cycles::no_targets nan
2698system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2
2699system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 3
2700system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8
2701system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3
2702system.l2c.ReadCleanReq_mshr_hits::total 16
2703system.l2c.demand_mshr_hits::cpu0.inst 2
2704system.l2c.demand_mshr_hits::cpu1.inst 3
2705system.l2c.demand_mshr_hits::cpu2.inst 8
2706system.l2c.demand_mshr_hits::cpu3.inst 3
2707system.l2c.demand_mshr_hits::total 16
2708system.l2c.overall_mshr_hits::cpu0.inst 2
2709system.l2c.overall_mshr_hits::cpu1.inst 3
2710system.l2c.overall_mshr_hits::cpu2.inst 8
2711system.l2c.overall_mshr_hits::cpu3.inst 3
2712system.l2c.overall_mshr_hits::total 16
2713system.l2c.ReadExReq_mshr_misses::cpu0.data 94
2714system.l2c.ReadExReq_mshr_misses::cpu1.data 13
2715system.l2c.ReadExReq_mshr_misses::cpu2.data 12
2716system.l2c.ReadExReq_mshr_misses::cpu3.data 12
2717system.l2c.ReadExReq_mshr_misses::total 131
2718system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 370
2719system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92
2720system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14
2721system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 12
2722system.l2c.ReadCleanReq_mshr_misses::total 488
2723system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75
2724system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8
2725system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2
2726system.l2c.ReadSharedReq_mshr_misses::cpu3.data 3
2727system.l2c.ReadSharedReq_mshr_misses::total 88
2728system.l2c.demand_mshr_misses::cpu0.inst 370
2729system.l2c.demand_mshr_misses::cpu0.data 169
2730system.l2c.demand_mshr_misses::cpu1.inst 92
2731system.l2c.demand_mshr_misses::cpu1.data 21
2732system.l2c.demand_mshr_misses::cpu2.inst 14
2733system.l2c.demand_mshr_misses::cpu2.data 14
2734system.l2c.demand_mshr_misses::cpu3.inst 12
2735system.l2c.demand_mshr_misses::cpu3.data 15
2736system.l2c.demand_mshr_misses::total 707
2737system.l2c.overall_mshr_misses::cpu0.inst 370
2738system.l2c.overall_mshr_misses::cpu0.data 169
2739system.l2c.overall_mshr_misses::cpu1.inst 92
2740system.l2c.overall_mshr_misses::cpu1.data 21
2741system.l2c.overall_mshr_misses::cpu2.inst 14
2742system.l2c.overall_mshr_misses::cpu2.data 14
2743system.l2c.overall_mshr_misses::cpu3.inst 12
2744system.l2c.overall_mshr_misses::cpu3.data 15
2745system.l2c.overall_mshr_misses::total 707
2746system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6971000
2747system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 939500
2748system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1094500
2749system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 835500
2750system.l2c.ReadExReq_mshr_miss_latency::total 9840500
2751system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 27347000
2752system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 7457000
2753system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1636500
2754system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2047500
2755system.l2c.ReadCleanReq_mshr_miss_latency::total 38488000
2756system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5857000
2757system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 601000
2758system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 159500
2759system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 266500
2760system.l2c.ReadSharedReq_mshr_miss_latency::total 6884000
2761system.l2c.demand_mshr_miss_latency::cpu0.inst 27347000
2762system.l2c.demand_mshr_miss_latency::cpu0.data 12828000
2763system.l2c.demand_mshr_miss_latency::cpu1.inst 7457000
2764system.l2c.demand_mshr_miss_latency::cpu1.data 1540500
2765system.l2c.demand_mshr_miss_latency::cpu2.inst 1636500
2766system.l2c.demand_mshr_miss_latency::cpu2.data 1254000
2767system.l2c.demand_mshr_miss_latency::cpu3.inst 2047500
2768system.l2c.demand_mshr_miss_latency::cpu3.data 1102000
2769system.l2c.demand_mshr_miss_latency::total 55212500
2770system.l2c.overall_mshr_miss_latency::cpu0.inst 27347000
2771system.l2c.overall_mshr_miss_latency::cpu0.data 12828000
2772system.l2c.overall_mshr_miss_latency::cpu1.inst 7457000
2773system.l2c.overall_mshr_miss_latency::cpu1.data 1540500
2774system.l2c.overall_mshr_miss_latency::cpu2.inst 1636500
2775system.l2c.overall_mshr_miss_latency::cpu2.data 1254000
2776system.l2c.overall_mshr_miss_latency::cpu3.inst 2047500
2777system.l2c.overall_mshr_miss_latency::cpu3.data 1102000
2778system.l2c.overall_mshr_miss_latency::total 55212500
2779system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1
2780system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1
2781system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1
2782system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1
2783system.l2c.ReadExReq_mshr_miss_rate::total 1
2784system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.536232
2785system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.124830
2786system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.020958
2787system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.016598
2788system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173172
2789system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500
2790system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.615385
2791system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.153846
2792system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286
2793system.l2c.ReadSharedReq_mshr_miss_rate::total 0.733333
2794system.l2c.demand_mshr_miss_rate::cpu0.inst 0.536232
2795system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264
2796system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124830
2797system.l2c.demand_mshr_miss_rate::cpu1.data 0.807692
2798system.l2c.demand_mshr_miss_rate::cpu2.inst 0.020958
2799system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000
2800system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016598
2801system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923
2802system.l2c.demand_mshr_miss_rate::total 0.230368
2803system.l2c.overall_mshr_miss_rate::cpu0.inst 0.536232
2804system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264
2805system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124830
2806system.l2c.overall_mshr_miss_rate::cpu1.data 0.807692
2807system.l2c.overall_mshr_miss_rate::cpu2.inst 0.020958
2808system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000
2809system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016598
2810system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923
2811system.l2c.overall_mshr_miss_rate::total 0.230368
2812system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74159.574468
2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72269.230769
2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 91208.333333
2815system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69625
2816system.l2c.ReadExReq_avg_mshr_miss_latency::total 75118.320611
2817system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73910.810811
2818system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 81054.347826
2819system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 116892.857143
2820system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 170625
2821system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78868.852459
2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78093.333333
2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75125
2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79750
2825system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 88833.333333
2826system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78227.272727
2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73910.810811
2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75905.325444
2829system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 81054.347826
2830system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73357.142857
2831system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 116892.857143
2832system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89571.428571
2833system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 170625
2834system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73466.666667
2835system.l2c.demand_avg_mshr_miss_latency::total 78094.059406
2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73910.810811
2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75905.325444
2838system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 81054.347826
2839system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73357.142857
2840system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 116892.857143
2841system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89571.428571
2842system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 170625
2843system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73466.666667
2844system.l2c.overall_avg_mshr_miss_latency::total 78094.059406
2845system.membus.snoop_filter.tot_requests 958
2846system.membus.snoop_filter.hit_single_requests 252
2847system.membus.snoop_filter.hit_multi_requests 0
2848system.membus.snoop_filter.tot_snoops 0
2849system.membus.snoop_filter.hit_single_snoops 0
2850system.membus.snoop_filter.hit_multi_snoops 0
2851system.membus.pwrStateResidencyTicks::UNDEFINED 126524000
2852system.membus.trans_dist::ReadResp 575
2853system.membus.trans_dist::UpgradeReq 198
2854system.membus.trans_dist::ReadExReq 185
2855system.membus.trans_dist::ReadExResp 131
2856system.membus.trans_dist::ReadSharedReq 575
2857system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1664
2858system.membus.pkt_count::total 1664
2859system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45184
2860system.membus.pkt_size::total 45184
2861system.membus.snoops 252
2862system.membus.snoopTraffic 0
2863system.membus.snoop_fanout::samples 958
2864system.membus.snoop_fanout::mean 0
2865system.membus.snoop_fanout::stdev 0
2866system.membus.snoop_fanout::underflows 0 0.00% 0.00%
2867system.membus.snoop_fanout::0 958 100.00% 100.00%
2868system.membus.snoop_fanout::1 0 0.00% 100.00%
2869system.membus.snoop_fanout::overflows 0 0.00% 100.00%
2870system.membus.snoop_fanout::min_value 0
2871system.membus.snoop_fanout::max_value 0
2872system.membus.snoop_fanout::total 958
2873system.membus.reqLayer0.occupancy 878500
2874system.membus.reqLayer0.utilization 0.7
2875system.membus.respLayer1.occupancy 3755250
2876system.membus.respLayer1.utilization 3.0
2877system.toL2Bus.snoop_filter.tot_requests 6322
2878system.toL2Bus.snoop_filter.hit_single_requests 1691
2879system.toL2Bus.snoop_filter.hit_multi_requests 3277
2880system.toL2Bus.snoop_filter.tot_snoops 0
2881system.toL2Bus.snoop_filter.hit_single_snoops 0
2882system.toL2Bus.snoop_filter.hit_multi_snoops 0
2883system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 126524000
2884system.toL2Bus.trans_dist::ReadResp 3512
2885system.toL2Bus.trans_dist::ReadRespWithInvalidate 6
2886system.toL2Bus.trans_dist::WritebackDirty 1
2887system.toL2Bus.trans_dist::WritebackClean 2113
2888system.toL2Bus.trans_dist::CleanEvict 1
2889system.toL2Bus.trans_dist::UpgradeReq 290
2890system.toL2Bus.trans_dist::UpgradeResp 290
2891system.toL2Bus.trans_dist::ReadExReq 398
2892system.toL2Bus.trans_dist::ReadExResp 398
2893system.toL2Bus.trans_dist::ReadCleanReq 2818
2894system.toL2Bus.trans_dist::ReadSharedReq 701
2895system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1768
2896system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 604
2897system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2076
2898system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367
2899system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1869
2900system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 392
2901system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2035
2902system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371
2903system.toL2Bus.pkt_count::total 9482
2904system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 68992
2905system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200
2906system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85696
2907system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664
2908system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 76864
2909system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600
2910system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83968
2911system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664
2912system.toL2Bus.pkt_size::total 331648
2913system.toL2Bus.snoops 1046
2914system.toL2Bus.snoopTraffic 54272
2915system.toL2Bus.snoop_fanout::samples 4207
2916system.toL2Bus.snoop_fanout::mean 1.309484
2917system.toL2Bus.snoop_fanout::stdev 1.132145
2918system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
2919system.toL2Bus.snoop_fanout::0 1354 32.18% 32.18%
2920system.toL2Bus.snoop_fanout::1 1089 25.89% 58.07%
2921system.toL2Bus.snoop_fanout::2 872 20.73% 78.80%
2922system.toL2Bus.snoop_fanout::3 892 21.20% 100.00%
2923system.toL2Bus.snoop_fanout::4 0 0.00% 100.00%
2924system.toL2Bus.snoop_fanout::5 0 0.00% 100.00%
2925system.toL2Bus.snoop_fanout::6 0 0.00% 100.00%
2926system.toL2Bus.snoop_fanout::7 0 0.00% 100.00%
2927system.toL2Bus.snoop_fanout::8 0 0.00% 100.00%
2928system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
2929system.toL2Bus.snoop_fanout::min_value 0
2930system.toL2Bus.snoop_fanout::max_value 3
2931system.toL2Bus.snoop_fanout::total 4207
2932system.toL2Bus.reqLayer0.occupancy 5288473
2933system.toL2Bus.reqLayer0.utilization 4.2
2934system.toL2Bus.respLayer0.occupancy 1034498
2935system.toL2Bus.respLayer0.utilization 0.8
2936system.toL2Bus.respLayer1.occupancy 532490
2937system.toL2Bus.respLayer1.utilization 0.4
2938system.toL2Bus.respLayer2.occupancy 1106497
2939system.toL2Bus.respLayer2.utilization 0.9
2940system.toL2Bus.respLayer3.occupancy 422474
2941system.toL2Bus.respLayer3.utilization 0.3
2942system.toL2Bus.respLayer4.occupancy 1006490
2943system.toL2Bus.respLayer4.utilization 0.8
2944system.toL2Bus.respLayer5.occupancy 458964
2945system.toL2Bus.respLayer5.utilization 0.4
2946system.toL2Bus.respLayer6.occupancy 1085498
2947system.toL2Bus.respLayer6.utilization 0.9
2948system.toL2Bus.respLayer7.occupancy 428967
2949system.toL2Bus.respLayer7.utilization 0.3
|