Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000125 # Number of seconds simulated
4sim_ticks 124830000 # Number of ticks simulated
5final_tick 124830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000126 # Number of seconds simulated
4sim_ticks 125996000 # Number of ticks simulated
5final_tick 125996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 284956 # Simulator instruction rate (inst/s)
8host_op_rate 284955 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30713692 # Simulator tick rate (ticks/s)
10host_mem_usage 268476 # Number of bytes of host memory used
11host_seconds 4.06 # Real time elapsed on the host
12sim_insts 1158143 # Number of instructions simulated
13sim_ops 1158143 # Number of ops (including micro ops) simulated

7host_inst_rate 71299 # Simulator instruction rate (inst/s)
8host_op_rate 71299 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 7711593 # Simulator tick rate (ticks/s)
10host_mem_usage 250104 # Number of bytes of host memory used
11host_seconds 16.34 # Real time elapsed on the host
12sim_insts 1164916 # Number of instructions simulated
13sim_ops 1164916 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory

16system.physmem.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 23872 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory

22system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.inst 896 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory
25system.physmem.bytes_read::total 45824 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory

22system.physmem.bytes_read::cpu2.data 896 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
25system.physmem.bytes_read::total 45440 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 23872 # Number of instructions bytes read from this memory

27system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory

29system.physmem.bytes_inst_read::cpu3.inst 896 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 31680 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory

29system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 373 # Number of read requests responded to by this memory

32system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory

36system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.inst 14 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory
39system.physmem.num_reads::total 716 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 192261476 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 87158536 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 47168149 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 11279340 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 7177762 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 7690459 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 7177762 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 7177762 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 367091244 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 192261476 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 47168149 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 7177762 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 7177762 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 253785148 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 192261476 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 87158536 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 47168149 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 11279340 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 7177762 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 7690459 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 7177762 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 7177762 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 367091244 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.readReqs 716 # Number of read requests accepted

36system.physmem.num_reads::cpu2.data 14 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
39system.physmem.num_reads::total 710 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 189466332 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 86351948 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 46731642 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 11174958 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 7111337 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 7111337 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 5079526 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 7619290 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 360646370 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 189466332 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 46731642 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 7111337 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 5079526 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 248388838 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 189466332 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 86351948 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 46731642 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 11174958 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 7111337 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 7111337 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 5079526 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 7619290 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 360646370 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.readReqs 710 # Number of read requests accepted

64system.physmem.writeReqs 0 # Number of write requests accepted

65system.physmem.readBursts 716 # Number of DRAM read bursts, including those serviced by the write queue

65system.physmem.readBursts 710 # Number of DRAM read bursts, including those serviced by the write queue

66system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue

67system.physmem.bytesReadDRAM 45824 # Total number of bytes read from DRAM

67system.physmem.bytesReadDRAM 45440 # Total number of bytes read from DRAM

68system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
69system.physmem.bytesWritten 0 # Total number of bytes written to DRAM

70system.physmem.bytesReadSys 45824 # Total read bytes from the system interface side

70system.physmem.bytesReadSys 45440 # Total read bytes from the system interface side

71system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
72system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
73system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
74system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
75system.physmem.perBankRdBursts::0 120 # Per bank write bursts
76system.physmem.perBankRdBursts::1 44 # Per bank write bursts

77system.physmem.perBankRdBursts::2 33 # Per bank write bursts
78system.physmem.perBankRdBursts::3 63 # Per bank write bursts

77system.physmem.perBankRdBursts::2 31 # Per bank write bursts
78system.physmem.perBankRdBursts::3 62 # Per bank write bursts

79system.physmem.perBankRdBursts::4 69 # Per bank write bursts
80system.physmem.perBankRdBursts::5 28 # Per bank write bursts
81system.physmem.perBankRdBursts::6 19 # Per bank write bursts
82system.physmem.perBankRdBursts::7 27 # Per bank write bursts
83system.physmem.perBankRdBursts::8 7 # Per bank write bursts
84system.physmem.perBankRdBursts::9 31 # Per bank write bursts
85system.physmem.perBankRdBursts::10 23 # Per bank write bursts
86system.physmem.perBankRdBursts::11 13 # Per bank write bursts

87system.physmem.perBankRdBursts::12 72 # Per bank write bursts

87system.physmem.perBankRdBursts::12 70 # Per bank write bursts

88system.physmem.perBankRdBursts::13 47 # Per bank write bursts

89system.physmem.perBankRdBursts::14 19 # Per bank write bursts

89system.physmem.perBankRdBursts::14 18 # Per bank write bursts

90system.physmem.perBankRdBursts::15 101 # Per bank write bursts
91system.physmem.perBankWrBursts::0 0 # Per bank write bursts
92system.physmem.perBankWrBursts::1 0 # Per bank write bursts
93system.physmem.perBankWrBursts::2 0 # Per bank write bursts
94system.physmem.perBankWrBursts::3 0 # Per bank write bursts
95system.physmem.perBankWrBursts::4 0 # Per bank write bursts
96system.physmem.perBankWrBursts::5 0 # Per bank write bursts
97system.physmem.perBankWrBursts::6 0 # Per bank write bursts
98system.physmem.perBankWrBursts::7 0 # Per bank write bursts
99system.physmem.perBankWrBursts::8 0 # Per bank write bursts
100system.physmem.perBankWrBursts::9 0 # Per bank write bursts
101system.physmem.perBankWrBursts::10 0 # Per bank write bursts
102system.physmem.perBankWrBursts::11 0 # Per bank write bursts
103system.physmem.perBankWrBursts::12 0 # Per bank write bursts
104system.physmem.perBankWrBursts::13 0 # Per bank write bursts
105system.physmem.perBankWrBursts::14 0 # Per bank write bursts
106system.physmem.perBankWrBursts::15 0 # Per bank write bursts
107system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
108system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

109system.physmem.totGap 124590000 # Total gap between requests

109system.physmem.totGap 125756000 # Total gap between requests

110system.physmem.readPktSize::0 0 # Read request sizes (log2)
111system.physmem.readPktSize::1 0 # Read request sizes (log2)
112system.physmem.readPktSize::2 0 # Read request sizes (log2)
113system.physmem.readPktSize::3 0 # Read request sizes (log2)
114system.physmem.readPktSize::4 0 # Read request sizes (log2)
115system.physmem.readPktSize::5 0 # Read request sizes (log2)

116system.physmem.readPktSize::6 716 # Read request sizes (log2)

116system.physmem.readPktSize::6 710 # Read request sizes (log2)

117system.physmem.writePktSize::0 0 # Write request sizes (log2)
118system.physmem.writePktSize::1 0 # Write request sizes (log2)
119system.physmem.writePktSize::2 0 # Write request sizes (log2)
120system.physmem.writePktSize::3 0 # Write request sizes (log2)
121system.physmem.writePktSize::4 0 # Write request sizes (log2)
122system.physmem.writePktSize::5 0 # Write request sizes (log2)
123system.physmem.writePktSize::6 0 # Write request sizes (log2)

124system.physmem.rdQLenPdf::0 416 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::1 218 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see

124system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::1 221 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see

128system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

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213system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
220system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation

221system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::gmean 161.758718 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::stdev 247.924177 # Bytes accessed per row activation
224system.physmem.bytesPerActivate::0-127 67 38.51% 38.51% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::128-255 43 24.71% 63.22% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::256-383 26 14.94% 78.16% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::384-511 12 6.90% 85.06% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::512-639 7 4.02% 89.08% # Bytes accessed per row activation

221system.physmem.bytesPerActivate::mean 244.597701 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::gmean 161.475219 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::stdev 245.687167 # Bytes accessed per row activation
224system.physmem.bytesPerActivate::0-127 66 37.93% 37.93% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::128-255 43 24.71% 62.64% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::256-383 29 16.67% 79.31% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::384-511 11 6.32% 85.63% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::512-639 6 3.45% 89.08% # Bytes accessed per row activation

229system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation

230system.physmem.bytesPerActivate::768-895 3 1.72% 95.40% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::896-1023 2 1.15% 96.55% # Bytes accessed per row activation

230system.physmem.bytesPerActivate::768-895 4 2.30% 95.98% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::896-1023 1 0.57% 96.55% # Bytes accessed per row activation

232system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation

234system.physmem.totQLat 12446750 # Total ticks spent queuing
235system.physmem.totMemAccLat 25871750 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 3580000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 17383.73 # Average queueing delay per DRAM burst

234system.physmem.totQLat 13059500 # Total ticks spent queuing
235system.physmem.totMemAccLat 26372000 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 3550000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 18393.66 # Average queueing delay per DRAM burst

238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

239system.physmem.avgMemAccLat 36133.73 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 367.09 # Average DRAM read bandwidth in MiByte/s

239system.physmem.avgMemAccLat 37143.66 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 360.65 # Average DRAM read bandwidth in MiByte/s

241system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

242system.physmem.avgRdBWSys 367.09 # Average system read bandwidth in MiByte/s

242system.physmem.avgRdBWSys 360.65 # Average system read bandwidth in MiByte/s

243system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s

245system.physmem.busUtil 2.87 # Data bus utilization in percentage
246system.physmem.busUtilRead 2.87 # Data bus utilization in percentage for reads

245system.physmem.busUtil 2.82 # Data bus utilization in percentage
246system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads

247system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
248system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
249system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

250system.physmem.readRowHits 530 # Number of row buffer hits during reads

250system.physmem.readRowHits 525 # Number of row buffer hits during reads

251system.physmem.writeRowHits 0 # Number of row buffer hits during writes

252system.physmem.readRowHitRate 74.02 # Row buffer hit rate for reads

252system.physmem.readRowHitRate 73.94 # Row buffer hit rate for reads

253system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

254system.physmem.avgGap 174008.38 # Average gap between requests
255system.physmem.pageHitRate 74.02 # Row buffer hit rate, read and write combined

254system.physmem.avgGap 177121.13 # Average gap between requests
255system.physmem.pageHitRate 73.94 # Row buffer hit rate, read and write combined

256system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ)
257system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ)

258system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ)

258system.physmem_0.readEnergy 2856000 # Energy for read commands per rank (pJ)

259system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)

260system.physmem_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
261system.physmem_0.actBackEnergy 6410790 # Energy for active background per rank (pJ)
262system.physmem_0.preBackEnergy 304320 # Energy for precharge background per rank (pJ)
263system.physmem_0.actPowerDownEnergy 34392090 # Energy for active power-down per rank (pJ)
264system.physmem_0.prePowerDownEnergy 13115040 # Energy for precharge power-down per rank (pJ)
265system.physmem_0.selfRefreshEnergy 649140.000000 # Energy for self refresh per rank (pJ)
266system.physmem_0.totalEnergy 68872470 # Total energy per rank (pJ)
267system.physmem_0.averagePower 551.730113 # Core power per rank (mW)
268system.physmem_0.totalIdleTime 109416750 # Total Idle time Per DRAM Rank
269system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states
270system.physmem_0.memoryStateTime::REF 4166000 # Time in different power states
271system.physmem_0.memoryStateTime::SREF 403000 # Time in different power states
272system.physmem_0.memoryStateTime::PRE_PDN 34152000 # Time in different power states
273system.physmem_0.memoryStateTime::ACT 10318500 # Time in different power states
274system.physmem_0.memoryStateTime::ACT_PDN 75432000 # Time in different power states
275system.physmem_1.actEnergy 471240 # Energy for activate commands per rank (pJ)

260system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
261system.physmem_0.actBackEnergy 6114390 # Energy for active background per rank (pJ)
262system.physmem_0.preBackEnergy 284160 # Energy for precharge background per rank (pJ)
263system.physmem_0.actPowerDownEnergy 31286160 # Energy for active power-down per rank (pJ)
264system.physmem_0.prePowerDownEnergy 8898240 # Energy for precharge power-down per rank (pJ)
265system.physmem_0.selfRefreshEnergy 5367840 # Energy for self refresh per rank (pJ)
266system.physmem_0.totalEnergy 64701180 # Total energy per rank (pJ)
267system.physmem_0.averagePower 513.516712 # Core power per rank (mW)
268system.physmem_0.totalIdleTime 111273500 # Total Idle time Per DRAM Rank
269system.physmem_0.memoryStateTime::IDLE 346500 # Time in different power states
270system.physmem_0.memoryStateTime::REF 3646000 # Time in different power states
271system.physmem_0.memoryStateTime::SREF 20064750 # Time in different power states
272system.physmem_0.memoryStateTime::PRE_PDN 23172500 # Time in different power states
273system.physmem_0.memoryStateTime::ACT 10159750 # Time in different power states
274system.physmem_0.memoryStateTime::ACT_PDN 68606500 # Time in different power states
275system.physmem_1.actEnergy 464100 # Energy for activate commands per rank (pJ)

276system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ)

277system.physmem_1.readEnergy 2234820 # Energy for read commands per rank (pJ)

277system.physmem_1.readEnergy 2213400 # Energy for read commands per rank (pJ)

278system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)

279system.physmem_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
280system.physmem_1.actBackEnergy 5188140 # Energy for active background per rank (pJ)
281system.physmem_1.preBackEnergy 617280 # Energy for precharge background per rank (pJ)
282system.physmem_1.actPowerDownEnergy 32401650 # Energy for active power-down per rank (pJ)
283system.physmem_1.prePowerDownEnergy 11725440 # Energy for precharge power-down per rank (pJ)
284system.physmem_1.selfRefreshEnergy 3565380 # Energy for self refresh per rank (pJ)
285system.physmem_1.totalEnergy 66265890 # Total energy per rank (pJ)
286system.physmem_1.averagePower 530.849075 # Core power per rank (mW)
287system.physmem_1.totalIdleTime 111659250 # Total Idle time Per DRAM Rank
288system.physmem_1.memoryStateTime::IDLE 1125500 # Time in different power states
289system.physmem_1.memoryStateTime::REF 4172000 # Time in different power states
290system.physmem_1.memoryStateTime::SREF 10253750 # Time in different power states
291system.physmem_1.memoryStateTime::PRE_PDN 30535250 # Time in different power states
292system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states
293system.physmem_1.memoryStateTime::ACT_PDN 71064000 # Time in different power states
294system.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
295system.cpu0.branchPred.lookups 98509 # Number of BP lookups
296system.cpu0.branchPred.condPredicted 93993 # Number of conditional branches predicted
297system.cpu0.branchPred.condIncorrect 1599 # Number of conditional branches incorrect
298system.cpu0.branchPred.BTBLookups 95823 # Number of BTB lookups

279system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
280system.physmem_1.actBackEnergy 4959000 # Energy for active background per rank (pJ)
281system.physmem_1.preBackEnergy 596640 # Energy for precharge background per rank (pJ)
282system.physmem_1.actPowerDownEnergy 28649910 # Energy for active power-down per rank (pJ)
283system.physmem_1.prePowerDownEnergy 9231840 # Energy for precharge power-down per rank (pJ)
284system.physmem_1.selfRefreshEnergy 7511880 # Energy for self refresh per rank (pJ)
285system.physmem_1.totalEnergy 62459430 # Total energy per rank (pJ)
286system.physmem_1.averagePower 495.724516 # Core power per rank (mW)
287system.physmem_1.totalIdleTime 113374250 # Total Idle time Per DRAM Rank
288system.physmem_1.memoryStateTime::IDLE 1113500 # Time in different power states
289system.physmem_1.memoryStateTime::REF 3652000 # Time in different power states
290system.physmem_1.memoryStateTime::SREF 26697750 # Time in different power states
291system.physmem_1.memoryStateTime::PRE_PDN 24040500 # Time in different power states
292system.physmem_1.memoryStateTime::ACT 7662500 # Time in different power states
293system.physmem_1.memoryStateTime::ACT_PDN 62829750 # Time in different power states
294system.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
295system.cpu0.branchPred.lookups 99694 # Number of BP lookups
296system.cpu0.branchPred.condPredicted 94929 # Number of conditional branches predicted
297system.cpu0.branchPred.condIncorrect 1689 # Number of conditional branches incorrect
298system.cpu0.branchPred.BTBLookups 96632 # Number of BTB lookups

299system.cpu0.branchPred.BTBHits 0 # Number of BTB hits
300system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
301system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

302system.cpu0.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target.

302system.cpu0.branchPred.usedRAS 1210 # Number of times the RAS was used to get a target.

303system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.

304system.cpu0.branchPred.indirectLookups 95823 # Number of indirect predictor lookups.
305system.cpu0.branchPred.indirectHits 88367 # Number of indirect target hits.
306system.cpu0.branchPred.indirectMisses 7456 # Number of indirect misses.
307system.cpu0.branchPredindirectMispredicted 1077 # Number of mispredicted indirect branches.

304system.cpu0.branchPred.indirectLookups 96632 # Number of indirect predictor lookups.
305system.cpu0.branchPred.indirectHits 88884 # Number of indirect target hits.
306system.cpu0.branchPred.indirectMisses 7748 # Number of indirect misses.
307system.cpu0.branchPredindirectMispredicted 1163 # Number of mispredicted indirect branches.

308system.cpu_clk_domain.clock 500 # Clock period in ticks
309system.cpu0.workload.num_syscalls 89 # Number of system calls

310system.cpu0.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states
311system.cpu0.numCycles 249661 # number of cpu cycles simulated

310system.cpu0.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states
311system.cpu0.numCycles 251993 # number of cpu cycles simulated

312system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
313system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

314system.cpu0.fetch.icacheStallCycles 22650 # Number of cycles fetch is stalled on an Icache miss
315system.cpu0.fetch.Insts 581099 # Number of instructions fetch has processed
316system.cpu0.fetch.Branches 98509 # Number of branches that fetch encountered
317system.cpu0.fetch.predictedBranches 89482 # Number of branches that fetch has predicted taken
318system.cpu0.fetch.Cycles 193985 # Number of cycles fetch has run and was not squashing or blocked
319system.cpu0.fetch.SquashCycles 3497 # Number of cycles fetch has spent squashing

314system.cpu0.fetch.icacheStallCycles 23206 # Number of cycles fetch is stalled on an Icache miss
315system.cpu0.fetch.Insts 587602 # Number of instructions fetch has processed
316system.cpu0.fetch.Branches 99694 # Number of branches that fetch encountered
317system.cpu0.fetch.predictedBranches 90094 # Number of branches that fetch has predicted taken
318system.cpu0.fetch.Cycles 195641 # Number of cycles fetch has run and was not squashing or blocked
319system.cpu0.fetch.SquashCycles 3677 # Number of cycles fetch has spent squashing

320system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb

321system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
322system.cpu0.fetch.PendingTrapStallCycles 2191 # Number of stall cycles due to pending traps
323system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
324system.cpu0.fetch.CacheLines 7995 # Number of cache lines fetched
325system.cpu0.fetch.IcacheSquashes 871 # Number of outstanding Icache misses that were squashed

321system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
322system.cpu0.fetch.PendingTrapStallCycles 2245 # Number of stall cycles due to pending traps
323system.cpu0.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR
324system.cpu0.fetch.CacheLines 8355 # Number of cache lines fetched
325system.cpu0.fetch.IcacheSquashes 903 # Number of outstanding Icache misses that were squashed

326system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed

327system.cpu0.fetch.rateDist::samples 220664 # Number of instructions fetched each cycle (Total)
328system.cpu0.fetch.rateDist::mean 2.633411 # Number of instructions fetched each cycle (Total)
329system.cpu0.fetch.rateDist::stdev 2.264413 # Number of instructions fetched each cycle (Total)

327system.cpu0.fetch.rateDist::samples 223034 # Number of instructions fetched each cycle (Total)
328system.cpu0.fetch.rateDist::mean 2.634585 # Number of instructions fetched each cycle (Total)
329system.cpu0.fetch.rateDist::stdev 2.272061 # Number of instructions fetched each cycle (Total)

330system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

331system.cpu0.fetch.rateDist::0 33866 15.35% 15.35% # Number of instructions fetched each cycle (Total)
332system.cpu0.fetch.rateDist::1 91353 41.40% 56.75% # Number of instructions fetched each cycle (Total)
333system.cpu0.fetch.rateDist::2 668 0.30% 57.05% # Number of instructions fetched each cycle (Total)
334system.cpu0.fetch.rateDist::3 983 0.45% 57.49% # Number of instructions fetched each cycle (Total)
335system.cpu0.fetch.rateDist::4 516 0.23% 57.73% # Number of instructions fetched each cycle (Total)
336system.cpu0.fetch.rateDist::5 86959 39.41% 97.14% # Number of instructions fetched each cycle (Total)
337system.cpu0.fetch.rateDist::6 734 0.33% 97.47% # Number of instructions fetched each cycle (Total)
338system.cpu0.fetch.rateDist::7 482 0.22% 97.69% # Number of instructions fetched each cycle (Total)
339system.cpu0.fetch.rateDist::8 5103 2.31% 100.00% # Number of instructions fetched each cycle (Total)

331system.cpu0.fetch.rateDist::0 34543 15.49% 15.49% # Number of instructions fetched each cycle (Total)
332system.cpu0.fetch.rateDist::1 92075 41.28% 56.77% # Number of instructions fetched each cycle (Total)
333system.cpu0.fetch.rateDist::2 690 0.31% 57.08% # Number of instructions fetched each cycle (Total)
334system.cpu0.fetch.rateDist::3 1016 0.46% 57.54% # Number of instructions fetched each cycle (Total)
335system.cpu0.fetch.rateDist::4 496 0.22% 57.76% # Number of instructions fetched each cycle (Total)
336system.cpu0.fetch.rateDist::5 87579 39.27% 97.03% # Number of instructions fetched each cycle (Total)
337system.cpu0.fetch.rateDist::6 656 0.29% 97.32% # Number of instructions fetched each cycle (Total)
338system.cpu0.fetch.rateDist::7 548 0.25% 97.56% # Number of instructions fetched each cycle (Total)
339system.cpu0.fetch.rateDist::8 5431 2.44% 100.00% # Number of instructions fetched each cycle (Total)

340system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
341system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
342system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

343system.cpu0.fetch.rateDist::total 220664 # Number of instructions fetched each cycle (Total)
344system.cpu0.fetch.branchRate 0.394571 # Number of branch fetches per cycle
345system.cpu0.fetch.rate 2.327552 # Number of inst fetches per cycle
346system.cpu0.decode.IdleCycles 17658 # Number of cycles decode is idle
347system.cpu0.decode.BlockedCycles 19166 # Number of cycles decode is blocked
348system.cpu0.decode.RunCycles 181260 # Number of cycles decode is running
349system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking
350system.cpu0.decode.SquashCycles 1748 # Number of cycles decode is squashing
351system.cpu0.decode.DecodedInsts 563638 # Number of instructions handled by decode
352system.cpu0.rename.SquashCycles 1748 # Number of cycles rename is squashing
353system.cpu0.rename.IdleCycles 18349 # Number of cycles rename is idle
354system.cpu0.rename.BlockCycles 2015 # Number of cycles rename is blocking
355system.cpu0.rename.serializeStallCycles 15764 # count of cycles rename stalled for serializing inst
356system.cpu0.rename.RunCycles 181386 # Number of cycles rename is running
357system.cpu0.rename.UnblockCycles 1402 # Number of cycles rename is unblocking
358system.cpu0.rename.RenamedInsts 558452 # Number of instructions processed by rename
359system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full

343system.cpu0.fetch.rateDist::total 223034 # Number of instructions fetched each cycle (Total)
344system.cpu0.fetch.branchRate 0.395622 # Number of branch fetches per cycle
345system.cpu0.fetch.rate 2.331819 # Number of inst fetches per cycle
346system.cpu0.decode.IdleCycles 18204 # Number of cycles decode is idle
347system.cpu0.decode.BlockedCycles 19474 # Number of cycles decode is blocked
348system.cpu0.decode.RunCycles 182674 # Number of cycles decode is running
349system.cpu0.decode.UnblockCycles 844 # Number of cycles decode is unblocking
350system.cpu0.decode.SquashCycles 1838 # Number of cycles decode is squashing
351system.cpu0.decode.DecodedInsts 568807 # Number of instructions handled by decode
352system.cpu0.rename.SquashCycles 1838 # Number of cycles rename is squashing
353system.cpu0.rename.IdleCycles 18897 # Number of cycles rename is idle
354system.cpu0.rename.BlockCycles 2138 # Number of cycles rename is blocking
355system.cpu0.rename.serializeStallCycles 15951 # count of cycles rename stalled for serializing inst
356system.cpu0.rename.RunCycles 182807 # Number of cycles rename is running
357system.cpu0.rename.UnblockCycles 1403 # Number of cycles rename is unblocking
358system.cpu0.rename.RenamedInsts 563480 # Number of instructions processed by rename
359system.cpu0.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full

360system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
361system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full

362system.cpu0.rename.RenamedOperands 382172 # Number of destination operands rename has renamed
363system.cpu0.rename.RenameLookups 1112707 # Number of register rename lookups that rename has made
364system.cpu0.rename.int_rename_lookups 840550 # Number of integer rename lookups
365system.cpu0.rename.fp_rename_lookups 4 # Number of floating rename lookups
366system.cpu0.rename.CommittedMaps 362927 # Number of HB maps that are committed
367system.cpu0.rename.UndoneMaps 19245 # Number of HB maps that are undone due to squashing
368system.cpu0.rename.serializingInsts 1073 # count of serializing insts renamed
369system.cpu0.rename.tempSerializingInsts 1102 # count of temporary serializing insts renamed
370system.cpu0.rename.skidInsts 5312 # count of insts added to the skid buffer
371system.cpu0.memDep0.insertedLoads 178069 # Number of loads inserted to the mem dependence unit.
372system.cpu0.memDep0.insertedStores 89965 # Number of stores inserted to the mem dependence unit.
373system.cpu0.memDep0.conflictingLoads 86828 # Number of conflicting loads.
374system.cpu0.memDep0.conflictingStores 86540 # Number of conflicting stores.
375system.cpu0.iq.iqInstsAdded 465662 # Number of instructions added to the IQ (excludes non-spec)
376system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ
377system.cpu0.iq.iqInstsIssued 461556 # Number of instructions issued
378system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
379system.cpu0.iq.iqSquashedInstsExamined 16666 # Number of squashed instructions iterated over during squash; mainly for profiling
380system.cpu0.iq.iqSquashedOperandsExamined 13597 # Number of squashed operands that are examined and possibly removed from graph
381system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed
382system.cpu0.iq.issued_per_cycle::samples 220664 # Number of insts issued each cycle
383system.cpu0.iq.issued_per_cycle::mean 2.091669 # Number of insts issued each cycle
384system.cpu0.iq.issued_per_cycle::stdev 1.110492 # Number of insts issued each cycle

362system.cpu0.rename.RenamedOperands 385856 # Number of destination operands rename has renamed
363system.cpu0.rename.RenameLookups 1122771 # Number of register rename lookups that rename has made
364system.cpu0.rename.int_rename_lookups 848321 # Number of integer rename lookups
365system.cpu0.rename.fp_rename_lookups 8 # Number of floating rename lookups
366system.cpu0.rename.CommittedMaps 365359 # Number of HB maps that are committed
367system.cpu0.rename.UndoneMaps 20497 # Number of HB maps that are undone due to squashing
368system.cpu0.rename.serializingInsts 1128 # count of serializing insts renamed
369system.cpu0.rename.tempSerializingInsts 1160 # count of temporary serializing insts renamed
370system.cpu0.rename.skidInsts 5339 # count of insts added to the skid buffer
371system.cpu0.memDep0.insertedLoads 179490 # Number of loads inserted to the mem dependence unit.
372system.cpu0.memDep0.insertedStores 90635 # Number of stores inserted to the mem dependence unit.
373system.cpu0.memDep0.conflictingLoads 87474 # Number of conflicting loads.
374system.cpu0.memDep0.conflictingStores 87162 # Number of conflicting stores.
375system.cpu0.iq.iqInstsAdded 469651 # Number of instructions added to the IQ (excludes non-spec)
376system.cpu0.iq.iqNonSpecInstsAdded 1149 # Number of non-speculative instructions added to the IQ
377system.cpu0.iq.iqInstsIssued 465284 # Number of instructions issued
378system.cpu0.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
379system.cpu0.iq.iqSquashedInstsExamined 17670 # Number of squashed instructions iterated over during squash; mainly for profiling
380system.cpu0.iq.iqSquashedOperandsExamined 14278 # Number of squashed operands that are examined and possibly removed from graph
381system.cpu0.iq.iqSquashedNonSpecRemoved 590 # Number of squashed non-spec instructions that were removed
382system.cpu0.iq.issued_per_cycle::samples 223034 # Number of insts issued each cycle
383system.cpu0.iq.issued_per_cycle::mean 2.086157 # Number of insts issued each cycle
384system.cpu0.iq.issued_per_cycle::stdev 1.115238 # Number of insts issued each cycle

385system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

386system.cpu0.iq.issued_per_cycle::0 36803 16.68% 16.68% # Number of insts issued each cycle
387system.cpu0.iq.issued_per_cycle::1 4402 1.99% 18.67% # Number of insts issued each cycle
388system.cpu0.iq.issued_per_cycle::2 88094 39.92% 58.60% # Number of insts issued each cycle
389system.cpu0.iq.issued_per_cycle::3 87764 39.77% 98.37% # Number of insts issued each cycle
390system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.14% # Number of insts issued each cycle
391system.cpu0.iq.issued_per_cycle::5 985 0.45% 99.58% # Number of insts issued each cycle
392system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.84% # Number of insts issued each cycle
393system.cpu0.iq.issued_per_cycle::7 247 0.11% 99.95% # Number of insts issued each cycle
394system.cpu0.iq.issued_per_cycle::8 102 0.05% 100.00% # Number of insts issued each cycle

386system.cpu0.iq.issued_per_cycle::0 37655 16.88% 16.88% # Number of insts issued each cycle
387system.cpu0.iq.issued_per_cycle::1 4554 2.04% 18.92% # Number of insts issued each cycle
388system.cpu0.iq.issued_per_cycle::2 88787 39.81% 58.73% # Number of insts issued each cycle
389system.cpu0.iq.issued_per_cycle::3 88368 39.62% 98.35% # Number of insts issued each cycle
390system.cpu0.iq.issued_per_cycle::4 1704 0.76% 99.12% # Number of insts issued each cycle
391system.cpu0.iq.issued_per_cycle::5 1021 0.46% 99.58% # Number of insts issued each cycle
392system.cpu0.iq.issued_per_cycle::6 603 0.27% 99.85% # Number of insts issued each cycle
393system.cpu0.iq.issued_per_cycle::7 223 0.10% 99.95% # Number of insts issued each cycle
394system.cpu0.iq.issued_per_cycle::8 119 0.05% 100.00% # Number of insts issued each cycle

395system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
396system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
397system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

398system.cpu0.iq.issued_per_cycle::total 220664 # Number of insts issued each cycle

398system.cpu0.iq.issued_per_cycle::total 223034 # Number of insts issued each cycle

399system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

400system.cpu0.iq.fu_full::IntAlu 129 39.09% 39.09% # attempts to use FU when none available
401system.cpu0.iq.fu_full::IntMult 0 0.00% 39.09% # attempts to use FU when none available
402system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.09% # attempts to use FU when none available
403system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.09% # attempts to use FU when none available
404system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.09% # attempts to use FU when none available
405system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.09% # attempts to use FU when none available
406system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.09% # attempts to use FU when none available
407system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available
408system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.09% # attempts to use FU when none available
409system.cpu0.iq.fu_full::FloatMisc 0 0.00% 39.09% # attempts to use FU when none available
410system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.09% # attempts to use FU when none available
411system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.09% # attempts to use FU when none available
412system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.09% # attempts to use FU when none available
413system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.09% # attempts to use FU when none available
414system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.09% # attempts to use FU when none available
415system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.09% # attempts to use FU when none available
416system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.09% # attempts to use FU when none available
417system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.09% # attempts to use FU when none available
418system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.09% # attempts to use FU when none available
419system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.09% # attempts to use FU when none available
420system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.09% # attempts to use FU when none available
421system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.09% # attempts to use FU when none available
422system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.09% # attempts to use FU when none available
423system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.09% # attempts to use FU when none available
424system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.09% # attempts to use FU when none available
425system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.09% # attempts to use FU when none available
426system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.09% # attempts to use FU when none available
427system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.09% # attempts to use FU when none available
428system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.09% # attempts to use FU when none available
429system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available
430system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.09% # attempts to use FU when none available
431system.cpu0.iq.fu_full::MemRead 77 23.33% 62.42% # attempts to use FU when none available
432system.cpu0.iq.fu_full::MemWrite 124 37.58% 100.00% # attempts to use FU when none available

400system.cpu0.iq.fu_full::IntAlu 140 40.46% 40.46% # attempts to use FU when none available
401system.cpu0.iq.fu_full::IntMult 0 0.00% 40.46% # attempts to use FU when none available
402system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.46% # attempts to use FU when none available
403system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.46% # attempts to use FU when none available
404system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.46% # attempts to use FU when none available
405system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.46% # attempts to use FU when none available
406system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.46% # attempts to use FU when none available
407system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available
408system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.46% # attempts to use FU when none available
409system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.46% # attempts to use FU when none available
410system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.46% # attempts to use FU when none available
411system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.46% # attempts to use FU when none available
412system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.46% # attempts to use FU when none available
413system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.46% # attempts to use FU when none available
414system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.46% # attempts to use FU when none available
415system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.46% # attempts to use FU when none available
416system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.46% # attempts to use FU when none available
417system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.46% # attempts to use FU when none available
418system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.46% # attempts to use FU when none available
419system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.46% # attempts to use FU when none available
420system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.46% # attempts to use FU when none available
421system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.46% # attempts to use FU when none available
422system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.46% # attempts to use FU when none available
423system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.46% # attempts to use FU when none available
424system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.46% # attempts to use FU when none available
425system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.46% # attempts to use FU when none available
426system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.46% # attempts to use FU when none available
427system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.46% # attempts to use FU when none available
428system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.46% # attempts to use FU when none available
429system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available
430system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.46% # attempts to use FU when none available
431system.cpu0.iq.fu_full::MemRead 83 23.99% 64.45% # attempts to use FU when none available
432system.cpu0.iq.fu_full::MemWrite 123 35.55% 100.00% # attempts to use FU when none available

433system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
434system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
435system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
436system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
437system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

438system.cpu0.iq.FU_type_0::IntAlu 194924 42.23% 42.23% # Type of FU issued
439system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued
440system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued
441system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued
442system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued
443system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued
444system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued
445system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.23% # Type of FU issued
446system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued
447system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.23% # Type of FU issued
448system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued
449system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued
450system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued
451system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued
452system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued
453system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued
454system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued
455system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued
456system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued
457system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued
458system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued
459system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued
460system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued
461system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued
462system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued
463system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued
464system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued
465system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued
466system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued
467system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued
468system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued
469system.cpu0.iq.FU_type_0::MemRead 177454 38.45% 80.68% # Type of FU issued
470system.cpu0.iq.FU_type_0::MemWrite 89178 19.32% 100.00% # Type of FU issued

438system.cpu0.iq.FU_type_0::IntAlu 196646 42.26% 42.26% # Type of FU issued
439system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.26% # Type of FU issued
440system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.26% # Type of FU issued
441system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.26% # Type of FU issued
442system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.26% # Type of FU issued
443system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.26% # Type of FU issued
444system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.26% # Type of FU issued
445system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.26% # Type of FU issued
446system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.26% # Type of FU issued
447system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.26% # Type of FU issued
448system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.26% # Type of FU issued
449system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.26% # Type of FU issued
450system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.26% # Type of FU issued
451system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.26% # Type of FU issued
452system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.26% # Type of FU issued
453system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.26% # Type of FU issued
454system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.26% # Type of FU issued
455system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.26% # Type of FU issued
456system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.26% # Type of FU issued
457system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.26% # Type of FU issued
458system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.26% # Type of FU issued
459system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.26% # Type of FU issued
460system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.26% # Type of FU issued
461system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.26% # Type of FU issued
462system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.26% # Type of FU issued
463system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.26% # Type of FU issued
464system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.26% # Type of FU issued
465system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.26% # Type of FU issued
466system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.26% # Type of FU issued
467system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.26% # Type of FU issued
468system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.26% # Type of FU issued
469system.cpu0.iq.FU_type_0::MemRead 178800 38.43% 80.69% # Type of FU issued
470system.cpu0.iq.FU_type_0::MemWrite 89838 19.31% 100.00% # Type of FU issued

471system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
472system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
473system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
474system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

475system.cpu0.iq.FU_type_0::total 461556 # Type of FU issued
476system.cpu0.iq.rate 1.848731 # Inst issue rate
477system.cpu0.iq.fu_busy_cnt 330 # FU busy when requested
478system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst)
479system.cpu0.iq.int_inst_queue_reads 1144224 # Number of integer instruction queue reads
480system.cpu0.iq.int_inst_queue_writes 483466 # Number of integer instruction queue writes
481system.cpu0.iq.int_inst_queue_wakeup_accesses 458888 # Number of integer instruction queue wakeup accesses

475system.cpu0.iq.FU_type_0::total 465284 # Type of FU issued
476system.cpu0.iq.rate 1.846416 # Inst issue rate
477system.cpu0.iq.fu_busy_cnt 346 # FU busy when requested
478system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
479system.cpu0.iq.int_inst_queue_reads 1154078 # Number of integer instruction queue reads
480system.cpu0.iq.int_inst_queue_writes 488506 # Number of integer instruction queue writes
481system.cpu0.iq.int_inst_queue_wakeup_accesses 462560 # Number of integer instruction queue wakeup accesses

482system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

483system.cpu0.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes

483system.cpu0.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes

484system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

485system.cpu0.iq.int_alu_accesses 461886 # Number of integer alu accesses

485system.cpu0.iq.int_alu_accesses 465630 # Number of integer alu accesses

486system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses

487system.cpu0.iew.lsq.thread0.forwLoads 86265 # Number of loads that had data forwarded from stores

487system.cpu0.iew.lsq.thread0.forwLoads 86875 # Number of loads that had data forwarded from stores

488system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

489system.cpu0.iew.lsq.thread0.squashedLoads 3016 # Number of loads squashed
490system.cpu0.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed

489system.cpu0.iew.lsq.thread0.squashedLoads 3221 # Number of loads squashed
490system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed

491system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations

492system.cpu0.iew.lsq.thread0.squashedStores 1932 # Number of stores squashed

492system.cpu0.iew.lsq.thread0.squashedStores 1994 # Number of stores squashed

493system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
494system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
495system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
496system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
497system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

498system.cpu0.iew.iewSquashCycles 1748 # Number of cycles IEW is squashing
499system.cpu0.iew.iewBlockCycles 2015 # Number of cycles IEW is blocking

498system.cpu0.iew.iewSquashCycles 1838 # Number of cycles IEW is squashing
499system.cpu0.iew.iewBlockCycles 2137 # Number of cycles IEW is blocking

500system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking

501system.cpu0.iew.iewDispatchedInsts 554202 # Number of instructions dispatched to IQ
502system.cpu0.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
503system.cpu0.iew.iewDispLoadInsts 178069 # Number of dispatched load instructions
504system.cpu0.iew.iewDispStoreInsts 89965 # Number of dispatched store instructions
505system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions

501system.cpu0.iew.iewDispatchedInsts 558923 # Number of instructions dispatched to IQ
502system.cpu0.iew.iewDispSquashedInsts 171 # Number of squashed instructions skipped by dispatch
503system.cpu0.iew.iewDispLoadInsts 179490 # Number of dispatched load instructions
504system.cpu0.iew.iewDispStoreInsts 90635 # Number of dispatched store instructions
505system.cpu0.iew.iewDispNonSpecInsts 1033 # Number of dispatched non-speculative instructions

506system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall
507system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
508system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations

509system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly
510system.cpu0.iew.predictedNotTakenIncorrect 1714 # Number of branches that were predicted not taken incorrectly
511system.cpu0.iew.branchMispredicts 1946 # Number of branch mispredicts detected at execute
512system.cpu0.iew.iewExecutedInsts 460023 # Number of executed instructions
513system.cpu0.iew.iewExecLoadInsts 177079 # Number of load instructions executed
514system.cpu0.iew.iewExecSquashedInsts 1533 # Number of squashed instructions skipped in execute

509system.cpu0.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly
510system.cpu0.iew.predictedNotTakenIncorrect 1860 # Number of branches that were predicted not taken incorrectly
511system.cpu0.iew.branchMispredicts 2078 # Number of branch mispredicts detected at execute
512system.cpu0.iew.iewExecutedInsts 463731 # Number of executed instructions
513system.cpu0.iew.iewExecLoadInsts 178412 # Number of load instructions executed
514system.cpu0.iew.iewExecSquashedInsts 1553 # Number of squashed instructions skipped in execute

515system.cpu0.iew.exec_swp 0 # number of swp insts executed

516system.cpu0.iew.exec_nop 87446 # number of nop insts executed
517system.cpu0.iew.exec_refs 266047 # number of memory reference insts executed
518system.cpu0.iew.exec_branches 91396 # Number of branches executed
519system.cpu0.iew.exec_stores 88968 # Number of stores executed
520system.cpu0.iew.exec_rate 1.842591 # Inst execution rate
521system.cpu0.iew.wb_sent 459364 # cumulative count of insts sent to commit
522system.cpu0.iew.wb_count 458888 # cumulative count of insts written-back
523system.cpu0.iew.wb_producers 272127 # num instructions producing a value
524system.cpu0.iew.wb_consumers 275688 # num instructions consuming a value
525system.cpu0.iew.wb_rate 1.838044 # insts written-back per cycle
526system.cpu0.iew.wb_fanout 0.987083 # average fanout of values written-back
527system.cpu0.commit.commitSquashedInsts 17379 # The number of squashed insts skipped by commit

516system.cpu0.iew.exec_nop 88123 # number of nop insts executed
517system.cpu0.iew.exec_refs 268032 # number of memory reference insts executed
518system.cpu0.iew.exec_branches 92124 # Number of branches executed
519system.cpu0.iew.exec_stores 89620 # Number of stores executed
520system.cpu0.iew.exec_rate 1.840253 # Inst execution rate
521system.cpu0.iew.wb_sent 463047 # cumulative count of insts sent to commit
522system.cpu0.iew.wb_count 462560 # cumulative count of insts written-back
523system.cpu0.iew.wb_producers 274104 # num instructions producing a value
524system.cpu0.iew.wb_consumers 277790 # num instructions consuming a value
525system.cpu0.iew.wb_rate 1.835607 # insts written-back per cycle
526system.cpu0.iew.wb_fanout 0.986731 # average fanout of values written-back
527system.cpu0.commit.commitSquashedInsts 18452 # The number of squashed insts skipped by commit

528system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards

529system.cpu0.commit.branchMispredicts 1599 # The number of times a branch was mispredicted
530system.cpu0.commit.committed_per_cycle::samples 217244 # Number of insts commited each cycle
531system.cpu0.commit.committed_per_cycle::mean 2.470687 # Number of insts commited each cycle
532system.cpu0.commit.committed_per_cycle::stdev 2.142582 # Number of insts commited each cycle

529system.cpu0.commit.branchMispredicts 1689 # The number of times a branch was mispredicted
530system.cpu0.commit.committed_per_cycle::samples 219410 # Number of insts commited each cycle
531system.cpu0.commit.committed_per_cycle::mean 2.462923 # Number of insts commited each cycle
532system.cpu0.commit.committed_per_cycle::stdev 2.143392 # Number of insts commited each cycle

533system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

534system.cpu0.commit.committed_per_cycle::0 36715 16.90% 16.90% # Number of insts commited each cycle
535system.cpu0.commit.committed_per_cycle::1 90144 41.49% 58.39% # Number of insts commited each cycle
536system.cpu0.commit.committed_per_cycle::2 2018 0.93% 59.32% # Number of insts commited each cycle
537system.cpu0.commit.committed_per_cycle::3 613 0.28% 59.61% # Number of insts commited each cycle
538system.cpu0.commit.committed_per_cycle::4 486 0.22% 59.83% # Number of insts commited each cycle
539system.cpu0.commit.committed_per_cycle::5 86051 39.61% 99.44% # Number of insts commited each cycle
540system.cpu0.commit.committed_per_cycle::6 459 0.21% 99.65% # Number of insts commited each cycle
541system.cpu0.commit.committed_per_cycle::7 294 0.14% 99.79% # Number of insts commited each cycle
542system.cpu0.commit.committed_per_cycle::8 464 0.21% 100.00% # Number of insts commited each cycle

534system.cpu0.commit.committed_per_cycle::0 37598 17.14% 17.14% # Number of insts commited each cycle
535system.cpu0.commit.committed_per_cycle::1 90827 41.40% 58.53% # Number of insts commited each cycle
536system.cpu0.commit.committed_per_cycle::2 2058 0.94% 59.47% # Number of insts commited each cycle
537system.cpu0.commit.committed_per_cycle::3 592 0.27% 59.74% # Number of insts commited each cycle
538system.cpu0.commit.committed_per_cycle::4 460 0.21% 59.95% # Number of insts commited each cycle
539system.cpu0.commit.committed_per_cycle::5 86620 39.48% 99.43% # Number of insts commited each cycle
540system.cpu0.commit.committed_per_cycle::6 500 0.23% 99.66% # Number of insts commited each cycle
541system.cpu0.commit.committed_per_cycle::7 309 0.14% 99.80% # Number of insts commited each cycle
542system.cpu0.commit.committed_per_cycle::8 446 0.20% 100.00% # Number of insts commited each cycle

543system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
544system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
545system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

546system.cpu0.commit.committed_per_cycle::total 217244 # Number of insts commited each cycle
547system.cpu0.commit.committedInsts 536742 # Number of instructions committed
548system.cpu0.commit.committedOps 536742 # Number of ops (including micro ops) committed

546system.cpu0.commit.committed_per_cycle::total 219410 # Number of insts commited each cycle
547system.cpu0.commit.committedInsts 540390 # Number of instructions committed
548system.cpu0.commit.committedOps 540390 # Number of ops (including micro ops) committed

549system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

550system.cpu0.commit.refs 263086 # Number of memory references committed
551system.cpu0.commit.loads 175053 # Number of loads committed

550system.cpu0.commit.refs 264910 # Number of memory references committed
551system.cpu0.commit.loads 176269 # Number of loads committed

552system.cpu0.commit.membars 84 # Number of memory barriers committed

553system.cpu0.commit.branches 89920 # Number of branches committed

553system.cpu0.commit.branches 90528 # Number of branches committed

554system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.

555system.cpu0.commit.int_insts 361258 # Number of committed integer instructions.

555system.cpu0.commit.int_insts 363690 # Number of committed integer instructions.

556system.cpu0.commit.function_calls 223 # Number of function calls committed.

557system.cpu0.commit.op_class_0::No_OpClass 86652 16.14% 16.14% # Class of committed instruction
558system.cpu0.commit.op_class_0::IntAlu 186920 34.82% 50.97% # Class of committed instruction
559system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction
560system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction
561system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction
562system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction
563system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction
564system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction
565system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.97% # Class of committed instruction
566system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction
567system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.97% # Class of committed instruction
568system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction
569system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction
570system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction
571system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.97% # Class of committed instruction
572system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.97% # Class of committed instruction
573system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.97% # Class of committed instruction
574system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.97% # Class of committed instruction
575system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.97% # Class of committed instruction
576system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.97% # Class of committed instruction
577system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.97% # Class of committed instruction
578system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.97% # Class of committed instruction
579system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.97% # Class of committed instruction
580system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.97% # Class of committed instruction
581system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction
582system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction
583system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction
584system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction
585system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction
586system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction
587system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction
588system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction
589system.cpu0.commit.op_class_0::MemRead 175137 32.63% 83.60% # Class of committed instruction
590system.cpu0.commit.op_class_0::MemWrite 88033 16.40% 100.00% # Class of committed instruction

557system.cpu0.commit.op_class_0::No_OpClass 87260 16.15% 16.15% # Class of committed instruction
558system.cpu0.commit.op_class_0::IntAlu 188136 34.81% 50.96% # Class of committed instruction
559system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96% # Class of committed instruction
560system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96% # Class of committed instruction
561system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96% # Class of committed instruction
562system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96% # Class of committed instruction
563system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96% # Class of committed instruction
564system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96% # Class of committed instruction
565system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96% # Class of committed instruction
566system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96% # Class of committed instruction
567system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96% # Class of committed instruction
568system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96% # Class of committed instruction
569system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96% # Class of committed instruction
570system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96% # Class of committed instruction
571system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96% # Class of committed instruction
572system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96% # Class of committed instruction
573system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96% # Class of committed instruction
574system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96% # Class of committed instruction
575system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96% # Class of committed instruction
576system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96% # Class of committed instruction
577system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96% # Class of committed instruction
578system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96% # Class of committed instruction
579system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96% # Class of committed instruction
580system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96% # Class of committed instruction
581system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96% # Class of committed instruction
582system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96% # Class of committed instruction
583system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96% # Class of committed instruction
584system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96% # Class of committed instruction
585system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96% # Class of committed instruction
586system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96% # Class of committed instruction
587system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96% # Class of committed instruction
588system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96% # Class of committed instruction
589system.cpu0.commit.op_class_0::MemRead 176353 32.63% 83.60% # Class of committed instruction
590system.cpu0.commit.op_class_0::MemWrite 88641 16.40% 100.00% # Class of committed instruction

591system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
592system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
593system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
594system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

595system.cpu0.commit.op_class_0::total 536742 # Class of committed instruction
596system.cpu0.commit.bw_lim_events 464 # number cycles where commit BW limit reached
597system.cpu0.rob.rob_reads 769740 # The number of ROB reads
598system.cpu0.rob.rob_writes 1111721 # The number of ROB writes
599system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself
600system.cpu0.idleCycles 28997 # Total number of cycles that the CPU has spent unscheduled due to idling
601system.cpu0.committedInsts 450006 # Number of Instructions Simulated
602system.cpu0.committedOps 450006 # Number of Ops (including micro ops) Simulated
603system.cpu0.cpi 0.554795 # CPI: Cycles Per Instruction
604system.cpu0.cpi_total 0.554795 # CPI: Total CPI of All Threads
605system.cpu0.ipc 1.802468 # IPC: Instructions Per Cycle
606system.cpu0.ipc_total 1.802468 # IPC: Total IPC of All Threads
607system.cpu0.int_regfile_reads 822274 # number of integer regfile reads
608system.cpu0.int_regfile_writes 370684 # number of integer regfile writes

595system.cpu0.commit.op_class_0::total 540390 # Class of committed instruction
596system.cpu0.commit.bw_lim_events 446 # number cycles where commit BW limit reached
597system.cpu0.rob.rob_reads 776645 # The number of ROB reads
598system.cpu0.rob.rob_writes 1121369 # The number of ROB writes
599system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
600system.cpu0.idleCycles 28959 # Total number of cycles that the CPU has spent unscheduled due to idling
601system.cpu0.committedInsts 453046 # Number of Instructions Simulated
602system.cpu0.committedOps 453046 # Number of Ops (including micro ops) Simulated
603system.cpu0.cpi 0.556219 # CPI: Cycles Per Instruction
604system.cpu0.cpi_total 0.556219 # CPI: Total CPI of All Threads
605system.cpu0.ipc 1.797852 # IPC: Instructions Per Cycle
606system.cpu0.ipc_total 1.797852 # IPC: Total IPC of All Threads
607system.cpu0.int_regfile_reads 828824 # number of integer regfile reads
608system.cpu0.int_regfile_writes 373673 # number of integer regfile writes

609system.cpu0.fp_regfile_reads 192 # number of floating regfile reads

610system.cpu0.misc_regfile_reads 268168 # number of misc regfile reads

610system.cpu0.misc_regfile_reads 270178 # number of misc regfile reads

611system.cpu0.misc_regfile_writes 564 # number of misc regfile writes

612system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

612system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

613system.cpu0.dcache.tags.replacements 2 # number of replacements

614system.cpu0.dcache.tags.tagsinuse 142.144997 # Cycle average of tags in use
615system.cpu0.dcache.tags.total_refs 177494 # Total number of references to valid blocks.

614system.cpu0.dcache.tags.tagsinuse 142.283862 # Cycle average of tags in use
615system.cpu0.dcache.tags.total_refs 178830 # Total number of references to valid blocks.

616system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks.

617system.cpu0.dcache.tags.avg_refs 1031.941860 # Average number of references to valid blocks.

617system.cpu0.dcache.tags.avg_refs 1039.709302 # Average number of references to valid blocks.

618system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

619system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.144997 # Average occupied blocks per requestor
620system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277627 # Average percentage of cache occupancy
621system.cpu0.dcache.tags.occ_percent::total 0.277627 # Average percentage of cache occupancy

619system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.283862 # Average occupied blocks per requestor
620system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277898 # Average percentage of cache occupancy
621system.cpu0.dcache.tags.occ_percent::total 0.277898 # Average percentage of cache occupancy

622system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id
623system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
624system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
625system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
626system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id

627system.cpu0.dcache.tags.tag_accesses 715284 # Number of tag accesses
628system.cpu0.dcache.tags.data_accesses 715284 # Number of data accesses
629system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
630system.cpu0.dcache.ReadReq_hits::cpu0.data 90136 # number of ReadReq hits
631system.cpu0.dcache.ReadReq_hits::total 90136 # number of ReadReq hits
632system.cpu0.dcache.WriteReq_hits::cpu0.data 87436 # number of WriteReq hits
633system.cpu0.dcache.WriteReq_hits::total 87436 # number of WriteReq hits

627system.cpu0.dcache.tags.tag_accesses 720603 # Number of tag accesses
628system.cpu0.dcache.tags.data_accesses 720603 # Number of data accesses
629system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
630system.cpu0.dcache.ReadReq_hits::cpu0.data 90862 # number of ReadReq hits
631system.cpu0.dcache.ReadReq_hits::total 90862 # number of ReadReq hits
632system.cpu0.dcache.WriteReq_hits::cpu0.data 88053 # number of WriteReq hits
633system.cpu0.dcache.WriteReq_hits::total 88053 # number of WriteReq hits

634system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits
635system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits

636system.cpu0.dcache.demand_hits::cpu0.data 177572 # number of demand (read+write) hits
637system.cpu0.dcache.demand_hits::total 177572 # number of demand (read+write) hits
638system.cpu0.dcache.overall_hits::cpu0.data 177572 # number of overall hits
639system.cpu0.dcache.overall_hits::total 177572 # number of overall hits
640system.cpu0.dcache.ReadReq_misses::cpu0.data 571 # number of ReadReq misses
641system.cpu0.dcache.ReadReq_misses::total 571 # number of ReadReq misses
642system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
643system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses

636system.cpu0.dcache.demand_hits::cpu0.data 178915 # number of demand (read+write) hits
637system.cpu0.dcache.demand_hits::total 178915 # number of demand (read+write) hits
638system.cpu0.dcache.overall_hits::cpu0.data 178915 # number of overall hits
639system.cpu0.dcache.overall_hits::total 178915 # number of overall hits
640system.cpu0.dcache.ReadReq_misses::cpu0.data 568 # number of ReadReq misses
641system.cpu0.dcache.ReadReq_misses::total 568 # number of ReadReq misses
642system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses
643system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses

644system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses
645system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses

646system.cpu0.dcache.demand_misses::cpu0.data 1126 # number of demand (read+write) misses
647system.cpu0.dcache.demand_misses::total 1126 # number of demand (read+write) misses
648system.cpu0.dcache.overall_misses::cpu0.data 1126 # number of overall misses
649system.cpu0.dcache.overall_misses::total 1126 # number of overall misses
650system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16338000 # number of ReadReq miss cycles
651system.cpu0.dcache.ReadReq_miss_latency::total 16338000 # number of ReadReq miss cycles
652system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35699989 # number of WriteReq miss cycles
653system.cpu0.dcache.WriteReq_miss_latency::total 35699989 # number of WriteReq miss cycles
654system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 501500 # number of SwapReq miss cycles
655system.cpu0.dcache.SwapReq_miss_latency::total 501500 # number of SwapReq miss cycles
656system.cpu0.dcache.demand_miss_latency::cpu0.data 52037989 # number of demand (read+write) miss cycles
657system.cpu0.dcache.demand_miss_latency::total 52037989 # number of demand (read+write) miss cycles
658system.cpu0.dcache.overall_miss_latency::cpu0.data 52037989 # number of overall miss cycles
659system.cpu0.dcache.overall_miss_latency::total 52037989 # number of overall miss cycles
660system.cpu0.dcache.ReadReq_accesses::cpu0.data 90707 # number of ReadReq accesses(hits+misses)
661system.cpu0.dcache.ReadReq_accesses::total 90707 # number of ReadReq accesses(hits+misses)
662system.cpu0.dcache.WriteReq_accesses::cpu0.data 87991 # number of WriteReq accesses(hits+misses)
663system.cpu0.dcache.WriteReq_accesses::total 87991 # number of WriteReq accesses(hits+misses)

646system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses
647system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses
648system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses
649system.cpu0.dcache.overall_misses::total 1114 # number of overall misses
650system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16630000 # number of ReadReq miss cycles
651system.cpu0.dcache.ReadReq_miss_latency::total 16630000 # number of ReadReq miss cycles
652system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35665989 # number of WriteReq miss cycles
653system.cpu0.dcache.WriteReq_miss_latency::total 35665989 # number of WriteReq miss cycles
654system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 490500 # number of SwapReq miss cycles
655system.cpu0.dcache.SwapReq_miss_latency::total 490500 # number of SwapReq miss cycles
656system.cpu0.dcache.demand_miss_latency::cpu0.data 52295989 # number of demand (read+write) miss cycles
657system.cpu0.dcache.demand_miss_latency::total 52295989 # number of demand (read+write) miss cycles
658system.cpu0.dcache.overall_miss_latency::cpu0.data 52295989 # number of overall miss cycles
659system.cpu0.dcache.overall_miss_latency::total 52295989 # number of overall miss cycles
660system.cpu0.dcache.ReadReq_accesses::cpu0.data 91430 # number of ReadReq accesses(hits+misses)
661system.cpu0.dcache.ReadReq_accesses::total 91430 # number of ReadReq accesses(hits+misses)
662system.cpu0.dcache.WriteReq_accesses::cpu0.data 88599 # number of WriteReq accesses(hits+misses)
663system.cpu0.dcache.WriteReq_accesses::total 88599 # number of WriteReq accesses(hits+misses)

664system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
665system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)

666system.cpu0.dcache.demand_accesses::cpu0.data 178698 # number of demand (read+write) accesses
667system.cpu0.dcache.demand_accesses::total 178698 # number of demand (read+write) accesses
668system.cpu0.dcache.overall_accesses::cpu0.data 178698 # number of overall (read+write) accesses
669system.cpu0.dcache.overall_accesses::total 178698 # number of overall (read+write) accesses
670system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006295 # miss rate for ReadReq accesses
671system.cpu0.dcache.ReadReq_miss_rate::total 0.006295 # miss rate for ReadReq accesses
672system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006307 # miss rate for WriteReq accesses
673system.cpu0.dcache.WriteReq_miss_rate::total 0.006307 # miss rate for WriteReq accesses

666system.cpu0.dcache.demand_accesses::cpu0.data 180029 # number of demand (read+write) accesses
667system.cpu0.dcache.demand_accesses::total 180029 # number of demand (read+write) accesses
668system.cpu0.dcache.overall_accesses::cpu0.data 180029 # number of overall (read+write) accesses
669system.cpu0.dcache.overall_accesses::total 180029 # number of overall (read+write) accesses
670system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006212 # miss rate for ReadReq accesses
671system.cpu0.dcache.ReadReq_miss_rate::total 0.006212 # miss rate for ReadReq accesses
672system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006163 # miss rate for WriteReq accesses
673system.cpu0.dcache.WriteReq_miss_rate::total 0.006163 # miss rate for WriteReq accesses

674system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses
675system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses

676system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006301 # miss rate for demand accesses
677system.cpu0.dcache.demand_miss_rate::total 0.006301 # miss rate for demand accesses
678system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006301 # miss rate for overall accesses
679system.cpu0.dcache.overall_miss_rate::total 0.006301 # miss rate for overall accesses
680system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720 # average ReadReq miss latency
681system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720 # average ReadReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505 # average WriteReq miss latency
683system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505 # average WriteReq miss latency
684system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111 # average SwapReq miss latency
685system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111 # average SwapReq miss latency
686system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency
687system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302 # average overall miss latency
688system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency
689system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302 # average overall miss latency

676system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006188 # miss rate for demand accesses
677system.cpu0.dcache.demand_miss_rate::total 0.006188 # miss rate for demand accesses
678system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006188 # miss rate for overall accesses
679system.cpu0.dcache.overall_miss_rate::total 0.006188 # miss rate for overall accesses
680system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29278.169014 # average ReadReq miss latency
681system.cpu0.dcache.ReadReq_avg_miss_latency::total 29278.169014 # average ReadReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65322.324176 # average WriteReq miss latency
683system.cpu0.dcache.WriteReq_avg_miss_latency::total 65322.324176 # average WriteReq miss latency
684system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27250 # average SwapReq miss latency
685system.cpu0.dcache.SwapReq_avg_miss_latency::total 27250 # average SwapReq miss latency
686system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency
687system.cpu0.dcache.demand_avg_miss_latency::total 46944.334829 # average overall miss latency
688system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency
689system.cpu0.dcache.overall_avg_miss_latency::total 46944.334829 # average overall miss latency

690system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked
691system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
694system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
696system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
697system.cpu0.dcache.writebacks::total 1 # number of writebacks

698system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 369 # number of ReadReq MSHR hits
699system.cpu0.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits
700system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 385 # number of WriteReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::total 385 # number of WriteReq MSHR hits
702system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits
703system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits
704system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits
705system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits
706system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202 # number of ReadReq MSHR misses
707system.cpu0.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
708system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses
709system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses

698system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits
699system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits
700system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 375 # number of WriteReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::total 375 # number of WriteReq MSHR hits
702system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits
703system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits
704system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits
705system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits
706system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198 # number of ReadReq MSHR misses
707system.cpu0.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses
708system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses
709system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses

710system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 18 # number of SwapReq MSHR misses
711system.cpu0.dcache.SwapReq_mshr_misses::total 18 # number of SwapReq MSHR misses

712system.cpu0.dcache.demand_mshr_misses::cpu0.data 372 # number of demand (read+write) MSHR misses
713system.cpu0.dcache.demand_mshr_misses::total 372 # number of demand (read+write) MSHR misses
714system.cpu0.dcache.overall_mshr_misses::cpu0.data 372 # number of overall MSHR misses
715system.cpu0.dcache.overall_mshr_misses::total 372 # number of overall MSHR misses
716system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7501000 # number of ReadReq MSHR miss cycles
717system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7501000 # number of ReadReq MSHR miss cycles
718system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8169500 # number of WriteReq MSHR miss cycles
719system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8169500 # number of WriteReq MSHR miss cycles
720system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 483500 # number of SwapReq MSHR miss cycles
721system.cpu0.dcache.SwapReq_mshr_miss_latency::total 483500 # number of SwapReq MSHR miss cycles
722system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15670500 # number of demand (read+write) MSHR miss cycles
723system.cpu0.dcache.demand_mshr_miss_latency::total 15670500 # number of demand (read+write) MSHR miss cycles
724system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15670500 # number of overall MSHR miss cycles
725system.cpu0.dcache.overall_mshr_miss_latency::total 15670500 # number of overall MSHR miss cycles
726system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002227 # mshr miss rate for ReadReq accesses
727system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002227 # mshr miss rate for ReadReq accesses
728system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001932 # mshr miss rate for WriteReq accesses
729system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001932 # mshr miss rate for WriteReq accesses

712system.cpu0.dcache.demand_mshr_misses::cpu0.data 369 # number of demand (read+write) MSHR misses
713system.cpu0.dcache.demand_mshr_misses::total 369 # number of demand (read+write) MSHR misses
714system.cpu0.dcache.overall_mshr_misses::cpu0.data 369 # number of overall MSHR misses
715system.cpu0.dcache.overall_mshr_misses::total 369 # number of overall MSHR misses
716system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7613500 # number of ReadReq MSHR miss cycles
717system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7613500 # number of ReadReq MSHR miss cycles
718system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8176500 # number of WriteReq MSHR miss cycles
719system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8176500 # number of WriteReq MSHR miss cycles
720system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 472500 # number of SwapReq MSHR miss cycles
721system.cpu0.dcache.SwapReq_mshr_miss_latency::total 472500 # number of SwapReq MSHR miss cycles
722system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15790000 # number of demand (read+write) MSHR miss cycles
723system.cpu0.dcache.demand_mshr_miss_latency::total 15790000 # number of demand (read+write) MSHR miss cycles
724system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15790000 # number of overall MSHR miss cycles
725system.cpu0.dcache.overall_mshr_miss_latency::total 15790000 # number of overall MSHR miss cycles
726system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002166 # mshr miss rate for ReadReq accesses
727system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses
728system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001930 # mshr miss rate for WriteReq accesses
729system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001930 # mshr miss rate for WriteReq accesses

730system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.428571 # mshr miss rate for SwapReq accesses
731system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SwapReq accesses

732system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for demand accesses
733system.cpu0.dcache.demand_mshr_miss_rate::total 0.002082 # mshr miss rate for demand accesses
734system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for overall accesses
735system.cpu0.dcache.overall_mshr_miss_rate::total 0.002082 # mshr miss rate for overall accesses
736system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37133.663366 # average ReadReq mshr miss latency
737system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37133.663366 # average ReadReq mshr miss latency
738system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48055.882353 # average WriteReq mshr miss latency
739system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48055.882353 # average WriteReq mshr miss latency
740system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111 # average SwapReq mshr miss latency
741system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111 # average SwapReq mshr miss latency
742system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency
743system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency
744system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency
745system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency
746system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
747system.cpu0.icache.tags.replacements 393 # number of replacements
748system.cpu0.icache.tags.tagsinuse 248.700617 # Cycle average of tags in use
749system.cpu0.icache.tags.total_refs 7078 # Total number of references to valid blocks.
750system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks.
751system.cpu0.icache.tags.avg_refs 10.184173 # Average number of references to valid blocks.

732system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for demand accesses
733system.cpu0.dcache.demand_mshr_miss_rate::total 0.002050 # mshr miss rate for demand accesses
734system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for overall accesses
735system.cpu0.dcache.overall_mshr_miss_rate::total 0.002050 # mshr miss rate for overall accesses
736system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38452.020202 # average ReadReq mshr miss latency
737system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38452.020202 # average ReadReq mshr miss latency
738system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47815.789474 # average WriteReq mshr miss latency
739system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47815.789474 # average WriteReq mshr miss latency
740system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26250 # average SwapReq mshr miss latency
741system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26250 # average SwapReq mshr miss latency
742system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency
743system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency
744system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency
745system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency
746system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
747system.cpu0.icache.tags.replacements 391 # number of replacements
748system.cpu0.icache.tags.tagsinuse 249.990139 # Cycle average of tags in use
749system.cpu0.icache.tags.total_refs 7433 # Total number of references to valid blocks.
750system.cpu0.icache.tags.sampled_refs 696 # Sample count of references to valid blocks.
751system.cpu0.icache.tags.avg_refs 10.679598 # Average number of references to valid blocks.

752system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

753system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.700617 # Average occupied blocks per requestor
754system.cpu0.icache.tags.occ_percent::cpu0.inst 0.485743 # Average percentage of cache occupancy
755system.cpu0.icache.tags.occ_percent::total 0.485743 # Average percentage of cache occupancy
756system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id
757system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id

753system.cpu0.icache.tags.occ_blocks::cpu0.inst 249.990139 # Average occupied blocks per requestor
754system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488262 # Average percentage of cache occupancy
755system.cpu0.icache.tags.occ_percent::total 0.488262 # Average percentage of cache occupancy
756system.cpu0.icache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id
757system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id

758system.cpu0.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id

759system.cpu0.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id
760system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id
761system.cpu0.icache.tags.tag_accesses 8690 # Number of tag accesses
762system.cpu0.icache.tags.data_accesses 8690 # Number of data accesses
763system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
764system.cpu0.icache.ReadReq_hits::cpu0.inst 7078 # number of ReadReq hits
765system.cpu0.icache.ReadReq_hits::total 7078 # number of ReadReq hits
766system.cpu0.icache.demand_hits::cpu0.inst 7078 # number of demand (read+write) hits
767system.cpu0.icache.demand_hits::total 7078 # number of demand (read+write) hits
768system.cpu0.icache.overall_hits::cpu0.inst 7078 # number of overall hits
769system.cpu0.icache.overall_hits::total 7078 # number of overall hits
770system.cpu0.icache.ReadReq_misses::cpu0.inst 917 # number of ReadReq misses
771system.cpu0.icache.ReadReq_misses::total 917 # number of ReadReq misses
772system.cpu0.icache.demand_misses::cpu0.inst 917 # number of demand (read+write) misses
773system.cpu0.icache.demand_misses::total 917 # number of demand (read+write) misses
774system.cpu0.icache.overall_misses::cpu0.inst 917 # number of overall misses
775system.cpu0.icache.overall_misses::total 917 # number of overall misses
776system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47775500 # number of ReadReq miss cycles
777system.cpu0.icache.ReadReq_miss_latency::total 47775500 # number of ReadReq miss cycles
778system.cpu0.icache.demand_miss_latency::cpu0.inst 47775500 # number of demand (read+write) miss cycles
779system.cpu0.icache.demand_miss_latency::total 47775500 # number of demand (read+write) miss cycles
780system.cpu0.icache.overall_miss_latency::cpu0.inst 47775500 # number of overall miss cycles
781system.cpu0.icache.overall_miss_latency::total 47775500 # number of overall miss cycles
782system.cpu0.icache.ReadReq_accesses::cpu0.inst 7995 # number of ReadReq accesses(hits+misses)
783system.cpu0.icache.ReadReq_accesses::total 7995 # number of ReadReq accesses(hits+misses)
784system.cpu0.icache.demand_accesses::cpu0.inst 7995 # number of demand (read+write) accesses
785system.cpu0.icache.demand_accesses::total 7995 # number of demand (read+write) accesses
786system.cpu0.icache.overall_accesses::cpu0.inst 7995 # number of overall (read+write) accesses
787system.cpu0.icache.overall_accesses::total 7995 # number of overall (read+write) accesses
788system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114697 # miss rate for ReadReq accesses
789system.cpu0.icache.ReadReq_miss_rate::total 0.114697 # miss rate for ReadReq accesses
790system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114697 # miss rate for demand accesses
791system.cpu0.icache.demand_miss_rate::total 0.114697 # miss rate for demand accesses
792system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114697 # miss rate for overall accesses
793system.cpu0.icache.overall_miss_rate::total 0.114697 # miss rate for overall accesses
794system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897 # average ReadReq miss latency
795system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897 # average ReadReq miss latency
796system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency
797system.cpu0.icache.demand_avg_miss_latency::total 52099.781897 # average overall miss latency
798system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency
799system.cpu0.icache.overall_avg_miss_latency::total 52099.781897 # average overall miss latency
800system.cpu0.icache.blocked_cycles::no_mshrs 151 # number of cycles access was blocked

759system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
760system.cpu0.icache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id
761system.cpu0.icache.tags.tag_accesses 9051 # Number of tag accesses
762system.cpu0.icache.tags.data_accesses 9051 # Number of data accesses
763system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
764system.cpu0.icache.ReadReq_hits::cpu0.inst 7433 # number of ReadReq hits
765system.cpu0.icache.ReadReq_hits::total 7433 # number of ReadReq hits
766system.cpu0.icache.demand_hits::cpu0.inst 7433 # number of demand (read+write) hits
767system.cpu0.icache.demand_hits::total 7433 # number of demand (read+write) hits
768system.cpu0.icache.overall_hits::cpu0.inst 7433 # number of overall hits
769system.cpu0.icache.overall_hits::total 7433 # number of overall hits
770system.cpu0.icache.ReadReq_misses::cpu0.inst 922 # number of ReadReq misses
771system.cpu0.icache.ReadReq_misses::total 922 # number of ReadReq misses
772system.cpu0.icache.demand_misses::cpu0.inst 922 # number of demand (read+write) misses
773system.cpu0.icache.demand_misses::total 922 # number of demand (read+write) misses
774system.cpu0.icache.overall_misses::cpu0.inst 922 # number of overall misses
775system.cpu0.icache.overall_misses::total 922 # number of overall misses
776system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48154500 # number of ReadReq miss cycles
777system.cpu0.icache.ReadReq_miss_latency::total 48154500 # number of ReadReq miss cycles
778system.cpu0.icache.demand_miss_latency::cpu0.inst 48154500 # number of demand (read+write) miss cycles
779system.cpu0.icache.demand_miss_latency::total 48154500 # number of demand (read+write) miss cycles
780system.cpu0.icache.overall_miss_latency::cpu0.inst 48154500 # number of overall miss cycles
781system.cpu0.icache.overall_miss_latency::total 48154500 # number of overall miss cycles
782system.cpu0.icache.ReadReq_accesses::cpu0.inst 8355 # number of ReadReq accesses(hits+misses)
783system.cpu0.icache.ReadReq_accesses::total 8355 # number of ReadReq accesses(hits+misses)
784system.cpu0.icache.demand_accesses::cpu0.inst 8355 # number of demand (read+write) accesses
785system.cpu0.icache.demand_accesses::total 8355 # number of demand (read+write) accesses
786system.cpu0.icache.overall_accesses::cpu0.inst 8355 # number of overall (read+write) accesses
787system.cpu0.icache.overall_accesses::total 8355 # number of overall (read+write) accesses
788system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110353 # miss rate for ReadReq accesses
789system.cpu0.icache.ReadReq_miss_rate::total 0.110353 # miss rate for ReadReq accesses
790system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110353 # miss rate for demand accesses
791system.cpu0.icache.demand_miss_rate::total 0.110353 # miss rate for demand accesses
792system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110353 # miss rate for overall accesses
793system.cpu0.icache.overall_miss_rate::total 0.110353 # miss rate for overall accesses
794system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52228.308026 # average ReadReq miss latency
795system.cpu0.icache.ReadReq_avg_miss_latency::total 52228.308026 # average ReadReq miss latency
796system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency
797system.cpu0.icache.demand_avg_miss_latency::total 52228.308026 # average overall miss latency
798system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency
799system.cpu0.icache.overall_avg_miss_latency::total 52228.308026 # average overall miss latency
800system.cpu0.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked

801system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

802system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked

802system.cpu0.icache.blocked::no_mshrs 8 # number of cycles access was blocked

803system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked

804system.cpu0.icache.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked

804system.cpu0.icache.avg_blocked_cycles::no_mshrs 50.125000 # average number of cycles each access was blocked

805system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

806system.cpu0.icache.writebacks::writebacks 393 # number of writebacks
807system.cpu0.icache.writebacks::total 393 # number of writebacks
808system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits
809system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits
810system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits
811system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
812system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits
813system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits
814system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses
815system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses
816system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses
817system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses
818system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses
819system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses
820system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36615000 # number of ReadReq MSHR miss cycles
821system.cpu0.icache.ReadReq_mshr_miss_latency::total 36615000 # number of ReadReq MSHR miss cycles
822system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36615000 # number of demand (read+write) MSHR miss cycles
823system.cpu0.icache.demand_mshr_miss_latency::total 36615000 # number of demand (read+write) MSHR miss cycles
824system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36615000 # number of overall MSHR miss cycles
825system.cpu0.icache.overall_mshr_miss_latency::total 36615000 # number of overall MSHR miss cycles
826system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for ReadReq accesses
827system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087054 # mshr miss rate for ReadReq accesses
828system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for demand accesses
829system.cpu0.icache.demand_mshr_miss_rate::total 0.087054 # mshr miss rate for demand accesses
830system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for overall accesses
831system.cpu0.icache.overall_mshr_miss_rate::total 0.087054 # mshr miss rate for overall accesses
832system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average ReadReq mshr miss latency
833system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621 # average ReadReq mshr miss latency
834system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency
835system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency
836system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency
837system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency
838system.cpu1.branchPred.lookups 69942 # Number of BP lookups
839system.cpu1.branchPred.condPredicted 62611 # Number of conditional branches predicted
840system.cpu1.branchPred.condIncorrect 2168 # Number of conditional branches incorrect
841system.cpu1.branchPred.BTBLookups 62876 # Number of BTB lookups

806system.cpu0.icache.writebacks::writebacks 391 # number of writebacks
807system.cpu0.icache.writebacks::total 391 # number of writebacks
808system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 225 # number of ReadReq MSHR hits
809system.cpu0.icache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits
810system.cpu0.icache.demand_mshr_hits::cpu0.inst 225 # number of demand (read+write) MSHR hits
811system.cpu0.icache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits
812system.cpu0.icache.overall_mshr_hits::cpu0.inst 225 # number of overall MSHR hits
813system.cpu0.icache.overall_mshr_hits::total 225 # number of overall MSHR hits
814system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697 # number of ReadReq MSHR misses
815system.cpu0.icache.ReadReq_mshr_misses::total 697 # number of ReadReq MSHR misses
816system.cpu0.icache.demand_mshr_misses::cpu0.inst 697 # number of demand (read+write) MSHR misses
817system.cpu0.icache.demand_mshr_misses::total 697 # number of demand (read+write) MSHR misses
818system.cpu0.icache.overall_mshr_misses::cpu0.inst 697 # number of overall MSHR misses
819system.cpu0.icache.overall_mshr_misses::total 697 # number of overall MSHR misses
820system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36741500 # number of ReadReq MSHR miss cycles
821system.cpu0.icache.ReadReq_mshr_miss_latency::total 36741500 # number of ReadReq MSHR miss cycles
822system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36741500 # number of demand (read+write) MSHR miss cycles
823system.cpu0.icache.demand_mshr_miss_latency::total 36741500 # number of demand (read+write) MSHR miss cycles
824system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36741500 # number of overall MSHR miss cycles
825system.cpu0.icache.overall_mshr_miss_latency::total 36741500 # number of overall MSHR miss cycles
826system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for ReadReq accesses
827system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.083423 # mshr miss rate for ReadReq accesses
828system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for demand accesses
829system.cpu0.icache.demand_mshr_miss_rate::total 0.083423 # mshr miss rate for demand accesses
830system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for overall accesses
831system.cpu0.icache.overall_mshr_miss_rate::total 0.083423 # mshr miss rate for overall accesses
832system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average ReadReq mshr miss latency
833system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52713.773314 # average ReadReq mshr miss latency
834system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency
835system.cpu0.icache.demand_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency
836system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency
837system.cpu0.icache.overall_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency
838system.cpu1.branchPred.lookups 67120 # Number of BP lookups
839system.cpu1.branchPred.condPredicted 59252 # Number of conditional branches predicted
840system.cpu1.branchPred.condIncorrect 2530 # Number of conditional branches incorrect
841system.cpu1.branchPred.BTBLookups 59078 # Number of BTB lookups

842system.cpu1.branchPred.BTBHits 0 # Number of BTB hits
843system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
844system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

845system.cpu1.branchPred.usedRAS 1880 # Number of times the RAS was used to get a target.

845system.cpu1.branchPred.usedRAS 2033 # Number of times the RAS was used to get a target.

846system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

847system.cpu1.branchPred.indirectLookups 62876 # Number of indirect predictor lookups.
848system.cpu1.branchPred.indirectHits 52518 # Number of indirect target hits.
849system.cpu1.branchPred.indirectMisses 10358 # Number of indirect misses.
850system.cpu1.branchPredindirectMispredicted 1122 # Number of mispredicted indirect branches.
851system.cpu1.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states
852system.cpu1.numCycles 191834 # number of cpu cycles simulated

847system.cpu1.branchPred.indirectLookups 59078 # Number of indirect predictor lookups.
848system.cpu1.branchPred.indirectHits 48199 # Number of indirect target hits.
849system.cpu1.branchPred.indirectMisses 10879 # Number of indirect misses.
850system.cpu1.branchPredindirectMispredicted 1412 # Number of mispredicted indirect branches.
851system.cpu1.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states
852system.cpu1.numCycles 194937 # number of cpu cycles simulated

853system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
854system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

855system.cpu1.fetch.icacheStallCycles 35275 # Number of cycles fetch is stalled on an Icache miss
856system.cpu1.fetch.Insts 386727 # Number of instructions fetch has processed
857system.cpu1.fetch.Branches 69942 # Number of branches that fetch encountered
858system.cpu1.fetch.predictedBranches 54398 # Number of branches that fetch has predicted taken
859system.cpu1.fetch.Cycles 146033 # Number of cycles fetch has run and was not squashing or blocked
860system.cpu1.fetch.SquashCycles 4493 # Number of cycles fetch has spent squashing
861system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

855system.cpu1.fetch.icacheStallCycles 38450 # Number of cycles fetch is stalled on an Icache miss
856system.cpu1.fetch.Insts 366689 # Number of instructions fetch has processed
857system.cpu1.fetch.Branches 67120 # Number of branches that fetch encountered
858system.cpu1.fetch.predictedBranches 50232 # Number of branches that fetch has predicted taken
859system.cpu1.fetch.Cycles 144025 # Number of cycles fetch has run and was not squashing or blocked
860system.cpu1.fetch.SquashCycles 5215 # Number of cycles fetch has spent squashing
861system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

862system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

863system.cpu1.fetch.PendingTrapStallCycles 1374 # Number of stall cycles due to pending traps
864system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
865system.cpu1.fetch.CacheLines 23469 # Number of cache lines fetched
866system.cpu1.fetch.IcacheSquashes 905 # Number of outstanding Icache misses that were squashed
867system.cpu1.fetch.rateDist::samples 184982 # Number of instructions fetched each cycle (Total)
868system.cpu1.fetch.rateDist::mean 2.090620 # Number of instructions fetched each cycle (Total)
869system.cpu1.fetch.rateDist::stdev 2.368236 # Number of instructions fetched each cycle (Total)

863system.cpu1.fetch.PendingTrapStallCycles 1847 # Number of stall cycles due to pending traps
864system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
865system.cpu1.fetch.CacheLines 26490 # Number of cache lines fetched
866system.cpu1.fetch.IcacheSquashes 1009 # Number of outstanding Icache misses that were squashed
867system.cpu1.fetch.rateDist::samples 186966 # Number of instructions fetched each cycle (Total)
868system.cpu1.fetch.rateDist::mean 1.961260 # Number of instructions fetched each cycle (Total)
869system.cpu1.fetch.rateDist::stdev 2.371242 # Number of instructions fetched each cycle (Total)

870system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

871system.cpu1.fetch.rateDist::0 58784 31.78% 31.78% # Number of instructions fetched each cycle (Total)
872system.cpu1.fetch.rateDist::1 61509 33.25% 65.03% # Number of instructions fetched each cycle (Total)
873system.cpu1.fetch.rateDist::2 6216 3.36% 68.39% # Number of instructions fetched each cycle (Total)
874system.cpu1.fetch.rateDist::3 3423 1.85% 70.24% # Number of instructions fetched each cycle (Total)
875system.cpu1.fetch.rateDist::4 694 0.38% 70.62% # Number of instructions fetched each cycle (Total)
876system.cpu1.fetch.rateDist::5 43897 23.73% 94.35% # Number of instructions fetched each cycle (Total)
877system.cpu1.fetch.rateDist::6 1064 0.58% 94.92% # Number of instructions fetched each cycle (Total)
878system.cpu1.fetch.rateDist::7 1288 0.70% 95.62% # Number of instructions fetched each cycle (Total)
879system.cpu1.fetch.rateDist::8 8107 4.38% 100.00% # Number of instructions fetched each cycle (Total)

871system.cpu1.fetch.rateDist::0 66801 35.73% 35.73% # Number of instructions fetched each cycle (Total)
872system.cpu1.fetch.rateDist::1 58781 31.44% 67.17% # Number of instructions fetched each cycle (Total)
873system.cpu1.fetch.rateDist::2 7398 3.96% 71.13% # Number of instructions fetched each cycle (Total)
874system.cpu1.fetch.rateDist::3 3358 1.80% 72.92% # Number of instructions fetched each cycle (Total)
875system.cpu1.fetch.rateDist::4 642 0.34% 73.26% # Number of instructions fetched each cycle (Total)
876system.cpu1.fetch.rateDist::5 38588 20.64% 93.90% # Number of instructions fetched each cycle (Total)
877system.cpu1.fetch.rateDist::6 1104 0.59% 94.49% # Number of instructions fetched each cycle (Total)
878system.cpu1.fetch.rateDist::7 1446 0.77% 95.27% # Number of instructions fetched each cycle (Total)
879system.cpu1.fetch.rateDist::8 8848 4.73% 100.00% # Number of instructions fetched each cycle (Total)

880system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
881system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
882system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

883system.cpu1.fetch.rateDist::total 184982 # Number of instructions fetched each cycle (Total)
884system.cpu1.fetch.branchRate 0.364596 # Number of branch fetches per cycle
885system.cpu1.fetch.rate 2.015946 # Number of inst fetches per cycle
886system.cpu1.decode.IdleCycles 21795 # Number of cycles decode is idle
887system.cpu1.decode.BlockedCycles 53545 # Number of cycles decode is blocked
888system.cpu1.decode.RunCycles 103882 # Number of cycles decode is running
889system.cpu1.decode.UnblockCycles 3504 # Number of cycles decode is unblocking
890system.cpu1.decode.SquashCycles 2246 # Number of cycles decode is squashing
891system.cpu1.decode.DecodedInsts 357234 # Number of instructions handled by decode
892system.cpu1.rename.SquashCycles 2246 # Number of cycles rename is squashing
893system.cpu1.rename.IdleCycles 22757 # Number of cycles rename is idle
894system.cpu1.rename.BlockCycles 24349 # Number of cycles rename is blocking
895system.cpu1.rename.serializeStallCycles 13357 # count of cycles rename stalled for serializing inst
896system.cpu1.rename.RunCycles 104467 # Number of cycles rename is running
897system.cpu1.rename.UnblockCycles 17796 # Number of cycles rename is unblocking
898system.cpu1.rename.RenamedInsts 350958 # Number of instructions processed by rename
899system.cpu1.rename.IQFullEvents 15108 # Number of times rename has blocked due to IQ full
900system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full

883system.cpu1.fetch.rateDist::total 186966 # Number of instructions fetched each cycle (Total)
884system.cpu1.fetch.branchRate 0.344316 # Number of branch fetches per cycle
885system.cpu1.fetch.rate 1.881064 # Number of inst fetches per cycle
886system.cpu1.decode.IdleCycles 23546 # Number of cycles decode is idle
887system.cpu1.decode.BlockedCycles 62450 # Number of cycles decode is blocked
888system.cpu1.decode.RunCycles 94215 # Number of cycles decode is running
889system.cpu1.decode.UnblockCycles 4138 # Number of cycles decode is unblocking
890system.cpu1.decode.SquashCycles 2607 # Number of cycles decode is squashing
891system.cpu1.decode.DecodedInsts 335701 # Number of instructions handled by decode
892system.cpu1.rename.SquashCycles 2607 # Number of cycles rename is squashing
893system.cpu1.rename.IdleCycles 24537 # Number of cycles rename is idle
894system.cpu1.rename.BlockCycles 29865 # Number of cycles rename is blocking
895system.cpu1.rename.serializeStallCycles 13172 # count of cycles rename stalled for serializing inst
896system.cpu1.rename.RunCycles 95090 # Number of cycles rename is running
897system.cpu1.rename.UnblockCycles 21685 # Number of cycles rename is unblocking
898system.cpu1.rename.RenamedInsts 329147 # Number of instructions processed by rename
899system.cpu1.rename.IQFullEvents 18681 # Number of times rename has blocked due to IQ full
900system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full

901system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers

902system.cpu1.rename.RenamedOperands 246923 # Number of destination operands rename has renamed
903system.cpu1.rename.RenameLookups 678000 # Number of register rename lookups that rename has made
904system.cpu1.rename.int_rename_lookups 525614 # Number of integer rename lookups
905system.cpu1.rename.fp_rename_lookups 22 # Number of floating rename lookups
906system.cpu1.rename.CommittedMaps 220975 # Number of HB maps that are committed
907system.cpu1.rename.UndoneMaps 25948 # Number of HB maps that are undone due to squashing
908system.cpu1.rename.serializingInsts 1579 # count of serializing insts renamed
909system.cpu1.rename.tempSerializingInsts 1706 # count of temporary serializing insts renamed
910system.cpu1.rename.skidInsts 23252 # count of insts added to the skid buffer
911system.cpu1.memDep0.insertedLoads 99419 # Number of loads inserted to the mem dependence unit.
912system.cpu1.memDep0.insertedStores 48107 # Number of stores inserted to the mem dependence unit.
913system.cpu1.memDep0.conflictingLoads 46982 # Number of conflicting loads.
914system.cpu1.memDep0.conflictingStores 41894 # Number of conflicting stores.
915system.cpu1.iq.iqInstsAdded 289725 # Number of instructions added to the IQ (excludes non-spec)
916system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ
917system.cpu1.iq.iqInstsIssued 288968 # Number of instructions issued
918system.cpu1.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued
919system.cpu1.iq.iqSquashedInstsExamined 22905 # Number of squashed instructions iterated over during squash; mainly for profiling
920system.cpu1.iq.iqSquashedOperandsExamined 18076 # Number of squashed operands that are examined and possibly removed from graph
921system.cpu1.iq.iqSquashedNonSpecRemoved 1082 # Number of squashed non-spec instructions that were removed
922system.cpu1.iq.issued_per_cycle::samples 184982 # Number of insts issued each cycle
923system.cpu1.iq.issued_per_cycle::mean 1.562141 # Number of insts issued each cycle
924system.cpu1.iq.issued_per_cycle::stdev 1.375121 # Number of insts issued each cycle

902system.cpu1.rename.RenamedOperands 231661 # Number of destination operands rename has renamed
903system.cpu1.rename.RenameLookups 629076 # Number of register rename lookups that rename has made
904system.cpu1.rename.int_rename_lookups 489741 # Number of integer rename lookups
905system.cpu1.rename.fp_rename_lookups 26 # Number of floating rename lookups
906system.cpu1.rename.CommittedMaps 200931 # Number of HB maps that are committed
907system.cpu1.rename.UndoneMaps 30730 # Number of HB maps that are undone due to squashing
908system.cpu1.rename.serializingInsts 1664 # count of serializing insts renamed
909system.cpu1.rename.tempSerializingInsts 1812 # count of temporary serializing insts renamed
910system.cpu1.rename.skidInsts 26977 # count of insts added to the skid buffer
911system.cpu1.memDep0.insertedLoads 90636 # Number of loads inserted to the mem dependence unit.
912system.cpu1.memDep0.insertedStores 43093 # Number of stores inserted to the mem dependence unit.
913system.cpu1.memDep0.conflictingLoads 42743 # Number of conflicting loads.
914system.cpu1.memDep0.conflictingStores 36583 # Number of conflicting stores.
915system.cpu1.iq.iqInstsAdded 268793 # Number of instructions added to the IQ (excludes non-spec)
916system.cpu1.iq.iqNonSpecInstsAdded 7661 # Number of non-speculative instructions added to the IQ
917system.cpu1.iq.iqInstsIssued 268125 # Number of instructions issued
918system.cpu1.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued
919system.cpu1.iq.iqSquashedInstsExamined 26316 # Number of squashed instructions iterated over during squash; mainly for profiling
920system.cpu1.iq.iqSquashedOperandsExamined 21262 # Number of squashed operands that are examined and possibly removed from graph
921system.cpu1.iq.iqSquashedNonSpecRemoved 1168 # Number of squashed non-spec instructions that were removed
922system.cpu1.iq.issued_per_cycle::samples 186966 # Number of insts issued each cycle
923system.cpu1.iq.issued_per_cycle::mean 1.434084 # Number of insts issued each cycle
924system.cpu1.iq.issued_per_cycle::stdev 1.397924 # Number of insts issued each cycle

925system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

926system.cpu1.iq.issued_per_cycle::0 62949 34.03% 34.03% # Number of insts issued each cycle
927system.cpu1.iq.issued_per_cycle::1 21563 11.66% 45.69% # Number of insts issued each cycle
928system.cpu1.iq.issued_per_cycle::2 46877 25.34% 71.03% # Number of insts issued each cycle
929system.cpu1.iq.issued_per_cycle::3 46716 25.25% 96.28% # Number of insts issued each cycle
930system.cpu1.iq.issued_per_cycle::4 3504 1.89% 98.18% # Number of insts issued each cycle
931system.cpu1.iq.issued_per_cycle::5 1701 0.92% 99.10% # Number of insts issued each cycle
932system.cpu1.iq.issued_per_cycle::6 999 0.54% 99.64% # Number of insts issued each cycle
933system.cpu1.iq.issued_per_cycle::7 396 0.21% 99.85% # Number of insts issued each cycle
934system.cpu1.iq.issued_per_cycle::8 277 0.15% 100.00% # Number of insts issued each cycle

926system.cpu1.iq.issued_per_cycle::0 71753 38.38% 38.38% # Number of insts issued each cycle
927system.cpu1.iq.issued_per_cycle::1 24944 13.34% 51.72% # Number of insts issued each cycle
928system.cpu1.iq.issued_per_cycle::2 41684 22.29% 74.01% # Number of insts issued each cycle
929system.cpu1.iq.issued_per_cycle::3 41301 22.09% 96.10% # Number of insts issued each cycle
930system.cpu1.iq.issued_per_cycle::4 3557 1.90% 98.01% # Number of insts issued each cycle
931system.cpu1.iq.issued_per_cycle::5 1804 0.96% 98.97% # Number of insts issued each cycle
932system.cpu1.iq.issued_per_cycle::6 1118 0.60% 99.57% # Number of insts issued each cycle
933system.cpu1.iq.issued_per_cycle::7 486 0.26% 99.83% # Number of insts issued each cycle
934system.cpu1.iq.issued_per_cycle::8 319 0.17% 100.00% # Number of insts issued each cycle

935system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
936system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
937system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

938system.cpu1.iq.issued_per_cycle::total 184982 # Number of insts issued each cycle

938system.cpu1.iq.issued_per_cycle::total 186966 # Number of insts issued each cycle

939system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

940system.cpu1.iq.fu_full::IntAlu 191 40.04% 40.04% # attempts to use FU when none available
941system.cpu1.iq.fu_full::IntMult 0 0.00% 40.04% # attempts to use FU when none available
942system.cpu1.iq.fu_full::IntDiv 0 0.00% 40.04% # attempts to use FU when none available
943system.cpu1.iq.fu_full::FloatAdd 0 0.00% 40.04% # attempts to use FU when none available
944system.cpu1.iq.fu_full::FloatCmp 0 0.00% 40.04% # attempts to use FU when none available
945system.cpu1.iq.fu_full::FloatCvt 0 0.00% 40.04% # attempts to use FU when none available
946system.cpu1.iq.fu_full::FloatMult 0 0.00% 40.04% # attempts to use FU when none available
947system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available
948system.cpu1.iq.fu_full::FloatDiv 0 0.00% 40.04% # attempts to use FU when none available
949system.cpu1.iq.fu_full::FloatMisc 0 0.00% 40.04% # attempts to use FU when none available
950system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 40.04% # attempts to use FU when none available
951system.cpu1.iq.fu_full::SimdAdd 0 0.00% 40.04% # attempts to use FU when none available
952system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 40.04% # attempts to use FU when none available
953system.cpu1.iq.fu_full::SimdAlu 0 0.00% 40.04% # attempts to use FU when none available
954system.cpu1.iq.fu_full::SimdCmp 0 0.00% 40.04% # attempts to use FU when none available
955system.cpu1.iq.fu_full::SimdCvt 0 0.00% 40.04% # attempts to use FU when none available
956system.cpu1.iq.fu_full::SimdMisc 0 0.00% 40.04% # attempts to use FU when none available
957system.cpu1.iq.fu_full::SimdMult 0 0.00% 40.04% # attempts to use FU when none available
958system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 40.04% # attempts to use FU when none available
959system.cpu1.iq.fu_full::SimdShift 0 0.00% 40.04% # attempts to use FU when none available
960system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 40.04% # attempts to use FU when none available
961system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 40.04% # attempts to use FU when none available
962system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 40.04% # attempts to use FU when none available
963system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 40.04% # attempts to use FU when none available
964system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 40.04% # attempts to use FU when none available
965system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 40.04% # attempts to use FU when none available
966system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 40.04% # attempts to use FU when none available
967system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 40.04% # attempts to use FU when none available
968system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 40.04% # attempts to use FU when none available
969system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available
970system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 40.04% # attempts to use FU when none available
971system.cpu1.iq.fu_full::MemRead 60 12.58% 52.62% # attempts to use FU when none available
972system.cpu1.iq.fu_full::MemWrite 226 47.38% 100.00% # attempts to use FU when none available

940system.cpu1.iq.fu_full::IntAlu 231 42.39% 42.39% # attempts to use FU when none available
941system.cpu1.iq.fu_full::IntMult 0 0.00% 42.39% # attempts to use FU when none available
942system.cpu1.iq.fu_full::IntDiv 0 0.00% 42.39% # attempts to use FU when none available
943system.cpu1.iq.fu_full::FloatAdd 0 0.00% 42.39% # attempts to use FU when none available
944system.cpu1.iq.fu_full::FloatCmp 0 0.00% 42.39% # attempts to use FU when none available
945system.cpu1.iq.fu_full::FloatCvt 0 0.00% 42.39% # attempts to use FU when none available
946system.cpu1.iq.fu_full::FloatMult 0 0.00% 42.39% # attempts to use FU when none available
947system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available
948system.cpu1.iq.fu_full::FloatDiv 0 0.00% 42.39% # attempts to use FU when none available
949system.cpu1.iq.fu_full::FloatMisc 0 0.00% 42.39% # attempts to use FU when none available
950system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 42.39% # attempts to use FU when none available
951system.cpu1.iq.fu_full::SimdAdd 0 0.00% 42.39% # attempts to use FU when none available
952system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 42.39% # attempts to use FU when none available
953system.cpu1.iq.fu_full::SimdAlu 0 0.00% 42.39% # attempts to use FU when none available
954system.cpu1.iq.fu_full::SimdCmp 0 0.00% 42.39% # attempts to use FU when none available
955system.cpu1.iq.fu_full::SimdCvt 0 0.00% 42.39% # attempts to use FU when none available
956system.cpu1.iq.fu_full::SimdMisc 0 0.00% 42.39% # attempts to use FU when none available
957system.cpu1.iq.fu_full::SimdMult 0 0.00% 42.39% # attempts to use FU when none available
958system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 42.39% # attempts to use FU when none available
959system.cpu1.iq.fu_full::SimdShift 0 0.00% 42.39% # attempts to use FU when none available
960system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 42.39% # attempts to use FU when none available
961system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 42.39% # attempts to use FU when none available
962system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 42.39% # attempts to use FU when none available
963system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 42.39% # attempts to use FU when none available
964system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 42.39% # attempts to use FU when none available
965system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 42.39% # attempts to use FU when none available
966system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 42.39% # attempts to use FU when none available
967system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 42.39% # attempts to use FU when none available
968system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 42.39% # attempts to use FU when none available
969system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available
970system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 42.39% # attempts to use FU when none available
971system.cpu1.iq.fu_full::MemRead 72 13.21% 55.60% # attempts to use FU when none available
972system.cpu1.iq.fu_full::MemWrite 242 44.40% 100.00% # attempts to use FU when none available

973system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
974system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
975system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
976system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
977system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

978system.cpu1.iq.FU_type_0::IntAlu 138690 47.99% 47.99% # Type of FU issued
979system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued
980system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued
981system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued
982system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued
983system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued
984system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued
985system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 47.99% # Type of FU issued
986system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued
987system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 47.99% # Type of FU issued
988system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued
989system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued
990system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued
991system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued
992system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued
993system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued
994system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued
995system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued
996system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued
997system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued
998system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued
999system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued
1000system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued
1001system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued
1002system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued
1003system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued
1004system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued
1005system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued
1006system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued
1007system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued
1008system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued
1009system.cpu1.iq.FU_type_0::MemRead 103154 35.70% 83.69% # Type of FU issued
1010system.cpu1.iq.FU_type_0::MemWrite 47124 16.31% 100.00% # Type of FU issued

978system.cpu1.iq.FU_type_0::IntAlu 130845 48.80% 48.80% # Type of FU issued
979system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued
980system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued
981system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued
982system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued
983system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued
984system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued
985system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued
986system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued
987system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued
988system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued
989system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued
990system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued
991system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued
992system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued
993system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued
994system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued
995system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued
996system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued
997system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued
998system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued
999system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued
1000system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued
1001system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued
1002system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued
1003system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued
1004system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued
1005system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued
1006system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued
1007system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued
1008system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued
1009system.cpu1.iq.FU_type_0::MemRead 95251 35.52% 84.32% # Type of FU issued
1010system.cpu1.iq.FU_type_0::MemWrite 42029 15.68% 100.00% # Type of FU issued

1011system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
1012system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
1013system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1014system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1015system.cpu1.iq.FU_type_0::total 288968 # Type of FU issued
1016system.cpu1.iq.rate 1.506344 # Inst issue rate
1017system.cpu1.iq.fu_busy_cnt 477 # FU busy when requested
1018system.cpu1.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst)
1019system.cpu1.iq.int_inst_queue_reads 763491 # Number of integer instruction queue reads
1020system.cpu1.iq.int_inst_queue_writes 319139 # Number of integer instruction queue writes
1021system.cpu1.iq.int_inst_queue_wakeup_accesses 285378 # Number of integer instruction queue wakeup accesses

1015system.cpu1.iq.FU_type_0::total 268125 # Type of FU issued
1016system.cpu1.iq.rate 1.375444 # Inst issue rate
1017system.cpu1.iq.fu_busy_cnt 545 # FU busy when requested
1018system.cpu1.iq.fu_busy_rate 0.002033 # FU busy rate (busy events/executed inst)
1019system.cpu1.iq.int_inst_queue_reads 723897 # Number of integer instruction queue reads
1020system.cpu1.iq.int_inst_queue_writes 302756 # Number of integer instruction queue writes
1021system.cpu1.iq.int_inst_queue_wakeup_accesses 263753 # Number of integer instruction queue wakeup accesses

1022system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

1023system.cpu1.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes

1023system.cpu1.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes

1024system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1025system.cpu1.iq.int_alu_accesses 289445 # Number of integer alu accesses

1025system.cpu1.iq.int_alu_accesses 268670 # Number of integer alu accesses

1026system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1027system.cpu1.iew.lsq.thread0.forwLoads 41785 # Number of loads that had data forwarded from stores

1027system.cpu1.iew.lsq.thread0.forwLoads 36498 # Number of loads that had data forwarded from stores

1028system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1029system.cpu1.iew.lsq.thread0.squashedLoads 4131 # Number of loads squashed
1030system.cpu1.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed
1031system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
1032system.cpu1.iew.lsq.thread0.squashedStores 2566 # Number of stores squashed

1029system.cpu1.iew.lsq.thread0.squashedLoads 4839 # Number of loads squashed
1030system.cpu1.iew.lsq.thread0.ignoredResponses 41 # Number of memory responses ignored because the instruction is squashed
1031system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
1032system.cpu1.iew.lsq.thread0.squashedStores 2826 # Number of stores squashed

1033system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1034system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1035system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1036system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1037system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1038system.cpu1.iew.iewSquashCycles 2246 # Number of cycles IEW is squashing
1039system.cpu1.iew.iewBlockCycles 7047 # Number of cycles IEW is blocking

1038system.cpu1.iew.iewSquashCycles 2607 # Number of cycles IEW is squashing
1039system.cpu1.iew.iewBlockCycles 8495 # Number of cycles IEW is blocking

1040system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking

1041system.cpu1.iew.iewDispatchedInsts 344310 # Number of instructions dispatched to IQ
1042system.cpu1.iew.iewDispSquashedInsts 276 # Number of squashed instructions skipped by dispatch
1043system.cpu1.iew.iewDispLoadInsts 99419 # Number of dispatched load instructions
1044system.cpu1.iew.iewDispStoreInsts 48107 # Number of dispatched store instructions
1045system.cpu1.iew.iewDispNonSpecInsts 1464 # Number of dispatched non-speculative instructions
1046system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall

1041system.cpu1.iew.iewDispatchedInsts 320469 # Number of instructions dispatched to IQ
1042system.cpu1.iew.iewDispSquashedInsts 297 # Number of squashed instructions skipped by dispatch
1043system.cpu1.iew.iewDispLoadInsts 90636 # Number of dispatched load instructions
1044system.cpu1.iew.iewDispStoreInsts 43093 # Number of dispatched store instructions
1045system.cpu1.iew.iewDispNonSpecInsts 1513 # Number of dispatched non-speculative instructions
1046system.cpu1.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall

1047system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1048system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
1049system.cpu1.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly
1050system.cpu1.iew.predictedNotTakenIncorrect 2268 # Number of branches that were predicted not taken incorrectly
1051system.cpu1.iew.branchMispredicts 2730 # Number of branch mispredicts detected at execute
1052system.cpu1.iew.iewExecutedInsts 286645 # Number of executed instructions
1053system.cpu1.iew.iewExecLoadInsts 97925 # Number of load instructions executed
1054system.cpu1.iew.iewExecSquashedInsts 2323 # Number of squashed instructions skipped in execute

1048system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
1049system.cpu1.iew.predictedTakenIncorrect 472 # Number of branches that were predicted taken incorrectly
1050system.cpu1.iew.predictedNotTakenIncorrect 2728 # Number of branches that were predicted not taken incorrectly
1051system.cpu1.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute
1052system.cpu1.iew.iewExecutedInsts 265301 # Number of executed instructions
1053system.cpu1.iew.iewExecLoadInsts 88817 # Number of load instructions executed
1054system.cpu1.iew.iewExecSquashedInsts 2824 # Number of squashed instructions skipped in execute

1055system.cpu1.iew.exec_swp 0 # number of swp insts executed

1056system.cpu1.iew.exec_nop 48075 # number of nop insts executed
1057system.cpu1.iew.exec_refs 144750 # number of memory reference insts executed
1058system.cpu1.iew.exec_branches 58305 # Number of branches executed
1059system.cpu1.iew.exec_stores 46825 # Number of stores executed
1060system.cpu1.iew.exec_rate 1.494235 # Inst execution rate
1061system.cpu1.iew.wb_sent 285841 # cumulative count of insts sent to commit
1062system.cpu1.iew.wb_count 285378 # cumulative count of insts written-back
1063system.cpu1.iew.wb_producers 162569 # num instructions producing a value
1064system.cpu1.iew.wb_consumers 170014 # num instructions consuming a value
1065system.cpu1.iew.wb_rate 1.487630 # insts written-back per cycle
1066system.cpu1.iew.wb_fanout 0.956209 # average fanout of values written-back
1067system.cpu1.commit.commitSquashedInsts 23932 # The number of squashed insts skipped by commit
1068system.cpu1.commit.commitNonSpecStalls 5428 # The number of times commit has been forced to stall to communicate backwards
1069system.cpu1.commit.branchMispredicts 2168 # The number of times a branch was mispredicted
1070system.cpu1.commit.committed_per_cycle::samples 180468 # Number of insts commited each cycle
1071system.cpu1.commit.committed_per_cycle::mean 1.775063 # Number of insts commited each cycle
1072system.cpu1.commit.committed_per_cycle::stdev 2.087699 # Number of insts commited each cycle

1056system.cpu1.iew.exec_nop 44015 # number of nop insts executed
1057system.cpu1.iew.exec_refs 130506 # number of memory reference insts executed
1058system.cpu1.iew.exec_branches 54427 # Number of branches executed
1059system.cpu1.iew.exec_stores 41689 # Number of stores executed
1060system.cpu1.iew.exec_rate 1.360958 # Inst execution rate
1061system.cpu1.iew.wb_sent 264333 # cumulative count of insts sent to commit
1062system.cpu1.iew.wb_count 263753 # cumulative count of insts written-back
1063system.cpu1.iew.wb_producers 148277 # num instructions producing a value
1064system.cpu1.iew.wb_consumers 156026 # num instructions consuming a value
1065system.cpu1.iew.wb_rate 1.353017 # insts written-back per cycle
1066system.cpu1.iew.wb_fanout 0.950335 # average fanout of values written-back
1067system.cpu1.commit.commitSquashedInsts 27498 # The number of squashed insts skipped by commit
1068system.cpu1.commit.commitNonSpecStalls 6493 # The number of times commit has been forced to stall to communicate backwards
1069system.cpu1.commit.branchMispredicts 2530 # The number of times a branch was mispredicted
1070system.cpu1.commit.committed_per_cycle::samples 181716 # Number of insts commited each cycle
1071system.cpu1.commit.committed_per_cycle::mean 1.612048 # Number of insts commited each cycle
1072system.cpu1.commit.committed_per_cycle::stdev 2.042470 # Number of insts commited each cycle

1073system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1074system.cpu1.commit.committed_per_cycle::0 67886 37.62% 37.62% # Number of insts commited each cycle
1075system.cpu1.commit.committed_per_cycle::1 54714 30.32% 67.93% # Number of insts commited each cycle
1076system.cpu1.commit.committed_per_cycle::2 5489 3.04% 70.98% # Number of insts commited each cycle
1077system.cpu1.commit.committed_per_cycle::3 6162 3.41% 74.39% # Number of insts commited each cycle
1078system.cpu1.commit.committed_per_cycle::4 1291 0.72% 75.11% # Number of insts commited each cycle
1079system.cpu1.commit.committed_per_cycle::5 41971 23.26% 98.36% # Number of insts commited each cycle
1080system.cpu1.commit.committed_per_cycle::6 718 0.40% 98.76% # Number of insts commited each cycle
1081system.cpu1.commit.committed_per_cycle::7 1059 0.59% 99.35% # Number of insts commited each cycle
1082system.cpu1.commit.committed_per_cycle::8 1178 0.65% 100.00% # Number of insts commited each cycle

1074system.cpu1.commit.committed_per_cycle::0 77632 42.72% 42.72% # Number of insts commited each cycle
1075system.cpu1.commit.committed_per_cycle::1 50511 27.80% 70.52% # Number of insts commited each cycle
1076system.cpu1.commit.committed_per_cycle::2 5466 3.01% 73.53% # Number of insts commited each cycle
1077system.cpu1.commit.committed_per_cycle::3 7144 3.93% 77.46% # Number of insts commited each cycle
1078system.cpu1.commit.committed_per_cycle::4 1253 0.69% 78.15% # Number of insts commited each cycle
1079system.cpu1.commit.committed_per_cycle::5 36670 20.18% 98.33% # Number of insts commited each cycle
1080system.cpu1.commit.committed_per_cycle::6 792 0.44% 98.76% # Number of insts commited each cycle
1081system.cpu1.commit.committed_per_cycle::7 1038 0.57% 99.33% # Number of insts commited each cycle
1082system.cpu1.commit.committed_per_cycle::8 1210 0.67% 100.00% # Number of insts commited each cycle

1083system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1084system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1085system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1086system.cpu1.commit.committed_per_cycle::total 180468 # Number of insts commited each cycle
1087system.cpu1.commit.committedInsts 320342 # Number of instructions committed
1088system.cpu1.commit.committedOps 320342 # Number of ops (including micro ops) committed

1086system.cpu1.commit.committed_per_cycle::total 181716 # Number of insts commited each cycle
1087system.cpu1.commit.committedInsts 292935 # Number of instructions committed
1088system.cpu1.commit.committedOps 292935 # Number of ops (including micro ops) committed

1089system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

1090system.cpu1.commit.refs 140829 # Number of memory references committed
1091system.cpu1.commit.loads 95288 # Number of loads committed
1092system.cpu1.commit.membars 4715 # Number of memory barriers committed
1093system.cpu1.commit.branches 56221 # Number of branches committed

1090system.cpu1.commit.refs 126064 # Number of memory references committed
1091system.cpu1.commit.loads 85797 # Number of loads committed
1092system.cpu1.commit.membars 5779 # Number of memory barriers committed
1093system.cpu1.commit.branches 52007 # Number of branches committed

1094system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.

1095system.cpu1.commit.int_insts 219172 # Number of committed integer instructions.

1095system.cpu1.commit.int_insts 200194 # Number of committed integer instructions.

1096system.cpu1.commit.function_calls 322 # Number of function calls committed.

1097system.cpu1.commit.op_class_0::No_OpClass 47012 14.68% 14.68% # Class of committed instruction
1098system.cpu1.commit.op_class_0::IntAlu 127786 39.89% 54.57% # Class of committed instruction
1099system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.57% # Class of committed instruction
1100system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.57% # Class of committed instruction
1101system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.57% # Class of committed instruction
1102system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.57% # Class of committed instruction
1103system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.57% # Class of committed instruction
1104system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.57% # Class of committed instruction
1105system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.57% # Class of committed instruction
1106system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.57% # Class of committed instruction
1107system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.57% # Class of committed instruction
1108system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.57% # Class of committed instruction
1109system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.57% # Class of committed instruction
1110system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.57% # Class of committed instruction
1111system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.57% # Class of committed instruction
1112system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.57% # Class of committed instruction
1113system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.57% # Class of committed instruction
1114system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.57% # Class of committed instruction
1115system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.57% # Class of committed instruction
1116system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.57% # Class of committed instruction
1117system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.57% # Class of committed instruction
1118system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.57% # Class of committed instruction
1119system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.57% # Class of committed instruction
1120system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.57% # Class of committed instruction
1121system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.57% # Class of committed instruction
1122system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.57% # Class of committed instruction
1123system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.57% # Class of committed instruction
1124system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.57% # Class of committed instruction
1125system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.57% # Class of committed instruction
1126system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.57% # Class of committed instruction
1127system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.57% # Class of committed instruction
1128system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.57% # Class of committed instruction
1129system.cpu1.commit.op_class_0::MemRead 100003 31.22% 85.78% # Class of committed instruction
1130system.cpu1.commit.op_class_0::MemWrite 45541 14.22% 100.00% # Class of committed instruction

1097system.cpu1.commit.op_class_0::No_OpClass 42797 14.61% 14.61% # Class of committed instruction
1098system.cpu1.commit.op_class_0::IntAlu 118295 40.38% 54.99% # Class of committed instruction
1099system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.99% # Class of committed instruction
1100system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.99% # Class of committed instruction
1101system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.99% # Class of committed instruction
1102system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.99% # Class of committed instruction
1103system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.99% # Class of committed instruction
1104system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.99% # Class of committed instruction
1105system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.99% # Class of committed instruction
1106system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.99% # Class of committed instruction
1107system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.99% # Class of committed instruction
1108system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.99% # Class of committed instruction
1109system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.99% # Class of committed instruction
1110system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.99% # Class of committed instruction
1111system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.99% # Class of committed instruction
1112system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.99% # Class of committed instruction
1113system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.99% # Class of committed instruction
1114system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.99% # Class of committed instruction
1115system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.99% # Class of committed instruction
1116system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.99% # Class of committed instruction
1117system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.99% # Class of committed instruction
1118system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.99% # Class of committed instruction
1119system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.99% # Class of committed instruction
1120system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.99% # Class of committed instruction
1121system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.99% # Class of committed instruction
1122system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.99% # Class of committed instruction
1123system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.99% # Class of committed instruction
1124system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.99% # Class of committed instruction
1125system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.99% # Class of committed instruction
1126system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.99% # Class of committed instruction
1127system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.99% # Class of committed instruction
1128system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.99% # Class of committed instruction
1129system.cpu1.commit.op_class_0::MemRead 91576 31.26% 86.25% # Class of committed instruction
1130system.cpu1.commit.op_class_0::MemWrite 40267 13.75% 100.00% # Class of committed instruction

1131system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
1132system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
1133system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1134system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1135system.cpu1.commit.op_class_0::total 320342 # Class of committed instruction
1136system.cpu1.commit.bw_lim_events 1178 # number cycles where commit BW limit reached
1137system.cpu1.rob.rob_reads 522978 # The number of ROB reads
1138system.cpu1.rob.rob_writes 693117 # The number of ROB writes
1139system.cpu1.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself
1140system.cpu1.idleCycles 6852 # Total number of cycles that the CPU has spent unscheduled due to idling
1141system.cpu1.quiesceCycles 49387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1142system.cpu1.committedInsts 268615 # Number of Instructions Simulated
1143system.cpu1.committedOps 268615 # Number of Ops (including micro ops) Simulated
1144system.cpu1.cpi 0.714160 # CPI: Cycles Per Instruction
1145system.cpu1.cpi_total 0.714160 # CPI: Total CPI of All Threads
1146system.cpu1.ipc 1.400247 # IPC: Instructions Per Cycle
1147system.cpu1.ipc_total 1.400247 # IPC: Total IPC of All Threads
1148system.cpu1.int_regfile_reads 497951 # number of integer regfile reads
1149system.cpu1.int_regfile_writes 231611 # number of integer regfile writes

1135system.cpu1.commit.op_class_0::total 292935 # Class of committed instruction
1136system.cpu1.commit.bw_lim_events 1210 # number cycles where commit BW limit reached
1137system.cpu1.rob.rob_reads 500353 # The number of ROB reads
1138system.cpu1.rob.rob_writes 646173 # The number of ROB writes
1139system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself
1140system.cpu1.idleCycles 7971 # Total number of cycles that the CPU has spent unscheduled due to idling
1141system.cpu1.quiesceCycles 49399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1142system.cpu1.committedInsts 244359 # Number of Instructions Simulated
1143system.cpu1.committedOps 244359 # Number of Ops (including micro ops) Simulated
1144system.cpu1.cpi 0.797748 # CPI: Cycles Per Instruction
1145system.cpu1.cpi_total 0.797748 # CPI: Total CPI of All Threads
1146system.cpu1.ipc 1.253528 # IPC: Instructions Per Cycle
1147system.cpu1.ipc_total 1.253528 # IPC: Total IPC of All Threads
1148system.cpu1.int_regfile_reads 456218 # number of integer regfile reads
1149system.cpu1.int_regfile_writes 213064 # number of integer regfile writes

1150system.cpu1.fp_regfile_writes 64 # number of floating regfile writes

1151system.cpu1.misc_regfile_reads 146596 # number of misc regfile reads

1151system.cpu1.misc_regfile_reads 132445 # number of misc regfile reads

1152system.cpu1.misc_regfile_writes 648 # number of misc regfile writes

1153system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

1153system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

1154system.cpu1.dcache.tags.replacements 0 # number of replacements

1155system.cpu1.dcache.tags.tagsinuse 26.433606 # Cycle average of tags in use
1156system.cpu1.dcache.tags.total_refs 52423 # Total number of references to valid blocks.
1157system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
1158system.cpu1.dcache.tags.avg_refs 1747.433333 # Average number of references to valid blocks.

1155system.cpu1.dcache.tags.tagsinuse 27.060700 # Cycle average of tags in use
1156system.cpu1.dcache.tags.total_refs 47652 # Total number of references to valid blocks.
1157system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
1158system.cpu1.dcache.tags.avg_refs 1537.161290 # Average number of references to valid blocks.

1159system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1160system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.433606 # Average occupied blocks per requestor
1161system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051628 # Average percentage of cache occupancy
1162system.cpu1.dcache.tags.occ_percent::total 0.051628 # Average percentage of cache occupancy
1163system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
1164system.cpu1.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
1165system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
1166system.cpu1.dcache.tags.tag_accesses 406876 # Number of tag accesses
1167system.cpu1.dcache.tags.data_accesses 406876 # Number of data accesses
1168system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1169system.cpu1.dcache.ReadReq_hits::cpu1.data 55612 # number of ReadReq hits
1170system.cpu1.dcache.ReadReq_hits::total 55612 # number of ReadReq hits
1171system.cpu1.dcache.WriteReq_hits::cpu1.data 45312 # number of WriteReq hits
1172system.cpu1.dcache.WriteReq_hits::total 45312 # number of WriteReq hits
1173system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
1174system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1175system.cpu1.dcache.demand_hits::cpu1.data 100924 # number of demand (read+write) hits
1176system.cpu1.dcache.demand_hits::total 100924 # number of demand (read+write) hits
1177system.cpu1.dcache.overall_hits::cpu1.data 100924 # number of overall hits
1178system.cpu1.dcache.overall_hits::total 100924 # number of overall hits
1179system.cpu1.dcache.ReadReq_misses::cpu1.data 502 # number of ReadReq misses
1180system.cpu1.dcache.ReadReq_misses::total 502 # number of ReadReq misses
1181system.cpu1.dcache.WriteReq_misses::cpu1.data 162 # number of WriteReq misses
1182system.cpu1.dcache.WriteReq_misses::total 162 # number of WriteReq misses
1183system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
1184system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
1185system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses
1186system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses
1187system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses
1188system.cpu1.dcache.overall_misses::total 664 # number of overall misses
1189system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5584500 # number of ReadReq miss cycles
1190system.cpu1.dcache.ReadReq_miss_latency::total 5584500 # number of ReadReq miss cycles
1191system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3659500 # number of WriteReq miss cycles
1192system.cpu1.dcache.WriteReq_miss_latency::total 3659500 # number of WriteReq miss cycles
1193system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 374500 # number of SwapReq miss cycles
1194system.cpu1.dcache.SwapReq_miss_latency::total 374500 # number of SwapReq miss cycles
1195system.cpu1.dcache.demand_miss_latency::cpu1.data 9244000 # number of demand (read+write) miss cycles
1196system.cpu1.dcache.demand_miss_latency::total 9244000 # number of demand (read+write) miss cycles
1197system.cpu1.dcache.overall_miss_latency::cpu1.data 9244000 # number of overall miss cycles
1198system.cpu1.dcache.overall_miss_latency::total 9244000 # number of overall miss cycles
1199system.cpu1.dcache.ReadReq_accesses::cpu1.data 56114 # number of ReadReq accesses(hits+misses)
1200system.cpu1.dcache.ReadReq_accesses::total 56114 # number of ReadReq accesses(hits+misses)
1201system.cpu1.dcache.WriteReq_accesses::cpu1.data 45474 # number of WriteReq accesses(hits+misses)
1202system.cpu1.dcache.WriteReq_accesses::total 45474 # number of WriteReq accesses(hits+misses)
1203system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses)
1204system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
1205system.cpu1.dcache.demand_accesses::cpu1.data 101588 # number of demand (read+write) accesses
1206system.cpu1.dcache.demand_accesses::total 101588 # number of demand (read+write) accesses
1207system.cpu1.dcache.overall_accesses::cpu1.data 101588 # number of overall (read+write) accesses
1208system.cpu1.dcache.overall_accesses::total 101588 # number of overall (read+write) accesses
1209system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008946 # miss rate for ReadReq accesses
1210system.cpu1.dcache.ReadReq_miss_rate::total 0.008946 # miss rate for ReadReq accesses
1211system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003562 # miss rate for WriteReq accesses
1212system.cpu1.dcache.WriteReq_miss_rate::total 0.003562 # miss rate for WriteReq accesses
1213system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.820896 # miss rate for SwapReq accesses
1214system.cpu1.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses
1215system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006536 # miss rate for demand accesses
1216system.cpu1.dcache.demand_miss_rate::total 0.006536 # miss rate for demand accesses
1217system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006536 # miss rate for overall accesses
1218system.cpu1.dcache.overall_miss_rate::total 0.006536 # miss rate for overall accesses
1219system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992 # average ReadReq miss latency
1220system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992 # average ReadReq miss latency
1221system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173 # average WriteReq miss latency
1222system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173 # average WriteReq miss latency
1223system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6809.090909 # average SwapReq miss latency
1224system.cpu1.dcache.SwapReq_avg_miss_latency::total 6809.090909 # average SwapReq miss latency
1225system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency
1226system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747 # average overall miss latency
1227system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency
1228system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747 # average overall miss latency

1160system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.060700 # Average occupied blocks per requestor
1161system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052853 # Average percentage of cache occupancy
1162system.cpu1.dcache.tags.occ_percent::total 0.052853 # Average percentage of cache occupancy
1163system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
1164system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
1165system.cpu1.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
1166system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
1167system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
1168system.cpu1.dcache.tags.tag_accesses 370474 # Number of tag accesses
1169system.cpu1.dcache.tags.data_accesses 370474 # Number of data accesses
1170system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1171system.cpu1.dcache.ReadReq_hits::cpu1.data 51817 # number of ReadReq hits
1172system.cpu1.dcache.ReadReq_hits::total 51817 # number of ReadReq hits
1173system.cpu1.dcache.WriteReq_hits::cpu1.data 40051 # number of WriteReq hits
1174system.cpu1.dcache.WriteReq_hits::total 40051 # number of WriteReq hits
1175system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
1176system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1177system.cpu1.dcache.demand_hits::cpu1.data 91868 # number of demand (read+write) hits
1178system.cpu1.dcache.demand_hits::total 91868 # number of demand (read+write) hits
1179system.cpu1.dcache.overall_hits::cpu1.data 91868 # number of overall hits
1180system.cpu1.dcache.overall_hits::total 91868 # number of overall hits
1181system.cpu1.dcache.ReadReq_misses::cpu1.data 471 # number of ReadReq misses
1182system.cpu1.dcache.ReadReq_misses::total 471 # number of ReadReq misses
1183system.cpu1.dcache.WriteReq_misses::cpu1.data 148 # number of WriteReq misses
1184system.cpu1.dcache.WriteReq_misses::total 148 # number of WriteReq misses
1185system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses
1186system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses
1187system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses
1188system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses
1189system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses
1190system.cpu1.dcache.overall_misses::total 619 # number of overall misses
1191system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4841500 # number of ReadReq miss cycles
1192system.cpu1.dcache.ReadReq_miss_latency::total 4841500 # number of ReadReq miss cycles
1193system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3638000 # number of WriteReq miss cycles
1194system.cpu1.dcache.WriteReq_miss_latency::total 3638000 # number of WriteReq miss cycles
1195system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 309000 # number of SwapReq miss cycles
1196system.cpu1.dcache.SwapReq_miss_latency::total 309000 # number of SwapReq miss cycles
1197system.cpu1.dcache.demand_miss_latency::cpu1.data 8479500 # number of demand (read+write) miss cycles
1198system.cpu1.dcache.demand_miss_latency::total 8479500 # number of demand (read+write) miss cycles
1199system.cpu1.dcache.overall_miss_latency::cpu1.data 8479500 # number of overall miss cycles
1200system.cpu1.dcache.overall_miss_latency::total 8479500 # number of overall miss cycles
1201system.cpu1.dcache.ReadReq_accesses::cpu1.data 52288 # number of ReadReq accesses(hits+misses)
1202system.cpu1.dcache.ReadReq_accesses::total 52288 # number of ReadReq accesses(hits+misses)
1203system.cpu1.dcache.WriteReq_accesses::cpu1.data 40199 # number of WriteReq accesses(hits+misses)
1204system.cpu1.dcache.WriteReq_accesses::total 40199 # number of WriteReq accesses(hits+misses)
1205system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses)
1206system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
1207system.cpu1.dcache.demand_accesses::cpu1.data 92487 # number of demand (read+write) accesses
1208system.cpu1.dcache.demand_accesses::total 92487 # number of demand (read+write) accesses
1209system.cpu1.dcache.overall_accesses::cpu1.data 92487 # number of overall (read+write) accesses
1210system.cpu1.dcache.overall_accesses::total 92487 # number of overall (read+write) accesses
1211system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009008 # miss rate for ReadReq accesses
1212system.cpu1.dcache.ReadReq_miss_rate::total 0.009008 # miss rate for ReadReq accesses
1213system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003682 # miss rate for WriteReq accesses
1214system.cpu1.dcache.WriteReq_miss_rate::total 0.003682 # miss rate for WriteReq accesses
1215system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.794118 # miss rate for SwapReq accesses
1216system.cpu1.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
1217system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006693 # miss rate for demand accesses
1218system.cpu1.dcache.demand_miss_rate::total 0.006693 # miss rate for demand accesses
1219system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006693 # miss rate for overall accesses
1220system.cpu1.dcache.overall_miss_rate::total 0.006693 # miss rate for overall accesses
1221system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10279.193206 # average ReadReq miss latency
1222system.cpu1.dcache.ReadReq_avg_miss_latency::total 10279.193206 # average ReadReq miss latency
1223system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24581.081081 # average WriteReq miss latency
1224system.cpu1.dcache.WriteReq_avg_miss_latency::total 24581.081081 # average WriteReq miss latency
1225system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5722.222222 # average SwapReq miss latency
1226system.cpu1.dcache.SwapReq_avg_miss_latency::total 5722.222222 # average SwapReq miss latency
1227system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency
1228system.cpu1.dcache.demand_avg_miss_latency::total 13698.707593 # average overall miss latency
1229system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency
1230system.cpu1.dcache.overall_avg_miss_latency::total 13698.707593 # average overall miss latency

1229system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1230system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1231system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1232system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1233system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1234system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1231system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1232system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1233system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1234system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1235system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1236system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1235system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 340 # number of ReadReq MSHR hits
1236system.cpu1.dcache.ReadReq_mshr_hits::total 340 # number of ReadReq MSHR hits
1237system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 55 # number of WriteReq MSHR hits
1238system.cpu1.dcache.WriteReq_mshr_hits::total 55 # number of WriteReq MSHR hits
1239system.cpu1.dcache.demand_mshr_hits::cpu1.data 395 # number of demand (read+write) MSHR hits
1240system.cpu1.dcache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits
1241system.cpu1.dcache.overall_mshr_hits::cpu1.data 395 # number of overall MSHR hits
1242system.cpu1.dcache.overall_mshr_hits::total 395 # number of overall MSHR hits
1243system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses
1244system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
1245system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
1246system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
1247system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
1248system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
1249system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses
1250system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
1251system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses
1252system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
1253system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2129000 # number of ReadReq MSHR miss cycles
1254system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2129000 # number of ReadReq MSHR miss cycles
1255system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1532000 # number of WriteReq MSHR miss cycles
1256system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1532000 # number of WriteReq MSHR miss cycles
1257system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 319500 # number of SwapReq MSHR miss cycles
1258system.cpu1.dcache.SwapReq_mshr_miss_latency::total 319500 # number of SwapReq MSHR miss cycles
1259system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3661000 # number of demand (read+write) MSHR miss cycles
1260system.cpu1.dcache.demand_mshr_miss_latency::total 3661000 # number of demand (read+write) MSHR miss cycles
1261system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3661000 # number of overall MSHR miss cycles
1262system.cpu1.dcache.overall_mshr_miss_latency::total 3661000 # number of overall MSHR miss cycles
1263system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for ReadReq accesses
1264system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002887 # mshr miss rate for ReadReq accesses
1265system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002353 # mshr miss rate for WriteReq accesses
1266system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002353 # mshr miss rate for WriteReq accesses
1267system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.820896 # mshr miss rate for SwapReq accesses
1268system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses
1269system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for demand accesses
1270system.cpu1.dcache.demand_mshr_miss_rate::total 0.002648 # mshr miss rate for demand accesses
1271system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for overall accesses
1272system.cpu1.dcache.overall_mshr_miss_rate::total 0.002648 # mshr miss rate for overall accesses
1273system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13141.975309 # average ReadReq mshr miss latency
1274system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13141.975309 # average ReadReq mshr miss latency
1275system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14317.757009 # average WriteReq mshr miss latency
1276system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14317.757009 # average WriteReq mshr miss latency
1277system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5809.090909 # average SwapReq mshr miss latency
1278system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5809.090909 # average SwapReq mshr miss latency
1279system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency
1280system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency
1281system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency
1282system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency
1283system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1284system.cpu1.icache.tags.replacements 556 # number of replacements
1285system.cpu1.icache.tags.tagsinuse 97.753950 # Cycle average of tags in use
1286system.cpu1.icache.tags.total_refs 22636 # Total number of references to valid blocks.
1287system.cpu1.icache.tags.sampled_refs 690 # Sample count of references to valid blocks.
1288system.cpu1.icache.tags.avg_refs 32.805797 # Average number of references to valid blocks.

1237system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 312 # number of ReadReq MSHR hits
1238system.cpu1.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits
1239system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 44 # number of WriteReq MSHR hits
1240system.cpu1.dcache.WriteReq_mshr_hits::total 44 # number of WriteReq MSHR hits
1241system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 1 # number of SwapReq MSHR hits
1242system.cpu1.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits
1243system.cpu1.dcache.demand_mshr_hits::cpu1.data 356 # number of demand (read+write) MSHR hits
1244system.cpu1.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits
1245system.cpu1.dcache.overall_mshr_hits::cpu1.data 356 # number of overall MSHR hits
1246system.cpu1.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits
1247system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses
1248system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
1249system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses
1250system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
1251system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses
1252system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
1253system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
1254system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
1255system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
1256system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
1257system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1599000 # number of ReadReq MSHR miss cycles
1258system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1599000 # number of ReadReq MSHR miss cycles
1259system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1536000 # number of WriteReq MSHR miss cycles
1260system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1536000 # number of WriteReq MSHR miss cycles
1261system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 255000 # number of SwapReq MSHR miss cycles
1262system.cpu1.dcache.SwapReq_mshr_miss_latency::total 255000 # number of SwapReq MSHR miss cycles
1263system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3135000 # number of demand (read+write) MSHR miss cycles
1264system.cpu1.dcache.demand_mshr_miss_latency::total 3135000 # number of demand (read+write) MSHR miss cycles
1265system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3135000 # number of overall MSHR miss cycles
1266system.cpu1.dcache.overall_mshr_miss_latency::total 3135000 # number of overall MSHR miss cycles
1267system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003041 # mshr miss rate for ReadReq accesses
1268system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003041 # mshr miss rate for ReadReq accesses
1269system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002587 # mshr miss rate for WriteReq accesses
1270system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002587 # mshr miss rate for WriteReq accesses
1271system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.779412 # mshr miss rate for SwapReq accesses
1272system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses
1273system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for demand accesses
1274system.cpu1.dcache.demand_mshr_miss_rate::total 0.002844 # mshr miss rate for demand accesses
1275system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for overall accesses
1276system.cpu1.dcache.overall_mshr_miss_rate::total 0.002844 # mshr miss rate for overall accesses
1277system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10056.603774 # average ReadReq mshr miss latency
1278system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10056.603774 # average ReadReq mshr miss latency
1279system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14769.230769 # average WriteReq mshr miss latency
1280system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14769.230769 # average WriteReq mshr miss latency
1281system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 4811.320755 # average SwapReq mshr miss latency
1282system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 4811.320755 # average SwapReq mshr miss latency
1283system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency
1284system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency
1285system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency
1286system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency
1287system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1288system.cpu1.icache.tags.replacements 598 # number of replacements
1289system.cpu1.icache.tags.tagsinuse 99.304712 # Cycle average of tags in use
1290system.cpu1.icache.tags.total_refs 25606 # Total number of references to valid blocks.
1291system.cpu1.icache.tags.sampled_refs 733 # Sample count of references to valid blocks.
1292system.cpu1.icache.tags.avg_refs 34.933151 # Average number of references to valid blocks.

1289system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1293system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1290system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.753950 # Average occupied blocks per requestor
1291system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190926 # Average percentage of cache occupancy
1292system.cpu1.icache.tags.occ_percent::total 0.190926 # Average percentage of cache occupancy
1293system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
1294system.cpu1.icache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
1295system.cpu1.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
1296system.cpu1.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
1297system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id
1298system.cpu1.icache.tags.tag_accesses 24159 # Number of tag accesses
1299system.cpu1.icache.tags.data_accesses 24159 # Number of data accesses
1300system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1301system.cpu1.icache.ReadReq_hits::cpu1.inst 22636 # number of ReadReq hits
1302system.cpu1.icache.ReadReq_hits::total 22636 # number of ReadReq hits
1303system.cpu1.icache.demand_hits::cpu1.inst 22636 # number of demand (read+write) hits
1304system.cpu1.icache.demand_hits::total 22636 # number of demand (read+write) hits
1305system.cpu1.icache.overall_hits::cpu1.inst 22636 # number of overall hits
1306system.cpu1.icache.overall_hits::total 22636 # number of overall hits
1307system.cpu1.icache.ReadReq_misses::cpu1.inst 833 # number of ReadReq misses
1308system.cpu1.icache.ReadReq_misses::total 833 # number of ReadReq misses
1309system.cpu1.icache.demand_misses::cpu1.inst 833 # number of demand (read+write) misses
1310system.cpu1.icache.demand_misses::total 833 # number of demand (read+write) misses
1311system.cpu1.icache.overall_misses::cpu1.inst 833 # number of overall misses
1312system.cpu1.icache.overall_misses::total 833 # number of overall misses
1313system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 20006500 # number of ReadReq miss cycles
1314system.cpu1.icache.ReadReq_miss_latency::total 20006500 # number of ReadReq miss cycles
1315system.cpu1.icache.demand_miss_latency::cpu1.inst 20006500 # number of demand (read+write) miss cycles
1316system.cpu1.icache.demand_miss_latency::total 20006500 # number of demand (read+write) miss cycles
1317system.cpu1.icache.overall_miss_latency::cpu1.inst 20006500 # number of overall miss cycles
1318system.cpu1.icache.overall_miss_latency::total 20006500 # number of overall miss cycles
1319system.cpu1.icache.ReadReq_accesses::cpu1.inst 23469 # number of ReadReq accesses(hits+misses)
1320system.cpu1.icache.ReadReq_accesses::total 23469 # number of ReadReq accesses(hits+misses)
1321system.cpu1.icache.demand_accesses::cpu1.inst 23469 # number of demand (read+write) accesses
1322system.cpu1.icache.demand_accesses::total 23469 # number of demand (read+write) accesses
1323system.cpu1.icache.overall_accesses::cpu1.inst 23469 # number of overall (read+write) accesses
1324system.cpu1.icache.overall_accesses::total 23469 # number of overall (read+write) accesses
1325system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.035494 # miss rate for ReadReq accesses
1326system.cpu1.icache.ReadReq_miss_rate::total 0.035494 # miss rate for ReadReq accesses
1327system.cpu1.icache.demand_miss_rate::cpu1.inst 0.035494 # miss rate for demand accesses
1328system.cpu1.icache.demand_miss_rate::total 0.035494 # miss rate for demand accesses
1329system.cpu1.icache.overall_miss_rate::cpu1.inst 0.035494 # miss rate for overall accesses
1330system.cpu1.icache.overall_miss_rate::total 0.035494 # miss rate for overall accesses
1331system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963 # average ReadReq miss latency
1332system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963 # average ReadReq miss latency
1333system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency
1334system.cpu1.icache.demand_avg_miss_latency::total 24017.406963 # average overall miss latency
1335system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency
1336system.cpu1.icache.overall_avg_miss_latency::total 24017.406963 # average overall miss latency
1337system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked

1294system.cpu1.icache.tags.occ_blocks::cpu1.inst 99.304712 # Average occupied blocks per requestor
1295system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193955 # Average percentage of cache occupancy
1296system.cpu1.icache.tags.occ_percent::total 0.193955 # Average percentage of cache occupancy
1297system.cpu1.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
1298system.cpu1.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
1299system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
1300system.cpu1.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
1301system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id
1302system.cpu1.icache.tags.tag_accesses 27223 # Number of tag accesses
1303system.cpu1.icache.tags.data_accesses 27223 # Number of data accesses
1304system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1305system.cpu1.icache.ReadReq_hits::cpu1.inst 25606 # number of ReadReq hits
1306system.cpu1.icache.ReadReq_hits::total 25606 # number of ReadReq hits
1307system.cpu1.icache.demand_hits::cpu1.inst 25606 # number of demand (read+write) hits
1308system.cpu1.icache.demand_hits::total 25606 # number of demand (read+write) hits
1309system.cpu1.icache.overall_hits::cpu1.inst 25606 # number of overall hits
1310system.cpu1.icache.overall_hits::total 25606 # number of overall hits
1311system.cpu1.icache.ReadReq_misses::cpu1.inst 884 # number of ReadReq misses
1312system.cpu1.icache.ReadReq_misses::total 884 # number of ReadReq misses
1313system.cpu1.icache.demand_misses::cpu1.inst 884 # number of demand (read+write) misses
1314system.cpu1.icache.demand_misses::total 884 # number of demand (read+write) misses
1315system.cpu1.icache.overall_misses::cpu1.inst 884 # number of overall misses
1316system.cpu1.icache.overall_misses::total 884 # number of overall misses
1317system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 21315000 # number of ReadReq miss cycles
1318system.cpu1.icache.ReadReq_miss_latency::total 21315000 # number of ReadReq miss cycles
1319system.cpu1.icache.demand_miss_latency::cpu1.inst 21315000 # number of demand (read+write) miss cycles
1320system.cpu1.icache.demand_miss_latency::total 21315000 # number of demand (read+write) miss cycles
1321system.cpu1.icache.overall_miss_latency::cpu1.inst 21315000 # number of overall miss cycles
1322system.cpu1.icache.overall_miss_latency::total 21315000 # number of overall miss cycles
1323system.cpu1.icache.ReadReq_accesses::cpu1.inst 26490 # number of ReadReq accesses(hits+misses)
1324system.cpu1.icache.ReadReq_accesses::total 26490 # number of ReadReq accesses(hits+misses)
1325system.cpu1.icache.demand_accesses::cpu1.inst 26490 # number of demand (read+write) accesses
1326system.cpu1.icache.demand_accesses::total 26490 # number of demand (read+write) accesses
1327system.cpu1.icache.overall_accesses::cpu1.inst 26490 # number of overall (read+write) accesses
1328system.cpu1.icache.overall_accesses::total 26490 # number of overall (read+write) accesses
1329system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033371 # miss rate for ReadReq accesses
1330system.cpu1.icache.ReadReq_miss_rate::total 0.033371 # miss rate for ReadReq accesses
1331system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033371 # miss rate for demand accesses
1332system.cpu1.icache.demand_miss_rate::total 0.033371 # miss rate for demand accesses
1333system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033371 # miss rate for overall accesses
1334system.cpu1.icache.overall_miss_rate::total 0.033371 # miss rate for overall accesses
1335system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24111.990950 # average ReadReq miss latency
1336system.cpu1.icache.ReadReq_avg_miss_latency::total 24111.990950 # average ReadReq miss latency
1337system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency
1338system.cpu1.icache.demand_avg_miss_latency::total 24111.990950 # average overall miss latency
1339system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency
1340system.cpu1.icache.overall_avg_miss_latency::total 24111.990950 # average overall miss latency
1341system.cpu1.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked

1338system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1342system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1339system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked

1343system.cpu1.icache.blocked::no_mshrs 5 # number of cycles access was blocked

1340system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked

1344system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked

1341system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked

1345system.cpu1.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked

1342system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1346system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1343system.cpu1.icache.writebacks::writebacks 556 # number of writebacks
1344system.cpu1.icache.writebacks::total 556 # number of writebacks
1345system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 143 # number of ReadReq MSHR hits
1346system.cpu1.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits
1347system.cpu1.icache.demand_mshr_hits::cpu1.inst 143 # number of demand (read+write) MSHR hits
1348system.cpu1.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits
1349system.cpu1.icache.overall_mshr_hits::cpu1.inst 143 # number of overall MSHR hits
1350system.cpu1.icache.overall_mshr_hits::total 143 # number of overall MSHR hits
1351system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 690 # number of ReadReq MSHR misses
1352system.cpu1.icache.ReadReq_mshr_misses::total 690 # number of ReadReq MSHR misses
1353system.cpu1.icache.demand_mshr_misses::cpu1.inst 690 # number of demand (read+write) MSHR misses
1354system.cpu1.icache.demand_mshr_misses::total 690 # number of demand (read+write) MSHR misses
1355system.cpu1.icache.overall_mshr_misses::cpu1.inst 690 # number of overall MSHR misses
1356system.cpu1.icache.overall_mshr_misses::total 690 # number of overall MSHR misses
1357system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15540500 # number of ReadReq MSHR miss cycles
1358system.cpu1.icache.ReadReq_mshr_miss_latency::total 15540500 # number of ReadReq MSHR miss cycles
1359system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15540500 # number of demand (read+write) MSHR miss cycles
1360system.cpu1.icache.demand_mshr_miss_latency::total 15540500 # number of demand (read+write) MSHR miss cycles
1361system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15540500 # number of overall MSHR miss cycles
1362system.cpu1.icache.overall_mshr_miss_latency::total 15540500 # number of overall MSHR miss cycles
1363system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for ReadReq accesses
1364system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029400 # mshr miss rate for ReadReq accesses
1365system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for demand accesses
1366system.cpu1.icache.demand_mshr_miss_rate::total 0.029400 # mshr miss rate for demand accesses
1367system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for overall accesses
1368system.cpu1.icache.overall_mshr_miss_rate::total 0.029400 # mshr miss rate for overall accesses
1369system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average ReadReq mshr miss latency
1370system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768 # average ReadReq mshr miss latency
1371system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency
1372system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency
1373system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency
1374system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency
1375system.cpu2.branchPred.lookups 60250 # Number of BP lookups
1376system.cpu2.branchPred.condPredicted 52369 # Number of conditional branches predicted
1377system.cpu2.branchPred.condIncorrect 2399 # Number of conditional branches incorrect
1378system.cpu2.branchPred.BTBLookups 52178 # Number of BTB lookups

1347system.cpu1.icache.writebacks::writebacks 598 # number of writebacks
1348system.cpu1.icache.writebacks::total 598 # number of writebacks
1349system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 151 # number of ReadReq MSHR hits
1350system.cpu1.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits
1351system.cpu1.icache.demand_mshr_hits::cpu1.inst 151 # number of demand (read+write) MSHR hits
1352system.cpu1.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits
1353system.cpu1.icache.overall_mshr_hits::cpu1.inst 151 # number of overall MSHR hits
1354system.cpu1.icache.overall_mshr_hits::total 151 # number of overall MSHR hits
1355system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 733 # number of ReadReq MSHR misses
1356system.cpu1.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
1357system.cpu1.icache.demand_mshr_misses::cpu1.inst 733 # number of demand (read+write) MSHR misses
1358system.cpu1.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
1359system.cpu1.icache.overall_mshr_misses::cpu1.inst 733 # number of overall MSHR misses
1360system.cpu1.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
1361system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16848000 # number of ReadReq MSHR miss cycles
1362system.cpu1.icache.ReadReq_mshr_miss_latency::total 16848000 # number of ReadReq MSHR miss cycles
1363system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16848000 # number of demand (read+write) MSHR miss cycles
1364system.cpu1.icache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles
1365system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16848000 # number of overall MSHR miss cycles
1366system.cpu1.icache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles
1367system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for ReadReq accesses
1368system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027671 # mshr miss rate for ReadReq accesses
1369system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for demand accesses
1370system.cpu1.icache.demand_mshr_miss_rate::total 0.027671 # mshr miss rate for demand accesses
1371system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for overall accesses
1372system.cpu1.icache.overall_mshr_miss_rate::total 0.027671 # mshr miss rate for overall accesses
1373system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average ReadReq mshr miss latency
1374system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22984.993179 # average ReadReq mshr miss latency
1375system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency
1376system.cpu1.icache.demand_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency
1377system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency
1378system.cpu1.icache.overall_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency
1379system.cpu2.branchPred.lookups 65968 # Number of BP lookups
1380system.cpu2.branchPred.condPredicted 58235 # Number of conditional branches predicted
1381system.cpu2.branchPred.condIncorrect 2375 # Number of conditional branches incorrect
1382system.cpu2.branchPred.BTBLookups 57871 # Number of BTB lookups

1379system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
1380system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1381system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1383system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
1384system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1385system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1382system.cpu2.branchPred.usedRAS 1981 # Number of times the RAS was used to get a target.

1386system.cpu2.branchPred.usedRAS 1935 # Number of times the RAS was used to get a target.

1383system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1387system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1384system.cpu2.branchPred.indirectLookups 52178 # Number of indirect predictor lookups.
1385system.cpu2.branchPred.indirectHits 41452 # Number of indirect target hits.
1386system.cpu2.branchPred.indirectMisses 10726 # Number of indirect misses.
1387system.cpu2.branchPredindirectMispredicted 1295 # Number of mispredicted indirect branches.
1388system.cpu2.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states
1389system.cpu2.numCycles 191431 # number of cpu cycles simulated

1388system.cpu2.branchPred.indirectLookups 57871 # Number of indirect predictor lookups.
1389system.cpu2.branchPred.indirectHits 47609 # Number of indirect target hits.
1390system.cpu2.branchPred.indirectMisses 10262 # Number of indirect misses.
1391system.cpu2.branchPredindirectMispredicted 1269 # Number of mispredicted indirect branches.
1392system.cpu2.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states
1393system.cpu2.numCycles 194536 # number of cpu cycles simulated

1390system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1391system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed

1394system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1395system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed

1392system.cpu2.fetch.icacheStallCycles 42696 # Number of cycles fetch is stalled on an Icache miss
1393system.cpu2.fetch.Insts 319764 # Number of instructions fetch has processed
1394system.cpu2.fetch.Branches 60250 # Number of branches that fetch encountered
1395system.cpu2.fetch.predictedBranches 43433 # Number of branches that fetch has predicted taken
1396system.cpu2.fetch.Cycles 142400 # Number of cycles fetch has run and was not squashing or blocked
1397system.cpu2.fetch.SquashCycles 4955 # Number of cycles fetch has spent squashing

1396system.cpu2.fetch.icacheStallCycles 39274 # Number of cycles fetch is stalled on an Icache miss
1397system.cpu2.fetch.Insts 356927 # Number of instructions fetch has processed
1398system.cpu2.fetch.Branches 65968 # Number of branches that fetch encountered
1399system.cpu2.fetch.predictedBranches 49544 # Number of branches that fetch has predicted taken
1400system.cpu2.fetch.Cycles 148178 # Number of cycles fetch has run and was not squashing or blocked
1401system.cpu2.fetch.SquashCycles 4907 # Number of cycles fetch has spent squashing

1398system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1399system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1402system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1403system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1400system.cpu2.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps
1401system.cpu2.fetch.CacheLines 31580 # Number of cache lines fetched
1402system.cpu2.fetch.IcacheSquashes 988 # Number of outstanding Icache misses that were squashed
1403system.cpu2.fetch.rateDist::samples 189804 # Number of instructions fetched each cycle (Total)
1404system.cpu2.fetch.rateDist::mean 1.684706 # Number of instructions fetched each cycle (Total)
1405system.cpu2.fetch.rateDist::stdev 2.290533 # Number of instructions fetched each cycle (Total)

1404system.cpu2.fetch.PendingTrapStallCycles 1834 # Number of stall cycles due to pending traps
1405system.cpu2.fetch.CacheLines 28474 # Number of cache lines fetched
1406system.cpu2.fetch.IcacheSquashes 909 # Number of outstanding Icache misses that were squashed
1407system.cpu2.fetch.rateDist::samples 191752 # Number of instructions fetched each cycle (Total)
1408system.cpu2.fetch.rateDist::mean 1.861399 # Number of instructions fetched each cycle (Total)
1409system.cpu2.fetch.rateDist::stdev 2.326800 # Number of instructions fetched each cycle (Total)

1406system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1410system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1407system.cpu2.fetch.rateDist::0 80855 42.60% 42.60% # Number of instructions fetched each cycle (Total)
1408system.cpu2.fetch.rateDist::1 54436 28.68% 71.28% # Number of instructions fetched each cycle (Total)
1409system.cpu2.fetch.rateDist::2 9994 5.27% 76.54% # Number of instructions fetched each cycle (Total)
1410system.cpu2.fetch.rateDist::3 3383 1.78% 78.33% # Number of instructions fetched each cycle (Total)
1411system.cpu2.fetch.rateDist::4 680 0.36% 78.69% # Number of instructions fetched each cycle (Total)
1412system.cpu2.fetch.rateDist::5 29156 15.36% 94.05% # Number of instructions fetched each cycle (Total)
1413system.cpu2.fetch.rateDist::6 1157 0.61% 94.66% # Number of instructions fetched each cycle (Total)
1414system.cpu2.fetch.rateDist::7 1395 0.73% 95.39% # Number of instructions fetched each cycle (Total)
1415system.cpu2.fetch.rateDist::8 8748 4.61% 100.00% # Number of instructions fetched each cycle (Total)

1411system.cpu2.fetch.rateDist::0 72282 37.70% 37.70% # Number of instructions fetched each cycle (Total)
1412system.cpu2.fetch.rateDist::1 59093 30.82% 68.51% # Number of instructions fetched each cycle (Total)
1413system.cpu2.fetch.rateDist::2 8567 4.47% 72.98% # Number of instructions fetched each cycle (Total)
1414system.cpu2.fetch.rateDist::3 3453 1.80% 74.78% # Number of instructions fetched each cycle (Total)
1415system.cpu2.fetch.rateDist::4 714 0.37% 75.15% # Number of instructions fetched each cycle (Total)
1416system.cpu2.fetch.rateDist::5 36701 19.14% 94.29% # Number of instructions fetched each cycle (Total)
1417system.cpu2.fetch.rateDist::6 1094 0.57% 94.86% # Number of instructions fetched each cycle (Total)
1418system.cpu2.fetch.rateDist::7 1368 0.71% 95.58% # Number of instructions fetched each cycle (Total)
1419system.cpu2.fetch.rateDist::8 8480 4.42% 100.00% # Number of instructions fetched each cycle (Total)

1416system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1417system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1418system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1420system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1421system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1422system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1419system.cpu2.fetch.rateDist::total 189804 # Number of instructions fetched each cycle (Total)
1420system.cpu2.fetch.branchRate 0.314735 # Number of branch fetches per cycle
1421system.cpu2.fetch.rate 1.670388 # Number of inst fetches per cycle
1422system.cpu2.decode.IdleCycles 22561 # Number of cycles decode is idle
1423system.cpu2.decode.BlockedCycles 83775 # Number of cycles decode is blocked
1424system.cpu2.decode.RunCycles 75624 # Number of cycles decode is running
1425system.cpu2.decode.UnblockCycles 5357 # Number of cycles decode is unblocking
1426system.cpu2.decode.SquashCycles 2477 # Number of cycles decode is squashing
1427system.cpu2.decode.DecodedInsts 288545 # Number of instructions handled by decode
1428system.cpu2.rename.SquashCycles 2477 # Number of cycles rename is squashing
1429system.cpu2.rename.IdleCycles 23562 # Number of cycles rename is idle
1430system.cpu2.rename.BlockCycles 41928 # Number of cycles rename is blocking
1431system.cpu2.rename.serializeStallCycles 13956 # count of cycles rename stalled for serializing inst
1432system.cpu2.rename.RunCycles 76490 # Number of cycles rename is running
1433system.cpu2.rename.UnblockCycles 31381 # Number of cycles rename is unblocking
1434system.cpu2.rename.RenamedInsts 281938 # Number of instructions processed by rename
1435system.cpu2.rename.IQFullEvents 27181 # Number of times rename has blocked due to IQ full
1436system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full

1423system.cpu2.fetch.rateDist::total 191752 # Number of instructions fetched each cycle (Total)
1424system.cpu2.fetch.branchRate 0.339104 # Number of branch fetches per cycle
1425system.cpu2.fetch.rate 1.834761 # Number of inst fetches per cycle
1426system.cpu2.decode.IdleCycles 22274 # Number of cycles decode is idle
1427system.cpu2.decode.BlockedCycles 72146 # Number of cycles decode is blocked
1428system.cpu2.decode.RunCycles 90170 # Number of cycles decode is running
1429system.cpu2.decode.UnblockCycles 4699 # Number of cycles decode is unblocking
1430system.cpu2.decode.SquashCycles 2453 # Number of cycles decode is squashing
1431system.cpu2.decode.DecodedInsts 325978 # Number of instructions handled by decode
1432system.cpu2.rename.SquashCycles 2453 # Number of cycles rename is squashing
1433system.cpu2.rename.IdleCycles 23346 # Number of cycles rename is idle
1434system.cpu2.rename.BlockCycles 35274 # Number of cycles rename is blocking
1435system.cpu2.rename.serializeStallCycles 13410 # count of cycles rename stalled for serializing inst
1436system.cpu2.rename.RunCycles 90655 # Number of cycles rename is running
1437system.cpu2.rename.UnblockCycles 26604 # Number of cycles rename is unblocking
1438system.cpu2.rename.RenamedInsts 319217 # Number of instructions processed by rename
1439system.cpu2.rename.IQFullEvents 22687 # Number of times rename has blocked due to IQ full
1440system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full

1437system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers

1441system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers

1438system.cpu2.rename.RenamedOperands 195781 # Number of destination operands rename has renamed
1439system.cpu2.rename.RenameLookups 524561 # Number of register rename lookups that rename has made
1440system.cpu2.rename.int_rename_lookups 411315 # Number of integer rename lookups
1441system.cpu2.rename.fp_rename_lookups 32 # Number of floating rename lookups
1442system.cpu2.rename.CommittedMaps 166026 # Number of HB maps that are committed
1443system.cpu2.rename.UndoneMaps 29755 # Number of HB maps that are undone due to squashing
1444system.cpu2.rename.serializingInsts 1653 # count of serializing insts renamed
1445system.cpu2.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed
1446system.cpu2.rename.skidInsts 36818 # count of insts added to the skid buffer
1447system.cpu2.memDep0.insertedLoads 74139 # Number of loads inserted to the mem dependence unit.
1448system.cpu2.memDep0.insertedStores 33614 # Number of stores inserted to the mem dependence unit.
1449system.cpu2.memDep0.conflictingLoads 35848 # Number of conflicting loads.
1450system.cpu2.memDep0.conflictingStores 27180 # Number of conflicting stores.
1451system.cpu2.iq.iqInstsAdded 226553 # Number of instructions added to the IQ (excludes non-spec)
1452system.cpu2.iq.iqNonSpecInstsAdded 10243 # Number of non-speculative instructions added to the IQ
1453system.cpu2.iq.iqInstsIssued 228568 # Number of instructions issued
1454system.cpu2.iq.iqSquashedInstsIssued 140 # Number of squashed instructions issued
1455system.cpu2.iq.iqSquashedInstsExamined 25915 # Number of squashed instructions iterated over during squash; mainly for profiling
1456system.cpu2.iq.iqSquashedOperandsExamined 20426 # Number of squashed operands that are examined and possibly removed from graph
1457system.cpu2.iq.iqSquashedNonSpecRemoved 1250 # Number of squashed non-spec instructions that were removed
1458system.cpu2.iq.issued_per_cycle::samples 189804 # Number of insts issued each cycle
1459system.cpu2.iq.issued_per_cycle::mean 1.204232 # Number of insts issued each cycle
1460system.cpu2.iq.issued_per_cycle::stdev 1.376602 # Number of insts issued each cycle

1442system.cpu2.rename.RenamedOperands 222060 # Number of destination operands rename has renamed
1443system.cpu2.rename.RenameLookups 604225 # Number of register rename lookups that rename has made
1444system.cpu2.rename.int_rename_lookups 470469 # Number of integer rename lookups
1445system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups
1446system.cpu2.rename.CommittedMaps 194795 # Number of HB maps that are committed
1447system.cpu2.rename.UndoneMaps 27265 # Number of HB maps that are undone due to squashing
1448system.cpu2.rename.serializingInsts 1650 # count of serializing insts renamed
1449system.cpu2.rename.tempSerializingInsts 1793 # count of temporary serializing insts renamed
1450system.cpu2.rename.skidInsts 32366 # count of insts added to the skid buffer
1451system.cpu2.memDep0.insertedLoads 87706 # Number of loads inserted to the mem dependence unit.
1452system.cpu2.memDep0.insertedStores 41007 # Number of stores inserted to the mem dependence unit.
1453system.cpu2.memDep0.conflictingLoads 42125 # Number of conflicting loads.
1454system.cpu2.memDep0.conflictingStores 34727 # Number of conflicting stores.
1455system.cpu2.iq.iqInstsAdded 259651 # Number of instructions added to the IQ (excludes non-spec)
1456system.cpu2.iq.iqNonSpecInstsAdded 8925 # Number of non-speculative instructions added to the IQ
1457system.cpu2.iq.iqInstsIssued 260809 # Number of instructions issued
1458system.cpu2.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued
1459system.cpu2.iq.iqSquashedInstsExamined 24016 # Number of squashed instructions iterated over during squash; mainly for profiling
1460system.cpu2.iq.iqSquashedOperandsExamined 18768 # Number of squashed operands that are examined and possibly removed from graph
1461system.cpu2.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed
1462system.cpu2.iq.issued_per_cycle::samples 191752 # Number of insts issued each cycle
1463system.cpu2.iq.issued_per_cycle::mean 1.360137 # Number of insts issued each cycle
1464system.cpu2.iq.issued_per_cycle::stdev 1.380681 # Number of insts issued each cycle

1461system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1465system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1462system.cpu2.iq.issued_per_cycle::0 85980 45.30% 45.30% # Number of insts issued each cycle
1463system.cpu2.iq.issued_per_cycle::1 32313 17.02% 62.32% # Number of insts issued each cycle
1464system.cpu2.iq.issued_per_cycle::2 32235 16.98% 79.31% # Number of insts issued each cycle
1465system.cpu2.iq.issued_per_cycle::3 31990 16.85% 96.16% # Number of insts issued each cycle
1466system.cpu2.iq.issued_per_cycle::4 3688 1.94% 98.10% # Number of insts issued each cycle
1467system.cpu2.iq.issued_per_cycle::5 1698 0.89% 99.00% # Number of insts issued each cycle
1468system.cpu2.iq.issued_per_cycle::6 1058 0.56% 99.56% # Number of insts issued each cycle
1469system.cpu2.iq.issued_per_cycle::7 511 0.27% 99.83% # Number of insts issued each cycle
1470system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00% # Number of insts issued each cycle

1466system.cpu2.iq.issued_per_cycle::0 77057 40.19% 40.19% # Number of insts issued each cycle
1467system.cpu2.iq.issued_per_cycle::1 28387 14.80% 54.99% # Number of insts issued each cycle
1468system.cpu2.iq.issued_per_cycle::2 39839 20.78% 75.77% # Number of insts issued each cycle
1469system.cpu2.iq.issued_per_cycle::3 39454 20.58% 96.34% # Number of insts issued each cycle
1470system.cpu2.iq.issued_per_cycle::4 3531 1.84% 98.18% # Number of insts issued each cycle
1471system.cpu2.iq.issued_per_cycle::5 1665 0.87% 99.05% # Number of insts issued each cycle
1472system.cpu2.iq.issued_per_cycle::6 1093 0.57% 99.62% # Number of insts issued each cycle
1473system.cpu2.iq.issued_per_cycle::7 433 0.23% 99.85% # Number of insts issued each cycle
1474system.cpu2.iq.issued_per_cycle::8 293 0.15% 100.00% # Number of insts issued each cycle

1471system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1472system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1473system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1475system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1476system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1477system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1474system.cpu2.iq.issued_per_cycle::total 189804 # Number of insts issued each cycle

1478system.cpu2.iq.issued_per_cycle::total 191752 # Number of insts issued each cycle

1475system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1479system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1476system.cpu2.iq.fu_full::IntAlu 232 44.96% 44.96% # attempts to use FU when none available
1477system.cpu2.iq.fu_full::IntMult 0 0.00% 44.96% # attempts to use FU when none available
1478system.cpu2.iq.fu_full::IntDiv 0 0.00% 44.96% # attempts to use FU when none available
1479system.cpu2.iq.fu_full::FloatAdd 0 0.00% 44.96% # attempts to use FU when none available
1480system.cpu2.iq.fu_full::FloatCmp 0 0.00% 44.96% # attempts to use FU when none available
1481system.cpu2.iq.fu_full::FloatCvt 0 0.00% 44.96% # attempts to use FU when none available
1482system.cpu2.iq.fu_full::FloatMult 0 0.00% 44.96% # attempts to use FU when none available
1483system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available
1484system.cpu2.iq.fu_full::FloatDiv 0 0.00% 44.96% # attempts to use FU when none available
1485system.cpu2.iq.fu_full::FloatMisc 0 0.00% 44.96% # attempts to use FU when none available
1486system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 44.96% # attempts to use FU when none available
1487system.cpu2.iq.fu_full::SimdAdd 0 0.00% 44.96% # attempts to use FU when none available
1488system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 44.96% # attempts to use FU when none available
1489system.cpu2.iq.fu_full::SimdAlu 0 0.00% 44.96% # attempts to use FU when none available
1490system.cpu2.iq.fu_full::SimdCmp 0 0.00% 44.96% # attempts to use FU when none available
1491system.cpu2.iq.fu_full::SimdCvt 0 0.00% 44.96% # attempts to use FU when none available
1492system.cpu2.iq.fu_full::SimdMisc 0 0.00% 44.96% # attempts to use FU when none available
1493system.cpu2.iq.fu_full::SimdMult 0 0.00% 44.96% # attempts to use FU when none available
1494system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 44.96% # attempts to use FU when none available
1495system.cpu2.iq.fu_full::SimdShift 0 0.00% 44.96% # attempts to use FU when none available
1496system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 44.96% # attempts to use FU when none available
1497system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 44.96% # attempts to use FU when none available
1498system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 44.96% # attempts to use FU when none available
1499system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 44.96% # attempts to use FU when none available
1500system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 44.96% # attempts to use FU when none available
1501system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 44.96% # attempts to use FU when none available
1502system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 44.96% # attempts to use FU when none available
1503system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 44.96% # attempts to use FU when none available
1504system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 44.96% # attempts to use FU when none available
1505system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available
1506system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 44.96% # attempts to use FU when none available
1507system.cpu2.iq.fu_full::MemRead 58 11.24% 56.20% # attempts to use FU when none available
1508system.cpu2.iq.fu_full::MemWrite 226 43.80% 100.00% # attempts to use FU when none available

1480system.cpu2.iq.fu_full::IntAlu 214 43.32% 43.32% # attempts to use FU when none available
1481system.cpu2.iq.fu_full::IntMult 0 0.00% 43.32% # attempts to use FU when none available
1482system.cpu2.iq.fu_full::IntDiv 0 0.00% 43.32% # attempts to use FU when none available
1483system.cpu2.iq.fu_full::FloatAdd 0 0.00% 43.32% # attempts to use FU when none available
1484system.cpu2.iq.fu_full::FloatCmp 0 0.00% 43.32% # attempts to use FU when none available
1485system.cpu2.iq.fu_full::FloatCvt 0 0.00% 43.32% # attempts to use FU when none available
1486system.cpu2.iq.fu_full::FloatMult 0 0.00% 43.32% # attempts to use FU when none available
1487system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available
1488system.cpu2.iq.fu_full::FloatDiv 0 0.00% 43.32% # attempts to use FU when none available
1489system.cpu2.iq.fu_full::FloatMisc 0 0.00% 43.32% # attempts to use FU when none available
1490system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 43.32% # attempts to use FU when none available
1491system.cpu2.iq.fu_full::SimdAdd 0 0.00% 43.32% # attempts to use FU when none available
1492system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 43.32% # attempts to use FU when none available
1493system.cpu2.iq.fu_full::SimdAlu 0 0.00% 43.32% # attempts to use FU when none available
1494system.cpu2.iq.fu_full::SimdCmp 0 0.00% 43.32% # attempts to use FU when none available
1495system.cpu2.iq.fu_full::SimdCvt 0 0.00% 43.32% # attempts to use FU when none available
1496system.cpu2.iq.fu_full::SimdMisc 0 0.00% 43.32% # attempts to use FU when none available
1497system.cpu2.iq.fu_full::SimdMult 0 0.00% 43.32% # attempts to use FU when none available
1498system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 43.32% # attempts to use FU when none available
1499system.cpu2.iq.fu_full::SimdShift 0 0.00% 43.32% # attempts to use FU when none available
1500system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 43.32% # attempts to use FU when none available
1501system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 43.32% # attempts to use FU when none available
1502system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 43.32% # attempts to use FU when none available
1503system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 43.32% # attempts to use FU when none available
1504system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 43.32% # attempts to use FU when none available
1505system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 43.32% # attempts to use FU when none available
1506system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 43.32% # attempts to use FU when none available
1507system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 43.32% # attempts to use FU when none available
1508system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 43.32% # attempts to use FU when none available
1509system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available
1510system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 43.32% # attempts to use FU when none available
1511system.cpu2.iq.fu_full::MemRead 44 8.91% 52.23% # attempts to use FU when none available
1512system.cpu2.iq.fu_full::MemWrite 236 47.77% 100.00% # attempts to use FU when none available

1509system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
1510system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
1511system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1512system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1513system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1513system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
1514system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
1515system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1516system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1517system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1514system.cpu2.iq.FU_type_0::IntAlu 114651 50.16% 50.16% # Type of FU issued
1515system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.16% # Type of FU issued
1516system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.16% # Type of FU issued
1517system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.16% # Type of FU issued
1518system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.16% # Type of FU issued
1519system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.16% # Type of FU issued
1520system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.16% # Type of FU issued
1521system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 50.16% # Type of FU issued
1522system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.16% # Type of FU issued
1523system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 50.16% # Type of FU issued
1524system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.16% # Type of FU issued
1525system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.16% # Type of FU issued
1526system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.16% # Type of FU issued
1527system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.16% # Type of FU issued
1528system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.16% # Type of FU issued
1529system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.16% # Type of FU issued
1530system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.16% # Type of FU issued
1531system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.16% # Type of FU issued
1532system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.16% # Type of FU issued
1533system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.16% # Type of FU issued
1534system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.16% # Type of FU issued
1535system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.16% # Type of FU issued
1536system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.16% # Type of FU issued
1537system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.16% # Type of FU issued
1538system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.16% # Type of FU issued
1539system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.16% # Type of FU issued
1540system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.16% # Type of FU issued
1541system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.16% # Type of FU issued
1542system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.16% # Type of FU issued
1543system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.16% # Type of FU issued
1544system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.16% # Type of FU issued
1545system.cpu2.iq.FU_type_0::MemRead 81333 35.58% 85.74% # Type of FU issued
1546system.cpu2.iq.FU_type_0::MemWrite 32584 14.26% 100.00% # Type of FU issued

1518system.cpu2.iq.FU_type_0::IntAlu 127216 48.78% 48.78% # Type of FU issued
1519system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.78% # Type of FU issued
1520system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.78% # Type of FU issued
1521system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.78% # Type of FU issued
1522system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.78% # Type of FU issued
1523system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.78% # Type of FU issued
1524system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.78% # Type of FU issued
1525system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.78% # Type of FU issued
1526system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.78% # Type of FU issued
1527system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.78% # Type of FU issued
1528system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.78% # Type of FU issued
1529system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.78% # Type of FU issued
1530system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.78% # Type of FU issued
1531system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.78% # Type of FU issued
1532system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.78% # Type of FU issued
1533system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.78% # Type of FU issued
1534system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.78% # Type of FU issued
1535system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.78% # Type of FU issued
1536system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.78% # Type of FU issued
1537system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.78% # Type of FU issued
1538system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.78% # Type of FU issued
1539system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.78% # Type of FU issued
1540system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.78% # Type of FU issued
1541system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.78% # Type of FU issued
1542system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.78% # Type of FU issued
1543system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.78% # Type of FU issued
1544system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.78% # Type of FU issued
1545system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.78% # Type of FU issued
1546system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.78% # Type of FU issued
1547system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.78% # Type of FU issued
1548system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.78% # Type of FU issued
1549system.cpu2.iq.FU_type_0::MemRead 93561 35.87% 84.65% # Type of FU issued
1550system.cpu2.iq.FU_type_0::MemWrite 40032 15.35% 100.00% # Type of FU issued

1547system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
1548system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
1549system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1550system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1551system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
1552system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
1553system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1554system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1551system.cpu2.iq.FU_type_0::total 228568 # Type of FU issued
1552system.cpu2.iq.rate 1.193997 # Inst issue rate
1553system.cpu2.iq.fu_busy_cnt 516 # FU busy when requested
1554system.cpu2.iq.fu_busy_rate 0.002258 # FU busy rate (busy events/executed inst)
1555system.cpu2.iq.int_inst_queue_reads 647596 # Number of integer instruction queue reads
1556system.cpu2.iq.int_inst_queue_writes 262684 # Number of integer instruction queue writes
1557system.cpu2.iq.int_inst_queue_wakeup_accesses 224391 # Number of integer instruction queue wakeup accesses

1555system.cpu2.iq.FU_type_0::total 260809 # Type of FU issued
1556system.cpu2.iq.rate 1.340672 # Inst issue rate
1557system.cpu2.iq.fu_busy_cnt 494 # FU busy when requested
1558system.cpu2.iq.fu_busy_rate 0.001894 # FU busy rate (busy events/executed inst)
1559system.cpu2.iq.int_inst_queue_reads 713946 # Number of integer instruction queue reads
1560system.cpu2.iq.int_inst_queue_writes 292577 # Number of integer instruction queue writes
1561system.cpu2.iq.int_inst_queue_wakeup_accesses 257120 # Number of integer instruction queue wakeup accesses

1558system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

1562system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

1559system.cpu2.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes

1563system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes

1560system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1564system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1561system.cpu2.iq.int_alu_accesses 229084 # Number of integer alu accesses

1565system.cpu2.iq.int_alu_accesses 261303 # Number of integer alu accesses

1562system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1566system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1563system.cpu2.iew.lsq.thread0.forwLoads 27120 # Number of loads that had data forwarded from stores

1567system.cpu2.iew.lsq.thread0.forwLoads 34638 # Number of loads that had data forwarded from stores

1564system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1568system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1565system.cpu2.iew.lsq.thread0.squashedLoads 4546 # Number of loads squashed
1566system.cpu2.iew.lsq.thread0.ignoredResponses 31 # Number of memory responses ignored because the instruction is squashed

1569system.cpu2.iew.lsq.thread0.squashedLoads 4387 # Number of loads squashed
1570system.cpu2.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed

1567system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations

1571system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations

1568system.cpu2.iew.lsq.thread0.squashedStores 2695 # Number of stores squashed

1572system.cpu2.iew.lsq.thread0.squashedStores 2568 # Number of stores squashed

1569system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1570system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1571system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1572system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1573system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1573system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1574system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1575system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1576system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1577system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1574system.cpu2.iew.iewSquashCycles 2477 # Number of cycles IEW is squashing
1575system.cpu2.iew.iewBlockCycles 10821 # Number of cycles IEW is blocking
1576system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
1577system.cpu2.iew.iewDispatchedInsts 273857 # Number of instructions dispatched to IQ
1578system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch
1579system.cpu2.iew.iewDispLoadInsts 74139 # Number of dispatched load instructions
1580system.cpu2.iew.iewDispStoreInsts 33614 # Number of dispatched store instructions
1581system.cpu2.iew.iewDispNonSpecInsts 1537 # Number of dispatched non-speculative instructions
1582system.cpu2.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall

1578system.cpu2.iew.iewSquashCycles 2453 # Number of cycles IEW is squashing
1579system.cpu2.iew.iewBlockCycles 9291 # Number of cycles IEW is blocking
1580system.cpu2.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
1581system.cpu2.iew.iewDispatchedInsts 312015 # Number of instructions dispatched to IQ
1582system.cpu2.iew.iewDispSquashedInsts 352 # Number of squashed instructions skipped by dispatch
1583system.cpu2.iew.iewDispLoadInsts 87706 # Number of dispatched load instructions
1584system.cpu2.iew.iewDispStoreInsts 41007 # Number of dispatched store instructions
1585system.cpu2.iew.iewDispNonSpecInsts 1521 # Number of dispatched non-speculative instructions
1586system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall

1583system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1584system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations

1587system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
1588system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations

1585system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly
1586system.cpu2.iew.predictedNotTakenIncorrect 2611 # Number of branches that were predicted not taken incorrectly
1587system.cpu2.iew.branchMispredicts 3072 # Number of branch mispredicts detected at execute
1588system.cpu2.iew.iewExecutedInsts 225860 # Number of executed instructions
1589system.cpu2.iew.iewExecLoadInsts 72453 # Number of load instructions executed
1590system.cpu2.iew.iewExecSquashedInsts 2708 # Number of squashed instructions skipped in execute

1589system.cpu2.iew.predictedTakenIncorrect 454 # Number of branches that were predicted taken incorrectly
1590system.cpu2.iew.predictedNotTakenIncorrect 2525 # Number of branches that were predicted not taken incorrectly
1591system.cpu2.iew.branchMispredicts 2979 # Number of branch mispredicts detected at execute
1592system.cpu2.iew.iewExecutedInsts 258429 # Number of executed instructions
1593system.cpu2.iew.iewExecLoadInsts 86072 # Number of load instructions executed
1594system.cpu2.iew.iewExecSquashedInsts 2380 # Number of squashed instructions skipped in execute

1591system.cpu2.iew.exec_swp 0 # number of swp insts executed

1595system.cpu2.iew.exec_swp 0 # number of swp insts executed

1592system.cpu2.iew.exec_nop 37061 # number of nop insts executed
1593system.cpu2.iew.exec_refs 104703 # number of memory reference insts executed
1594system.cpu2.iew.exec_branches 47570 # Number of branches executed
1595system.cpu2.iew.exec_stores 32250 # Number of stores executed
1596system.cpu2.iew.exec_rate 1.179851 # Inst execution rate
1597system.cpu2.iew.wb_sent 224905 # cumulative count of insts sent to commit
1598system.cpu2.iew.wb_count 224391 # cumulative count of insts written-back
1599system.cpu2.iew.wb_producers 122751 # num instructions producing a value
1600system.cpu2.iew.wb_consumers 130504 # num instructions consuming a value
1601system.cpu2.iew.wb_rate 1.172177 # insts written-back per cycle
1602system.cpu2.iew.wb_fanout 0.940592 # average fanout of values written-back
1603system.cpu2.commit.commitSquashedInsts 27003 # The number of squashed insts skipped by commit
1604system.cpu2.commit.commitNonSpecStalls 8993 # The number of times commit has been forced to stall to communicate backwards
1605system.cpu2.commit.branchMispredicts 2399 # The number of times a branch was mispredicted
1606system.cpu2.commit.committed_per_cycle::samples 184731 # Number of insts commited each cycle
1607system.cpu2.commit.committed_per_cycle::mean 1.336127 # Number of insts commited each cycle
1608system.cpu2.commit.committed_per_cycle::stdev 1.921991 # Number of insts commited each cycle

1596system.cpu2.iew.exec_nop 43439 # number of nop insts executed
1597system.cpu2.iew.exec_refs 125830 # number of memory reference insts executed
1598system.cpu2.iew.exec_branches 53606 # Number of branches executed
1599system.cpu2.iew.exec_stores 39758 # Number of stores executed
1600system.cpu2.iew.exec_rate 1.328438 # Inst execution rate
1601system.cpu2.iew.wb_sent 257596 # cumulative count of insts sent to commit
1602system.cpu2.iew.wb_count 257120 # cumulative count of insts written-back
1603system.cpu2.iew.wb_producers 143610 # num instructions producing a value
1604system.cpu2.iew.wb_consumers 151220 # num instructions consuming a value
1605system.cpu2.iew.wb_rate 1.321709 # insts written-back per cycle
1606system.cpu2.iew.wb_fanout 0.949676 # average fanout of values written-back
1607system.cpu2.commit.commitSquashedInsts 25270 # The number of squashed insts skipped by commit
1608system.cpu2.commit.commitNonSpecStalls 7691 # The number of times commit has been forced to stall to communicate backwards
1609system.cpu2.commit.branchMispredicts 2375 # The number of times a branch was mispredicted
1610system.cpu2.commit.committed_per_cycle::samples 186904 # Number of insts commited each cycle
1611system.cpu2.commit.committed_per_cycle::mean 1.534044 # Number of insts commited each cycle
1612system.cpu2.commit.committed_per_cycle::stdev 2.009689 # Number of insts commited each cycle

1609system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1613system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1610system.cpu2.commit.committed_per_cycle::0 94349 51.07% 51.07% # Number of insts commited each cycle
1611system.cpu2.commit.committed_per_cycle::1 43685 23.65% 74.72% # Number of insts commited each cycle
1612system.cpu2.commit.committed_per_cycle::2 5440 2.94% 77.67% # Number of insts commited each cycle
1613system.cpu2.commit.committed_per_cycle::3 9609 5.20% 82.87% # Number of insts commited each cycle
1614system.cpu2.commit.committed_per_cycle::4 1281 0.69% 83.56% # Number of insts commited each cycle
1615system.cpu2.commit.committed_per_cycle::5 27371 14.82% 98.38% # Number of insts commited each cycle
1616system.cpu2.commit.committed_per_cycle::6 737 0.40% 98.78% # Number of insts commited each cycle
1617system.cpu2.commit.committed_per_cycle::7 1041 0.56% 99.34% # Number of insts commited each cycle
1618system.cpu2.commit.committed_per_cycle::8 1218 0.66% 100.00% # Number of insts commited each cycle

1614system.cpu2.commit.committed_per_cycle::0 84130 45.01% 45.01% # Number of insts commited each cycle
1615system.cpu2.commit.committed_per_cycle::1 49844 26.67% 71.68% # Number of insts commited each cycle
1616system.cpu2.commit.committed_per_cycle::2 5407 2.89% 74.57% # Number of insts commited each cycle
1617system.cpu2.commit.committed_per_cycle::3 8359 4.47% 79.05% # Number of insts commited each cycle
1618system.cpu2.commit.committed_per_cycle::4 1323 0.71% 79.75% # Number of insts commited each cycle
1619system.cpu2.commit.committed_per_cycle::5 34855 18.65% 98.40% # Number of insts commited each cycle
1620system.cpu2.commit.committed_per_cycle::6 714 0.38% 98.78% # Number of insts commited each cycle
1621system.cpu2.commit.committed_per_cycle::7 1043 0.56% 99.34% # Number of insts commited each cycle
1622system.cpu2.commit.committed_per_cycle::8 1229 0.66% 100.00% # Number of insts commited each cycle

1619system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1620system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1621system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1623system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1624system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1625system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1622system.cpu2.commit.committed_per_cycle::total 184731 # Number of insts commited each cycle
1623system.cpu2.commit.committedInsts 246824 # Number of instructions committed
1624system.cpu2.commit.committedOps 246824 # Number of ops (including micro ops) committed

1626system.cpu2.commit.committed_per_cycle::total 186904 # Number of insts commited each cycle
1627system.cpu2.commit.committedInsts 286719 # Number of instructions committed
1628system.cpu2.commit.committedOps 286719 # Number of ops (including micro ops) committed

1625system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1629system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1626system.cpu2.commit.refs 100512 # Number of memory references committed
1627system.cpu2.commit.loads 69593 # Number of loads committed
1628system.cpu2.commit.membars 8278 # Number of memory barriers committed
1629system.cpu2.commit.branches 45154 # Number of branches committed

1630system.cpu2.commit.refs 121758 # Number of memory references committed
1631system.cpu2.commit.loads 83319 # Number of loads committed
1632system.cpu2.commit.membars 6971 # Number of memory barriers committed
1633system.cpu2.commit.branches 51375 # Number of branches committed

1630system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1634system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1631system.cpu2.commit.int_insts 167790 # Number of committed integer instructions.

1635system.cpu2.commit.int_insts 195248 # Number of committed integer instructions.

1632system.cpu2.commit.function_calls 322 # Number of function calls committed.

1636system.cpu2.commit.function_calls 322 # Number of function calls committed.

1633system.cpu2.commit.op_class_0::No_OpClass 35943 14.56% 14.56% # Class of committed instruction
1634system.cpu2.commit.op_class_0::IntAlu 102091 41.36% 55.92% # Class of committed instruction
1635system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction
1636system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction
1637system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction
1638system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction
1639system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction
1640system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction
1641system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.92% # Class of committed instruction
1642system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction
1643system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.92% # Class of committed instruction
1644system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction
1645system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction
1646system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction
1647system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction
1648system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction
1649system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction
1650system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction
1651system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction
1652system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction
1653system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction
1654system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction
1655system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction
1656system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction
1657system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction
1658system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction
1659system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction
1660system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction
1661system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction
1662system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction
1663system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction
1664system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction
1665system.cpu2.commit.op_class_0::MemRead 77871 31.55% 87.47% # Class of committed instruction
1666system.cpu2.commit.op_class_0::MemWrite 30919 12.53% 100.00% # Class of committed instruction

1637system.cpu2.commit.op_class_0::No_OpClass 42159 14.70% 14.70% # Class of committed instruction
1638system.cpu2.commit.op_class_0::IntAlu 115831 40.40% 55.10% # Class of committed instruction
1639system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.10% # Class of committed instruction
1640system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.10% # Class of committed instruction
1641system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.10% # Class of committed instruction
1642system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.10% # Class of committed instruction
1643system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.10% # Class of committed instruction
1644system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.10% # Class of committed instruction
1645system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.10% # Class of committed instruction
1646system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.10% # Class of committed instruction
1647system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.10% # Class of committed instruction
1648system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.10% # Class of committed instruction
1649system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.10% # Class of committed instruction
1650system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.10% # Class of committed instruction
1651system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.10% # Class of committed instruction
1652system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.10% # Class of committed instruction
1653system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.10% # Class of committed instruction
1654system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.10% # Class of committed instruction
1655system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.10% # Class of committed instruction
1656system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.10% # Class of committed instruction
1657system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.10% # Class of committed instruction
1658system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.10% # Class of committed instruction
1659system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.10% # Class of committed instruction
1660system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.10% # Class of committed instruction
1661system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.10% # Class of committed instruction
1662system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.10% # Class of committed instruction
1663system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.10% # Class of committed instruction
1664system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.10% # Class of committed instruction
1665system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.10% # Class of committed instruction
1666system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.10% # Class of committed instruction
1667system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.10% # Class of committed instruction
1668system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.10% # Class of committed instruction
1669system.cpu2.commit.op_class_0::MemRead 90290 31.49% 86.59% # Class of committed instruction
1670system.cpu2.commit.op_class_0::MemWrite 38439 13.41% 100.00% # Class of committed instruction

1667system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
1668system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
1669system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1670system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1671system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
1672system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
1673system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1674system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1671system.cpu2.commit.op_class_0::total 246824 # Class of committed instruction
1672system.cpu2.commit.bw_lim_events 1218 # number cycles where commit BW limit reached
1673system.cpu2.rob.rob_reads 456754 # The number of ROB reads
1674system.cpu2.rob.rob_writes 552779 # The number of ROB writes
1675system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
1676system.cpu2.idleCycles 1627 # Total number of cycles that the CPU has spent unscheduled due to idling
1677system.cpu2.quiesceCycles 49789 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1678system.cpu2.committedInsts 202603 # Number of Instructions Simulated
1679system.cpu2.committedOps 202603 # Number of Ops (including micro ops) Simulated
1680system.cpu2.cpi 0.944858 # CPI: Cycles Per Instruction
1681system.cpu2.cpi_total 0.944858 # CPI: Total CPI of All Threads
1682system.cpu2.ipc 1.058360 # IPC: Instructions Per Cycle
1683system.cpu2.ipc_total 1.058360 # IPC: Total IPC of All Threads
1684system.cpu2.int_regfile_reads 379324 # number of integer regfile reads
1685system.cpu2.int_regfile_writes 178066 # number of integer regfile writes

1675system.cpu2.commit.op_class_0::total 286719 # Class of committed instruction
1676system.cpu2.commit.bw_lim_events 1229 # number cycles where commit BW limit reached
1677system.cpu2.rob.rob_reads 497078 # The number of ROB reads
1678system.cpu2.rob.rob_writes 628878 # The number of ROB writes
1679system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
1680system.cpu2.idleCycles 2784 # Total number of cycles that the CPU has spent unscheduled due to idling
1681system.cpu2.quiesceCycles 49801 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1682system.cpu2.committedInsts 237589 # Number of Instructions Simulated
1683system.cpu2.committedOps 237589 # Number of Ops (including micro ops) Simulated
1684system.cpu2.cpi 0.818792 # CPI: Cycles Per Instruction
1685system.cpu2.cpi_total 0.818792 # CPI: Total CPI of All Threads
1686system.cpu2.ipc 1.221311 # IPC: Instructions Per Cycle
1687system.cpu2.ipc_total 1.221311 # IPC: Total IPC of All Threads
1688system.cpu2.int_regfile_reads 441330 # number of integer regfile reads
1689system.cpu2.int_regfile_writes 205867 # number of integer regfile writes

1686system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1690system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1687system.cpu2.misc_regfile_reads 106600 # number of misc regfile reads

1691system.cpu2.misc_regfile_reads 127741 # number of misc regfile reads

1688system.cpu2.misc_regfile_writes 648 # number of misc regfile writes

1692system.cpu2.misc_regfile_writes 648 # number of misc regfile writes

1689system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

1693system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

1690system.cpu2.dcache.tags.replacements 0 # number of replacements

1694system.cpu2.dcache.tags.replacements 0 # number of replacements

1691system.cpu2.dcache.tags.tagsinuse 24.613342 # Cycle average of tags in use
1692system.cpu2.dcache.tags.total_refs 38229 # Total number of references to valid blocks.
1693system.cpu2.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
1694system.cpu2.dcache.tags.avg_refs 1233.193548 # Average number of references to valid blocks.

1695system.cpu2.dcache.tags.tagsinuse 25.326014 # Cycle average of tags in use
1696system.cpu2.dcache.tags.total_refs 45457 # Total number of references to valid blocks.
1697system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1698system.cpu2.dcache.tags.avg_refs 1567.482759 # Average number of references to valid blocks.

1695system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1699system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1696system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.613342 # Average occupied blocks per requestor
1697system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048073 # Average percentage of cache occupancy
1698system.cpu2.dcache.tags.occ_percent::total 0.048073 # Average percentage of cache occupancy
1699system.cpu2.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
1700system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
1701system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
1702system.cpu2.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
1703system.cpu2.dcache.tags.tag_accesses 305153 # Number of tag accesses
1704system.cpu2.dcache.tags.data_accesses 305153 # Number of data accesses
1705system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1706system.cpu2.dcache.ReadReq_hits::cpu2.data 44839 # number of ReadReq hits
1707system.cpu2.dcache.ReadReq_hits::total 44839 # number of ReadReq hits
1708system.cpu2.dcache.WriteReq_hits::cpu2.data 30714 # number of WriteReq hits
1709system.cpu2.dcache.WriteReq_hits::total 30714 # number of WriteReq hits
1710system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits
1711system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits
1712system.cpu2.dcache.demand_hits::cpu2.data 75553 # number of demand (read+write) hits
1713system.cpu2.dcache.demand_hits::total 75553 # number of demand (read+write) hits
1714system.cpu2.dcache.overall_hits::cpu2.data 75553 # number of overall hits
1715system.cpu2.dcache.overall_hits::total 75553 # number of overall hits
1716system.cpu2.dcache.ReadReq_misses::cpu2.data 467 # number of ReadReq misses
1717system.cpu2.dcache.ReadReq_misses::total 467 # number of ReadReq misses
1718system.cpu2.dcache.WriteReq_misses::cpu2.data 136 # number of WriteReq misses
1719system.cpu2.dcache.WriteReq_misses::total 136 # number of WriteReq misses
1720system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses
1721system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses
1722system.cpu2.dcache.demand_misses::cpu2.data 603 # number of demand (read+write) misses
1723system.cpu2.dcache.demand_misses::total 603 # number of demand (read+write) misses
1724system.cpu2.dcache.overall_misses::cpu2.data 603 # number of overall misses
1725system.cpu2.dcache.overall_misses::total 603 # number of overall misses
1726system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3772500 # number of ReadReq miss cycles
1727system.cpu2.dcache.ReadReq_miss_latency::total 3772500 # number of ReadReq miss cycles
1728system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3722500 # number of WriteReq miss cycles
1729system.cpu2.dcache.WriteReq_miss_latency::total 3722500 # number of WriteReq miss cycles
1730system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 339500 # number of SwapReq miss cycles
1731system.cpu2.dcache.SwapReq_miss_latency::total 339500 # number of SwapReq miss cycles
1732system.cpu2.dcache.demand_miss_latency::cpu2.data 7495000 # number of demand (read+write) miss cycles
1733system.cpu2.dcache.demand_miss_latency::total 7495000 # number of demand (read+write) miss cycles
1734system.cpu2.dcache.overall_miss_latency::cpu2.data 7495000 # number of overall miss cycles
1735system.cpu2.dcache.overall_miss_latency::total 7495000 # number of overall miss cycles
1736system.cpu2.dcache.ReadReq_accesses::cpu2.data 45306 # number of ReadReq accesses(hits+misses)
1737system.cpu2.dcache.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses)
1738system.cpu2.dcache.WriteReq_accesses::cpu2.data 30850 # number of WriteReq accesses(hits+misses)
1739system.cpu2.dcache.WriteReq_accesses::total 30850 # number of WriteReq accesses(hits+misses)
1740system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
1741system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
1742system.cpu2.dcache.demand_accesses::cpu2.data 76156 # number of demand (read+write) accesses
1743system.cpu2.dcache.demand_accesses::total 76156 # number of demand (read+write) accesses
1744system.cpu2.dcache.overall_accesses::cpu2.data 76156 # number of overall (read+write) accesses
1745system.cpu2.dcache.overall_accesses::total 76156 # number of overall (read+write) accesses
1746system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010308 # miss rate for ReadReq accesses
1747system.cpu2.dcache.ReadReq_miss_rate::total 0.010308 # miss rate for ReadReq accesses
1748system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004408 # miss rate for WriteReq accesses
1749system.cpu2.dcache.WriteReq_miss_rate::total 0.004408 # miss rate for WriteReq accesses
1750system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.768116 # miss rate for SwapReq accesses
1751system.cpu2.dcache.SwapReq_miss_rate::total 0.768116 # miss rate for SwapReq accesses
1752system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007918 # miss rate for demand accesses
1753system.cpu2.dcache.demand_miss_rate::total 0.007918 # miss rate for demand accesses
1754system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007918 # miss rate for overall accesses
1755system.cpu2.dcache.overall_miss_rate::total 0.007918 # miss rate for overall accesses
1756system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8078.158458 # average ReadReq miss latency
1757system.cpu2.dcache.ReadReq_avg_miss_latency::total 8078.158458 # average ReadReq miss latency
1758system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 27371.323529 # average WriteReq miss latency
1759system.cpu2.dcache.WriteReq_avg_miss_latency::total 27371.323529 # average WriteReq miss latency
1760system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6405.660377 # average SwapReq miss latency
1761system.cpu2.dcache.SwapReq_avg_miss_latency::total 6405.660377 # average SwapReq miss latency
1762system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency
1763system.cpu2.dcache.demand_avg_miss_latency::total 12429.519071 # average overall miss latency
1764system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency
1765system.cpu2.dcache.overall_avg_miss_latency::total 12429.519071 # average overall miss latency

1700system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.326014 # Average occupied blocks per requestor
1701system.cpu2.dcache.tags.occ_percent::cpu2.data 0.049465 # Average percentage of cache occupancy
1702system.cpu2.dcache.tags.occ_percent::total 0.049465 # Average percentage of cache occupancy
1703system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1704system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
1705system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
1706system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1707system.cpu2.dcache.tags.tag_accesses 359653 # Number of tag accesses
1708system.cpu2.dcache.tags.data_accesses 359653 # Number of data accesses
1709system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1710system.cpu2.dcache.ReadReq_hits::cpu2.data 50904 # number of ReadReq hits
1711system.cpu2.dcache.ReadReq_hits::total 50904 # number of ReadReq hits
1712system.cpu2.dcache.WriteReq_hits::cpu2.data 38221 # number of WriteReq hits
1713system.cpu2.dcache.WriteReq_hits::total 38221 # number of WriteReq hits
1714system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
1715system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1716system.cpu2.dcache.demand_hits::cpu2.data 89125 # number of demand (read+write) hits
1717system.cpu2.dcache.demand_hits::total 89125 # number of demand (read+write) hits
1718system.cpu2.dcache.overall_hits::cpu2.data 89125 # number of overall hits
1719system.cpu2.dcache.overall_hits::total 89125 # number of overall hits
1720system.cpu2.dcache.ReadReq_misses::cpu2.data 505 # number of ReadReq misses
1721system.cpu2.dcache.ReadReq_misses::total 505 # number of ReadReq misses
1722system.cpu2.dcache.WriteReq_misses::cpu2.data 144 # number of WriteReq misses
1723system.cpu2.dcache.WriteReq_misses::total 144 # number of WriteReq misses
1724system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses
1725system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses
1726system.cpu2.dcache.demand_misses::cpu2.data 649 # number of demand (read+write) misses
1727system.cpu2.dcache.demand_misses::total 649 # number of demand (read+write) misses
1728system.cpu2.dcache.overall_misses::cpu2.data 649 # number of overall misses
1729system.cpu2.dcache.overall_misses::total 649 # number of overall misses
1730system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3857000 # number of ReadReq miss cycles
1731system.cpu2.dcache.ReadReq_miss_latency::total 3857000 # number of ReadReq miss cycles
1732system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3021500 # number of WriteReq miss cycles
1733system.cpu2.dcache.WriteReq_miss_latency::total 3021500 # number of WriteReq miss cycles
1734system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 367000 # number of SwapReq miss cycles
1735system.cpu2.dcache.SwapReq_miss_latency::total 367000 # number of SwapReq miss cycles
1736system.cpu2.dcache.demand_miss_latency::cpu2.data 6878500 # number of demand (read+write) miss cycles
1737system.cpu2.dcache.demand_miss_latency::total 6878500 # number of demand (read+write) miss cycles
1738system.cpu2.dcache.overall_miss_latency::cpu2.data 6878500 # number of overall miss cycles
1739system.cpu2.dcache.overall_miss_latency::total 6878500 # number of overall miss cycles
1740system.cpu2.dcache.ReadReq_accesses::cpu2.data 51409 # number of ReadReq accesses(hits+misses)
1741system.cpu2.dcache.ReadReq_accesses::total 51409 # number of ReadReq accesses(hits+misses)
1742system.cpu2.dcache.WriteReq_accesses::cpu2.data 38365 # number of WriteReq accesses(hits+misses)
1743system.cpu2.dcache.WriteReq_accesses::total 38365 # number of WriteReq accesses(hits+misses)
1744system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses)
1745system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses)
1746system.cpu2.dcache.demand_accesses::cpu2.data 89774 # number of demand (read+write) accesses
1747system.cpu2.dcache.demand_accesses::total 89774 # number of demand (read+write) accesses
1748system.cpu2.dcache.overall_accesses::cpu2.data 89774 # number of overall (read+write) accesses
1749system.cpu2.dcache.overall_accesses::total 89774 # number of overall (read+write) accesses
1750system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009823 # miss rate for ReadReq accesses
1751system.cpu2.dcache.ReadReq_miss_rate::total 0.009823 # miss rate for ReadReq accesses
1752system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003753 # miss rate for WriteReq accesses
1753system.cpu2.dcache.WriteReq_miss_rate::total 0.003753 # miss rate for WriteReq accesses
1754system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838 # miss rate for SwapReq accesses
1755system.cpu2.dcache.SwapReq_miss_rate::total 0.837838 # miss rate for SwapReq accesses
1756system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007229 # miss rate for demand accesses
1757system.cpu2.dcache.demand_miss_rate::total 0.007229 # miss rate for demand accesses
1758system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007229 # miss rate for overall accesses
1759system.cpu2.dcache.overall_miss_rate::total 0.007229 # miss rate for overall accesses
1760system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7637.623762 # average ReadReq miss latency
1761system.cpu2.dcache.ReadReq_avg_miss_latency::total 7637.623762 # average ReadReq miss latency
1762system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20982.638889 # average WriteReq miss latency
1763system.cpu2.dcache.WriteReq_avg_miss_latency::total 20982.638889 # average WriteReq miss latency
1764system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5919.354839 # average SwapReq miss latency
1765system.cpu2.dcache.SwapReq_avg_miss_latency::total 5919.354839 # average SwapReq miss latency
1766system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency
1767system.cpu2.dcache.demand_avg_miss_latency::total 10598.613251 # average overall miss latency
1768system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency
1769system.cpu2.dcache.overall_avg_miss_latency::total 10598.613251 # average overall miss latency

1766system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1767system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1768system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1769system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1770system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1771system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1770system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1771system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1772system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1773system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1774system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1775system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1772system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 301 # number of ReadReq MSHR hits
1773system.cpu2.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits
1774system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
1775system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
1776system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 1 # number of SwapReq MSHR hits
1777system.cpu2.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits
1778system.cpu2.dcache.demand_mshr_hits::cpu2.data 335 # number of demand (read+write) MSHR hits
1779system.cpu2.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
1780system.cpu2.dcache.overall_mshr_hits::cpu2.data 335 # number of overall MSHR hits
1781system.cpu2.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits
1782system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses
1783system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
1784system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses
1785system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
1786system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses
1787system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
1788system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
1789system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1790system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
1791system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1792system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1217000 # number of ReadReq MSHR miss cycles
1793system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1217000 # number of ReadReq MSHR miss cycles
1794system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1941500 # number of WriteReq MSHR miss cycles
1795system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1941500 # number of WriteReq MSHR miss cycles
1796system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 286500 # number of SwapReq MSHR miss cycles
1797system.cpu2.dcache.SwapReq_mshr_miss_latency::total 286500 # number of SwapReq MSHR miss cycles
1798system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3158500 # number of demand (read+write) MSHR miss cycles
1799system.cpu2.dcache.demand_mshr_miss_latency::total 3158500 # number of demand (read+write) MSHR miss cycles
1800system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3158500 # number of overall MSHR miss cycles
1801system.cpu2.dcache.overall_mshr_miss_latency::total 3158500 # number of overall MSHR miss cycles
1802system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003664 # mshr miss rate for ReadReq accesses
1803system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003664 # mshr miss rate for ReadReq accesses
1804system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003306 # mshr miss rate for WriteReq accesses
1805system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003306 # mshr miss rate for WriteReq accesses
1806system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.753623 # mshr miss rate for SwapReq accesses
1807system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses
1808system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for demand accesses
1809system.cpu2.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses
1810system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for overall accesses
1811system.cpu2.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses
1812system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7331.325301 # average ReadReq mshr miss latency
1813system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7331.325301 # average ReadReq mshr miss latency
1814system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725 # average WriteReq mshr miss latency
1815system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725 # average WriteReq mshr miss latency
1816system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5509.615385 # average SwapReq mshr miss latency
1817system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5509.615385 # average SwapReq mshr miss latency
1818system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency
1819system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency
1820system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency
1821system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency
1822system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1823system.cpu2.icache.tags.replacements 564 # number of replacements
1824system.cpu2.icache.tags.tagsinuse 92.356205 # Cycle average of tags in use
1825system.cpu2.icache.tags.total_refs 30734 # Total number of references to valid blocks.
1826system.cpu2.icache.tags.sampled_refs 702 # Sample count of references to valid blocks.
1827system.cpu2.icache.tags.avg_refs 43.780627 # Average number of references to valid blocks.

1776system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 337 # number of ReadReq MSHR hits
1777system.cpu2.dcache.ReadReq_mshr_hits::total 337 # number of ReadReq MSHR hits
1778system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits
1779system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits
1780system.cpu2.dcache.demand_mshr_hits::cpu2.data 378 # number of demand (read+write) MSHR hits
1781system.cpu2.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits
1782system.cpu2.dcache.overall_mshr_hits::cpu2.data 378 # number of overall MSHR hits
1783system.cpu2.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits
1784system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 168 # number of ReadReq MSHR misses
1785system.cpu2.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses
1786system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses
1787system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
1788system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses
1789system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses
1790system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
1791system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
1792system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
1793system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
1794system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1115500 # number of ReadReq MSHR miss cycles
1795system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1115500 # number of ReadReq MSHR miss cycles
1796system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1450500 # number of WriteReq MSHR miss cycles
1797system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles
1798system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 305000 # number of SwapReq MSHR miss cycles
1799system.cpu2.dcache.SwapReq_mshr_miss_latency::total 305000 # number of SwapReq MSHR miss cycles
1800system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2566000 # number of demand (read+write) MSHR miss cycles
1801system.cpu2.dcache.demand_mshr_miss_latency::total 2566000 # number of demand (read+write) MSHR miss cycles
1802system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2566000 # number of overall MSHR miss cycles
1803system.cpu2.dcache.overall_mshr_miss_latency::total 2566000 # number of overall MSHR miss cycles
1804system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003268 # mshr miss rate for ReadReq accesses
1805system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003268 # mshr miss rate for ReadReq accesses
1806system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses
1807system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses
1808system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.837838 # mshr miss rate for SwapReq accesses
1809system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.837838 # mshr miss rate for SwapReq accesses
1810system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for demand accesses
1811system.cpu2.dcache.demand_mshr_miss_rate::total 0.003019 # mshr miss rate for demand accesses
1812system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for overall accesses
1813system.cpu2.dcache.overall_mshr_miss_rate::total 0.003019 # mshr miss rate for overall accesses
1814system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6639.880952 # average ReadReq mshr miss latency
1815system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6639.880952 # average ReadReq mshr miss latency
1816system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14082.524272 # average WriteReq mshr miss latency
1817system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14082.524272 # average WriteReq mshr miss latency
1818system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 4919.354839 # average SwapReq mshr miss latency
1819system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 4919.354839 # average SwapReq mshr miss latency
1820system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency
1821system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency
1822system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency
1823system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency
1824system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1825system.cpu2.icache.tags.replacements 551 # number of replacements
1826system.cpu2.icache.tags.tagsinuse 96.895068 # Cycle average of tags in use
1827system.cpu2.icache.tags.total_refs 27659 # Total number of references to valid blocks.
1828system.cpu2.icache.tags.sampled_refs 687 # Sample count of references to valid blocks.
1829system.cpu2.icache.tags.avg_refs 40.260553 # Average number of references to valid blocks.

1828system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1830system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1829system.cpu2.icache.tags.occ_blocks::cpu2.inst 92.356205 # Average occupied blocks per requestor
1830system.cpu2.icache.tags.occ_percent::cpu2.inst 0.180383 # Average percentage of cache occupancy
1831system.cpu2.icache.tags.occ_percent::total 0.180383 # Average percentage of cache occupancy
1832system.cpu2.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
1833system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
1834system.cpu2.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
1835system.cpu2.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id
1836system.cpu2.icache.tags.tag_accesses 32282 # Number of tag accesses
1837system.cpu2.icache.tags.data_accesses 32282 # Number of data accesses
1838system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
1839system.cpu2.icache.ReadReq_hits::cpu2.inst 30734 # number of ReadReq hits
1840system.cpu2.icache.ReadReq_hits::total 30734 # number of ReadReq hits
1841system.cpu2.icache.demand_hits::cpu2.inst 30734 # number of demand (read+write) hits
1842system.cpu2.icache.demand_hits::total 30734 # number of demand (read+write) hits
1843system.cpu2.icache.overall_hits::cpu2.inst 30734 # number of overall hits
1844system.cpu2.icache.overall_hits::total 30734 # number of overall hits
1845system.cpu2.icache.ReadReq_misses::cpu2.inst 846 # number of ReadReq misses
1846system.cpu2.icache.ReadReq_misses::total 846 # number of ReadReq misses
1847system.cpu2.icache.demand_misses::cpu2.inst 846 # number of demand (read+write) misses
1848system.cpu2.icache.demand_misses::total 846 # number of demand (read+write) misses
1849system.cpu2.icache.overall_misses::cpu2.inst 846 # number of overall misses
1850system.cpu2.icache.overall_misses::total 846 # number of overall misses
1851system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12713000 # number of ReadReq miss cycles
1852system.cpu2.icache.ReadReq_miss_latency::total 12713000 # number of ReadReq miss cycles
1853system.cpu2.icache.demand_miss_latency::cpu2.inst 12713000 # number of demand (read+write) miss cycles
1854system.cpu2.icache.demand_miss_latency::total 12713000 # number of demand (read+write) miss cycles
1855system.cpu2.icache.overall_miss_latency::cpu2.inst 12713000 # number of overall miss cycles
1856system.cpu2.icache.overall_miss_latency::total 12713000 # number of overall miss cycles
1857system.cpu2.icache.ReadReq_accesses::cpu2.inst 31580 # number of ReadReq accesses(hits+misses)
1858system.cpu2.icache.ReadReq_accesses::total 31580 # number of ReadReq accesses(hits+misses)
1859system.cpu2.icache.demand_accesses::cpu2.inst 31580 # number of demand (read+write) accesses
1860system.cpu2.icache.demand_accesses::total 31580 # number of demand (read+write) accesses
1861system.cpu2.icache.overall_accesses::cpu2.inst 31580 # number of overall (read+write) accesses
1862system.cpu2.icache.overall_accesses::total 31580 # number of overall (read+write) accesses
1863system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.026789 # miss rate for ReadReq accesses
1864system.cpu2.icache.ReadReq_miss_rate::total 0.026789 # miss rate for ReadReq accesses
1865system.cpu2.icache.demand_miss_rate::cpu2.inst 0.026789 # miss rate for demand accesses
1866system.cpu2.icache.demand_miss_rate::total 0.026789 # miss rate for demand accesses
1867system.cpu2.icache.overall_miss_rate::cpu2.inst 0.026789 # miss rate for overall accesses
1868system.cpu2.icache.overall_miss_rate::total 0.026789 # miss rate for overall accesses
1869system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15027.186761 # average ReadReq miss latency
1870system.cpu2.icache.ReadReq_avg_miss_latency::total 15027.186761 # average ReadReq miss latency
1871system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency
1872system.cpu2.icache.demand_avg_miss_latency::total 15027.186761 # average overall miss latency
1873system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency
1874system.cpu2.icache.overall_avg_miss_latency::total 15027.186761 # average overall miss latency

1831system.cpu2.icache.tags.occ_blocks::cpu2.inst 96.895068 # Average occupied blocks per requestor
1832system.cpu2.icache.tags.occ_percent::cpu2.inst 0.189248 # Average percentage of cache occupancy
1833system.cpu2.icache.tags.occ_percent::total 0.189248 # Average percentage of cache occupancy
1834system.cpu2.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id
1835system.cpu2.icache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
1836system.cpu2.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
1837system.cpu2.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
1838system.cpu2.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id
1839system.cpu2.icache.tags.tag_accesses 29161 # Number of tag accesses
1840system.cpu2.icache.tags.data_accesses 29161 # Number of data accesses
1841system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
1842system.cpu2.icache.ReadReq_hits::cpu2.inst 27659 # number of ReadReq hits
1843system.cpu2.icache.ReadReq_hits::total 27659 # number of ReadReq hits
1844system.cpu2.icache.demand_hits::cpu2.inst 27659 # number of demand (read+write) hits
1845system.cpu2.icache.demand_hits::total 27659 # number of demand (read+write) hits
1846system.cpu2.icache.overall_hits::cpu2.inst 27659 # number of overall hits
1847system.cpu2.icache.overall_hits::total 27659 # number of overall hits
1848system.cpu2.icache.ReadReq_misses::cpu2.inst 815 # number of ReadReq misses
1849system.cpu2.icache.ReadReq_misses::total 815 # number of ReadReq misses
1850system.cpu2.icache.demand_misses::cpu2.inst 815 # number of demand (read+write) misses
1851system.cpu2.icache.demand_misses::total 815 # number of demand (read+write) misses
1852system.cpu2.icache.overall_misses::cpu2.inst 815 # number of overall misses
1853system.cpu2.icache.overall_misses::total 815 # number of overall misses
1854system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12882000 # number of ReadReq miss cycles
1855system.cpu2.icache.ReadReq_miss_latency::total 12882000 # number of ReadReq miss cycles
1856system.cpu2.icache.demand_miss_latency::cpu2.inst 12882000 # number of demand (read+write) miss cycles
1857system.cpu2.icache.demand_miss_latency::total 12882000 # number of demand (read+write) miss cycles
1858system.cpu2.icache.overall_miss_latency::cpu2.inst 12882000 # number of overall miss cycles
1859system.cpu2.icache.overall_miss_latency::total 12882000 # number of overall miss cycles
1860system.cpu2.icache.ReadReq_accesses::cpu2.inst 28474 # number of ReadReq accesses(hits+misses)
1861system.cpu2.icache.ReadReq_accesses::total 28474 # number of ReadReq accesses(hits+misses)
1862system.cpu2.icache.demand_accesses::cpu2.inst 28474 # number of demand (read+write) accesses
1863system.cpu2.icache.demand_accesses::total 28474 # number of demand (read+write) accesses
1864system.cpu2.icache.overall_accesses::cpu2.inst 28474 # number of overall (read+write) accesses
1865system.cpu2.icache.overall_accesses::total 28474 # number of overall (read+write) accesses
1866system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028623 # miss rate for ReadReq accesses
1867system.cpu2.icache.ReadReq_miss_rate::total 0.028623 # miss rate for ReadReq accesses
1868system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028623 # miss rate for demand accesses
1869system.cpu2.icache.demand_miss_rate::total 0.028623 # miss rate for demand accesses
1870system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028623 # miss rate for overall accesses
1871system.cpu2.icache.overall_miss_rate::total 0.028623 # miss rate for overall accesses
1872system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15806.134969 # average ReadReq miss latency
1873system.cpu2.icache.ReadReq_avg_miss_latency::total 15806.134969 # average ReadReq miss latency
1874system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency
1875system.cpu2.icache.demand_avg_miss_latency::total 15806.134969 # average overall miss latency
1876system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency
1877system.cpu2.icache.overall_avg_miss_latency::total 15806.134969 # average overall miss latency

1875system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
1876system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1877system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
1878system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1879system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked
1880system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1878system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
1879system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1880system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
1881system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
1882system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked
1883system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1881system.cpu2.icache.writebacks::writebacks 564 # number of writebacks
1882system.cpu2.icache.writebacks::total 564 # number of writebacks
1883system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 144 # number of ReadReq MSHR hits
1884system.cpu2.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits
1885system.cpu2.icache.demand_mshr_hits::cpu2.inst 144 # number of demand (read+write) MSHR hits
1886system.cpu2.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits
1887system.cpu2.icache.overall_mshr_hits::cpu2.inst 144 # number of overall MSHR hits
1888system.cpu2.icache.overall_mshr_hits::total 144 # number of overall MSHR hits
1889system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 702 # number of ReadReq MSHR misses
1890system.cpu2.icache.ReadReq_mshr_misses::total 702 # number of ReadReq MSHR misses
1891system.cpu2.icache.demand_mshr_misses::cpu2.inst 702 # number of demand (read+write) MSHR misses
1892system.cpu2.icache.demand_mshr_misses::total 702 # number of demand (read+write) MSHR misses
1893system.cpu2.icache.overall_mshr_misses::cpu2.inst 702 # number of overall MSHR misses
1894system.cpu2.icache.overall_mshr_misses::total 702 # number of overall MSHR misses
1895system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10591000 # number of ReadReq MSHR miss cycles
1896system.cpu2.icache.ReadReq_mshr_miss_latency::total 10591000 # number of ReadReq MSHR miss cycles
1897system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10591000 # number of demand (read+write) MSHR miss cycles
1898system.cpu2.icache.demand_mshr_miss_latency::total 10591000 # number of demand (read+write) MSHR miss cycles
1899system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10591000 # number of overall MSHR miss cycles
1900system.cpu2.icache.overall_mshr_miss_latency::total 10591000 # number of overall MSHR miss cycles
1901system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for ReadReq accesses
1902system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.022229 # mshr miss rate for ReadReq accesses
1903system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for demand accesses
1904system.cpu2.icache.demand_mshr_miss_rate::total 0.022229 # mshr miss rate for demand accesses
1905system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for overall accesses
1906system.cpu2.icache.overall_mshr_miss_rate::total 0.022229 # mshr miss rate for overall accesses
1907system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average ReadReq mshr miss latency
1908system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587 # average ReadReq mshr miss latency
1909system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency
1910system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency
1911system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency
1912system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency
1913system.cpu3.branchPred.lookups 65607 # Number of BP lookups
1914system.cpu3.branchPred.condPredicted 57989 # Number of conditional branches predicted
1915system.cpu3.branchPred.condIncorrect 2329 # Number of conditional branches incorrect
1916system.cpu3.branchPred.BTBLookups 57945 # Number of BTB lookups

1884system.cpu2.icache.writebacks::writebacks 551 # number of writebacks
1885system.cpu2.icache.writebacks::total 551 # number of writebacks
1886system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 128 # number of ReadReq MSHR hits
1887system.cpu2.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits
1888system.cpu2.icache.demand_mshr_hits::cpu2.inst 128 # number of demand (read+write) MSHR hits
1889system.cpu2.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits
1890system.cpu2.icache.overall_mshr_hits::cpu2.inst 128 # number of overall MSHR hits
1891system.cpu2.icache.overall_mshr_hits::total 128 # number of overall MSHR hits
1892system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 687 # number of ReadReq MSHR misses
1893system.cpu2.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses
1894system.cpu2.icache.demand_mshr_misses::cpu2.inst 687 # number of demand (read+write) MSHR misses
1895system.cpu2.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses
1896system.cpu2.icache.overall_mshr_misses::cpu2.inst 687 # number of overall MSHR misses
1897system.cpu2.icache.overall_mshr_misses::total 687 # number of overall MSHR misses
1898system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10903000 # number of ReadReq MSHR miss cycles
1899system.cpu2.icache.ReadReq_mshr_miss_latency::total 10903000 # number of ReadReq MSHR miss cycles
1900system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10903000 # number of demand (read+write) MSHR miss cycles
1901system.cpu2.icache.demand_mshr_miss_latency::total 10903000 # number of demand (read+write) MSHR miss cycles
1902system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10903000 # number of overall MSHR miss cycles
1903system.cpu2.icache.overall_mshr_miss_latency::total 10903000 # number of overall MSHR miss cycles
1904system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for ReadReq accesses
1905system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses
1906system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for demand accesses
1907system.cpu2.icache.demand_mshr_miss_rate::total 0.024127 # mshr miss rate for demand accesses
1908system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for overall accesses
1909system.cpu2.icache.overall_mshr_miss_rate::total 0.024127 # mshr miss rate for overall accesses
1910system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average ReadReq mshr miss latency
1911system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15870.451237 # average ReadReq mshr miss latency
1912system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency
1913system.cpu2.icache.demand_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency
1914system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency
1915system.cpu2.icache.overall_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency
1916system.cpu3.branchPred.lookups 64271 # Number of BP lookups
1917system.cpu3.branchPred.condPredicted 56758 # Number of conditional branches predicted
1918system.cpu3.branchPred.condIncorrect 2271 # Number of conditional branches incorrect
1919system.cpu3.branchPred.BTBLookups 55794 # Number of BTB lookups

1917system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
1918system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1919system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1920system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
1921system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1922system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1920system.cpu3.branchPred.usedRAS 1972 # Number of times the RAS was used to get a target.

1923system.cpu3.branchPred.usedRAS 1884 # Number of times the RAS was used to get a target.

1921system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1924system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1922system.cpu3.branchPred.indirectLookups 57945 # Number of indirect predictor lookups.
1923system.cpu3.branchPred.indirectHits 47394 # Number of indirect target hits.
1924system.cpu3.branchPred.indirectMisses 10551 # Number of indirect misses.
1925system.cpu3.branchPredindirectMispredicted 1239 # Number of mispredicted indirect branches.
1926system.cpu3.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states
1927system.cpu3.numCycles 191064 # number of cpu cycles simulated

1925system.cpu3.branchPred.indirectLookups 55794 # Number of indirect predictor lookups.
1926system.cpu3.branchPred.indirectHits 46245 # Number of indirect target hits.
1927system.cpu3.branchPred.indirectMisses 9549 # Number of indirect misses.
1928system.cpu3.branchPredindirectMispredicted 1200 # Number of mispredicted indirect branches.
1929system.cpu3.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states
1930system.cpu3.numCycles 194168 # number of cpu cycles simulated

1928system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1929system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed

1931system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1932system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed

1930system.cpu3.fetch.icacheStallCycles 38959 # Number of cycles fetch is stalled on an Icache miss
1931system.cpu3.fetch.Insts 355945 # Number of instructions fetch has processed
1932system.cpu3.fetch.Branches 65607 # Number of branches that fetch encountered
1933system.cpu3.fetch.predictedBranches 49366 # Number of branches that fetch has predicted taken
1934system.cpu3.fetch.Cycles 146283 # Number of cycles fetch has run and was not squashing or blocked
1935system.cpu3.fetch.SquashCycles 4811 # Number of cycles fetch has spent squashing

1933system.cpu3.fetch.icacheStallCycles 40168 # Number of cycles fetch is stalled on an Icache miss
1934system.cpu3.fetch.Insts 346607 # Number of instructions fetch has processed
1935system.cpu3.fetch.Branches 64271 # Number of branches that fetch encountered
1936system.cpu3.fetch.predictedBranches 48129 # Number of branches that fetch has predicted taken
1937system.cpu3.fetch.Cycles 146969 # Number of cycles fetch has run and was not squashing or blocked
1938system.cpu3.fetch.SquashCycles 4697 # Number of cycles fetch has spent squashing

1936system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1937system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1939system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1940system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1938system.cpu3.fetch.PendingTrapStallCycles 1648 # Number of stall cycles due to pending traps
1939system.cpu3.fetch.CacheLines 27872 # Number of cache lines fetched
1940system.cpu3.fetch.IcacheSquashes 954 # Number of outstanding Icache misses that were squashed
1941system.cpu3.fetch.rateDist::samples 189308 # Number of instructions fetched each cycle (Total)
1942system.cpu3.fetch.rateDist::mean 1.880243 # Number of instructions fetched each cycle (Total)
1943system.cpu3.fetch.rateDist::stdev 2.334212 # Number of instructions fetched each cycle (Total)

1941system.cpu3.fetch.PendingTrapStallCycles 1673 # Number of stall cycles due to pending traps
1942system.cpu3.fetch.CacheLines 29039 # Number of cache lines fetched
1943system.cpu3.fetch.IcacheSquashes 911 # Number of outstanding Icache misses that were squashed
1944system.cpu3.fetch.rateDist::samples 191171 # Number of instructions fetched each cycle (Total)
1945system.cpu3.fetch.rateDist::mean 1.813073 # Number of instructions fetched each cycle (Total)
1946system.cpu3.fetch.rateDist::stdev 2.312592 # Number of instructions fetched each cycle (Total)

1944system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1947system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1945system.cpu3.fetch.rateDist::0 70601 37.29% 37.29% # Number of instructions fetched each cycle (Total)
1946system.cpu3.fetch.rateDist::1 58551 30.93% 68.22% # Number of instructions fetched each cycle (Total)
1947system.cpu3.fetch.rateDist::2 8289 4.38% 72.60% # Number of instructions fetched each cycle (Total)
1948system.cpu3.fetch.rateDist::3 3543 1.87% 74.47% # Number of instructions fetched each cycle (Total)
1949system.cpu3.fetch.rateDist::4 620 0.33% 74.80% # Number of instructions fetched each cycle (Total)
1950system.cpu3.fetch.rateDist::5 36795 19.44% 94.24% # Number of instructions fetched each cycle (Total)
1951system.cpu3.fetch.rateDist::6 1123 0.59% 94.83% # Number of instructions fetched each cycle (Total)
1952system.cpu3.fetch.rateDist::7 1294 0.68% 95.51% # Number of instructions fetched each cycle (Total)
1953system.cpu3.fetch.rateDist::8 8492 4.49% 100.00% # Number of instructions fetched each cycle (Total)

1948system.cpu3.fetch.rateDist::0 74400 38.92% 38.92% # Number of instructions fetched each cycle (Total)
1949system.cpu3.fetch.rateDist::1 57993 30.34% 69.25% # Number of instructions fetched each cycle (Total)
1950system.cpu3.fetch.rateDist::2 8887 4.65% 73.90% # Number of instructions fetched each cycle (Total)
1951system.cpu3.fetch.rateDist::3 3426 1.79% 75.69% # Number of instructions fetched each cycle (Total)
1952system.cpu3.fetch.rateDist::4 613 0.32% 76.02% # Number of instructions fetched each cycle (Total)
1953system.cpu3.fetch.rateDist::5 35081 18.35% 94.37% # Number of instructions fetched each cycle (Total)
1954system.cpu3.fetch.rateDist::6 1105 0.58% 94.94% # Number of instructions fetched each cycle (Total)
1955system.cpu3.fetch.rateDist::7 1253 0.66% 95.60% # Number of instructions fetched each cycle (Total)
1956system.cpu3.fetch.rateDist::8 8413 4.40% 100.00% # Number of instructions fetched each cycle (Total)

1954system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1955system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1956system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1957system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1958system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1959system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1957system.cpu3.fetch.rateDist::total 189308 # Number of instructions fetched each cycle (Total)
1958system.cpu3.fetch.branchRate 0.343377 # Number of branch fetches per cycle
1959system.cpu3.fetch.rate 1.862962 # Number of inst fetches per cycle
1960system.cpu3.decode.IdleCycles 22011 # Number of cycles decode is idle
1961system.cpu3.decode.BlockedCycles 70196 # Number of cycles decode is blocked
1962system.cpu3.decode.RunCycles 90137 # Number of cycles decode is running
1963system.cpu3.decode.UnblockCycles 4549 # Number of cycles decode is unblocking
1964system.cpu3.decode.SquashCycles 2405 # Number of cycles decode is squashing
1965system.cpu3.decode.DecodedInsts 325577 # Number of instructions handled by decode
1966system.cpu3.rename.SquashCycles 2405 # Number of cycles rename is squashing
1967system.cpu3.rename.IdleCycles 23040 # Number of cycles rename is idle
1968system.cpu3.rename.BlockCycles 34162 # Number of cycles rename is blocking
1969system.cpu3.rename.serializeStallCycles 13425 # count of cycles rename stalled for serializing inst
1970system.cpu3.rename.RunCycles 90919 # Number of cycles rename is running
1971system.cpu3.rename.UnblockCycles 25347 # Number of cycles rename is unblocking
1972system.cpu3.rename.RenamedInsts 318974 # Number of instructions processed by rename
1973system.cpu3.rename.IQFullEvents 21885 # Number of times rename has blocked due to IQ full
1974system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
1975system.cpu3.rename.RenamedOperands 222576 # Number of destination operands rename has renamed
1976system.cpu3.rename.RenameLookups 605183 # Number of register rename lookups that rename has made
1977system.cpu3.rename.int_rename_lookups 471258 # Number of integer rename lookups
1978system.cpu3.rename.fp_rename_lookups 38 # Number of floating rename lookups
1979system.cpu3.rename.CommittedMaps 194403 # Number of HB maps that are committed
1980system.cpu3.rename.UndoneMaps 28173 # Number of HB maps that are undone due to squashing
1981system.cpu3.rename.serializingInsts 1623 # count of serializing insts renamed
1982system.cpu3.rename.tempSerializingInsts 1757 # count of temporary serializing insts renamed
1983system.cpu3.rename.skidInsts 30798 # count of insts added to the skid buffer
1984system.cpu3.memDep0.insertedLoads 87479 # Number of loads inserted to the mem dependence unit.
1985system.cpu3.memDep0.insertedStores 41118 # Number of stores inserted to the mem dependence unit.
1986system.cpu3.memDep0.conflictingLoads 41854 # Number of conflicting loads.
1987system.cpu3.memDep0.conflictingStores 34728 # Number of conflicting stores.
1988system.cpu3.iq.iqInstsAdded 259350 # Number of instructions added to the IQ (excludes non-spec)
1989system.cpu3.iq.iqNonSpecInstsAdded 8662 # Number of non-speculative instructions added to the IQ
1990system.cpu3.iq.iqInstsIssued 260097 # Number of instructions issued
1991system.cpu3.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued
1992system.cpu3.iq.iqSquashedInstsExamined 24362 # Number of squashed instructions iterated over during squash; mainly for profiling
1993system.cpu3.iq.iqSquashedOperandsExamined 19655 # Number of squashed operands that are examined and possibly removed from graph
1994system.cpu3.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed
1995system.cpu3.iq.issued_per_cycle::samples 189308 # Number of insts issued each cycle
1996system.cpu3.iq.issued_per_cycle::mean 1.373936 # Number of insts issued each cycle
1997system.cpu3.iq.issued_per_cycle::stdev 1.388628 # Number of insts issued each cycle

1960system.cpu3.fetch.rateDist::total 191171 # Number of instructions fetched each cycle (Total)
1961system.cpu3.fetch.branchRate 0.331007 # Number of branch fetches per cycle
1962system.cpu3.fetch.rate 1.785088 # Number of inst fetches per cycle
1963system.cpu3.decode.IdleCycles 21895 # Number of cycles decode is idle
1964system.cpu3.decode.BlockedCycles 75534 # Number of cycles decode is blocked
1965system.cpu3.decode.RunCycles 86562 # Number of cycles decode is running
1966system.cpu3.decode.UnblockCycles 4822 # Number of cycles decode is unblocking
1967system.cpu3.decode.SquashCycles 2348 # Number of cycles decode is squashing
1968system.cpu3.decode.DecodedInsts 316867 # Number of instructions handled by decode
1969system.cpu3.rename.SquashCycles 2348 # Number of cycles rename is squashing
1970system.cpu3.rename.IdleCycles 22878 # Number of cycles rename is idle
1971system.cpu3.rename.BlockCycles 37474 # Number of cycles rename is blocking
1972system.cpu3.rename.serializeStallCycles 13003 # count of cycles rename stalled for serializing inst
1973system.cpu3.rename.RunCycles 86814 # Number of cycles rename is running
1974system.cpu3.rename.UnblockCycles 28644 # Number of cycles rename is unblocking
1975system.cpu3.rename.RenamedInsts 310654 # Number of instructions processed by rename
1976system.cpu3.rename.IQFullEvents 24310 # Number of times rename has blocked due to IQ full
1977system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
1978system.cpu3.rename.RenamedOperands 215725 # Number of destination operands rename has renamed
1979system.cpu3.rename.RenameLookups 585696 # Number of register rename lookups that rename has made
1980system.cpu3.rename.int_rename_lookups 456528 # Number of integer rename lookups
1981system.cpu3.rename.fp_rename_lookups 32 # Number of floating rename lookups
1982system.cpu3.rename.CommittedMaps 188410 # Number of HB maps that are committed
1983system.cpu3.rename.UndoneMaps 27315 # Number of HB maps that are undone due to squashing
1984system.cpu3.rename.serializingInsts 1561 # count of serializing insts renamed
1985system.cpu3.rename.tempSerializingInsts 1705 # count of temporary serializing insts renamed
1986system.cpu3.rename.skidInsts 33909 # count of insts added to the skid buffer
1987system.cpu3.memDep0.insertedLoads 84645 # Number of loads inserted to the mem dependence unit.
1988system.cpu3.memDep0.insertedStores 39227 # Number of stores inserted to the mem dependence unit.
1989system.cpu3.memDep0.conflictingLoads 40799 # Number of conflicting loads.
1990system.cpu3.memDep0.conflictingStores 33015 # Number of conflicting stores.
1991system.cpu3.iq.iqInstsAdded 251387 # Number of instructions added to the IQ (excludes non-spec)
1992system.cpu3.iq.iqNonSpecInstsAdded 9227 # Number of non-speculative instructions added to the IQ
1993system.cpu3.iq.iqInstsIssued 253114 # Number of instructions issued
1994system.cpu3.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
1995system.cpu3.iq.iqSquashedInstsExamined 23294 # Number of squashed instructions iterated over during squash; mainly for profiling
1996system.cpu3.iq.iqSquashedOperandsExamined 18618 # Number of squashed operands that are examined and possibly removed from graph
1997system.cpu3.iq.iqSquashedNonSpecRemoved 1117 # Number of squashed non-spec instructions that were removed
1998system.cpu3.iq.issued_per_cycle::samples 191171 # Number of insts issued each cycle
1999system.cpu3.iq.issued_per_cycle::mean 1.324019 # Number of insts issued each cycle
2000system.cpu3.iq.issued_per_cycle::stdev 1.377234 # Number of insts issued each cycle

1998system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

2001system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1999system.cpu3.iq.issued_per_cycle::0 75622 39.95% 39.95% # Number of insts issued each cycle
2000system.cpu3.iq.issued_per_cycle::1 27531 14.54% 54.49% # Number of insts issued each cycle
2001system.cpu3.iq.issued_per_cycle::2 39579 20.91% 75.40% # Number of insts issued each cycle
2002system.cpu3.iq.issued_per_cycle::3 39359 20.79% 96.19% # Number of insts issued each cycle
2003system.cpu3.iq.issued_per_cycle::4 3671 1.94% 98.13% # Number of insts issued each cycle
2004system.cpu3.iq.issued_per_cycle::5 1727 0.91% 99.04% # Number of insts issued each cycle
2005system.cpu3.iq.issued_per_cycle::6 1045 0.55% 99.59% # Number of insts issued each cycle
2006system.cpu3.iq.issued_per_cycle::7 450 0.24% 99.83% # Number of insts issued each cycle
2007system.cpu3.iq.issued_per_cycle::8 324 0.17% 100.00% # Number of insts issued each cycle

2002system.cpu3.iq.issued_per_cycle::0 78925 41.29% 41.29% # Number of insts issued each cycle
2003system.cpu3.iq.issued_per_cycle::1 29485 15.42% 56.71% # Number of insts issued each cycle
2004system.cpu3.iq.issued_per_cycle::2 37890 19.82% 76.53% # Number of insts issued each cycle
2005system.cpu3.iq.issued_per_cycle::3 37772 19.76% 96.29% # Number of insts issued each cycle
2006system.cpu3.iq.issued_per_cycle::4 3652 1.91% 98.20% # Number of insts issued each cycle
2007system.cpu3.iq.issued_per_cycle::5 1740 0.91% 99.11% # Number of insts issued each cycle
2008system.cpu3.iq.issued_per_cycle::6 1013 0.53% 99.64% # Number of insts issued each cycle
2009system.cpu3.iq.issued_per_cycle::7 405 0.21% 99.85% # Number of insts issued each cycle
2010system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00% # Number of insts issued each cycle

2008system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2009system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2010system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

2011system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2012system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2013system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

2011system.cpu3.iq.issued_per_cycle::total 189308 # Number of insts issued each cycle

2014system.cpu3.iq.issued_per_cycle::total 191171 # Number of insts issued each cycle

2012system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

2015system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

2013system.cpu3.iq.fu_full::IntAlu 198 41.42% 41.42% # attempts to use FU when none available
2014system.cpu3.iq.fu_full::IntMult 0 0.00% 41.42% # attempts to use FU when none available
2015system.cpu3.iq.fu_full::IntDiv 0 0.00% 41.42% # attempts to use FU when none available
2016system.cpu3.iq.fu_full::FloatAdd 0 0.00% 41.42% # attempts to use FU when none available
2017system.cpu3.iq.fu_full::FloatCmp 0 0.00% 41.42% # attempts to use FU when none available
2018system.cpu3.iq.fu_full::FloatCvt 0 0.00% 41.42% # attempts to use FU when none available
2019system.cpu3.iq.fu_full::FloatMult 0 0.00% 41.42% # attempts to use FU when none available
2020system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available
2021system.cpu3.iq.fu_full::FloatDiv 0 0.00% 41.42% # attempts to use FU when none available
2022system.cpu3.iq.fu_full::FloatMisc 0 0.00% 41.42% # attempts to use FU when none available
2023system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 41.42% # attempts to use FU when none available
2024system.cpu3.iq.fu_full::SimdAdd 0 0.00% 41.42% # attempts to use FU when none available
2025system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 41.42% # attempts to use FU when none available
2026system.cpu3.iq.fu_full::SimdAlu 0 0.00% 41.42% # attempts to use FU when none available
2027system.cpu3.iq.fu_full::SimdCmp 0 0.00% 41.42% # attempts to use FU when none available
2028system.cpu3.iq.fu_full::SimdCvt 0 0.00% 41.42% # attempts to use FU when none available
2029system.cpu3.iq.fu_full::SimdMisc 0 0.00% 41.42% # attempts to use FU when none available
2030system.cpu3.iq.fu_full::SimdMult 0 0.00% 41.42% # attempts to use FU when none available
2031system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 41.42% # attempts to use FU when none available
2032system.cpu3.iq.fu_full::SimdShift 0 0.00% 41.42% # attempts to use FU when none available
2033system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 41.42% # attempts to use FU when none available
2034system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 41.42% # attempts to use FU when none available
2035system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 41.42% # attempts to use FU when none available
2036system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 41.42% # attempts to use FU when none available
2037system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 41.42% # attempts to use FU when none available
2038system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 41.42% # attempts to use FU when none available
2039system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 41.42% # attempts to use FU when none available
2040system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 41.42% # attempts to use FU when none available
2041system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 41.42% # attempts to use FU when none available
2042system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available
2043system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 41.42% # attempts to use FU when none available
2044system.cpu3.iq.fu_full::MemRead 48 10.04% 51.46% # attempts to use FU when none available
2045system.cpu3.iq.fu_full::MemWrite 232 48.54% 100.00% # attempts to use FU when none available

2016system.cpu3.iq.fu_full::IntAlu 186 40.88% 40.88% # attempts to use FU when none available
2017system.cpu3.iq.fu_full::IntMult 0 0.00% 40.88% # attempts to use FU when none available
2018system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.88% # attempts to use FU when none available
2019system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.88% # attempts to use FU when none available
2020system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.88% # attempts to use FU when none available
2021system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.88% # attempts to use FU when none available
2022system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.88% # attempts to use FU when none available
2023system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available
2024system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.88% # attempts to use FU when none available
2025system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.88% # attempts to use FU when none available
2026system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.88% # attempts to use FU when none available
2027system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.88% # attempts to use FU when none available
2028system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.88% # attempts to use FU when none available
2029system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.88% # attempts to use FU when none available
2030system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.88% # attempts to use FU when none available
2031system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.88% # attempts to use FU when none available
2032system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.88% # attempts to use FU when none available
2033system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.88% # attempts to use FU when none available
2034system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.88% # attempts to use FU when none available
2035system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.88% # attempts to use FU when none available
2036system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.88% # attempts to use FU when none available
2037system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.88% # attempts to use FU when none available
2038system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.88% # attempts to use FU when none available
2039system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.88% # attempts to use FU when none available
2040system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.88% # attempts to use FU when none available
2041system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.88% # attempts to use FU when none available
2042system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.88% # attempts to use FU when none available
2043system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.88% # attempts to use FU when none available
2044system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.88% # attempts to use FU when none available
2045system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available
2046system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.88% # attempts to use FU when none available
2047system.cpu3.iq.fu_full::MemRead 39 8.57% 49.45% # attempts to use FU when none available
2048system.cpu3.iq.fu_full::MemWrite 230 50.55% 100.00% # attempts to use FU when none available

2046system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
2047system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
2048system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2049system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2050system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

2049system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
2050system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
2051system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2052system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2053system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

2051system.cpu3.iq.FU_type_0::IntAlu 126919 48.80% 48.80% # Type of FU issued
2052system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued
2053system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued
2054system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued
2055system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued
2056system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued
2057system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued
2058system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued
2059system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued
2060system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued
2061system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued
2062system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued
2063system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued
2064system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued
2065system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued
2066system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued
2067system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued
2068system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued
2069system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued
2070system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued
2071system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued
2072system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued
2073system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued
2074system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued
2075system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued
2076system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued
2077system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued
2078system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued
2079system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued
2080system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued
2081system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued
2082system.cpu3.iq.FU_type_0::MemRead 93130 35.81% 84.60% # Type of FU issued
2083system.cpu3.iq.FU_type_0::MemWrite 40048 15.40% 100.00% # Type of FU issued

2054system.cpu3.iq.FU_type_0::IntAlu 123835 48.92% 48.92% # Type of FU issued
2055system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued
2056system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued
2057system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued
2058system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued
2059system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued
2060system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued
2061system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.92% # Type of FU issued
2062system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued
2063system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.92% # Type of FU issued
2064system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued
2065system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued
2066system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued
2067system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued
2068system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued
2069system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued
2070system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued
2071system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued
2072system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued
2073system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued
2074system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued
2075system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued
2076system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued
2077system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued
2078system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued
2079system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued
2080system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued
2081system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued
2082system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued
2083system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued
2084system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued
2085system.cpu3.iq.FU_type_0::MemRead 91015 35.96% 84.88% # Type of FU issued
2086system.cpu3.iq.FU_type_0::MemWrite 38264 15.12% 100.00% # Type of FU issued

2084system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
2085system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
2086system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2087system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

2087system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
2088system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
2089system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2090system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

2088system.cpu3.iq.FU_type_0::total 260097 # Type of FU issued
2089system.cpu3.iq.rate 1.361308 # Inst issue rate
2090system.cpu3.iq.fu_busy_cnt 478 # FU busy when requested
2091system.cpu3.iq.fu_busy_rate 0.001838 # FU busy rate (busy events/executed inst)
2092system.cpu3.iq.int_inst_queue_reads 710080 # Number of integer instruction queue reads
2093system.cpu3.iq.int_inst_queue_writes 292336 # Number of integer instruction queue writes
2094system.cpu3.iq.int_inst_queue_wakeup_accesses 256163 # Number of integer instruction queue wakeup accesses

2091system.cpu3.iq.FU_type_0::total 253114 # Type of FU issued
2092system.cpu3.iq.rate 1.303582 # Inst issue rate
2093system.cpu3.iq.fu_busy_cnt 455 # FU busy when requested
2094system.cpu3.iq.fu_busy_rate 0.001798 # FU busy rate (busy events/executed inst)
2095system.cpu3.iq.int_inst_queue_reads 697933 # Number of integer instruction queue reads
2096system.cpu3.iq.int_inst_queue_writes 283879 # Number of integer instruction queue writes
2097system.cpu3.iq.int_inst_queue_wakeup_accesses 249400 # Number of integer instruction queue wakeup accesses

2095system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

2098system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

2096system.cpu3.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes

2099system.cpu3.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes

2097system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

2100system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

2098system.cpu3.iq.int_alu_accesses 260575 # Number of integer alu accesses

2101system.cpu3.iq.int_alu_accesses 253569 # Number of integer alu accesses

2099system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses

2102system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses

2100system.cpu3.iew.lsq.thread0.forwLoads 34620 # Number of loads that had data forwarded from stores

2103system.cpu3.iew.lsq.thread0.forwLoads 32960 # Number of loads that had data forwarded from stores

2101system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

2104system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

2102system.cpu3.iew.lsq.thread0.squashedLoads 4474 # Number of loads squashed

2105system.cpu3.iew.lsq.thread0.squashedLoads 4297 # Number of loads squashed

2103system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed

2106system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed

2104system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
2105system.cpu3.iew.lsq.thread0.squashedStores 2718 # Number of stores squashed

2107system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
2108system.cpu3.iew.lsq.thread0.squashedStores 2496 # Number of stores squashed

2106system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2107system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2108system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2109system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2110system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle

2109system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2110system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2111system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2112system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2113system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle

2111system.cpu3.iew.iewSquashCycles 2405 # Number of cycles IEW is squashing
2112system.cpu3.iew.iewBlockCycles 9114 # Number of cycles IEW is blocking
2113system.cpu3.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
2114system.cpu3.iew.iewDispatchedInsts 311067 # Number of instructions dispatched to IQ
2115system.cpu3.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch
2116system.cpu3.iew.iewDispLoadInsts 87479 # Number of dispatched load instructions
2117system.cpu3.iew.iewDispStoreInsts 41118 # Number of dispatched store instructions
2118system.cpu3.iew.iewDispNonSpecInsts 1508 # Number of dispatched non-speculative instructions
2119system.cpu3.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall

2114system.cpu3.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing
2115system.cpu3.iew.iewBlockCycles 9647 # Number of cycles IEW is blocking
2116system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
2117system.cpu3.iew.iewDispatchedInsts 302650 # Number of instructions dispatched to IQ
2118system.cpu3.iew.iewDispSquashedInsts 426 # Number of squashed instructions skipped by dispatch
2119system.cpu3.iew.iewDispLoadInsts 84645 # Number of dispatched load instructions
2120system.cpu3.iew.iewDispStoreInsts 39227 # Number of dispatched store instructions
2121system.cpu3.iew.iewDispNonSpecInsts 1449 # Number of dispatched non-speculative instructions
2122system.cpu3.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall

2120system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

2123system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

2121system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations
2122system.cpu3.iew.predictedTakenIncorrect 450 # Number of branches that were predicted taken incorrectly
2123system.cpu3.iew.predictedNotTakenIncorrect 2479 # Number of branches that were predicted not taken incorrectly
2124system.cpu3.iew.branchMispredicts 2929 # Number of branch mispredicts detected at execute
2125system.cpu3.iew.iewExecutedInsts 257518 # Number of executed instructions
2126system.cpu3.iew.iewExecLoadInsts 85797 # Number of load instructions executed
2127system.cpu3.iew.iewExecSquashedInsts 2579 # Number of squashed instructions skipped in execute

2124system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations
2125system.cpu3.iew.predictedTakenIncorrect 408 # Number of branches that were predicted taken incorrectly
2126system.cpu3.iew.predictedNotTakenIncorrect 2445 # Number of branches that were predicted not taken incorrectly
2127system.cpu3.iew.branchMispredicts 2853 # Number of branch mispredicts detected at execute
2128system.cpu3.iew.iewExecutedInsts 250680 # Number of executed instructions
2129system.cpu3.iew.iewExecLoadInsts 83030 # Number of load instructions executed
2130system.cpu3.iew.iewExecSquashedInsts 2434 # Number of squashed instructions skipped in execute

2128system.cpu3.iew.exec_swp 0 # number of swp insts executed

2131system.cpu3.iew.exec_swp 0 # number of swp insts executed

2129system.cpu3.iew.exec_nop 43055 # number of nop insts executed
2130system.cpu3.iew.exec_refs 125534 # number of memory reference insts executed
2131system.cpu3.iew.exec_branches 53219 # Number of branches executed
2132system.cpu3.iew.exec_stores 39737 # Number of stores executed
2133system.cpu3.iew.exec_rate 1.347810 # Inst execution rate
2134system.cpu3.iew.wb_sent 256666 # cumulative count of insts sent to commit
2135system.cpu3.iew.wb_count 256163 # cumulative count of insts written-back
2136system.cpu3.iew.wb_producers 143359 # num instructions producing a value
2137system.cpu3.iew.wb_consumers 150866 # num instructions consuming a value
2138system.cpu3.iew.wb_rate 1.340718 # insts written-back per cycle
2139system.cpu3.iew.wb_fanout 0.950241 # average fanout of values written-back
2140system.cpu3.commit.commitSquashedInsts 25509 # The number of squashed insts skipped by commit
2141system.cpu3.commit.commitNonSpecStalls 7449 # The number of times commit has been forced to stall to communicate backwards
2142system.cpu3.commit.branchMispredicts 2329 # The number of times a branch was mispredicted
2143system.cpu3.commit.committed_per_cycle::samples 184454 # Number of insts commited each cycle
2144system.cpu3.commit.committed_per_cycle::mean 1.547985 # Number of insts commited each cycle
2145system.cpu3.commit.committed_per_cycle::stdev 2.017686 # Number of insts commited each cycle

2132system.cpu3.iew.exec_nop 42036 # number of nop insts executed
2133system.cpu3.iew.exec_refs 121032 # number of memory reference insts executed
2134system.cpu3.iew.exec_branches 52206 # Number of branches executed
2135system.cpu3.iew.exec_stores 38002 # Number of stores executed
2136system.cpu3.iew.exec_rate 1.291047 # Inst execution rate
2137system.cpu3.iew.wb_sent 249859 # cumulative count of insts sent to commit
2138system.cpu3.iew.wb_count 249400 # cumulative count of insts written-back
2139system.cpu3.iew.wb_producers 138774 # num instructions producing a value
2140system.cpu3.iew.wb_consumers 146167 # num instructions consuming a value
2141system.cpu3.iew.wb_rate 1.284455 # insts written-back per cycle
2142system.cpu3.iew.wb_fanout 0.949421 # average fanout of values written-back
2143system.cpu3.commit.commitSquashedInsts 24422 # The number of squashed insts skipped by commit
2144system.cpu3.commit.commitNonSpecStalls 8110 # The number of times commit has been forced to stall to communicate backwards
2145system.cpu3.commit.branchMispredicts 2271 # The number of times a branch was mispredicted
2146system.cpu3.commit.committed_per_cycle::samples 186514 # Number of insts commited each cycle
2147system.cpu3.commit.committed_per_cycle::mean 1.491588 # Number of insts commited each cycle
2148system.cpu3.commit.committed_per_cycle::stdev 1.991895 # Number of insts commited each cycle

2146system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2149system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2147system.cpu3.commit.committed_per_cycle::0 82386 44.66% 44.66% # Number of insts commited each cycle
2148system.cpu3.commit.committed_per_cycle::1 49463 26.82% 71.48% # Number of insts commited each cycle
2149system.cpu3.commit.committed_per_cycle::2 5369 2.91% 74.39% # Number of insts commited each cycle
2150system.cpu3.commit.committed_per_cycle::3 8071 4.38% 78.77% # Number of insts commited each cycle
2151system.cpu3.commit.committed_per_cycle::4 1252 0.68% 79.45% # Number of insts commited each cycle
2152system.cpu3.commit.committed_per_cycle::5 34869 18.90% 98.35% # Number of insts commited each cycle
2153system.cpu3.commit.committed_per_cycle::6 786 0.43% 98.78% # Number of insts commited each cycle
2154system.cpu3.commit.committed_per_cycle::7 1015 0.55% 99.33% # Number of insts commited each cycle
2155system.cpu3.commit.committed_per_cycle::8 1243 0.67% 100.00% # Number of insts commited each cycle

2150system.cpu3.commit.committed_per_cycle::0 86424 46.34% 46.34% # Number of insts commited each cycle
2151system.cpu3.commit.committed_per_cycle::1 48393 25.95% 72.28% # Number of insts commited each cycle
2152system.cpu3.commit.committed_per_cycle::2 5395 2.89% 75.18% # Number of insts commited each cycle
2153system.cpu3.commit.committed_per_cycle::3 8809 4.72% 79.90% # Number of insts commited each cycle
2154system.cpu3.commit.committed_per_cycle::4 1333 0.71% 80.61% # Number of insts commited each cycle
2155system.cpu3.commit.committed_per_cycle::5 33156 17.78% 98.39% # Number of insts commited each cycle
2156system.cpu3.commit.committed_per_cycle::6 761 0.41% 98.80% # Number of insts commited each cycle
2157system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.35% # Number of insts commited each cycle
2158system.cpu3.commit.committed_per_cycle::8 1213 0.65% 100.00% # Number of insts commited each cycle

2156system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2157system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2158system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2159system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2160system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2161system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2159system.cpu3.commit.committed_per_cycle::total 184454 # Number of insts commited each cycle
2160system.cpu3.commit.committedInsts 285532 # Number of instructions committed
2161system.cpu3.commit.committedOps 285532 # Number of ops (including micro ops) committed

2162system.cpu3.commit.committed_per_cycle::total 186514 # Number of insts commited each cycle
2163system.cpu3.commit.committedInsts 278202 # Number of instructions committed
2164system.cpu3.commit.committedOps 278202 # Number of ops (including micro ops) committed

2162system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed

2165system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed

2163system.cpu3.commit.refs 121405 # Number of memory references committed
2164system.cpu3.commit.loads 83005 # Number of loads committed
2165system.cpu3.commit.membars 6731 # Number of memory barriers committed
2166system.cpu3.commit.branches 51096 # Number of branches committed

2166system.cpu3.commit.refs 117079 # Number of memory references committed
2167system.cpu3.commit.loads 80348 # Number of loads committed
2168system.cpu3.commit.membars 7398 # Number of memory barriers committed
2169system.cpu3.commit.branches 50090 # Number of branches committed

2167system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.

2170system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.

2168system.cpu3.commit.int_insts 194617 # Number of committed integer instructions.

2171system.cpu3.commit.int_insts 189293 # Number of committed integer instructions.

2169system.cpu3.commit.function_calls 322 # Number of function calls committed.

2172system.cpu3.commit.function_calls 322 # Number of function calls committed.

2170system.cpu3.commit.op_class_0::No_OpClass 41882 14.67% 14.67% # Class of committed instruction
2171system.cpu3.commit.op_class_0::IntAlu 115514 40.46% 55.12% # Class of committed instruction
2172system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.12% # Class of committed instruction
2173system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.12% # Class of committed instruction
2174system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.12% # Class of committed instruction
2175system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.12% # Class of committed instruction
2176system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.12% # Class of committed instruction
2177system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.12% # Class of committed instruction
2178system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.12% # Class of committed instruction
2179system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.12% # Class of committed instruction
2180system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.12% # Class of committed instruction
2181system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.12% # Class of committed instruction
2182system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.12% # Class of committed instruction
2183system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.12% # Class of committed instruction
2184system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.12% # Class of committed instruction
2185system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.12% # Class of committed instruction
2186system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.12% # Class of committed instruction
2187system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.12% # Class of committed instruction
2188system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.12% # Class of committed instruction
2189system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.12% # Class of committed instruction
2190system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.12% # Class of committed instruction
2191system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.12% # Class of committed instruction
2192system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.12% # Class of committed instruction
2193system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.12% # Class of committed instruction
2194system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.12% # Class of committed instruction
2195system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.12% # Class of committed instruction
2196system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.12% # Class of committed instruction
2197system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.12% # Class of committed instruction
2198system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.12% # Class of committed instruction
2199system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.12% # Class of committed instruction
2200system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.12% # Class of committed instruction
2201system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.12% # Class of committed instruction
2202system.cpu3.commit.op_class_0::MemRead 89736 31.43% 86.55% # Class of committed instruction
2203system.cpu3.commit.op_class_0::MemWrite 38400 13.45% 100.00% # Class of committed instruction

2173system.cpu3.commit.op_class_0::No_OpClass 40882 14.70% 14.70% # Class of committed instruction
2174system.cpu3.commit.op_class_0::IntAlu 112843 40.56% 55.26% # Class of committed instruction
2175system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.26% # Class of committed instruction
2176system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.26% # Class of committed instruction
2177system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.26% # Class of committed instruction
2178system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.26% # Class of committed instruction
2179system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.26% # Class of committed instruction
2180system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.26% # Class of committed instruction
2181system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.26% # Class of committed instruction
2182system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.26% # Class of committed instruction
2183system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.26% # Class of committed instruction
2184system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.26% # Class of committed instruction
2185system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.26% # Class of committed instruction
2186system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.26% # Class of committed instruction
2187system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.26% # Class of committed instruction
2188system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.26% # Class of committed instruction
2189system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.26% # Class of committed instruction
2190system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.26% # Class of committed instruction
2191system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.26% # Class of committed instruction
2192system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.26% # Class of committed instruction
2193system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.26% # Class of committed instruction
2194system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.26% # Class of committed instruction
2195system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.26% # Class of committed instruction
2196system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.26% # Class of committed instruction
2197system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.26% # Class of committed instruction
2198system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.26% # Class of committed instruction
2199system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.26% # Class of committed instruction
2200system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.26% # Class of committed instruction
2201system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.26% # Class of committed instruction
2202system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.26% # Class of committed instruction
2203system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.26% # Class of committed instruction
2204system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.26% # Class of committed instruction
2205system.cpu3.commit.op_class_0::MemRead 87746 31.54% 86.80% # Class of committed instruction
2206system.cpu3.commit.op_class_0::MemWrite 36731 13.20% 100.00% # Class of committed instruction

2204system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
2205system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
2206system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2207system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2207system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
2208system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
2209system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2210system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2208system.cpu3.commit.op_class_0::total 285532 # Class of committed instruction
2209system.cpu3.commit.bw_lim_events 1243 # number cycles where commit BW limit reached
2210system.cpu3.rob.rob_reads 493666 # The number of ROB reads
2211system.cpu3.rob.rob_writes 626988 # The number of ROB writes
2212system.cpu3.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself
2213system.cpu3.idleCycles 1756 # Total number of cycles that the CPU has spent unscheduled due to idling
2214system.cpu3.quiesceCycles 50157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2215system.cpu3.committedInsts 236919 # Number of Instructions Simulated
2216system.cpu3.committedOps 236919 # Number of Ops (including micro ops) Simulated
2217system.cpu3.cpi 0.806453 # CPI: Cycles Per Instruction
2218system.cpu3.cpi_total 0.806453 # CPI: Total CPI of All Threads
2219system.cpu3.ipc 1.239998 # IPC: Instructions Per Cycle
2220system.cpu3.ipc_total 1.239998 # IPC: Total IPC of All Threads
2221system.cpu3.int_regfile_reads 440410 # number of integer regfile reads
2222system.cpu3.int_regfile_writes 205469 # number of integer regfile writes

2211system.cpu3.commit.op_class_0::total 278202 # Class of committed instruction
2212system.cpu3.commit.bw_lim_events 1213 # number cycles where commit BW limit reached
2213system.cpu3.rob.rob_reads 487339 # The number of ROB reads
2214system.cpu3.rob.rob_writes 609957 # The number of ROB writes
2215system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself
2216system.cpu3.idleCycles 2997 # Total number of cycles that the CPU has spent unscheduled due to idling
2217system.cpu3.quiesceCycles 50169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2218system.cpu3.committedInsts 229922 # Number of Instructions Simulated
2219system.cpu3.committedOps 229922 # Number of Ops (including micro ops) Simulated
2220system.cpu3.cpi 0.844495 # CPI: Cycles Per Instruction
2221system.cpu3.cpi_total 0.844495 # CPI: Total CPI of All Threads
2222system.cpu3.ipc 1.184140 # IPC: Instructions Per Cycle
2223system.cpu3.ipc_total 1.184140 # IPC: Total IPC of All Threads
2224system.cpu3.int_regfile_reads 426644 # number of integer regfile reads
2225system.cpu3.int_regfile_writes 199085 # number of integer regfile writes

2223system.cpu3.fp_regfile_writes 64 # number of floating regfile writes

2226system.cpu3.fp_regfile_writes 64 # number of floating regfile writes

2224system.cpu3.misc_regfile_reads 127408 # number of misc regfile reads

2227system.cpu3.misc_regfile_reads 122920 # number of misc regfile reads

2225system.cpu3.misc_regfile_writes 648 # number of misc regfile writes

2228system.cpu3.misc_regfile_writes 648 # number of misc regfile writes

2226system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

2229system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

2227system.cpu3.dcache.tags.replacements 0 # number of replacements

2230system.cpu3.dcache.tags.replacements 0 # number of replacements

2228system.cpu3.dcache.tags.tagsinuse 25.184575 # Cycle average of tags in use
2229system.cpu3.dcache.tags.total_refs 45468 # Total number of references to valid blocks.
2230system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
2231system.cpu3.dcache.tags.avg_refs 1567.862069 # Average number of references to valid blocks.

2231system.cpu3.dcache.tags.tagsinuse 24.889715 # Cycle average of tags in use
2232system.cpu3.dcache.tags.total_refs 43728 # Total number of references to valid blocks.
2233system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
2234system.cpu3.dcache.tags.avg_refs 1457.600000 # Average number of references to valid blocks.

2232system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2235system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2233system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.184575 # Average occupied blocks per requestor
2234system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049189 # Average percentage of cache occupancy
2235system.cpu3.dcache.tags.occ_percent::total 0.049189 # Average percentage of cache occupancy
2236system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
2237system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
2238system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
2239system.cpu3.dcache.tags.tag_accesses 358446 # Number of tag accesses
2240system.cpu3.dcache.tags.data_accesses 358446 # Number of data accesses
2241system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
2242system.cpu3.dcache.ReadReq_hits::cpu3.data 50650 # number of ReadReq hits
2243system.cpu3.dcache.ReadReq_hits::total 50650 # number of ReadReq hits
2244system.cpu3.dcache.WriteReq_hits::cpu3.data 38188 # number of WriteReq hits
2245system.cpu3.dcache.WriteReq_hits::total 38188 # number of WriteReq hits
2246system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
2247system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
2248system.cpu3.dcache.demand_hits::cpu3.data 88838 # number of demand (read+write) hits
2249system.cpu3.dcache.demand_hits::total 88838 # number of demand (read+write) hits
2250system.cpu3.dcache.overall_hits::cpu3.data 88838 # number of overall hits
2251system.cpu3.dcache.overall_hits::total 88838 # number of overall hits
2252system.cpu3.dcache.ReadReq_misses::cpu3.data 496 # number of ReadReq misses
2253system.cpu3.dcache.ReadReq_misses::total 496 # number of ReadReq misses
2254system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses
2255system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses
2256system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses
2257system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses
2258system.cpu3.dcache.demand_misses::cpu3.data 636 # number of demand (read+write) misses
2259system.cpu3.dcache.demand_misses::total 636 # number of demand (read+write) misses
2260system.cpu3.dcache.overall_misses::cpu3.data 636 # number of overall misses
2261system.cpu3.dcache.overall_misses::total 636 # number of overall misses
2262system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3601500 # number of ReadReq miss cycles
2263system.cpu3.dcache.ReadReq_miss_latency::total 3601500 # number of ReadReq miss cycles
2264system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2913500 # number of WriteReq miss cycles
2265system.cpu3.dcache.WriteReq_miss_latency::total 2913500 # number of WriteReq miss cycles
2266system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 356500 # number of SwapReq miss cycles
2267system.cpu3.dcache.SwapReq_miss_latency::total 356500 # number of SwapReq miss cycles
2268system.cpu3.dcache.demand_miss_latency::cpu3.data 6515000 # number of demand (read+write) miss cycles
2269system.cpu3.dcache.demand_miss_latency::total 6515000 # number of demand (read+write) miss cycles
2270system.cpu3.dcache.overall_miss_latency::cpu3.data 6515000 # number of overall miss cycles
2271system.cpu3.dcache.overall_miss_latency::total 6515000 # number of overall miss cycles
2272system.cpu3.dcache.ReadReq_accesses::cpu3.data 51146 # number of ReadReq accesses(hits+misses)
2273system.cpu3.dcache.ReadReq_accesses::total 51146 # number of ReadReq accesses(hits+misses)
2274system.cpu3.dcache.WriteReq_accesses::cpu3.data 38328 # number of WriteReq accesses(hits+misses)
2275system.cpu3.dcache.WriteReq_accesses::total 38328 # number of WriteReq accesses(hits+misses)
2276system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
2277system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
2278system.cpu3.dcache.demand_accesses::cpu3.data 89474 # number of demand (read+write) accesses
2279system.cpu3.dcache.demand_accesses::total 89474 # number of demand (read+write) accesses
2280system.cpu3.dcache.overall_accesses::cpu3.data 89474 # number of overall (read+write) accesses
2281system.cpu3.dcache.overall_accesses::total 89474 # number of overall (read+write) accesses
2282system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009698 # miss rate for ReadReq accesses
2283system.cpu3.dcache.ReadReq_miss_rate::total 0.009698 # miss rate for ReadReq accesses
2284system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003653 # miss rate for WriteReq accesses
2285system.cpu3.dcache.WriteReq_miss_rate::total 0.003653 # miss rate for WriteReq accesses
2286system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.833333 # miss rate for SwapReq accesses
2287system.cpu3.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
2288system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007108 # miss rate for demand accesses
2289system.cpu3.dcache.demand_miss_rate::total 0.007108 # miss rate for demand accesses
2290system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007108 # miss rate for overall accesses
2291system.cpu3.dcache.overall_miss_rate::total 0.007108 # miss rate for overall accesses
2292system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7261.088710 # average ReadReq miss latency
2293system.cpu3.dcache.ReadReq_avg_miss_latency::total 7261.088710 # average ReadReq miss latency
2294system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286 # average WriteReq miss latency
2295system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286 # average WriteReq miss latency
2296system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5941.666667 # average SwapReq miss latency
2297system.cpu3.dcache.SwapReq_avg_miss_latency::total 5941.666667 # average SwapReq miss latency
2298system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency
2299system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692 # average overall miss latency
2300system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency
2301system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692 # average overall miss latency

2236system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.889715 # Average occupied blocks per requestor
2237system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048613 # Average percentage of cache occupancy
2238system.cpu3.dcache.tags.occ_percent::total 0.048613 # Average percentage of cache occupancy
2239system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
2240system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
2241system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
2242system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
2243system.cpu3.dcache.tags.tag_accesses 347346 # Number of tag accesses
2244system.cpu3.dcache.tags.data_accesses 347346 # Number of data accesses
2245system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
2246system.cpu3.dcache.ReadReq_hits::cpu3.data 49561 # number of ReadReq hits
2247system.cpu3.dcache.ReadReq_hits::total 49561 # number of ReadReq hits
2248system.cpu3.dcache.WriteReq_hits::cpu3.data 36521 # number of WriteReq hits
2249system.cpu3.dcache.WriteReq_hits::total 36521 # number of WriteReq hits
2250system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
2251system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
2252system.cpu3.dcache.demand_hits::cpu3.data 86082 # number of demand (read+write) hits
2253system.cpu3.dcache.demand_hits::total 86082 # number of demand (read+write) hits
2254system.cpu3.dcache.overall_hits::cpu3.data 86082 # number of overall hits
2255system.cpu3.dcache.overall_hits::total 86082 # number of overall hits
2256system.cpu3.dcache.ReadReq_misses::cpu3.data 482 # number of ReadReq misses
2257system.cpu3.dcache.ReadReq_misses::total 482 # number of ReadReq misses
2258system.cpu3.dcache.WriteReq_misses::cpu3.data 144 # number of WriteReq misses
2259system.cpu3.dcache.WriteReq_misses::total 144 # number of WriteReq misses
2260system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
2261system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
2262system.cpu3.dcache.demand_misses::cpu3.data 626 # number of demand (read+write) misses
2263system.cpu3.dcache.demand_misses::total 626 # number of demand (read+write) misses
2264system.cpu3.dcache.overall_misses::cpu3.data 626 # number of overall misses
2265system.cpu3.dcache.overall_misses::total 626 # number of overall misses
2266system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4340000 # number of ReadReq miss cycles
2267system.cpu3.dcache.ReadReq_miss_latency::total 4340000 # number of ReadReq miss cycles
2268system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3297000 # number of WriteReq miss cycles
2269system.cpu3.dcache.WriteReq_miss_latency::total 3297000 # number of WriteReq miss cycles
2270system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 320500 # number of SwapReq miss cycles
2271system.cpu3.dcache.SwapReq_miss_latency::total 320500 # number of SwapReq miss cycles
2272system.cpu3.dcache.demand_miss_latency::cpu3.data 7637000 # number of demand (read+write) miss cycles
2273system.cpu3.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles
2274system.cpu3.dcache.overall_miss_latency::cpu3.data 7637000 # number of overall miss cycles
2275system.cpu3.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles
2276system.cpu3.dcache.ReadReq_accesses::cpu3.data 50043 # number of ReadReq accesses(hits+misses)
2277system.cpu3.dcache.ReadReq_accesses::total 50043 # number of ReadReq accesses(hits+misses)
2278system.cpu3.dcache.WriteReq_accesses::cpu3.data 36665 # number of WriteReq accesses(hits+misses)
2279system.cpu3.dcache.WriteReq_accesses::total 36665 # number of WriteReq accesses(hits+misses)
2280system.cpu3.dcache.SwapReq_accesses::cpu3.data 66 # number of SwapReq accesses(hits+misses)
2281system.cpu3.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
2282system.cpu3.dcache.demand_accesses::cpu3.data 86708 # number of demand (read+write) accesses
2283system.cpu3.dcache.demand_accesses::total 86708 # number of demand (read+write) accesses
2284system.cpu3.dcache.overall_accesses::cpu3.data 86708 # number of overall (read+write) accesses
2285system.cpu3.dcache.overall_accesses::total 86708 # number of overall (read+write) accesses
2286system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009632 # miss rate for ReadReq accesses
2287system.cpu3.dcache.ReadReq_miss_rate::total 0.009632 # miss rate for ReadReq accesses
2288system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003927 # miss rate for WriteReq accesses
2289system.cpu3.dcache.WriteReq_miss_rate::total 0.003927 # miss rate for WriteReq accesses
2290system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.787879 # miss rate for SwapReq accesses
2291system.cpu3.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses
2292system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007220 # miss rate for demand accesses
2293system.cpu3.dcache.demand_miss_rate::total 0.007220 # miss rate for demand accesses
2294system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007220 # miss rate for overall accesses
2295system.cpu3.dcache.overall_miss_rate::total 0.007220 # miss rate for overall accesses
2296system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 9004.149378 # average ReadReq miss latency
2297system.cpu3.dcache.ReadReq_avg_miss_latency::total 9004.149378 # average ReadReq miss latency
2298system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22895.833333 # average WriteReq miss latency
2299system.cpu3.dcache.WriteReq_avg_miss_latency::total 22895.833333 # average WriteReq miss latency
2300system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6163.461538 # average SwapReq miss latency
2301system.cpu3.dcache.SwapReq_avg_miss_latency::total 6163.461538 # average SwapReq miss latency
2302system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency
2303system.cpu3.dcache.demand_avg_miss_latency::total 12199.680511 # average overall miss latency
2304system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency
2305system.cpu3.dcache.overall_avg_miss_latency::total 12199.680511 # average overall miss latency

2302system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2303system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2304system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2305system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2306system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2307system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2306system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2307system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2308system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2309system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2310system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2311system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2308system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 326 # number of ReadReq MSHR hits
2309system.cpu3.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits
2310system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits
2311system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits

2312system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 322 # number of ReadReq MSHR hits
2313system.cpu3.dcache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits
2314system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 40 # number of WriteReq MSHR hits
2315system.cpu3.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits

2312system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits
2313system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits

2316system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits
2317system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits

2314system.cpu3.dcache.demand_mshr_hits::cpu3.data 361 # number of demand (read+write) MSHR hits
2315system.cpu3.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits
2316system.cpu3.dcache.overall_mshr_hits::cpu3.data 361 # number of overall MSHR hits
2317system.cpu3.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits
2318system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 170 # number of ReadReq MSHR misses
2319system.cpu3.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
2320system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
2321system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
2322system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses
2323system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
2324system.cpu3.dcache.demand_mshr_misses::cpu3.data 275 # number of demand (read+write) MSHR misses
2325system.cpu3.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
2326system.cpu3.dcache.overall_mshr_misses::cpu3.data 275 # number of overall MSHR misses
2327system.cpu3.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
2328system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1125000 # number of ReadReq MSHR miss cycles
2329system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1125000 # number of ReadReq MSHR miss cycles
2330system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1450500 # number of WriteReq MSHR miss cycles
2331system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles
2332system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 296500 # number of SwapReq MSHR miss cycles
2333system.cpu3.dcache.SwapReq_mshr_miss_latency::total 296500 # number of SwapReq MSHR miss cycles
2334system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2575500 # number of demand (read+write) MSHR miss cycles
2335system.cpu3.dcache.demand_mshr_miss_latency::total 2575500 # number of demand (read+write) MSHR miss cycles
2336system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2575500 # number of overall MSHR miss cycles
2337system.cpu3.dcache.overall_mshr_miss_latency::total 2575500 # number of overall MSHR miss cycles
2338system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003324 # mshr miss rate for ReadReq accesses
2339system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003324 # mshr miss rate for ReadReq accesses
2340system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002740 # mshr miss rate for WriteReq accesses
2341system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses
2342system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.819444 # mshr miss rate for SwapReq accesses
2343system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.819444 # mshr miss rate for SwapReq accesses
2344system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for demand accesses
2345system.cpu3.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses
2346system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for overall accesses
2347system.cpu3.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses
2348system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6617.647059 # average ReadReq mshr miss latency
2349system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6617.647059 # average ReadReq mshr miss latency
2350system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13814.285714 # average WriteReq mshr miss latency
2351system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13814.285714 # average WriteReq mshr miss latency
2352system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5025.423729 # average SwapReq mshr miss latency
2353system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5025.423729 # average SwapReq mshr miss latency
2354system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency
2355system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency
2356system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency
2357system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency
2358system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
2359system.cpu3.icache.tags.replacements 586 # number of replacements
2360system.cpu3.icache.tags.tagsinuse 96.347148 # Cycle average of tags in use
2361system.cpu3.icache.tags.total_refs 27016 # Total number of references to valid blocks.
2362system.cpu3.icache.tags.sampled_refs 724 # Sample count of references to valid blocks.
2363system.cpu3.icache.tags.avg_refs 37.314917 # Average number of references to valid blocks.

2318system.cpu3.dcache.demand_mshr_hits::cpu3.data 362 # number of demand (read+write) MSHR hits
2319system.cpu3.dcache.demand_mshr_hits::total 362 # number of demand (read+write) MSHR hits
2320system.cpu3.dcache.overall_mshr_hits::cpu3.data 362 # number of overall MSHR hits
2321system.cpu3.dcache.overall_mshr_hits::total 362 # number of overall MSHR hits
2322system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
2323system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
2324system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
2325system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
2326system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
2327system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
2328system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses
2329system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses
2330system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses
2331system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
2332system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1241000 # number of ReadReq MSHR miss cycles
2333system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1241000 # number of ReadReq MSHR miss cycles
2334system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles
2335system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles
2336system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 268500 # number of SwapReq MSHR miss cycles
2337system.cpu3.dcache.SwapReq_mshr_miss_latency::total 268500 # number of SwapReq MSHR miss cycles
2338system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2872000 # number of demand (read+write) MSHR miss cycles
2339system.cpu3.dcache.demand_mshr_miss_latency::total 2872000 # number of demand (read+write) MSHR miss cycles
2340system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2872000 # number of overall MSHR miss cycles
2341system.cpu3.dcache.overall_mshr_miss_latency::total 2872000 # number of overall MSHR miss cycles
2342system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003197 # mshr miss rate for ReadReq accesses
2343system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003197 # mshr miss rate for ReadReq accesses
2344system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002836 # mshr miss rate for WriteReq accesses
2345system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002836 # mshr miss rate for WriteReq accesses
2346system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.772727 # mshr miss rate for SwapReq accesses
2347system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses
2348system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for demand accesses
2349system.cpu3.dcache.demand_mshr_miss_rate::total 0.003045 # mshr miss rate for demand accesses
2350system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for overall accesses
2351system.cpu3.dcache.overall_mshr_miss_rate::total 0.003045 # mshr miss rate for overall accesses
2352system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7756.250000 # average ReadReq mshr miss latency
2353system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7756.250000 # average ReadReq mshr miss latency
2354system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15682.692308 # average WriteReq mshr miss latency
2355system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15682.692308 # average WriteReq mshr miss latency
2356system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5264.705882 # average SwapReq mshr miss latency
2357system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5264.705882 # average SwapReq mshr miss latency
2358system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency
2359system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency
2360system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency
2361system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency
2362system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
2363system.cpu3.icache.tags.replacements 575 # number of replacements
2364system.cpu3.icache.tags.tagsinuse 93.289458 # Cycle average of tags in use
2365system.cpu3.icache.tags.total_refs 28201 # Total number of references to valid blocks.
2366system.cpu3.icache.tags.sampled_refs 712 # Sample count of references to valid blocks.
2367system.cpu3.icache.tags.avg_refs 39.608146 # Average number of references to valid blocks.

2364system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2368system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2365system.cpu3.icache.tags.occ_blocks::cpu3.inst 96.347148 # Average occupied blocks per requestor
2366system.cpu3.icache.tags.occ_percent::cpu3.inst 0.188178 # Average percentage of cache occupancy
2367system.cpu3.icache.tags.occ_percent::total 0.188178 # Average percentage of cache occupancy
2368system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
2369system.cpu3.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
2370system.cpu3.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
2371system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id
2372system.cpu3.icache.tags.tag_accesses 28596 # Number of tag accesses
2373system.cpu3.icache.tags.data_accesses 28596 # Number of data accesses
2374system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
2375system.cpu3.icache.ReadReq_hits::cpu3.inst 27016 # number of ReadReq hits
2376system.cpu3.icache.ReadReq_hits::total 27016 # number of ReadReq hits
2377system.cpu3.icache.demand_hits::cpu3.inst 27016 # number of demand (read+write) hits
2378system.cpu3.icache.demand_hits::total 27016 # number of demand (read+write) hits
2379system.cpu3.icache.overall_hits::cpu3.inst 27016 # number of overall hits
2380system.cpu3.icache.overall_hits::total 27016 # number of overall hits
2381system.cpu3.icache.ReadReq_misses::cpu3.inst 856 # number of ReadReq misses
2382system.cpu3.icache.ReadReq_misses::total 856 # number of ReadReq misses
2383system.cpu3.icache.demand_misses::cpu3.inst 856 # number of demand (read+write) misses
2384system.cpu3.icache.demand_misses::total 856 # number of demand (read+write) misses
2385system.cpu3.icache.overall_misses::cpu3.inst 856 # number of overall misses
2386system.cpu3.icache.overall_misses::total 856 # number of overall misses
2387system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 12888000 # number of ReadReq miss cycles
2388system.cpu3.icache.ReadReq_miss_latency::total 12888000 # number of ReadReq miss cycles
2389system.cpu3.icache.demand_miss_latency::cpu3.inst 12888000 # number of demand (read+write) miss cycles
2390system.cpu3.icache.demand_miss_latency::total 12888000 # number of demand (read+write) miss cycles
2391system.cpu3.icache.overall_miss_latency::cpu3.inst 12888000 # number of overall miss cycles
2392system.cpu3.icache.overall_miss_latency::total 12888000 # number of overall miss cycles
2393system.cpu3.icache.ReadReq_accesses::cpu3.inst 27872 # number of ReadReq accesses(hits+misses)
2394system.cpu3.icache.ReadReq_accesses::total 27872 # number of ReadReq accesses(hits+misses)
2395system.cpu3.icache.demand_accesses::cpu3.inst 27872 # number of demand (read+write) accesses
2396system.cpu3.icache.demand_accesses::total 27872 # number of demand (read+write) accesses
2397system.cpu3.icache.overall_accesses::cpu3.inst 27872 # number of overall (read+write) accesses
2398system.cpu3.icache.overall_accesses::total 27872 # number of overall (read+write) accesses
2399system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.030712 # miss rate for ReadReq accesses
2400system.cpu3.icache.ReadReq_miss_rate::total 0.030712 # miss rate for ReadReq accesses
2401system.cpu3.icache.demand_miss_rate::cpu3.inst 0.030712 # miss rate for demand accesses
2402system.cpu3.icache.demand_miss_rate::total 0.030712 # miss rate for demand accesses
2403system.cpu3.icache.overall_miss_rate::cpu3.inst 0.030712 # miss rate for overall accesses
2404system.cpu3.icache.overall_miss_rate::total 0.030712 # miss rate for overall accesses
2405system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15056.074766 # average ReadReq miss latency
2406system.cpu3.icache.ReadReq_avg_miss_latency::total 15056.074766 # average ReadReq miss latency
2407system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15056.074766 # average overall miss latency
2408system.cpu3.icache.demand_avg_miss_latency::total 15056.074766 # average overall miss latency
2409system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15056.074766 # average overall miss latency
2410system.cpu3.icache.overall_avg_miss_latency::total 15056.074766 # average overall miss latency
2411system.cpu3.icache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked

2369system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.289458 # Average occupied blocks per requestor
2370system.cpu3.icache.tags.occ_percent::cpu3.inst 0.182206 # Average percentage of cache occupancy
2371system.cpu3.icache.tags.occ_percent::total 0.182206 # Average percentage of cache occupancy
2372system.cpu3.icache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
2373system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
2374system.cpu3.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
2375system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
2376system.cpu3.icache.tags.occ_task_id_percent::1024 0.267578 # Percentage of cache occupancy per task id
2377system.cpu3.icache.tags.tag_accesses 29751 # Number of tag accesses
2378system.cpu3.icache.tags.data_accesses 29751 # Number of data accesses
2379system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
2380system.cpu3.icache.ReadReq_hits::cpu3.inst 28201 # number of ReadReq hits
2381system.cpu3.icache.ReadReq_hits::total 28201 # number of ReadReq hits
2382system.cpu3.icache.demand_hits::cpu3.inst 28201 # number of demand (read+write) hits
2383system.cpu3.icache.demand_hits::total 28201 # number of demand (read+write) hits
2384system.cpu3.icache.overall_hits::cpu3.inst 28201 # number of overall hits
2385system.cpu3.icache.overall_hits::total 28201 # number of overall hits
2386system.cpu3.icache.ReadReq_misses::cpu3.inst 838 # number of ReadReq misses
2387system.cpu3.icache.ReadReq_misses::total 838 # number of ReadReq misses
2388system.cpu3.icache.demand_misses::cpu3.inst 838 # number of demand (read+write) misses
2389system.cpu3.icache.demand_misses::total 838 # number of demand (read+write) misses
2390system.cpu3.icache.overall_misses::cpu3.inst 838 # number of overall misses
2391system.cpu3.icache.overall_misses::total 838 # number of overall misses
2392system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 13273000 # number of ReadReq miss cycles
2393system.cpu3.icache.ReadReq_miss_latency::total 13273000 # number of ReadReq miss cycles
2394system.cpu3.icache.demand_miss_latency::cpu3.inst 13273000 # number of demand (read+write) miss cycles
2395system.cpu3.icache.demand_miss_latency::total 13273000 # number of demand (read+write) miss cycles
2396system.cpu3.icache.overall_miss_latency::cpu3.inst 13273000 # number of overall miss cycles
2397system.cpu3.icache.overall_miss_latency::total 13273000 # number of overall miss cycles
2398system.cpu3.icache.ReadReq_accesses::cpu3.inst 29039 # number of ReadReq accesses(hits+misses)
2399system.cpu3.icache.ReadReq_accesses::total 29039 # number of ReadReq accesses(hits+misses)
2400system.cpu3.icache.demand_accesses::cpu3.inst 29039 # number of demand (read+write) accesses
2401system.cpu3.icache.demand_accesses::total 29039 # number of demand (read+write) accesses
2402system.cpu3.icache.overall_accesses::cpu3.inst 29039 # number of overall (read+write) accesses
2403system.cpu3.icache.overall_accesses::total 29039 # number of overall (read+write) accesses
2404system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.028858 # miss rate for ReadReq accesses
2405system.cpu3.icache.ReadReq_miss_rate::total 0.028858 # miss rate for ReadReq accesses
2406system.cpu3.icache.demand_miss_rate::cpu3.inst 0.028858 # miss rate for demand accesses
2407system.cpu3.icache.demand_miss_rate::total 0.028858 # miss rate for demand accesses
2408system.cpu3.icache.overall_miss_rate::cpu3.inst 0.028858 # miss rate for overall accesses
2409system.cpu3.icache.overall_miss_rate::total 0.028858 # miss rate for overall accesses
2410system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15838.902148 # average ReadReq miss latency
2411system.cpu3.icache.ReadReq_avg_miss_latency::total 15838.902148 # average ReadReq miss latency
2412system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency
2413system.cpu3.icache.demand_avg_miss_latency::total 15838.902148 # average overall miss latency
2414system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency
2415system.cpu3.icache.overall_avg_miss_latency::total 15838.902148 # average overall miss latency
2416system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

2412system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2417system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2413system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked

2418system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked

2414system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked

2419system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked

2415system.cpu3.icache.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked

2420system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

2416system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2421system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2417system.cpu3.icache.writebacks::writebacks 586 # number of writebacks
2418system.cpu3.icache.writebacks::total 586 # number of writebacks
2419system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 132 # number of ReadReq MSHR hits
2420system.cpu3.icache.ReadReq_mshr_hits::total 132 # number of ReadReq MSHR hits
2421system.cpu3.icache.demand_mshr_hits::cpu3.inst 132 # number of demand (read+write) MSHR hits
2422system.cpu3.icache.demand_mshr_hits::total 132 # number of demand (read+write) MSHR hits
2423system.cpu3.icache.overall_mshr_hits::cpu3.inst 132 # number of overall MSHR hits
2424system.cpu3.icache.overall_mshr_hits::total 132 # number of overall MSHR hits
2425system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 724 # number of ReadReq MSHR misses
2426system.cpu3.icache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses
2427system.cpu3.icache.demand_mshr_misses::cpu3.inst 724 # number of demand (read+write) MSHR misses
2428system.cpu3.icache.demand_mshr_misses::total 724 # number of demand (read+write) MSHR misses
2429system.cpu3.icache.overall_mshr_misses::cpu3.inst 724 # number of overall MSHR misses
2430system.cpu3.icache.overall_mshr_misses::total 724 # number of overall MSHR misses
2431system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11106000 # number of ReadReq MSHR miss cycles
2432system.cpu3.icache.ReadReq_mshr_miss_latency::total 11106000 # number of ReadReq MSHR miss cycles
2433system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11106000 # number of demand (read+write) MSHR miss cycles
2434system.cpu3.icache.demand_mshr_miss_latency::total 11106000 # number of demand (read+write) MSHR miss cycles
2435system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11106000 # number of overall MSHR miss cycles
2436system.cpu3.icache.overall_mshr_miss_latency::total 11106000 # number of overall MSHR miss cycles
2437system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for ReadReq accesses
2438system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses
2439system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for demand accesses
2440system.cpu3.icache.demand_mshr_miss_rate::total 0.025976 # mshr miss rate for demand accesses
2441system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for overall accesses
2442system.cpu3.icache.overall_mshr_miss_rate::total 0.025976 # mshr miss rate for overall accesses
2443system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average ReadReq mshr miss latency
2444system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15339.779006 # average ReadReq mshr miss latency
2445system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average overall mshr miss latency
2446system.cpu3.icache.demand_avg_mshr_miss_latency::total 15339.779006 # average overall mshr miss latency
2447system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average overall mshr miss latency
2448system.cpu3.icache.overall_avg_mshr_miss_latency::total 15339.779006 # average overall mshr miss latency
2449system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

2422system.cpu3.icache.writebacks::writebacks 575 # number of writebacks
2423system.cpu3.icache.writebacks::total 575 # number of writebacks
2424system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # number of ReadReq MSHR hits
2425system.cpu3.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits
2426system.cpu3.icache.demand_mshr_hits::cpu3.inst 126 # number of demand (read+write) MSHR hits
2427system.cpu3.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits
2428system.cpu3.icache.overall_mshr_hits::cpu3.inst 126 # number of overall MSHR hits
2429system.cpu3.icache.overall_mshr_hits::total 126 # number of overall MSHR hits
2430system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 712 # number of ReadReq MSHR misses
2431system.cpu3.icache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses
2432system.cpu3.icache.demand_mshr_misses::cpu3.inst 712 # number of demand (read+write) MSHR misses
2433system.cpu3.icache.demand_mshr_misses::total 712 # number of demand (read+write) MSHR misses
2434system.cpu3.icache.overall_mshr_misses::cpu3.inst 712 # number of overall MSHR misses
2435system.cpu3.icache.overall_mshr_misses::total 712 # number of overall MSHR misses
2436system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11453500 # number of ReadReq MSHR miss cycles
2437system.cpu3.icache.ReadReq_mshr_miss_latency::total 11453500 # number of ReadReq MSHR miss cycles
2438system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11453500 # number of demand (read+write) MSHR miss cycles
2439system.cpu3.icache.demand_mshr_miss_latency::total 11453500 # number of demand (read+write) MSHR miss cycles
2440system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11453500 # number of overall MSHR miss cycles
2441system.cpu3.icache.overall_mshr_miss_latency::total 11453500 # number of overall MSHR miss cycles
2442system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for ReadReq accesses
2443system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.024519 # mshr miss rate for ReadReq accesses
2444system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for demand accesses
2445system.cpu3.icache.demand_mshr_miss_rate::total 0.024519 # mshr miss rate for demand accesses
2446system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for overall accesses
2447system.cpu3.icache.overall_mshr_miss_rate::total 0.024519 # mshr miss rate for overall accesses
2448system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average ReadReq mshr miss latency
2449system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 16086.376404 # average ReadReq mshr miss latency
2450system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average overall mshr miss latency
2451system.cpu3.icache.demand_avg_mshr_miss_latency::total 16086.376404 # average overall mshr miss latency
2452system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average overall mshr miss latency
2453system.cpu3.icache.overall_avg_mshr_miss_latency::total 16086.376404 # average overall mshr miss latency
2454system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

2450system.l2c.tags.replacements 0 # number of replacements

2455system.l2c.tags.replacements 0 # number of replacements

2451system.l2c.tags.tagsinuse 566.391309 # Cycle average of tags in use
2452system.l2c.tags.total_refs 3152 # Total number of references to valid blocks.
2453system.l2c.tags.sampled_refs 716 # Sample count of references to valid blocks.
2454system.l2c.tags.avg_refs 4.402235 # Average number of references to valid blocks.

2456system.l2c.tags.tagsinuse 566.450222 # Cycle average of tags in use
2457system.l2c.tags.total_refs 3196 # Total number of references to valid blocks.
2458system.l2c.tags.sampled_refs 710 # Sample count of references to valid blocks.
2459system.l2c.tags.avg_refs 4.501408 # Average number of references to valid blocks.

2455system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2460system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2456system.l2c.tags.occ_blocks::cpu0.inst 300.631868 # Average occupied blocks per requestor
2457system.l2c.tags.occ_blocks::cpu0.data 144.597180 # Average occupied blocks per requestor
2458system.l2c.tags.occ_blocks::cpu1.inst 70.863487 # Average occupied blocks per requestor
2459system.l2c.tags.occ_blocks::cpu1.data 15.770640 # Average occupied blocks per requestor
2460system.l2c.tags.occ_blocks::cpu2.inst 7.294857 # Average occupied blocks per requestor
2461system.l2c.tags.occ_blocks::cpu2.data 10.082216 # Average occupied blocks per requestor
2462system.l2c.tags.occ_blocks::cpu3.inst 7.192526 # Average occupied blocks per requestor
2463system.l2c.tags.occ_blocks::cpu3.data 9.958536 # Average occupied blocks per requestor
2464system.l2c.tags.occ_percent::cpu0.inst 0.004587 # Average percentage of cache occupancy
2465system.l2c.tags.occ_percent::cpu0.data 0.002206 # Average percentage of cache occupancy
2466system.l2c.tags.occ_percent::cpu1.inst 0.001081 # Average percentage of cache occupancy
2467system.l2c.tags.occ_percent::cpu1.data 0.000241 # Average percentage of cache occupancy
2468system.l2c.tags.occ_percent::cpu2.inst 0.000111 # Average percentage of cache occupancy

2461system.l2c.tags.occ_blocks::cpu0.inst 300.277327 # Average occupied blocks per requestor
2462system.l2c.tags.occ_blocks::cpu0.data 144.720872 # Average occupied blocks per requestor
2463system.l2c.tags.occ_blocks::cpu1.inst 69.261985 # Average occupied blocks per requestor
2464system.l2c.tags.occ_blocks::cpu1.data 16.352170 # Average occupied blocks per requestor
2465system.l2c.tags.occ_blocks::cpu2.inst 9.533779 # Average occupied blocks per requestor
2466system.l2c.tags.occ_blocks::cpu2.data 10.075907 # Average occupied blocks per requestor
2467system.l2c.tags.occ_blocks::cpu3.inst 5.908934 # Average occupied blocks per requestor
2468system.l2c.tags.occ_blocks::cpu3.data 10.319248 # Average occupied blocks per requestor
2469system.l2c.tags.occ_percent::cpu0.inst 0.004582 # Average percentage of cache occupancy
2470system.l2c.tags.occ_percent::cpu0.data 0.002208 # Average percentage of cache occupancy
2471system.l2c.tags.occ_percent::cpu1.inst 0.001057 # Average percentage of cache occupancy
2472system.l2c.tags.occ_percent::cpu1.data 0.000250 # Average percentage of cache occupancy
2473system.l2c.tags.occ_percent::cpu2.inst 0.000145 # Average percentage of cache occupancy

2469system.l2c.tags.occ_percent::cpu2.data 0.000154 # Average percentage of cache occupancy

2474system.l2c.tags.occ_percent::cpu2.data 0.000154 # Average percentage of cache occupancy

2470system.l2c.tags.occ_percent::cpu3.inst 0.000110 # Average percentage of cache occupancy
2471system.l2c.tags.occ_percent::cpu3.data 0.000152 # Average percentage of cache occupancy
2472system.l2c.tags.occ_percent::total 0.008642 # Average percentage of cache occupancy
2473system.l2c.tags.occ_task_id_blocks::1024 716 # Occupied blocks per task id
2474system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
2475system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
2476system.l2c.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id
2477system.l2c.tags.occ_task_id_percent::1024 0.010925 # Percentage of cache occupancy per task id
2478system.l2c.tags.tag_accesses 31812 # Number of tag accesses
2479system.l2c.tags.data_accesses 31812 # Number of data accesses
2480system.l2c.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states

2475system.l2c.tags.occ_percent::cpu3.inst 0.000090 # Average percentage of cache occupancy
2476system.l2c.tags.occ_percent::cpu3.data 0.000157 # Average percentage of cache occupancy
2477system.l2c.tags.occ_percent::total 0.008643 # Average percentage of cache occupancy
2478system.l2c.tags.occ_task_id_blocks::1024 710 # Occupied blocks per task id
2479system.l2c.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
2480system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
2481system.l2c.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
2482system.l2c.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
2483system.l2c.tags.tag_accesses 32110 # Number of tag accesses
2484system.l2c.tags.data_accesses 32110 # Number of data accesses
2485system.l2c.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states

2481system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
2482system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits

2486system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
2487system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits

2483system.l2c.WritebackClean_hits::writebacks 730 # number of WritebackClean hits
2484system.l2c.WritebackClean_hits::total 730 # number of WritebackClean hits
2485system.l2c.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits
2486system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits
2487system.l2c.UpgradeReq_hits::cpu2.data 25 # number of UpgradeReq hits
2488system.l2c.UpgradeReq_hits::cpu3.data 20 # number of UpgradeReq hits
2489system.l2c.UpgradeReq_hits::total 90 # number of UpgradeReq hits
2490system.l2c.ReadCleanReq_hits::cpu0.inst 318 # number of ReadCleanReq hits
2491system.l2c.ReadCleanReq_hits::cpu1.inst 594 # number of ReadCleanReq hits
2492system.l2c.ReadCleanReq_hits::cpu2.inst 679 # number of ReadCleanReq hits
2493system.l2c.ReadCleanReq_hits::cpu3.inst 707 # number of ReadCleanReq hits
2494system.l2c.ReadCleanReq_hits::total 2298 # number of ReadCleanReq hits

2488system.l2c.WritebackClean_hits::writebacks 757 # number of WritebackClean hits
2489system.l2c.WritebackClean_hits::total 757 # number of WritebackClean hits
2490system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits
2491system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits
2492system.l2c.UpgradeReq_hits::cpu2.data 21 # number of UpgradeReq hits
2493system.l2c.UpgradeReq_hits::cpu3.data 21 # number of UpgradeReq hits
2494system.l2c.UpgradeReq_hits::total 84 # number of UpgradeReq hits
2495system.l2c.ReadCleanReq_hits::cpu0.inst 321 # number of ReadCleanReq hits
2496system.l2c.ReadCleanReq_hits::cpu1.inst 637 # number of ReadCleanReq hits
2497system.l2c.ReadCleanReq_hits::cpu2.inst 664 # number of ReadCleanReq hits
2498system.l2c.ReadCleanReq_hits::cpu3.inst 699 # number of ReadCleanReq hits
2499system.l2c.ReadCleanReq_hits::total 2321 # number of ReadCleanReq hits

2495system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
2496system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
2497system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
2498system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
2499system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits

2500system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
2501system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
2502system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
2503system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
2504system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits

2500system.l2c.demand_hits::cpu0.inst 318 # number of demand (read+write) hits

2505system.l2c.demand_hits::cpu0.inst 321 # number of demand (read+write) hits

2501system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2506system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2502system.l2c.demand_hits::cpu1.inst 594 # number of demand (read+write) hits

2507system.l2c.demand_hits::cpu1.inst 637 # number of demand (read+write) hits

2503system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits

2508system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits

2504system.l2c.demand_hits::cpu2.inst 679 # number of demand (read+write) hits

2509system.l2c.demand_hits::cpu2.inst 664 # number of demand (read+write) hits

2505system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits

2510system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits

2506system.l2c.demand_hits::cpu3.inst 707 # number of demand (read+write) hits

2511system.l2c.demand_hits::cpu3.inst 699 # number of demand (read+write) hits

2507system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2512system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2508system.l2c.demand_hits::total 2330 # number of demand (read+write) hits
2509system.l2c.overall_hits::cpu0.inst 318 # number of overall hits

2513system.l2c.demand_hits::total 2353 # number of demand (read+write) hits
2514system.l2c.overall_hits::cpu0.inst 321 # number of overall hits

2510system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2515system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2511system.l2c.overall_hits::cpu1.inst 594 # number of overall hits

2516system.l2c.overall_hits::cpu1.inst 637 # number of overall hits

2512system.l2c.overall_hits::cpu1.data 5 # number of overall hits

2517system.l2c.overall_hits::cpu1.data 5 # number of overall hits

2513system.l2c.overall_hits::cpu2.inst 679 # number of overall hits

2518system.l2c.overall_hits::cpu2.inst 664 # number of overall hits

2514system.l2c.overall_hits::cpu2.data 11 # number of overall hits

2519system.l2c.overall_hits::cpu2.data 11 # number of overall hits

2515system.l2c.overall_hits::cpu3.inst 707 # number of overall hits

2520system.l2c.overall_hits::cpu3.inst 699 # number of overall hits

2516system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2521system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2517system.l2c.overall_hits::total 2330 # number of overall hits

2522system.l2c.overall_hits::total 2353 # number of overall hits

2518system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2519system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2520system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2521system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2522system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2523system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2524system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2525system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2526system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2527system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2523system.l2c.ReadCleanReq_misses::cpu0.inst 378 # number of ReadCleanReq misses

2528system.l2c.ReadCleanReq_misses::cpu0.inst 376 # number of ReadCleanReq misses

2524system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses
2525system.l2c.ReadCleanReq_misses::cpu2.inst 23 # number of ReadCleanReq misses

2529system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses
2530system.l2c.ReadCleanReq_misses::cpu2.inst 23 # number of ReadCleanReq misses

2526system.l2c.ReadCleanReq_misses::cpu3.inst 17 # number of ReadCleanReq misses
2527system.l2c.ReadCleanReq_misses::total 514 # number of ReadCleanReq misses

2531system.l2c.ReadCleanReq_misses::cpu3.inst 13 # number of ReadCleanReq misses
2532system.l2c.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses

2528system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses
2529system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses

2533system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses
2534system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses

2530system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses
2531system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses

2535system.l2c.ReadSharedReq_misses::cpu2.data 2 # number of ReadSharedReq misses
2536system.l2c.ReadSharedReq_misses::cpu3.data 3 # number of ReadSharedReq misses

2532system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses

2537system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses

2533system.l2c.demand_misses::cpu0.inst 378 # number of demand (read+write) misses

2538system.l2c.demand_misses::cpu0.inst 376 # number of demand (read+write) misses

2534system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses
2535system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses
2536system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses
2537system.l2c.demand_misses::cpu2.inst 23 # number of demand (read+write) misses

2539system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses
2540system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses
2541system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses
2542system.l2c.demand_misses::cpu2.inst 23 # number of demand (read+write) misses

2538system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses
2539system.l2c.demand_misses::cpu3.inst 17 # number of demand (read+write) misses
2540system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses
2541system.l2c.demand_misses::total 735 # number of demand (read+write) misses
2542system.l2c.overall_misses::cpu0.inst 378 # number of overall misses

2543system.l2c.demand_misses::cpu2.data 14 # number of demand (read+write) misses
2544system.l2c.demand_misses::cpu3.inst 13 # number of demand (read+write) misses
2545system.l2c.demand_misses::cpu3.data 15 # number of demand (read+write) misses
2546system.l2c.demand_misses::total 729 # number of demand (read+write) misses
2547system.l2c.overall_misses::cpu0.inst 376 # number of overall misses

2543system.l2c.overall_misses::cpu0.data 170 # number of overall misses
2544system.l2c.overall_misses::cpu1.inst 96 # number of overall misses
2545system.l2c.overall_misses::cpu1.data 22 # number of overall misses
2546system.l2c.overall_misses::cpu2.inst 23 # number of overall misses

2548system.l2c.overall_misses::cpu0.data 170 # number of overall misses
2549system.l2c.overall_misses::cpu1.inst 96 # number of overall misses
2550system.l2c.overall_misses::cpu1.data 22 # number of overall misses
2551system.l2c.overall_misses::cpu2.inst 23 # number of overall misses

2547system.l2c.overall_misses::cpu2.data 15 # number of overall misses
2548system.l2c.overall_misses::cpu3.inst 17 # number of overall misses
2549system.l2c.overall_misses::cpu3.data 14 # number of overall misses
2550system.l2c.overall_misses::total 735 # number of overall misses
2551system.l2c.ReadExReq_miss_latency::cpu0.data 7962000 # number of ReadExReq miss cycles
2552system.l2c.ReadExReq_miss_latency::cpu1.data 1092000 # number of ReadExReq miss cycles
2553system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles
2554system.l2c.ReadExReq_miss_latency::cpu3.data 1007500 # number of ReadExReq miss cycles
2555system.l2c.ReadExReq_miss_latency::total 11547000 # number of ReadExReq miss cycles
2556system.l2c.ReadCleanReq_miss_latency::cpu0.inst 32045000 # number of ReadCleanReq miss cycles
2557system.l2c.ReadCleanReq_miss_latency::cpu1.inst 7767000 # number of ReadCleanReq miss cycles
2558system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1841000 # number of ReadCleanReq miss cycles
2559system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2001000 # number of ReadCleanReq miss cycles
2560system.l2c.ReadCleanReq_miss_latency::total 43654000 # number of ReadCleanReq miss cycles
2561system.l2c.ReadSharedReq_miss_latency::cpu0.data 6727000 # number of ReadSharedReq miss cycles
2562system.l2c.ReadSharedReq_miss_latency::cpu1.data 1292500 # number of ReadSharedReq miss cycles
2563system.l2c.ReadSharedReq_miss_latency::cpu2.data 289000 # number of ReadSharedReq miss cycles
2564system.l2c.ReadSharedReq_miss_latency::cpu3.data 179500 # number of ReadSharedReq miss cycles
2565system.l2c.ReadSharedReq_miss_latency::total 8488000 # number of ReadSharedReq miss cycles
2566system.l2c.demand_miss_latency::cpu0.inst 32045000 # number of demand (read+write) miss cycles
2567system.l2c.demand_miss_latency::cpu0.data 14689000 # number of demand (read+write) miss cycles
2568system.l2c.demand_miss_latency::cpu1.inst 7767000 # number of demand (read+write) miss cycles
2569system.l2c.demand_miss_latency::cpu1.data 2384500 # number of demand (read+write) miss cycles
2570system.l2c.demand_miss_latency::cpu2.inst 1841000 # number of demand (read+write) miss cycles
2571system.l2c.demand_miss_latency::cpu2.data 1774500 # number of demand (read+write) miss cycles
2572system.l2c.demand_miss_latency::cpu3.inst 2001000 # number of demand (read+write) miss cycles
2573system.l2c.demand_miss_latency::cpu3.data 1187000 # number of demand (read+write) miss cycles
2574system.l2c.demand_miss_latency::total 63689000 # number of demand (read+write) miss cycles
2575system.l2c.overall_miss_latency::cpu0.inst 32045000 # number of overall miss cycles
2576system.l2c.overall_miss_latency::cpu0.data 14689000 # number of overall miss cycles
2577system.l2c.overall_miss_latency::cpu1.inst 7767000 # number of overall miss cycles
2578system.l2c.overall_miss_latency::cpu1.data 2384500 # number of overall miss cycles
2579system.l2c.overall_miss_latency::cpu2.inst 1841000 # number of overall miss cycles
2580system.l2c.overall_miss_latency::cpu2.data 1774500 # number of overall miss cycles
2581system.l2c.overall_miss_latency::cpu3.inst 2001000 # number of overall miss cycles
2582system.l2c.overall_miss_latency::cpu3.data 1187000 # number of overall miss cycles
2583system.l2c.overall_miss_latency::total 63689000 # number of overall miss cycles

2552system.l2c.overall_misses::cpu2.data 14 # number of overall misses
2553system.l2c.overall_misses::cpu3.inst 13 # number of overall misses
2554system.l2c.overall_misses::cpu3.data 15 # number of overall misses
2555system.l2c.overall_misses::total 729 # number of overall misses
2556system.l2c.ReadExReq_miss_latency::cpu0.data 7962500 # number of ReadExReq miss cycles
2557system.l2c.ReadExReq_miss_latency::cpu1.data 1106000 # number of ReadExReq miss cycles
2558system.l2c.ReadExReq_miss_latency::cpu2.data 1022500 # number of ReadExReq miss cycles
2559system.l2c.ReadExReq_miss_latency::cpu3.data 1199500 # number of ReadExReq miss cycles
2560system.l2c.ReadExReq_miss_latency::total 11290500 # number of ReadExReq miss cycles
2561system.l2c.ReadCleanReq_miss_latency::cpu0.inst 32133500 # number of ReadCleanReq miss cycles
2562system.l2c.ReadCleanReq_miss_latency::cpu1.inst 8531500 # number of ReadCleanReq miss cycles
2563system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2347000 # number of ReadCleanReq miss cycles
2564system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2460500 # number of ReadCleanReq miss cycles
2565system.l2c.ReadCleanReq_miss_latency::total 45472500 # number of ReadCleanReq miss cycles
2566system.l2c.ReadSharedReq_miss_latency::cpu0.data 6902500 # number of ReadSharedReq miss cycles
2567system.l2c.ReadSharedReq_miss_latency::cpu1.data 767000 # number of ReadSharedReq miss cycles
2568system.l2c.ReadSharedReq_miss_latency::cpu2.data 179000 # number of ReadSharedReq miss cycles
2569system.l2c.ReadSharedReq_miss_latency::cpu3.data 339000 # number of ReadSharedReq miss cycles
2570system.l2c.ReadSharedReq_miss_latency::total 8187500 # number of ReadSharedReq miss cycles
2571system.l2c.demand_miss_latency::cpu0.inst 32133500 # number of demand (read+write) miss cycles
2572system.l2c.demand_miss_latency::cpu0.data 14865000 # number of demand (read+write) miss cycles
2573system.l2c.demand_miss_latency::cpu1.inst 8531500 # number of demand (read+write) miss cycles
2574system.l2c.demand_miss_latency::cpu1.data 1873000 # number of demand (read+write) miss cycles
2575system.l2c.demand_miss_latency::cpu2.inst 2347000 # number of demand (read+write) miss cycles
2576system.l2c.demand_miss_latency::cpu2.data 1201500 # number of demand (read+write) miss cycles
2577system.l2c.demand_miss_latency::cpu3.inst 2460500 # number of demand (read+write) miss cycles
2578system.l2c.demand_miss_latency::cpu3.data 1538500 # number of demand (read+write) miss cycles
2579system.l2c.demand_miss_latency::total 64950500 # number of demand (read+write) miss cycles
2580system.l2c.overall_miss_latency::cpu0.inst 32133500 # number of overall miss cycles
2581system.l2c.overall_miss_latency::cpu0.data 14865000 # number of overall miss cycles
2582system.l2c.overall_miss_latency::cpu1.inst 8531500 # number of overall miss cycles
2583system.l2c.overall_miss_latency::cpu1.data 1873000 # number of overall miss cycles
2584system.l2c.overall_miss_latency::cpu2.inst 2347000 # number of overall miss cycles
2585system.l2c.overall_miss_latency::cpu2.data 1201500 # number of overall miss cycles
2586system.l2c.overall_miss_latency::cpu3.inst 2460500 # number of overall miss cycles
2587system.l2c.overall_miss_latency::cpu3.data 1538500 # number of overall miss cycles
2588system.l2c.overall_miss_latency::total 64950500 # number of overall miss cycles

2584system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
2585system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)

2589system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
2590system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)

2586system.l2c.WritebackClean_accesses::writebacks 730 # number of WritebackClean accesses(hits+misses)
2587system.l2c.WritebackClean_accesses::total 730 # number of WritebackClean accesses(hits+misses)
2588system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses)
2589system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses)
2590system.l2c.UpgradeReq_accesses::cpu2.data 25 # number of UpgradeReq accesses(hits+misses)
2591system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
2592system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses)

2591system.l2c.WritebackClean_accesses::writebacks 757 # number of WritebackClean accesses(hits+misses)
2592system.l2c.WritebackClean_accesses::total 757 # number of WritebackClean accesses(hits+misses)
2593system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses)
2594system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses)
2595system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
2596system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses)
2597system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses)

2593system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2594system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2595system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2596system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2597system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2598system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2599system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2600system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2601system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2602system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2598system.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses)
2599system.l2c.ReadCleanReq_accesses::cpu1.inst 690 # number of ReadCleanReq accesses(hits+misses)
2600system.l2c.ReadCleanReq_accesses::cpu2.inst 702 # number of ReadCleanReq accesses(hits+misses)
2601system.l2c.ReadCleanReq_accesses::cpu3.inst 724 # number of ReadCleanReq accesses(hits+misses)
2602system.l2c.ReadCleanReq_accesses::total 2812 # number of ReadCleanReq accesses(hits+misses)

2603system.l2c.ReadCleanReq_accesses::cpu0.inst 697 # number of ReadCleanReq accesses(hits+misses)
2604system.l2c.ReadCleanReq_accesses::cpu1.inst 733 # number of ReadCleanReq accesses(hits+misses)
2605system.l2c.ReadCleanReq_accesses::cpu2.inst 687 # number of ReadCleanReq accesses(hits+misses)
2606system.l2c.ReadCleanReq_accesses::cpu3.inst 712 # number of ReadCleanReq accesses(hits+misses)
2607system.l2c.ReadCleanReq_accesses::total 2829 # number of ReadCleanReq accesses(hits+misses)

2603system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses)
2604system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses)

2608system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses)
2609system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses)

2605system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses)
2606system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses)

2610system.l2c.ReadSharedReq_accesses::cpu2.data 13 # number of ReadSharedReq accesses(hits+misses)
2611system.l2c.ReadSharedReq_accesses::cpu3.data 14 # number of ReadSharedReq accesses(hits+misses)

2607system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses)

2612system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses)

2608system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses

2613system.l2c.demand_accesses::cpu0.inst 697 # number of demand (read+write) accesses

2609system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses

2614system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses

2610system.l2c.demand_accesses::cpu1.inst 690 # number of demand (read+write) accesses

2615system.l2c.demand_accesses::cpu1.inst 733 # number of demand (read+write) accesses

2611system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses

2616system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses

2612system.l2c.demand_accesses::cpu2.inst 702 # number of demand (read+write) accesses
2613system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
2614system.l2c.demand_accesses::cpu3.inst 724 # number of demand (read+write) accesses
2615system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
2616system.l2c.demand_accesses::total 3065 # number of demand (read+write) accesses
2617system.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses

2617system.l2c.demand_accesses::cpu2.inst 687 # number of demand (read+write) accesses
2618system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
2619system.l2c.demand_accesses::cpu3.inst 712 # number of demand (read+write) accesses
2620system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses
2621system.l2c.demand_accesses::total 3082 # number of demand (read+write) accesses
2622system.l2c.overall_accesses::cpu0.inst 697 # number of overall (read+write) accesses

2618system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses

2623system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses

2619system.l2c.overall_accesses::cpu1.inst 690 # number of overall (read+write) accesses

2624system.l2c.overall_accesses::cpu1.inst 733 # number of overall (read+write) accesses

2620system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses

2625system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses

2621system.l2c.overall_accesses::cpu2.inst 702 # number of overall (read+write) accesses
2622system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
2623system.l2c.overall_accesses::cpu3.inst 724 # number of overall (read+write) accesses
2624system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
2625system.l2c.overall_accesses::total 3065 # number of overall (read+write) accesses

2626system.l2c.overall_accesses::cpu2.inst 687 # number of overall (read+write) accesses
2627system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
2628system.l2c.overall_accesses::cpu3.inst 712 # number of overall (read+write) accesses
2629system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses
2630system.l2c.overall_accesses::total 3082 # number of overall (read+write) accesses

2626system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2627system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2628system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2629system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2630system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2631system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2632system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2633system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2634system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2635system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2631system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.543103 # miss rate for ReadCleanReq accesses
2632system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.139130 # miss rate for ReadCleanReq accesses
2633system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.032764 # miss rate for ReadCleanReq accesses
2634system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.023481 # miss rate for ReadCleanReq accesses
2635system.l2c.ReadCleanReq_miss_rate::total 0.182788 # miss rate for ReadCleanReq accesses

2636system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.539455 # miss rate for ReadCleanReq accesses
2637system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.130969 # miss rate for ReadCleanReq accesses
2638system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.033479 # miss rate for ReadCleanReq accesses
2639system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018258 # miss rate for ReadCleanReq accesses
2640system.l2c.ReadCleanReq_miss_rate::total 0.179569 # miss rate for ReadCleanReq accesses

2636system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses
2637system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses

2641system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses
2642system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses

2638system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses
2639system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses

2643system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadSharedReq accesses
2644system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.214286 # miss rate for ReadSharedReq accesses

2640system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses

2645system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses

2641system.l2c.demand_miss_rate::cpu0.inst 0.543103 # miss rate for demand accesses

2646system.l2c.demand_miss_rate::cpu0.inst 0.539455 # miss rate for demand accesses

2642system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses

2647system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses

2643system.l2c.demand_miss_rate::cpu1.inst 0.139130 # miss rate for demand accesses

2648system.l2c.demand_miss_rate::cpu1.inst 0.130969 # miss rate for demand accesses

2644system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses

2649system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses

2645system.l2c.demand_miss_rate::cpu2.inst 0.032764 # miss rate for demand accesses
2646system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses
2647system.l2c.demand_miss_rate::cpu3.inst 0.023481 # miss rate for demand accesses
2648system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses
2649system.l2c.demand_miss_rate::total 0.239804 # miss rate for demand accesses
2650system.l2c.overall_miss_rate::cpu0.inst 0.543103 # miss rate for overall accesses

2650system.l2c.demand_miss_rate::cpu2.inst 0.033479 # miss rate for demand accesses
2651system.l2c.demand_miss_rate::cpu2.data 0.560000 # miss rate for demand accesses
2652system.l2c.demand_miss_rate::cpu3.inst 0.018258 # miss rate for demand accesses
2653system.l2c.demand_miss_rate::cpu3.data 0.576923 # miss rate for demand accesses
2654system.l2c.demand_miss_rate::total 0.236535 # miss rate for demand accesses
2655system.l2c.overall_miss_rate::cpu0.inst 0.539455 # miss rate for overall accesses

2651system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses

2656system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses

2652system.l2c.overall_miss_rate::cpu1.inst 0.139130 # miss rate for overall accesses

2657system.l2c.overall_miss_rate::cpu1.inst 0.130969 # miss rate for overall accesses

2653system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses

2658system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses

2654system.l2c.overall_miss_rate::cpu2.inst 0.032764 # miss rate for overall accesses
2655system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses
2656system.l2c.overall_miss_rate::cpu3.inst 0.023481 # miss rate for overall accesses
2657system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses
2658system.l2c.overall_miss_rate::total 0.239804 # miss rate for overall accesses
2659system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84702.127660 # average ReadExReq miss latency
2660system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84000 # average ReadExReq miss latency
2661system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency
2662system.l2c.ReadExReq_avg_miss_latency::cpu3.data 83958.333333 # average ReadExReq miss latency
2663system.l2c.ReadExReq_avg_miss_latency::total 88145.038168 # average ReadExReq miss latency
2664system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84775.132275 # average ReadCleanReq miss latency
2665system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80906.250000 # average ReadCleanReq miss latency
2666system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 80043.478261 # average ReadCleanReq miss latency
2667system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 117705.882353 # average ReadCleanReq miss latency
2668system.l2c.ReadCleanReq_avg_miss_latency::total 84929.961089 # average ReadCleanReq miss latency
2669system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88513.157895 # average ReadSharedReq miss latency
2670system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143611.111111 # average ReadSharedReq miss latency
2671system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96333.333333 # average ReadSharedReq miss latency
2672system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 89750 # average ReadSharedReq miss latency
2673system.l2c.ReadSharedReq_avg_miss_latency::total 94311.111111 # average ReadSharedReq miss latency
2674system.l2c.demand_avg_miss_latency::cpu0.inst 84775.132275 # average overall miss latency
2675system.l2c.demand_avg_miss_latency::cpu0.data 86405.882353 # average overall miss latency
2676system.l2c.demand_avg_miss_latency::cpu1.inst 80906.250000 # average overall miss latency
2677system.l2c.demand_avg_miss_latency::cpu1.data 108386.363636 # average overall miss latency
2678system.l2c.demand_avg_miss_latency::cpu2.inst 80043.478261 # average overall miss latency
2679system.l2c.demand_avg_miss_latency::cpu2.data 118300 # average overall miss latency
2680system.l2c.demand_avg_miss_latency::cpu3.inst 117705.882353 # average overall miss latency
2681system.l2c.demand_avg_miss_latency::cpu3.data 84785.714286 # average overall miss latency
2682system.l2c.demand_avg_miss_latency::total 86651.700680 # average overall miss latency
2683system.l2c.overall_avg_miss_latency::cpu0.inst 84775.132275 # average overall miss latency
2684system.l2c.overall_avg_miss_latency::cpu0.data 86405.882353 # average overall miss latency
2685system.l2c.overall_avg_miss_latency::cpu1.inst 80906.250000 # average overall miss latency
2686system.l2c.overall_avg_miss_latency::cpu1.data 108386.363636 # average overall miss latency
2687system.l2c.overall_avg_miss_latency::cpu2.inst 80043.478261 # average overall miss latency
2688system.l2c.overall_avg_miss_latency::cpu2.data 118300 # average overall miss latency
2689system.l2c.overall_avg_miss_latency::cpu3.inst 117705.882353 # average overall miss latency
2690system.l2c.overall_avg_miss_latency::cpu3.data 84785.714286 # average overall miss latency
2691system.l2c.overall_avg_miss_latency::total 86651.700680 # average overall miss latency

2659system.l2c.overall_miss_rate::cpu2.inst 0.033479 # miss rate for overall accesses
2660system.l2c.overall_miss_rate::cpu2.data 0.560000 # miss rate for overall accesses
2661system.l2c.overall_miss_rate::cpu3.inst 0.018258 # miss rate for overall accesses
2662system.l2c.overall_miss_rate::cpu3.data 0.576923 # miss rate for overall accesses
2663system.l2c.overall_miss_rate::total 0.236535 # miss rate for overall accesses
2664system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84707.446809 # average ReadExReq miss latency
2665system.l2c.ReadExReq_avg_miss_latency::cpu1.data 85076.923077 # average ReadExReq miss latency
2666system.l2c.ReadExReq_avg_miss_latency::cpu2.data 85208.333333 # average ReadExReq miss latency
2667system.l2c.ReadExReq_avg_miss_latency::cpu3.data 99958.333333 # average ReadExReq miss latency
2668system.l2c.ReadExReq_avg_miss_latency::total 86187.022901 # average ReadExReq miss latency
2669system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85461.436170 # average ReadCleanReq miss latency
2670system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 88869.791667 # average ReadCleanReq miss latency
2671system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 102043.478261 # average ReadCleanReq miss latency
2672system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 189269.230769 # average ReadCleanReq miss latency
2673system.l2c.ReadCleanReq_avg_miss_latency::total 89512.795276 # average ReadCleanReq miss latency
2674system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90822.368421 # average ReadSharedReq miss latency
2675system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85222.222222 # average ReadSharedReq miss latency
2676system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 89500 # average ReadSharedReq miss latency
2677system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 113000 # average ReadSharedReq miss latency
2678system.l2c.ReadSharedReq_avg_miss_latency::total 90972.222222 # average ReadSharedReq miss latency
2679system.l2c.demand_avg_miss_latency::cpu0.inst 85461.436170 # average overall miss latency
2680system.l2c.demand_avg_miss_latency::cpu0.data 87441.176471 # average overall miss latency
2681system.l2c.demand_avg_miss_latency::cpu1.inst 88869.791667 # average overall miss latency
2682system.l2c.demand_avg_miss_latency::cpu1.data 85136.363636 # average overall miss latency
2683system.l2c.demand_avg_miss_latency::cpu2.inst 102043.478261 # average overall miss latency
2684system.l2c.demand_avg_miss_latency::cpu2.data 85821.428571 # average overall miss latency
2685system.l2c.demand_avg_miss_latency::cpu3.inst 189269.230769 # average overall miss latency
2686system.l2c.demand_avg_miss_latency::cpu3.data 102566.666667 # average overall miss latency
2687system.l2c.demand_avg_miss_latency::total 89095.336077 # average overall miss latency
2688system.l2c.overall_avg_miss_latency::cpu0.inst 85461.436170 # average overall miss latency
2689system.l2c.overall_avg_miss_latency::cpu0.data 87441.176471 # average overall miss latency
2690system.l2c.overall_avg_miss_latency::cpu1.inst 88869.791667 # average overall miss latency
2691system.l2c.overall_avg_miss_latency::cpu1.data 85136.363636 # average overall miss latency
2692system.l2c.overall_avg_miss_latency::cpu2.inst 102043.478261 # average overall miss latency
2693system.l2c.overall_avg_miss_latency::cpu2.data 85821.428571 # average overall miss latency
2694system.l2c.overall_avg_miss_latency::cpu3.inst 189269.230769 # average overall miss latency
2695system.l2c.overall_avg_miss_latency::cpu3.data 102566.666667 # average overall miss latency
2696system.l2c.overall_avg_miss_latency::total 89095.336077 # average overall miss latency

2692system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2693system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2694system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2695system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2696system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2697system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2698system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits
2699system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits

--- 10 unchanged lines hidden (view full) ---

2710system.l2c.overall_mshr_hits::cpu2.inst 9 # number of overall MSHR hits
2711system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2712system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
2713system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2714system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
2715system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2716system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2717system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses

2697system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2698system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2699system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2700system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2701system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2702system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2703system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits
2704system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits

--- 10 unchanged lines hidden (view full) ---

2715system.l2c.overall_mshr_hits::cpu2.inst 9 # number of overall MSHR hits
2716system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2717system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
2718system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
2719system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
2720system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
2721system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2722system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses

2718system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses

2723system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 374 # number of ReadCleanReq MSHR misses

2719system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses
2720system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses

2724system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses
2725system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses

2721system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 14 # number of ReadCleanReq MSHR misses
2722system.l2c.ReadCleanReq_mshr_misses::total 496 # number of ReadCleanReq MSHR misses

2726system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 10 # number of ReadCleanReq MSHR misses
2727system.l2c.ReadCleanReq_mshr_misses::total 490 # number of ReadCleanReq MSHR misses

2723system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses
2724system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses

2728system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses
2729system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses

2725system.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses
2726system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses

2730system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2 # number of ReadSharedReq MSHR misses
2731system.l2c.ReadSharedReq_mshr_misses::cpu3.data 3 # number of ReadSharedReq MSHR misses

2727system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses

2732system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses

2728system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses

2733system.l2c.demand_mshr_misses::cpu0.inst 374 # number of demand (read+write) MSHR misses

2729system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses
2730system.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses
2731system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
2732system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses

2734system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses
2735system.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses
2736system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses
2737system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses

2733system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses
2734system.l2c.demand_mshr_misses::cpu3.inst 14 # number of demand (read+write) MSHR misses
2735system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses
2736system.l2c.demand_mshr_misses::total 717 # number of demand (read+write) MSHR misses
2737system.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses

2738system.l2c.demand_mshr_misses::cpu2.data 14 # number of demand (read+write) MSHR misses
2739system.l2c.demand_mshr_misses::cpu3.inst 10 # number of demand (read+write) MSHR misses
2740system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
2741system.l2c.demand_mshr_misses::total 711 # number of demand (read+write) MSHR misses
2742system.l2c.overall_mshr_misses::cpu0.inst 374 # number of overall MSHR misses

2738system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses
2739system.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses
2740system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
2741system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses

2743system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses
2744system.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses
2745system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses
2746system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses

2742system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses
2743system.l2c.overall_mshr_misses::cpu3.inst 14 # number of overall MSHR misses
2744system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses
2745system.l2c.overall_mshr_misses::total 717 # number of overall MSHR misses
2746system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7022000 # number of ReadExReq MSHR miss cycles
2747system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 962000 # number of ReadExReq MSHR miss cycles
2748system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1365500 # number of ReadExReq MSHR miss cycles
2749system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 887500 # number of ReadExReq MSHR miss cycles
2750system.l2c.ReadExReq_mshr_miss_latency::total 10237000 # number of ReadExReq MSHR miss cycles
2751system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 28190500 # number of ReadCleanReq MSHR miss cycles
2752system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6632500 # number of ReadCleanReq MSHR miss cycles
2753system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1096000 # number of ReadCleanReq MSHR miss cycles
2754system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1627000 # number of ReadCleanReq MSHR miss cycles
2755system.l2c.ReadCleanReq_mshr_miss_latency::total 37546000 # number of ReadCleanReq MSHR miss cycles
2756system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5967000 # number of ReadSharedReq MSHR miss cycles
2757system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1202500 # number of ReadSharedReq MSHR miss cycles
2758system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 259000 # number of ReadSharedReq MSHR miss cycles
2759system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 159500 # number of ReadSharedReq MSHR miss cycles
2760system.l2c.ReadSharedReq_mshr_miss_latency::total 7588000 # number of ReadSharedReq MSHR miss cycles
2761system.l2c.demand_mshr_miss_latency::cpu0.inst 28190500 # number of demand (read+write) MSHR miss cycles
2762system.l2c.demand_mshr_miss_latency::cpu0.data 12989000 # number of demand (read+write) MSHR miss cycles
2763system.l2c.demand_mshr_miss_latency::cpu1.inst 6632500 # number of demand (read+write) MSHR miss cycles
2764system.l2c.demand_mshr_miss_latency::cpu1.data 2164500 # number of demand (read+write) MSHR miss cycles
2765system.l2c.demand_mshr_miss_latency::cpu2.inst 1096000 # number of demand (read+write) MSHR miss cycles
2766system.l2c.demand_mshr_miss_latency::cpu2.data 1624500 # number of demand (read+write) MSHR miss cycles
2767system.l2c.demand_mshr_miss_latency::cpu3.inst 1627000 # number of demand (read+write) MSHR miss cycles
2768system.l2c.demand_mshr_miss_latency::cpu3.data 1047000 # number of demand (read+write) MSHR miss cycles
2769system.l2c.demand_mshr_miss_latency::total 55371000 # number of demand (read+write) MSHR miss cycles
2770system.l2c.overall_mshr_miss_latency::cpu0.inst 28190500 # number of overall MSHR miss cycles
2771system.l2c.overall_mshr_miss_latency::cpu0.data 12989000 # number of overall MSHR miss cycles
2772system.l2c.overall_mshr_miss_latency::cpu1.inst 6632500 # number of overall MSHR miss cycles
2773system.l2c.overall_mshr_miss_latency::cpu1.data 2164500 # number of overall MSHR miss cycles
2774system.l2c.overall_mshr_miss_latency::cpu2.inst 1096000 # number of overall MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::cpu2.data 1624500 # number of overall MSHR miss cycles
2776system.l2c.overall_mshr_miss_latency::cpu3.inst 1627000 # number of overall MSHR miss cycles
2777system.l2c.overall_mshr_miss_latency::cpu3.data 1047000 # number of overall MSHR miss cycles
2778system.l2c.overall_mshr_miss_latency::total 55371000 # number of overall MSHR miss cycles

2747system.l2c.overall_mshr_misses::cpu2.data 14 # number of overall MSHR misses
2748system.l2c.overall_mshr_misses::cpu3.inst 10 # number of overall MSHR misses
2749system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
2750system.l2c.overall_mshr_misses::total 711 # number of overall MSHR misses
2751system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7022500 # number of ReadExReq MSHR miss cycles
2752system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 976000 # number of ReadExReq MSHR miss cycles
2753system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 902500 # number of ReadExReq MSHR miss cycles
2754system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1079500 # number of ReadExReq MSHR miss cycles
2755system.l2c.ReadExReq_mshr_miss_latency::total 9980500 # number of ReadExReq MSHR miss cycles
2756system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 28295000 # number of ReadCleanReq MSHR miss cycles
2757system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 7392500 # number of ReadCleanReq MSHR miss cycles
2758system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1074500 # number of ReadCleanReq MSHR miss cycles
2759system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1591500 # number of ReadCleanReq MSHR miss cycles
2760system.l2c.ReadCleanReq_mshr_miss_latency::total 38353500 # number of ReadCleanReq MSHR miss cycles
2761system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 6142500 # number of ReadSharedReq MSHR miss cycles
2762system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 677000 # number of ReadSharedReq MSHR miss cycles
2763system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 159000 # number of ReadSharedReq MSHR miss cycles
2764system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 309000 # number of ReadSharedReq MSHR miss cycles
2765system.l2c.ReadSharedReq_mshr_miss_latency::total 7287500 # number of ReadSharedReq MSHR miss cycles
2766system.l2c.demand_mshr_miss_latency::cpu0.inst 28295000 # number of demand (read+write) MSHR miss cycles
2767system.l2c.demand_mshr_miss_latency::cpu0.data 13165000 # number of demand (read+write) MSHR miss cycles
2768system.l2c.demand_mshr_miss_latency::cpu1.inst 7392500 # number of demand (read+write) MSHR miss cycles
2769system.l2c.demand_mshr_miss_latency::cpu1.data 1653000 # number of demand (read+write) MSHR miss cycles
2770system.l2c.demand_mshr_miss_latency::cpu2.inst 1074500 # number of demand (read+write) MSHR miss cycles
2771system.l2c.demand_mshr_miss_latency::cpu2.data 1061500 # number of demand (read+write) MSHR miss cycles
2772system.l2c.demand_mshr_miss_latency::cpu3.inst 1591500 # number of demand (read+write) MSHR miss cycles
2773system.l2c.demand_mshr_miss_latency::cpu3.data 1388500 # number of demand (read+write) MSHR miss cycles
2774system.l2c.demand_mshr_miss_latency::total 55621500 # number of demand (read+write) MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::cpu0.inst 28295000 # number of overall MSHR miss cycles
2776system.l2c.overall_mshr_miss_latency::cpu0.data 13165000 # number of overall MSHR miss cycles
2777system.l2c.overall_mshr_miss_latency::cpu1.inst 7392500 # number of overall MSHR miss cycles
2778system.l2c.overall_mshr_miss_latency::cpu1.data 1653000 # number of overall MSHR miss cycles
2779system.l2c.overall_mshr_miss_latency::cpu2.inst 1074500 # number of overall MSHR miss cycles
2780system.l2c.overall_mshr_miss_latency::cpu2.data 1061500 # number of overall MSHR miss cycles
2781system.l2c.overall_mshr_miss_latency::cpu3.inst 1591500 # number of overall MSHR miss cycles
2782system.l2c.overall_mshr_miss_latency::cpu3.data 1388500 # number of overall MSHR miss cycles
2783system.l2c.overall_mshr_miss_latency::total 55621500 # number of overall MSHR miss cycles

2779system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2780system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2781system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2782system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2783system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2784system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2785system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2786system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2787system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2788system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2784system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses
2785system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for ReadCleanReq accesses
2786system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for ReadCleanReq accesses
2787system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for ReadCleanReq accesses
2788system.l2c.ReadCleanReq_mshr_miss_rate::total 0.176387 # mshr miss rate for ReadCleanReq accesses

2789system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for ReadCleanReq accesses
2790system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for ReadCleanReq accesses
2791system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for ReadCleanReq accesses
2792system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for ReadCleanReq accesses
2793system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173206 # mshr miss rate for ReadCleanReq accesses

2789system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses
2790system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses

2794system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses
2795system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses

2791system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses
2792system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses

2796system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadSharedReq accesses
2797system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286 # mshr miss rate for ReadSharedReq accesses

2793system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses

2798system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses

2794system.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses

2799system.l2c.demand_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for demand accesses

2795system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses

2800system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses

2796system.l2c.demand_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for demand accesses

2801system.l2c.demand_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for demand accesses

2797system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses

2802system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses

2798system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for demand accesses
2799system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses
2800system.l2c.demand_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for demand accesses
2801system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses
2802system.l2c.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses
2803system.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses

2803system.l2c.demand_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for demand accesses
2804system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for demand accesses
2805system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for demand accesses
2806system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for demand accesses
2807system.l2c.demand_mshr_miss_rate::total 0.230694 # mshr miss rate for demand accesses
2808system.l2c.overall_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for overall accesses

2804system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses

2809system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses

2805system.l2c.overall_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for overall accesses

2810system.l2c.overall_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for overall accesses

2806system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses

2811system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses

2807system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for overall accesses
2808system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses
2809system.l2c.overall_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for overall accesses
2810system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses
2811system.l2c.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses
2812system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74702.127660 # average ReadExReq mshr miss latency
2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74000 # average ReadExReq mshr miss latency
2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency
2815system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 73958.333333 # average ReadExReq mshr miss latency
2816system.l2c.ReadExReq_avg_mshr_miss_latency::total 78145.038168 # average ReadExReq mshr miss latency
2817system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average ReadCleanReq mshr miss latency
2818system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average ReadCleanReq mshr miss latency
2819system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average ReadCleanReq mshr miss latency
2820system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average ReadCleanReq mshr miss latency
2821system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75697.580645 # average ReadCleanReq mshr miss latency
2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78513.157895 # average ReadSharedReq mshr miss latency
2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133611.111111 # average ReadSharedReq mshr miss latency
2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86333.333333 # average ReadSharedReq mshr miss latency
2825system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79750 # average ReadSharedReq mshr miss latency
2826system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84311.111111 # average ReadSharedReq mshr miss latency
2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency
2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency
2829system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency
2830system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency
2831system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency
2832system.l2c.demand_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency
2833system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency
2834system.l2c.demand_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency
2835system.l2c.demand_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency
2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency
2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency
2838system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency
2839system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency
2840system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency
2841system.l2c.overall_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency
2842system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency
2843system.l2c.overall_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency
2844system.l2c.overall_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency
2845system.membus.snoop_filter.tot_requests 969 # Total number of requests made to the snoop filter.
2846system.membus.snoop_filter.hit_single_requests 253 # Number of requests hitting in the snoop filter with a single holder of the requested data.

2812system.l2c.overall_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for overall accesses
2813system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for overall accesses
2814system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for overall accesses
2815system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for overall accesses
2816system.l2c.overall_mshr_miss_rate::total 0.230694 # mshr miss rate for overall accesses
2817system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74707.446809 # average ReadExReq mshr miss latency
2818system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75076.923077 # average ReadExReq mshr miss latency
2819system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75208.333333 # average ReadExReq mshr miss latency
2820system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89958.333333 # average ReadExReq mshr miss latency
2821system.l2c.ReadExReq_avg_mshr_miss_latency::total 76187.022901 # average ReadExReq mshr miss latency
2822system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average ReadCleanReq mshr miss latency
2823system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average ReadCleanReq mshr miss latency
2824system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 76750 # average ReadCleanReq mshr miss latency
2825system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 159150 # average ReadCleanReq mshr miss latency
2826system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78272.448980 # average ReadCleanReq mshr miss latency
2827system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80822.368421 # average ReadSharedReq mshr miss latency
2828system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75222.222222 # average ReadSharedReq mshr miss latency
2829system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79500 # average ReadSharedReq mshr miss latency
2830system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 103000 # average ReadSharedReq mshr miss latency
2831system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80972.222222 # average ReadSharedReq mshr miss latency
2832system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency
2833system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency
2834system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency
2835system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency
2836system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency
2837system.l2c.demand_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency
2838system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency
2839system.l2c.demand_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency
2840system.l2c.demand_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency
2841system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency
2842system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency
2843system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency
2844system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency
2845system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency
2846system.l2c.overall_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency
2847system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency
2848system.l2c.overall_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency
2849system.l2c.overall_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency
2850system.membus.snoop_filter.tot_requests 961 # Total number of requests made to the snoop filter.
2851system.membus.snoop_filter.hit_single_requests 251 # Number of requests hitting in the snoop filter with a single holder of the requested data.

2847system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2848system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2849system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2850system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2852system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2853system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2854system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2855system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2851system.membus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
2852system.membus.trans_dist::ReadResp 585 # Transaction distribution
2853system.membus.trans_dist::UpgradeReq 194 # Transaction distribution
2854system.membus.trans_dist::ReadExReq 190 # Transaction distribution

2856system.membus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
2857system.membus.trans_dist::ReadResp 579 # Transaction distribution
2858system.membus.trans_dist::UpgradeReq 193 # Transaction distribution
2859system.membus.trans_dist::ReadExReq 189 # Transaction distribution

2855system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2860system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2856system.membus.trans_dist::ReadSharedReq 585 # Transaction distribution
2857system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1685 # Packet count per connected master and slave (bytes)
2858system.membus.pkt_count::total 1685 # Packet count per connected master and slave (bytes)
2859system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45824 # Cumulative packet size per connected master and slave (bytes)
2860system.membus.pkt_size::total 45824 # Cumulative packet size per connected master and slave (bytes)
2861system.membus.snoops 253 # Total snoops (count)

2861system.membus.trans_dist::ReadSharedReq 579 # Transaction distribution
2862system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1671 # Packet count per connected master and slave (bytes)
2863system.membus.pkt_count::total 1671 # Packet count per connected master and slave (bytes)
2864system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45440 # Cumulative packet size per connected master and slave (bytes)
2865system.membus.pkt_size::total 45440 # Cumulative packet size per connected master and slave (bytes)
2866system.membus.snoops 251 # Total snoops (count)

2862system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

2867system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

2863system.membus.snoop_fanout::samples 969 # Request fanout histogram

2868system.membus.snoop_fanout::samples 961 # Request fanout histogram

2864system.membus.snoop_fanout::mean 0 # Request fanout histogram
2865system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2866system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2869system.membus.snoop_fanout::mean 0 # Request fanout histogram
2870system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2871system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2867system.membus.snoop_fanout::0 969 100.00% 100.00% # Request fanout histogram

2872system.membus.snoop_fanout::0 961 100.00% 100.00% # Request fanout histogram

2868system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2869system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2870system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2871system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2873system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2874system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2875system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2876system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2872system.membus.snoop_fanout::total 969 # Request fanout histogram
2873system.membus.reqLayer0.occupancy 889500 # Layer occupancy (ticks)

2877system.membus.snoop_fanout::total 961 # Request fanout histogram
2878system.membus.reqLayer0.occupancy 879000 # Layer occupancy (ticks)

2874system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)

2879system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)

2875system.membus.respLayer1.occupancy 3809250 # Layer occupancy (ticks)
2876system.membus.respLayer1.utilization 3.1 # Layer utilization (%)
2877system.toL2Bus.snoop_filter.tot_requests 6292 # Total number of requests made to the snoop filter.
2878system.toL2Bus.snoop_filter.hit_single_requests 1720 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2879system.toL2Bus.snoop_filter.hit_multi_requests 3250 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

2880system.membus.respLayer1.occupancy 3778500 # Layer occupancy (ticks)
2881system.membus.respLayer1.utilization 3.0 # Layer utilization (%)
2882system.toL2Bus.snoop_filter.tot_requests 6307 # Total number of requests made to the snoop filter.
2883system.toL2Bus.snoop_filter.hit_single_requests 1738 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2884system.toL2Bus.snoop_filter.hit_multi_requests 3220 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

2880system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2881system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2882system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2885system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2886system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2887system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2883system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states
2884system.toL2Bus.trans_dist::ReadResp 3503 # Transaction distribution
2885system.toL2Bus.trans_dist::ReadRespWithInvalidate 8 # Transaction distribution

2888system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states
2889system.toL2Bus.trans_dist::ReadResp 3510 # Transaction distribution
2890system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution

2886system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution

2891system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution

2887system.toL2Bus.trans_dist::WritebackClean 2099 # Transaction distribution

2892system.toL2Bus.trans_dist::WritebackClean 2115 # Transaction distribution

2888system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution

2893system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution

2889system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution
2890system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution
2891system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution
2892system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution
2893system.toL2Bus.trans_dist::ReadCleanReq 2812 # Transaction distribution
2894system.toL2Bus.trans_dist::ReadSharedReq 700 # Transaction distribution

2894system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
2895system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
2896system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution
2897system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution
2898system.toL2Bus.trans_dist::ReadCleanReq 2829 # Transaction distribution
2899system.toL2Bus.trans_dist::ReadSharedReq 685 # Transaction distribution

2895system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes)

2900system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes)

2896system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 599 # Packet count per connected master and slave (bytes)
2897system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1936 # Packet count per connected master and slave (bytes)
2898system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes)
2899system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1968 # Packet count per connected master and slave (bytes)
2900system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
2901system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2034 # Packet count per connected master and slave (bytes)
2902system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes)
2903system.toL2Bus.pkt_count::total 9446 # Packet count per connected master and slave (bytes)
2904system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes)

2901system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 594 # Packet count per connected master and slave (bytes)
2902system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes)
2903system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes)
2904system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1925 # Packet count per connected master and slave (bytes)
2905system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes)
2906system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1999 # Packet count per connected master and slave (bytes)
2907system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
2908system.toL2Bus.pkt_count::total 9472 # Packet count per connected master and slave (bytes)
2909system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69568 # Cumulative packet size per connected master and slave (bytes)

2905system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes)

2910system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes)

2906system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79744 # Cumulative packet size per connected master and slave (bytes)

2911system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes)

2907system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes)

2912system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes)

2908system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 81024 # Cumulative packet size per connected master and slave (bytes)
2909system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
2910system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83840 # Cumulative packet size per connected master and slave (bytes)
2911system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2912system.toL2Bus.pkt_size::total 330496 # Cumulative packet size per connected master and slave (bytes)
2913system.toL2Bus.snoops 1036 # Total snoops (count)
2914system.toL2Bus.snoopTraffic 53888 # Total snoop traffic (bytes)
2915system.toL2Bus.snoop_fanout::samples 4191 # Request fanout histogram
2916system.toL2Bus.snoop_fanout::mean 1.288475 # Request fanout histogram
2917system.toL2Bus.snoop_fanout::stdev 1.109326 # Request fanout histogram

2913system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79232 # Cumulative packet size per connected master and slave (bytes)
2914system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2915system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82368 # Cumulative packet size per connected master and slave (bytes)
2916system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
2917system.toL2Bus.pkt_size::total 332608 # Cumulative packet size per connected master and slave (bytes)
2918system.toL2Bus.snoops 1024 # Total snoops (count)
2919system.toL2Bus.snoopTraffic 53184 # Total snoop traffic (bytes)
2920system.toL2Bus.snoop_fanout::samples 4190 # Request fanout histogram
2921system.toL2Bus.snoop_fanout::mean 1.288067 # Request fanout histogram
2922system.toL2Bus.snoop_fanout::stdev 1.121770 # Request fanout histogram

2918system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2923system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2919system.toL2Bus.snoop_fanout::0 1322 31.54% 31.54% # Request fanout histogram
2920system.toL2Bus.snoop_fanout::1 1164 27.77% 59.32% # Request fanout histogram
2921system.toL2Bus.snoop_fanout::2 879 20.97% 80.29% # Request fanout histogram
2922system.toL2Bus.snoop_fanout::3 826 19.71% 100.00% # Request fanout histogram

2924system.toL2Bus.snoop_fanout::0 1349 32.20% 32.20% # Request fanout histogram
2925system.toL2Bus.snoop_fanout::1 1142 27.26% 59.45% # Request fanout histogram
2926system.toL2Bus.snoop_fanout::2 842 20.10% 79.55% # Request fanout histogram
2927system.toL2Bus.snoop_fanout::3 857 20.45% 100.00% # Request fanout histogram

2923system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2924system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
2925system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
2926system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2927system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2928system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2929system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2930system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

2928system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2929system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
2930system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
2931system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2932system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2933system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2934system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2935system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

2931system.toL2Bus.snoop_fanout::total 4191 # Request fanout histogram
2932system.toL2Bus.reqLayer0.occupancy 5261968 # Layer occupancy (ticks)

2936system.toL2Bus.snoop_fanout::total 4190 # Request fanout histogram
2937system.toL2Bus.reqLayer0.occupancy 5284470 # Layer occupancy (ticks)

2933system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%)

2938system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%)

2934system.toL2Bus.respLayer0.occupancy 1043496 # Layer occupancy (ticks)

2939system.toL2Bus.respLayer0.occupancy 1044996 # Layer occupancy (ticks)

2935system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)

2940system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)

2936system.toL2Bus.respLayer1.occupancy 528992 # Layer occupancy (ticks)

2941system.toL2Bus.respLayer1.occupancy 522995 # Layer occupancy (ticks)

2937system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

2942system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

2938system.toL2Bus.respLayer2.occupancy 1037993 # Layer occupancy (ticks)
2939system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%)
2940system.toL2Bus.respLayer3.occupancy 434459 # Layer occupancy (ticks)

2943system.toL2Bus.respLayer2.occupancy 1103492 # Layer occupancy (ticks)
2944system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%)
2945system.toL2Bus.respLayer3.occupancy 425474 # Layer occupancy (ticks)

2941system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)

2946system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)

2942system.toL2Bus.respLayer4.occupancy 1056988 # Layer occupancy (ticks)

2947system.toL2Bus.respLayer4.occupancy 1034985 # Layer occupancy (ticks)

2943system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%)

2948system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%)

2944system.toL2Bus.respLayer5.occupancy 424982 # Layer occupancy (ticks)
2945system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
2946system.toL2Bus.respLayer6.occupancy 1087497 # Layer occupancy (ticks)

2949system.toL2Bus.respLayer5.occupancy 441461 # Layer occupancy (ticks)
2950system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
2951system.toL2Bus.respLayer6.occupancy 1070994 # Layer occupancy (ticks)

2947system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%)

2952system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%)

2948system.toL2Bus.respLayer7.occupancy 445966 # Layer occupancy (ticks)
2949system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)

2953system.toL2Bus.respLayer7.occupancy 421970 # Layer occupancy (ticks)
2954system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)