Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000125 # Number of seconds simulated
4sim_ticks 124523000 # Number of ticks simulated
5final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000124 # Number of seconds simulated
4sim_ticks 123936000 # Number of ticks simulated
5final_tick 123936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 143029 # Simulator instruction rate (inst/s)
8host_op_rate 143029 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 15434351 # Simulator tick rate (ticks/s)
10host_mem_usage 263456 # Number of bytes of host memory used
11host_seconds 8.07 # Real time elapsed on the host
12sim_insts 1153943 # Number of instructions simulated
13sim_ops 1153943 # Number of ops (including micro ops) simulated

7host_inst_rate 188054 # Simulator instruction rate (inst/s)
8host_op_rate 188053 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20091950 # Simulator tick rate (ticks/s)
10host_mem_usage 268856 # Number of bytes of host memory used
11host_seconds 6.17 # Real time elapsed on the host
12sim_insts 1159992 # Number of instructions simulated
13sim_ops 1159992 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory

16system.physmem.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 24064 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory

19system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory

19system.physmem.bytes_read::cpu1.inst 5696 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 1344 # Number of bytes read from this memory

21system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory

23system.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory

23system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory

24system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory

25system.physmem.bytes_read::total 45632 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory

25system.physmem.bytes_read::total 45376 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 24064 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 5696 # Number of instructions bytes read from this memory

28system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory

29system.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory

29system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory
31system.physmem.num_reads::cpu0.inst 376 # Number of read requests responded to by this memory

32system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory

33system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory

33system.physmem.num_reads::cpu1.inst 89 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu1.data 21 # Number of read requests responded to by this memory

35system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory

37system.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory

37system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory

38system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory

39system.physmem.num_reads::total 713 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.readReqs 713 # Number of read requests accepted

39system.physmem.num_reads::total 709 # Number of read requests responded to by this memory
40system.physmem.bw_read::cpu0.inst 194164730 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu0.data 87787245 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.inst 45959205 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu1.data 10844307 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.inst 7229538 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu2.data 7745933 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.inst 5163956 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu3.data 7229538 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::total 366124451 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu0.inst 194164730 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu1.inst 45959205 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu2.inst 7229538 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu3.inst 5163956 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 252517428 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_total::cpu0.inst 194164730 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu0.data 87787245 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.inst 45959205 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu1.data 10844307 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.inst 7229538 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu2.data 7745933 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.inst 5163956 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu3.data 7229538 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::total 366124451 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.readReqs 709 # Number of read requests accepted

64system.physmem.writeReqs 0 # Number of write requests accepted

65system.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue

65system.physmem.readBursts 709 # Number of DRAM read bursts, including those serviced by the write queue

66system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue

67system.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM

67system.physmem.bytesReadDRAM 45376 # Total number of bytes read from DRAM

68system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
69system.physmem.bytesWritten 0 # Total number of bytes written to DRAM

70system.physmem.bytesReadSys 45632 # Total read bytes from the system interface side

70system.physmem.bytesReadSys 45376 # Total read bytes from the system interface side

71system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
72system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
73system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
74system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
75system.physmem.perBankRdBursts::0 120 # Per bank write bursts

76system.physmem.perBankRdBursts::1 45 # Per bank write bursts

76system.physmem.perBankRdBursts::1 44 # Per bank write bursts

77system.physmem.perBankRdBursts::2 31 # Per bank write bursts
78system.physmem.perBankRdBursts::3 62 # Per bank write bursts
79system.physmem.perBankRdBursts::4 69 # Per bank write bursts
80system.physmem.perBankRdBursts::5 28 # Per bank write bursts
81system.physmem.perBankRdBursts::6 19 # Per bank write bursts
82system.physmem.perBankRdBursts::7 28 # Per bank write bursts
83system.physmem.perBankRdBursts::8 7 # Per bank write bursts
84system.physmem.perBankRdBursts::9 31 # Per bank write bursts
85system.physmem.perBankRdBursts::10 23 # Per bank write bursts
86system.physmem.perBankRdBursts::11 13 # Per bank write bursts

87system.physmem.perBankRdBursts::12 70 # Per bank write bursts
88system.physmem.perBankRdBursts::13 47 # Per bank write bursts

87system.physmem.perBankRdBursts::12 69 # Per bank write bursts
88system.physmem.perBankRdBursts::13 45 # Per bank write bursts

89system.physmem.perBankRdBursts::14 19 # Per bank write bursts
90system.physmem.perBankRdBursts::15 101 # Per bank write bursts
91system.physmem.perBankWrBursts::0 0 # Per bank write bursts
92system.physmem.perBankWrBursts::1 0 # Per bank write bursts
93system.physmem.perBankWrBursts::2 0 # Per bank write bursts
94system.physmem.perBankWrBursts::3 0 # Per bank write bursts
95system.physmem.perBankWrBursts::4 0 # Per bank write bursts
96system.physmem.perBankWrBursts::5 0 # Per bank write bursts

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101system.physmem.perBankWrBursts::10 0 # Per bank write bursts
102system.physmem.perBankWrBursts::11 0 # Per bank write bursts
103system.physmem.perBankWrBursts::12 0 # Per bank write bursts
104system.physmem.perBankWrBursts::13 0 # Per bank write bursts
105system.physmem.perBankWrBursts::14 0 # Per bank write bursts
106system.physmem.perBankWrBursts::15 0 # Per bank write bursts
107system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
108system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

109system.physmem.totGap 124288000 # Total gap between requests

109system.physmem.totGap 123701000 # Total gap between requests

110system.physmem.readPktSize::0 0 # Read request sizes (log2)
111system.physmem.readPktSize::1 0 # Read request sizes (log2)
112system.physmem.readPktSize::2 0 # Read request sizes (log2)
113system.physmem.readPktSize::3 0 # Read request sizes (log2)
114system.physmem.readPktSize::4 0 # Read request sizes (log2)
115system.physmem.readPktSize::5 0 # Read request sizes (log2)

116system.physmem.readPktSize::6 713 # Read request sizes (log2)

116system.physmem.readPktSize::6 709 # Read request sizes (log2)

117system.physmem.writePktSize::0 0 # Write request sizes (log2)
118system.physmem.writePktSize::1 0 # Write request sizes (log2)
119system.physmem.writePktSize::2 0 # Write request sizes (log2)
120system.physmem.writePktSize::3 0 # Write request sizes (log2)
121system.physmem.writePktSize::4 0 # Write request sizes (log2)
122system.physmem.writePktSize::5 0 # Write request sizes (log2)
123system.physmem.writePktSize::6 0 # Write request sizes (log2)

124system.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see

124system.physmem.rdQLenPdf::0 430 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::1 203 # What read queue length does an incoming req see

126system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see

--- 78 unchanged lines hidden (view full) ---

212system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see

220system.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation
221system.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation
224system.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation
234system.physmem.totQLat 6387250 # Total ticks spent queuing
235system.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 3565000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst

220system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation
221system.physmem.bytesPerActivate::mean 251.076923 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::gmean 166.451829 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::stdev 245.101340 # Bytes accessed per row activation
224system.physmem.bytesPerActivate::0-127 63 37.28% 37.28% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::128-255 39 23.08% 60.36% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::256-383 28 16.57% 76.92% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::384-511 13 7.69% 84.62% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::512-639 8 4.73% 89.35% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::640-767 8 4.73% 94.08% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::768-895 3 1.78% 95.86% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation
234system.physmem.totQLat 6766000 # Total ticks spent queuing
235system.physmem.totMemAccLat 20059750 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 3545000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 9543.02 # Average queueing delay per DRAM burst

238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

239system.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s

239system.physmem.avgMemAccLat 28293.02 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 366.12 # Average DRAM read bandwidth in MiByte/s

241system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

242system.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s

242system.physmem.avgRdBWSys 366.12 # Average system read bandwidth in MiByte/s

243system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
245system.physmem.busUtil 2.86 # Data bus utilization in percentage
246system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads
247system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
248system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
249system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

250system.physmem.readRowHits 530 # Number of row buffer hits during reads

250system.physmem.readRowHits 528 # Number of row buffer hits during reads

251system.physmem.writeRowHits 0 # Number of row buffer hits during writes

252system.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads

252system.physmem.readRowHitRate 74.47 # Row buffer hit rate for reads

253system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

254system.physmem.avgGap 174316.97 # Average gap between requests
255system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined
256system.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ)
257system.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ)
258system.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ)

254system.physmem.avgGap 174472.50 # Average gap between requests
255system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined
256system.physmem_0.actEnergy 831600 # Energy for activate commands per rank (pJ)
257system.physmem_0.preEnergy 453750 # Energy for precharge commands per rank (pJ)
258system.physmem_0.readEnergy 2925000 # Energy for read commands per rank (pJ)

259system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
260system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)

261system.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ)
262system.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ)
263system.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ)
264system.physmem_0.averagePower 749.845263 # Core power per rank (mW)
265system.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states

261system.physmem_0.actBackEnergy 49377960 # Energy for active background per rank (pJ)
262system.physmem_0.preBackEnergy 26918250 # Energy for precharge background per rank (pJ)
263system.physmem_0.totalEnergy 88134960 # Total energy per rank (pJ)
264system.physmem_0.averagePower 752.944352 # Core power per rank (mW)
265system.physmem_0.memoryStateTime::IDLE 47288500 # Time in different power states

266system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states
267system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

268system.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states

268system.physmem_0.memoryStateTime::ACT 68692500 # Time in different power states

269system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

270system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ)
271system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ)
272system.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ)

270system.physmem_1.actEnergy 408240 # Energy for activate commands per rank (pJ)
271system.physmem_1.preEnergy 222750 # Energy for precharge commands per rank (pJ)
272system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ)

273system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
274system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)

275system.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ)
276system.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ)
277system.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ)
278system.physmem_1.averagePower 743.076065 # Core power per rank (mW)
279system.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states

275system.physmem_1.actBackEnergy 42901335 # Energy for active background per rank (pJ)
276system.physmem_1.preBackEnergy 32591250 # Energy for precharge background per rank (pJ)
277system.physmem_1.totalEnergy 85935975 # Total energy per rank (pJ)
278system.physmem_1.averagePower 734.244489 # Core power per rank (mW)
279system.physmem_1.memoryStateTime::IDLE 54352750 # Time in different power states

280system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states
281system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

282system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states

282system.physmem_1.memoryStateTime::ACT 59251250 # Time in different power states

283system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

284system.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
285system.cpu0.branchPred.lookups 98739 # Number of BP lookups
286system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted
287system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect
288system.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups

284system.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
285system.cpu0.branchPred.lookups 98531 # Number of BP lookups
286system.cpu0.branchPred.condPredicted 94014 # Number of conditional branches predicted
287system.cpu0.branchPred.condIncorrect 1575 # Number of conditional branches incorrect
288system.cpu0.branchPred.BTBLookups 95788 # Number of BTB lookups

289system.cpu0.branchPred.BTBHits 0 # Number of BTB hits
290system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
291system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

292system.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target.

292system.cpu0.branchPred.usedRAS 1142 # Number of times the RAS was used to get a target.

293system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.

294system.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups.
295system.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits.
296system.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses.
297system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches.

294system.cpu0.branchPred.indirectLookups 95788 # Number of indirect predictor lookups.
295system.cpu0.branchPred.indirectHits 88519 # Number of indirect target hits.
296system.cpu0.branchPred.indirectMisses 7269 # Number of indirect misses.
297system.cpu0.branchPredindirectMispredicted 1054 # Number of mispredicted indirect branches.

298system.cpu_clk_domain.clock 500 # Clock period in ticks
299system.cpu0.workload.num_syscalls 89 # Number of system calls

300system.cpu0.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
301system.cpu0.numCycles 249047 # number of cpu cycles simulated

300system.cpu0.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
301system.cpu0.numCycles 247873 # number of cpu cycles simulated

302system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
303system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

304system.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss
305system.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed
306system.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered
307system.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken
308system.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked
309system.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing

304system.cpu0.fetch.icacheStallCycles 23367 # Number of cycles fetch is stalled on an Icache miss
305system.cpu0.fetch.Insts 581451 # Number of instructions fetch has processed
306system.cpu0.fetch.Branches 98531 # Number of branches that fetch encountered
307system.cpu0.fetch.predictedBranches 89661 # Number of branches that fetch has predicted taken
308system.cpu0.fetch.Cycles 193123 # Number of cycles fetch has run and was not squashing or blocked
309system.cpu0.fetch.SquashCycles 3449 # Number of cycles fetch has spent squashing

310system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb
311system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

312system.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps

312system.cpu0.fetch.PendingTrapStallCycles 2208 # Number of stall cycles due to pending traps

313system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR

314system.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched
315system.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed

314system.cpu0.fetch.CacheLines 7997 # Number of cache lines fetched
315system.cpu0.fetch.IcacheSquashes 861 # Number of outstanding Icache misses that were squashed

316system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed

317system.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total)
318system.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total)
319system.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total)

317system.cpu0.fetch.rateDist::samples 220500 # Number of instructions fetched each cycle (Total)
318system.cpu0.fetch.rateDist::mean 2.636966 # Number of instructions fetched each cycle (Total)
319system.cpu0.fetch.rateDist::stdev 2.261585 # Number of instructions fetched each cycle (Total)

320system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

321system.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total)
322system.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total)
323system.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total)
324system.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total)
325system.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total)
326system.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total)
327system.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total)
328system.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total)
329system.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total)

321system.cpu0.fetch.rateDist::0 33425 15.16% 15.16% # Number of instructions fetched each cycle (Total)
322system.cpu0.fetch.rateDist::1 91538 41.51% 56.67% # Number of instructions fetched each cycle (Total)
323system.cpu0.fetch.rateDist::2 694 0.31% 56.99% # Number of instructions fetched each cycle (Total)
324system.cpu0.fetch.rateDist::3 1015 0.46% 57.45% # Number of instructions fetched each cycle (Total)
325system.cpu0.fetch.rateDist::4 497 0.23% 57.67% # Number of instructions fetched each cycle (Total)
326system.cpu0.fetch.rateDist::5 87060 39.48% 97.16% # Number of instructions fetched each cycle (Total)
327system.cpu0.fetch.rateDist::6 731 0.33% 97.49% # Number of instructions fetched each cycle (Total)
328system.cpu0.fetch.rateDist::7 514 0.23% 97.72% # Number of instructions fetched each cycle (Total)
329system.cpu0.fetch.rateDist::8 5026 2.28% 100.00% # Number of instructions fetched each cycle (Total)

330system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
331system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
332system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

333system.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total)
334system.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle
335system.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle
336system.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle
337system.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked
338system.cpu0.decode.RunCycles 181778 # Number of cycles decode is running
339system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking
340system.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing
341system.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode
342system.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing
343system.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle
344system.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking
345system.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst
346system.cpu0.rename.RunCycles 181922 # Number of cycles rename is running
347system.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking
348system.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename

333system.cpu0.fetch.rateDist::total 220500 # Number of instructions fetched each cycle (Total)
334system.cpu0.fetch.branchRate 0.397506 # Number of branch fetches per cycle
335system.cpu0.fetch.rate 2.345762 # Number of inst fetches per cycle
336system.cpu0.decode.IdleCycles 17843 # Number of cycles decode is idle
337system.cpu0.decode.BlockedCycles 18591 # Number of cycles decode is blocked
338system.cpu0.decode.RunCycles 181526 # Number of cycles decode is running
339system.cpu0.decode.UnblockCycles 816 # Number of cycles decode is unblocking
340system.cpu0.decode.SquashCycles 1724 # Number of cycles decode is squashing
341system.cpu0.decode.DecodedInsts 563984 # Number of instructions handled by decode
342system.cpu0.rename.SquashCycles 1724 # Number of cycles rename is squashing
343system.cpu0.rename.IdleCycles 18505 # Number of cycles rename is idle
344system.cpu0.rename.BlockCycles 1935 # Number of cycles rename is blocking
345system.cpu0.rename.serializeStallCycles 15328 # count of cycles rename stalled for serializing inst
346system.cpu0.rename.RunCycles 181668 # Number of cycles rename is running
347system.cpu0.rename.UnblockCycles 1340 # Number of cycles rename is unblocking
348system.cpu0.rename.RenamedInsts 558880 # Number of instructions processed by rename

349system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
350system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
351system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full

352system.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed
353system.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made
354system.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups
355system.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed
356system.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing
357system.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed
358system.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed
359system.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer
360system.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit.
361system.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit.
362system.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads.
363system.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores.
364system.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec)
365system.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ
366system.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued
367system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
368system.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling
369system.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph
370system.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed
371system.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle
372system.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle
373system.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle

352system.cpu0.rename.RenamedOperands 382489 # Number of destination operands rename has renamed
353system.cpu0.rename.RenameLookups 1113780 # Number of register rename lookups that rename has made
354system.cpu0.rename.int_rename_lookups 841332 # Number of integer rename lookups
355system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups
356system.cpu0.rename.CommittedMaps 363591 # Number of HB maps that are committed
357system.cpu0.rename.UndoneMaps 18898 # Number of HB maps that are undone due to squashing
358system.cpu0.rename.serializingInsts 1094 # count of serializing insts renamed
359system.cpu0.rename.tempSerializingInsts 1121 # count of temporary serializing insts renamed
360system.cpu0.rename.skidInsts 5347 # count of insts added to the skid buffer
361system.cpu0.memDep0.insertedLoads 178321 # Number of loads inserted to the mem dependence unit.
362system.cpu0.memDep0.insertedStores 90063 # Number of stores inserted to the mem dependence unit.
363system.cpu0.memDep0.conflictingLoads 86944 # Number of conflicting loads.
364system.cpu0.memDep0.conflictingStores 86670 # Number of conflicting stores.
365system.cpu0.iq.iqInstsAdded 466208 # Number of instructions added to the IQ (excludes non-spec)
366system.cpu0.iq.iqNonSpecInstsAdded 1118 # Number of non-speculative instructions added to the IQ
367system.cpu0.iq.iqInstsIssued 462266 # Number of instructions issued
368system.cpu0.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
369system.cpu0.iq.iqSquashedInstsExamined 16406 # Number of squashed instructions iterated over during squash; mainly for profiling
370system.cpu0.iq.iqSquashedOperandsExamined 13115 # Number of squashed operands that are examined and possibly removed from graph
371system.cpu0.iq.iqSquashedNonSpecRemoved 559 # Number of squashed non-spec instructions that were removed
372system.cpu0.iq.issued_per_cycle::samples 220500 # Number of insts issued each cycle
373system.cpu0.iq.issued_per_cycle::mean 2.096444 # Number of insts issued each cycle
374system.cpu0.iq.issued_per_cycle::stdev 1.103875 # Number of insts issued each cycle

374system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

375system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

375system.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle
376system.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle
377system.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle
378system.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle
379system.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle
380system.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle
381system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle
382system.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle
383system.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle

376system.cpu0.iq.issued_per_cycle::0 36239 16.43% 16.43% # Number of insts issued each cycle
377system.cpu0.iq.issued_per_cycle::1 4459 2.02% 18.46% # Number of insts issued each cycle
378system.cpu0.iq.issued_per_cycle::2 88275 40.03% 58.49% # Number of insts issued each cycle
379system.cpu0.iq.issued_per_cycle::3 87972 39.90% 98.39% # Number of insts issued each cycle
380system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.16% # Number of insts issued each cycle
381system.cpu0.iq.issued_per_cycle::5 988 0.45% 99.61% # Number of insts issued each cycle
382system.cpu0.iq.issued_per_cycle::6 572 0.26% 99.87% # Number of insts issued each cycle
383system.cpu0.iq.issued_per_cycle::7 195 0.09% 99.95% # Number of insts issued each cycle
384system.cpu0.iq.issued_per_cycle::8 101 0.05% 100.00% # Number of insts issued each cycle

384system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
385system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
386system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

385system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
386system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
387system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

387system.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle

388system.cpu0.iq.issued_per_cycle::total 220500 # Number of insts issued each cycle

388system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

389system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

389system.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available
390system.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available
391system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available
392system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available
393system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available
394system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available
395system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available
396system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available
397system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available
398system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available
399system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available
400system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available
401system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available
402system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available
403system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available
404system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available
405system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available
406system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available
407system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available
408system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available
409system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available
410system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available
411system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available
412system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available
413system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available
414system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available
415system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available
416system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available
417system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available
418system.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available
419system.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available

390system.cpu0.iq.fu_full::IntAlu 126 38.77% 38.77% # attempts to use FU when none available
391system.cpu0.iq.fu_full::IntMult 0 0.00% 38.77% # attempts to use FU when none available
392system.cpu0.iq.fu_full::IntDiv 0 0.00% 38.77% # attempts to use FU when none available
393system.cpu0.iq.fu_full::FloatAdd 0 0.00% 38.77% # attempts to use FU when none available
394system.cpu0.iq.fu_full::FloatCmp 0 0.00% 38.77% # attempts to use FU when none available
395system.cpu0.iq.fu_full::FloatCvt 0 0.00% 38.77% # attempts to use FU when none available
396system.cpu0.iq.fu_full::FloatMult 0 0.00% 38.77% # attempts to use FU when none available
397system.cpu0.iq.fu_full::FloatDiv 0 0.00% 38.77% # attempts to use FU when none available
398system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 38.77% # attempts to use FU when none available
399system.cpu0.iq.fu_full::SimdAdd 0 0.00% 38.77% # attempts to use FU when none available
400system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 38.77% # attempts to use FU when none available
401system.cpu0.iq.fu_full::SimdAlu 0 0.00% 38.77% # attempts to use FU when none available
402system.cpu0.iq.fu_full::SimdCmp 0 0.00% 38.77% # attempts to use FU when none available
403system.cpu0.iq.fu_full::SimdCvt 0 0.00% 38.77% # attempts to use FU when none available
404system.cpu0.iq.fu_full::SimdMisc 0 0.00% 38.77% # attempts to use FU when none available
405system.cpu0.iq.fu_full::SimdMult 0 0.00% 38.77% # attempts to use FU when none available
406system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 38.77% # attempts to use FU when none available
407system.cpu0.iq.fu_full::SimdShift 0 0.00% 38.77% # attempts to use FU when none available
408system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 38.77% # attempts to use FU when none available
409system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 38.77% # attempts to use FU when none available
410system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 38.77% # attempts to use FU when none available
411system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 38.77% # attempts to use FU when none available
412system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 38.77% # attempts to use FU when none available
413system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 38.77% # attempts to use FU when none available
414system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 38.77% # attempts to use FU when none available
415system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 38.77% # attempts to use FU when none available
416system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 38.77% # attempts to use FU when none available
417system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.77% # attempts to use FU when none available
418system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 38.77% # attempts to use FU when none available
419system.cpu0.iq.fu_full::MemRead 78 24.00% 62.77% # attempts to use FU when none available
420system.cpu0.iq.fu_full::MemWrite 121 37.23% 100.00% # attempts to use FU when none available

420system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
421system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
422system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

421system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
422system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
423system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

423system.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued
424system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued
425system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued
426system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued
427system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued
428system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued
429system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued
430system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued
431system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued
432system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued
433system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued
434system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued
435system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued
436system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued
437system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued
438system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued
439system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued
440system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued
441system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued
442system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued
443system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued
444system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued
445system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued
446system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued
447system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued
448system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued
449system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued
450system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued
451system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued
452system.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued
453system.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued

424system.cpu0.iq.FU_type_0::IntAlu 195215 42.23% 42.23% # Type of FU issued
425system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued
426system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued
427system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued
428system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued
429system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued
430system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued
431system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued
432system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued
433system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued
434system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued
435system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued
436system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued
437system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued
438system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued
439system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued
440system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued
441system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued
442system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued
443system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued
444system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued
445system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued
446system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued
447system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued
448system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued
449system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued
450system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued
451system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued
452system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued
453system.cpu0.iq.FU_type_0::MemRead 177740 38.45% 80.68% # Type of FU issued
454system.cpu0.iq.FU_type_0::MemWrite 89311 19.32% 100.00% # Type of FU issued

454system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
455system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

455system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
456system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

456system.cpu0.iq.FU_type_0::total 463006 # Type of FU issued
457system.cpu0.iq.rate 1.859111 # Inst issue rate
458system.cpu0.iq.fu_busy_cnt 331 # FU busy when requested
459system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst)
460system.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads
461system.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes
462system.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses

457system.cpu0.iq.FU_type_0::total 462266 # Type of FU issued
458system.cpu0.iq.rate 1.864931 # Inst issue rate
459system.cpu0.iq.fu_busy_cnt 325 # FU busy when requested
460system.cpu0.iq.fu_busy_rate 0.000703 # FU busy rate (busy events/executed inst)
461system.cpu0.iq.int_inst_queue_reads 1145469 # Number of integer instruction queue reads
462system.cpu0.iq.int_inst_queue_writes 483779 # Number of integer instruction queue writes
463system.cpu0.iq.int_inst_queue_wakeup_accesses 459725 # Number of integer instruction queue wakeup accesses

463system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

464system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

464system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes

465system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes

465system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

466system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

466system.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses

467system.cpu0.iq.int_alu_accesses 462591 # Number of integer alu accesses

467system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses

468system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses

468system.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores

469system.cpu0.iew.lsq.thread0.forwLoads 86430 # Number of loads that had data forwarded from stores

469system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

470system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

470system.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed
471system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
472system.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations
473system.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed

471system.cpu0.iew.lsq.thread0.squashedLoads 2936 # Number of loads squashed
472system.cpu0.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
473system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
474system.cpu0.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed

474system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
475system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
476system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
477system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked
478system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

475system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
476system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
477system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
478system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked
479system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

479system.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing
480system.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking

480system.cpu0.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing
481system.cpu0.iew.iewBlockCycles 1933 # Number of cycles IEW is blocking

481system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking

482system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking

482system.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ
483system.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch
484system.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions
485system.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions
486system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions

483system.cpu0.iew.iewDispatchedInsts 554898 # Number of instructions dispatched to IQ
484system.cpu0.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
485system.cpu0.iew.iewDispLoadInsts 178321 # Number of dispatched load instructions
486system.cpu0.iew.iewDispStoreInsts 90063 # Number of dispatched store instructions
487system.cpu0.iew.iewDispNonSpecInsts 1001 # Number of dispatched non-speculative instructions

487system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall
488system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

488system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall
489system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

489system.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations
490system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly
491system.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly
492system.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute
493system.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions
494system.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed
495system.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute

490system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
491system.cpu0.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly
492system.cpu0.iew.predictedNotTakenIncorrect 1693 # Number of branches that were predicted not taken incorrectly
493system.cpu0.iew.branchMispredicts 1922 # Number of branch mispredicts detected at execute
494system.cpu0.iew.iewExecutedInsts 460834 # Number of executed instructions
495system.cpu0.iew.iewExecLoadInsts 177384 # Number of load instructions executed
496system.cpu0.iew.iewExecSquashedInsts 1432 # Number of squashed instructions skipped in execute

496system.cpu0.iew.exec_swp 0 # number of swp insts executed

497system.cpu0.iew.exec_swp 0 # number of swp insts executed

497system.cpu0.iew.exec_nop 87723 # number of nop insts executed
498system.cpu0.iew.exec_refs 266935 # number of memory reference insts executed
499system.cpu0.iew.exec_branches 91696 # Number of branches executed
500system.cpu0.iew.exec_stores 89256 # Number of stores executed
501system.cpu0.iew.exec_rate 1.853208 # Inst execution rate
502system.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit
503system.cpu0.iew.wb_count 460421 # cumulative count of insts written-back
504system.cpu0.iew.wb_producers 273043 # num instructions producing a value
505system.cpu0.iew.wb_consumers 276596 # num instructions consuming a value
506system.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle
507system.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back
508system.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit

498system.cpu0.iew.exec_nop 87572 # number of nop insts executed
499system.cpu0.iew.exec_refs 266499 # number of memory reference insts executed
500system.cpu0.iew.exec_branches 91565 # Number of branches executed
501system.cpu0.iew.exec_stores 89115 # Number of stores executed
502system.cpu0.iew.exec_rate 1.859154 # Inst execution rate
503system.cpu0.iew.wb_sent 460184 # cumulative count of insts sent to commit
504system.cpu0.iew.wb_count 459725 # cumulative count of insts written-back
505system.cpu0.iew.wb_producers 272583 # num instructions producing a value
506system.cpu0.iew.wb_consumers 276120 # num instructions consuming a value
507system.cpu0.iew.wb_rate 1.854680 # insts written-back per cycle
508system.cpu0.iew.wb_fanout 0.987190 # average fanout of values written-back
509system.cpu0.commit.commitSquashedInsts 17076 # The number of squashed insts skipped by commit

509system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards

510system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards

510system.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted
511system.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle
512system.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle
513system.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle

511system.cpu0.commit.branchMispredicts 1575 # The number of times a branch was mispredicted
512system.cpu0.commit.committed_per_cycle::samples 217161 # Number of insts commited each cycle
513system.cpu0.commit.committed_per_cycle::mean 2.476218 # Number of insts commited each cycle
514system.cpu0.commit.committed_per_cycle::stdev 2.140669 # Number of insts commited each cycle

514system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

515system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

515system.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle
516system.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle
517system.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle
518system.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle
519system.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle
520system.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle
521system.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle
522system.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle
523system.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle

516system.cpu0.commit.committed_per_cycle::0 36214 16.68% 16.68% # Number of insts commited each cycle
517system.cpu0.commit.committed_per_cycle::1 90367 41.61% 58.29% # Number of insts commited each cycle
518system.cpu0.commit.committed_per_cycle::2 2049 0.94% 59.23% # Number of insts commited each cycle
519system.cpu0.commit.committed_per_cycle::3 624 0.29% 59.52% # Number of insts commited each cycle
520system.cpu0.commit.committed_per_cycle::4 510 0.23% 59.75% # Number of insts commited each cycle
521system.cpu0.commit.committed_per_cycle::5 86212 39.70% 99.45% # Number of insts commited each cycle
522system.cpu0.commit.committed_per_cycle::6 445 0.20% 99.66% # Number of insts commited each cycle
523system.cpu0.commit.committed_per_cycle::7 289 0.13% 99.79% # Number of insts commited each cycle
524system.cpu0.commit.committed_per_cycle::8 451 0.21% 100.00% # Number of insts commited each cycle

524system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
525system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
526system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

525system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
526system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
527system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

527system.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle
528system.cpu0.commit.committedInsts 538608 # Number of instructions committed
529system.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed

528system.cpu0.commit.committed_per_cycle::total 217161 # Number of insts commited each cycle
529system.cpu0.commit.committedInsts 537738 # Number of instructions committed
530system.cpu0.commit.committedOps 537738 # Number of ops (including micro ops) committed

530system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

531system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

531system.cpu0.commit.refs 264019 # Number of memory references committed
532system.cpu0.commit.loads 175675 # Number of loads committed

532system.cpu0.commit.refs 263584 # Number of memory references committed
533system.cpu0.commit.loads 175385 # Number of loads committed

533system.cpu0.commit.membars 84 # Number of memory barriers committed

534system.cpu0.commit.membars 84 # Number of memory barriers committed

534system.cpu0.commit.branches 90231 # Number of branches committed

535system.cpu0.commit.branches 90086 # Number of branches committed

535system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.

536system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.

536system.cpu0.commit.int_insts 362502 # Number of committed integer instructions.

537system.cpu0.commit.int_insts 361922 # Number of committed integer instructions.

537system.cpu0.commit.function_calls 223 # Number of function calls committed.

538system.cpu0.commit.function_calls 223 # Number of function calls committed.

538system.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction
539system.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction

539system.cpu0.commit.op_class_0::No_OpClass 86818 16.15% 16.15% # Class of committed instruction
540system.cpu0.commit.op_class_0::IntAlu 187252 34.82% 50.97% # Class of committed instruction

540system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction
541system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction
542system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction
543system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction
544system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction
545system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction
546system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction
547system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction

--- 12 unchanged lines hidden (view full) ---

560system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction
561system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction
562system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction
563system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction
564system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction
565system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction
566system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction
567system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction

541system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction
542system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction
543system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction
544system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction
545system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction
546system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction
547system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction
548system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction

--- 12 unchanged lines hidden (view full) ---

561system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction
562system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction
563system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction
564system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction
565system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction
566system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction
567system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction
568system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction

568system.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction
569system.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction

569system.cpu0.commit.op_class_0::MemRead 175469 32.63% 83.60% # Class of committed instruction
570system.cpu0.commit.op_class_0::MemWrite 88199 16.40% 100.00% # Class of committed instruction

570system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
571system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

571system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
572system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

572system.cpu0.commit.op_class_0::total 538608 # Class of committed instruction
573system.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached
574system.cpu0.rob.rob_reads 772578 # The number of ROB reads
575system.cpu0.rob.rob_writes 1114998 # The number of ROB writes
576system.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself
577system.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling
578system.cpu0.committedInsts 451561 # Number of Instructions Simulated
579system.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated
580system.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction
581system.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads
582system.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle
583system.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads
584system.cpu0.int_regfile_reads 825039 # number of integer regfile reads
585system.cpu0.int_regfile_writes 371919 # number of integer regfile writes

573system.cpu0.commit.op_class_0::total 537738 # Class of committed instruction
574system.cpu0.commit.bw_lim_events 451 # number cycles where commit BW limit reached
575system.cpu0.rob.rob_reads 770363 # The number of ROB reads
576system.cpu0.rob.rob_writes 1113018 # The number of ROB writes
577system.cpu0.timesIdled 321 # Number of times that the entire CPU went into an idle state and unscheduled itself
578system.cpu0.idleCycles 27373 # Total number of cycles that the CPU has spent unscheduled due to idling
579system.cpu0.committedInsts 450836 # Number of Instructions Simulated
580system.cpu0.committedOps 450836 # Number of Ops (including micro ops) Simulated
581system.cpu0.cpi 0.549807 # CPI: Cycles Per Instruction
582system.cpu0.cpi_total 0.549807 # CPI: Total CPI of All Threads
583system.cpu0.ipc 1.818819 # IPC: Instructions Per Cycle
584system.cpu0.ipc_total 1.818819 # IPC: Total IPC of All Threads
585system.cpu0.int_regfile_reads 823745 # number of integer regfile reads
586system.cpu0.int_regfile_writes 371341 # number of integer regfile writes

586system.cpu0.fp_regfile_reads 192 # number of floating regfile reads

587system.cpu0.fp_regfile_reads 192 # number of floating regfile reads

587system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads

588system.cpu0.misc_regfile_reads 268638 # number of misc regfile reads

588system.cpu0.misc_regfile_writes 564 # number of misc regfile writes

589system.cpu0.misc_regfile_writes 564 # number of misc regfile writes

589system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

590system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

590system.cpu0.dcache.tags.replacements 2 # number of replacements

591system.cpu0.dcache.tags.replacements 2 # number of replacements

591system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use
592system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks.

592system.cpu0.dcache.tags.tagsinuse 142.669467 # Cycle average of tags in use
593system.cpu0.dcache.tags.total_refs 177790 # Total number of references to valid blocks.

593system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks.

594system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks.

594system.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks.

595system.cpu0.dcache.tags.avg_refs 1033.662791 # Average number of references to valid blocks.

595system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

596system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

596system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor
597system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy
598system.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy

597system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.669467 # Average occupied blocks per requestor
598system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278651 # Average percentage of cache occupancy
599system.cpu0.dcache.tags.occ_percent::total 0.278651 # Average percentage of cache occupancy

599system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id
600system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
601system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
602system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
603system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id

600system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id
601system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
602system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
603system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
604system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id

604system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses
605system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses
606system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
607system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits
608system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits
609system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits
610system.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits
611system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits
612system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits
613system.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits
614system.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits
615system.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits
616system.cpu0.dcache.overall_hits::total 178161 # number of overall hits
617system.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses
618system.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses
619system.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses
620system.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses
621system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses
622system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses
623system.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses
624system.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses
625system.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses
626system.cpu0.dcache.overall_misses::total 1132 # number of overall misses
627system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles
628system.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles
629system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles
630system.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles
631system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles
632system.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles
633system.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles
634system.cpu0.dcache.demand_miss_latency::total 54320490 # number of demand (read+write) miss cycles
635system.cpu0.dcache.overall_miss_latency::cpu0.data 54320490 # number of overall miss cycles
636system.cpu0.dcache.overall_miss_latency::total 54320490 # number of overall miss cycles
637system.cpu0.dcache.ReadReq_accesses::cpu0.data 90991 # number of ReadReq accesses(hits+misses)
638system.cpu0.dcache.ReadReq_accesses::total 90991 # number of ReadReq accesses(hits+misses)
639system.cpu0.dcache.WriteReq_accesses::cpu0.data 88302 # number of WriteReq accesses(hits+misses)
640system.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses)

605system.cpu0.dcache.tags.tag_accesses 716504 # Number of tag accesses
606system.cpu0.dcache.tags.data_accesses 716504 # Number of data accesses
607system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
608system.cpu0.dcache.ReadReq_hits::cpu0.data 90267 # number of ReadReq hits
609system.cpu0.dcache.ReadReq_hits::total 90267 # number of ReadReq hits
610system.cpu0.dcache.WriteReq_hits::cpu0.data 87606 # number of WriteReq hits
611system.cpu0.dcache.WriteReq_hits::total 87606 # number of WriteReq hits
612system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits
613system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits
614system.cpu0.dcache.demand_hits::cpu0.data 177873 # number of demand (read+write) hits
615system.cpu0.dcache.demand_hits::total 177873 # number of demand (read+write) hits
616system.cpu0.dcache.overall_hits::cpu0.data 177873 # number of overall hits
617system.cpu0.dcache.overall_hits::total 177873 # number of overall hits
618system.cpu0.dcache.ReadReq_misses::cpu0.data 580 # number of ReadReq misses
619system.cpu0.dcache.ReadReq_misses::total 580 # number of ReadReq misses
620system.cpu0.dcache.WriteReq_misses::cpu0.data 551 # number of WriteReq misses
621system.cpu0.dcache.WriteReq_misses::total 551 # number of WriteReq misses
622system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses
623system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses
624system.cpu0.dcache.demand_misses::cpu0.data 1131 # number of demand (read+write) misses
625system.cpu0.dcache.demand_misses::total 1131 # number of demand (read+write) misses
626system.cpu0.dcache.overall_misses::cpu0.data 1131 # number of overall misses
627system.cpu0.dcache.overall_misses::total 1131 # number of overall misses
628system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15004000 # number of ReadReq miss cycles
629system.cpu0.dcache.ReadReq_miss_latency::total 15004000 # number of ReadReq miss cycles
630system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35761990 # number of WriteReq miss cycles
631system.cpu0.dcache.WriteReq_miss_latency::total 35761990 # number of WriteReq miss cycles
632system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 487500 # number of SwapReq miss cycles
633system.cpu0.dcache.SwapReq_miss_latency::total 487500 # number of SwapReq miss cycles
634system.cpu0.dcache.demand_miss_latency::cpu0.data 50765990 # number of demand (read+write) miss cycles
635system.cpu0.dcache.demand_miss_latency::total 50765990 # number of demand (read+write) miss cycles
636system.cpu0.dcache.overall_miss_latency::cpu0.data 50765990 # number of overall miss cycles
637system.cpu0.dcache.overall_miss_latency::total 50765990 # number of overall miss cycles
638system.cpu0.dcache.ReadReq_accesses::cpu0.data 90847 # number of ReadReq accesses(hits+misses)
639system.cpu0.dcache.ReadReq_accesses::total 90847 # number of ReadReq accesses(hits+misses)
640system.cpu0.dcache.WriteReq_accesses::cpu0.data 88157 # number of WriteReq accesses(hits+misses)
641system.cpu0.dcache.WriteReq_accesses::total 88157 # number of WriteReq accesses(hits+misses)

641system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
642system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)

642system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
643system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)

643system.cpu0.dcache.demand_accesses::cpu0.data 179293 # number of demand (read+write) accesses
644system.cpu0.dcache.demand_accesses::total 179293 # number of demand (read+write) accesses
645system.cpu0.dcache.overall_accesses::cpu0.data 179293 # number of overall (read+write) accesses
646system.cpu0.dcache.overall_accesses::total 179293 # number of overall (read+write) accesses
647system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006352 # miss rate for ReadReq accesses
648system.cpu0.dcache.ReadReq_miss_rate::total 0.006352 # miss rate for ReadReq accesses
649system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006274 # miss rate for WriteReq accesses
650system.cpu0.dcache.WriteReq_miss_rate::total 0.006274 # miss rate for WriteReq accesses
651system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses
652system.cpu0.dcache.SwapReq_miss_rate::total 0.452381 # miss rate for SwapReq accesses
653system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006314 # miss rate for demand accesses
654system.cpu0.dcache.demand_miss_rate::total 0.006314 # miss rate for demand accesses
655system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006314 # miss rate for overall accesses
656system.cpu0.dcache.overall_miss_rate::total 0.006314 # miss rate for overall accesses
657system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31432.525952 # average ReadReq miss latency
658system.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency
659system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65257.202166 # average WriteReq miss latency
660system.cpu0.dcache.WriteReq_avg_miss_latency::total 65257.202166 # average WriteReq miss latency
661system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency
662system.cpu0.dcache.SwapReq_avg_miss_latency::total 27421.052632 # average SwapReq miss latency
663system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency
664system.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency
665system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency
666system.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency

644system.cpu0.dcache.demand_accesses::cpu0.data 179004 # number of demand (read+write) accesses
645system.cpu0.dcache.demand_accesses::total 179004 # number of demand (read+write) accesses
646system.cpu0.dcache.overall_accesses::cpu0.data 179004 # number of overall (read+write) accesses
647system.cpu0.dcache.overall_accesses::total 179004 # number of overall (read+write) accesses
648system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006384 # miss rate for ReadReq accesses
649system.cpu0.dcache.ReadReq_miss_rate::total 0.006384 # miss rate for ReadReq accesses
650system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006250 # miss rate for WriteReq accesses
651system.cpu0.dcache.WriteReq_miss_rate::total 0.006250 # miss rate for WriteReq accesses
652system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses
653system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses
654system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006318 # miss rate for demand accesses
655system.cpu0.dcache.demand_miss_rate::total 0.006318 # miss rate for demand accesses
656system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006318 # miss rate for overall accesses
657system.cpu0.dcache.overall_miss_rate::total 0.006318 # miss rate for overall accesses
658system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517 # average ReadReq miss latency
659system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517 # average ReadReq miss latency
660system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103 # average WriteReq miss latency
661system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103 # average WriteReq miss latency
662system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 24375 # average SwapReq miss latency
663system.cpu0.dcache.SwapReq_avg_miss_latency::total 24375 # average SwapReq miss latency
664system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency
665system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803 # average overall miss latency
666system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency
667system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803 # average overall miss latency

667system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked
668system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
669system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
670system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
671system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked
672system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
674system.cpu0.dcache.writebacks::total 1 # number of writebacks

668system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked
669system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
670system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
671system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
672system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked
673system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
674system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
675system.cpu0.dcache.writebacks::total 1 # number of writebacks

675system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 385 # number of ReadReq MSHR hits
676system.cpu0.dcache.ReadReq_mshr_hits::total 385 # number of ReadReq MSHR hits
677system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 387 # number of WriteReq MSHR hits
678system.cpu0.dcache.WriteReq_mshr_hits::total 387 # number of WriteReq MSHR hits
679system.cpu0.dcache.demand_mshr_hits::cpu0.data 772 # number of demand (read+write) MSHR hits
680system.cpu0.dcache.demand_mshr_hits::total 772 # number of demand (read+write) MSHR hits
681system.cpu0.dcache.overall_mshr_hits::cpu0.data 772 # number of overall MSHR hits
682system.cpu0.dcache.overall_mshr_hits::total 772 # number of overall MSHR hits
683system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses
684system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses
685system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 # number of WriteReq MSHR misses
686system.cpu0.dcache.WriteReq_mshr_misses::total 167 # number of WriteReq MSHR misses
687system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses
688system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses
689system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
690system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
691system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
692system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
693system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7230000 # number of ReadReq MSHR miss cycles
694system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7230000 # number of ReadReq MSHR miss cycles
695system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8425000 # number of WriteReq MSHR miss cycles
696system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8425000 # number of WriteReq MSHR miss cycles
697system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 502000 # number of SwapReq MSHR miss cycles
698system.cpu0.dcache.SwapReq_mshr_miss_latency::total 502000 # number of SwapReq MSHR miss cycles
699system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15655000 # number of demand (read+write) MSHR miss cycles
700system.cpu0.dcache.demand_mshr_miss_latency::total 15655000 # number of demand (read+write) MSHR miss cycles
701system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15655000 # number of overall MSHR miss cycles
702system.cpu0.dcache.overall_mshr_miss_latency::total 15655000 # number of overall MSHR miss cycles
703system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002121 # mshr miss rate for ReadReq accesses
704system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002121 # mshr miss rate for ReadReq accesses
705system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001891 # mshr miss rate for WriteReq accesses
706system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001891 # mshr miss rate for WriteReq accesses
707system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses
708system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.452381 # mshr miss rate for SwapReq accesses
709system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for demand accesses
710system.cpu0.dcache.demand_mshr_miss_rate::total 0.002008 # mshr miss rate for demand accesses
711system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for overall accesses
712system.cpu0.dcache.overall_mshr_miss_rate::total 0.002008 # mshr miss rate for overall accesses
713system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37461.139896 # average ReadReq mshr miss latency
714system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37461.139896 # average ReadReq mshr miss latency
715system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50449.101796 # average WriteReq mshr miss latency
716system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50449.101796 # average WriteReq mshr miss latency
717system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26421.052632 # average SwapReq mshr miss latency
718system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26421.052632 # average SwapReq mshr miss latency
719system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency
720system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency
721system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency
722system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency
723system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
724system.cpu0.icache.tags.replacements 394 # number of replacements
725system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use
726system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks.
727system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks.
728system.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks.

676system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits
677system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits
678system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 383 # number of WriteReq MSHR hits
679system.cpu0.dcache.WriteReq_mshr_hits::total 383 # number of WriteReq MSHR hits
680system.cpu0.dcache.demand_mshr_hits::cpu0.data 761 # number of demand (read+write) MSHR hits
681system.cpu0.dcache.demand_mshr_hits::total 761 # number of demand (read+write) MSHR hits
682system.cpu0.dcache.overall_mshr_hits::cpu0.data 761 # number of overall MSHR hits
683system.cpu0.dcache.overall_mshr_hits::total 761 # number of overall MSHR hits
684system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202 # number of ReadReq MSHR misses
685system.cpu0.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
686system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 168 # number of WriteReq MSHR misses
687system.cpu0.dcache.WriteReq_mshr_misses::total 168 # number of WriteReq MSHR misses
688system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses
689system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses
690system.cpu0.dcache.demand_mshr_misses::cpu0.data 370 # number of demand (read+write) MSHR misses
691system.cpu0.dcache.demand_mshr_misses::total 370 # number of demand (read+write) MSHR misses
692system.cpu0.dcache.overall_mshr_misses::cpu0.data 370 # number of overall MSHR misses
693system.cpu0.dcache.overall_mshr_misses::total 370 # number of overall MSHR misses
694system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6835500 # number of ReadReq MSHR miss cycles
695system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles
696system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8076500 # number of WriteReq MSHR miss cycles
697system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8076500 # number of WriteReq MSHR miss cycles
698system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 467500 # number of SwapReq MSHR miss cycles
699system.cpu0.dcache.SwapReq_mshr_miss_latency::total 467500 # number of SwapReq MSHR miss cycles
700system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14912000 # number of demand (read+write) MSHR miss cycles
701system.cpu0.dcache.demand_mshr_miss_latency::total 14912000 # number of demand (read+write) MSHR miss cycles
702system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14912000 # number of overall MSHR miss cycles
703system.cpu0.dcache.overall_mshr_miss_latency::total 14912000 # number of overall MSHR miss cycles
704system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002224 # mshr miss rate for ReadReq accesses
705system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002224 # mshr miss rate for ReadReq accesses
706system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001906 # mshr miss rate for WriteReq accesses
707system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001906 # mshr miss rate for WriteReq accesses
708system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses
709system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses
710system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for demand accesses
711system.cpu0.dcache.demand_mshr_miss_rate::total 0.002067 # mshr miss rate for demand accesses
712system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for overall accesses
713system.cpu0.dcache.overall_mshr_miss_rate::total 0.002067 # mshr miss rate for overall accesses
714system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33839.108911 # average ReadReq mshr miss latency
715system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33839.108911 # average ReadReq mshr miss latency
716system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48074.404762 # average WriteReq mshr miss latency
717system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48074.404762 # average WriteReq mshr miss latency
718system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 23375 # average SwapReq mshr miss latency
719system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 23375 # average SwapReq mshr miss latency
720system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency
721system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency
722system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency
723system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency
724system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
725system.cpu0.icache.tags.replacements 413 # number of replacements
726system.cpu0.icache.tags.tagsinuse 250.106503 # Cycle average of tags in use
727system.cpu0.icache.tags.total_refs 7058 # Total number of references to valid blocks.
728system.cpu0.icache.tags.sampled_refs 712 # Sample count of references to valid blocks.
729system.cpu0.icache.tags.avg_refs 9.912921 # Average number of references to valid blocks.

729system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

730system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

730system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.905102 # Average occupied blocks per requestor
731system.cpu0.icache.tags.occ_percent::cpu0.inst 0.486143 # Average percentage of cache occupancy
732system.cpu0.icache.tags.occ_percent::total 0.486143 # Average percentage of cache occupancy
733system.cpu0.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
734system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
735system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
736system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
737system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id
738system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses
739system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses
740system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
741system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits
742system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits
743system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits
744system.cpu0.icache.demand_hits::total 7041 # number of demand (read+write) hits
745system.cpu0.icache.overall_hits::cpu0.inst 7041 # number of overall hits
746system.cpu0.icache.overall_hits::total 7041 # number of overall hits
747system.cpu0.icache.ReadReq_misses::cpu0.inst 911 # number of ReadReq misses
748system.cpu0.icache.ReadReq_misses::total 911 # number of ReadReq misses
749system.cpu0.icache.demand_misses::cpu0.inst 911 # number of demand (read+write) misses
750system.cpu0.icache.demand_misses::total 911 # number of demand (read+write) misses
751system.cpu0.icache.overall_misses::cpu0.inst 911 # number of overall misses
752system.cpu0.icache.overall_misses::total 911 # number of overall misses
753system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43691000 # number of ReadReq miss cycles
754system.cpu0.icache.ReadReq_miss_latency::total 43691000 # number of ReadReq miss cycles
755system.cpu0.icache.demand_miss_latency::cpu0.inst 43691000 # number of demand (read+write) miss cycles
756system.cpu0.icache.demand_miss_latency::total 43691000 # number of demand (read+write) miss cycles
757system.cpu0.icache.overall_miss_latency::cpu0.inst 43691000 # number of overall miss cycles
758system.cpu0.icache.overall_miss_latency::total 43691000 # number of overall miss cycles
759system.cpu0.icache.ReadReq_accesses::cpu0.inst 7952 # number of ReadReq accesses(hits+misses)
760system.cpu0.icache.ReadReq_accesses::total 7952 # number of ReadReq accesses(hits+misses)
761system.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses
762system.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses
763system.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses
764system.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses
765system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses
766system.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses
767system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses
768system.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses
769system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses
770system.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses
771system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency
772system.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency
773system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency
774system.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency
775system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency
776system.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency

731system.cpu0.icache.tags.occ_blocks::cpu0.inst 250.106503 # Average occupied blocks per requestor
732system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488489 # Average percentage of cache occupancy
733system.cpu0.icache.tags.occ_percent::total 0.488489 # Average percentage of cache occupancy
734system.cpu0.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id
735system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
736system.cpu0.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id
737system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id
738system.cpu0.icache.tags.occ_task_id_percent::1024 0.583984 # Percentage of cache occupancy per task id
739system.cpu0.icache.tags.tag_accesses 8709 # Number of tag accesses
740system.cpu0.icache.tags.data_accesses 8709 # Number of data accesses
741system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
742system.cpu0.icache.ReadReq_hits::cpu0.inst 7058 # number of ReadReq hits
743system.cpu0.icache.ReadReq_hits::total 7058 # number of ReadReq hits
744system.cpu0.icache.demand_hits::cpu0.inst 7058 # number of demand (read+write) hits
745system.cpu0.icache.demand_hits::total 7058 # number of demand (read+write) hits
746system.cpu0.icache.overall_hits::cpu0.inst 7058 # number of overall hits
747system.cpu0.icache.overall_hits::total 7058 # number of overall hits
748system.cpu0.icache.ReadReq_misses::cpu0.inst 939 # number of ReadReq misses
749system.cpu0.icache.ReadReq_misses::total 939 # number of ReadReq misses
750system.cpu0.icache.demand_misses::cpu0.inst 939 # number of demand (read+write) misses
751system.cpu0.icache.demand_misses::total 939 # number of demand (read+write) misses
752system.cpu0.icache.overall_misses::cpu0.inst 939 # number of overall misses
753system.cpu0.icache.overall_misses::total 939 # number of overall misses
754system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44243500 # number of ReadReq miss cycles
755system.cpu0.icache.ReadReq_miss_latency::total 44243500 # number of ReadReq miss cycles
756system.cpu0.icache.demand_miss_latency::cpu0.inst 44243500 # number of demand (read+write) miss cycles
757system.cpu0.icache.demand_miss_latency::total 44243500 # number of demand (read+write) miss cycles
758system.cpu0.icache.overall_miss_latency::cpu0.inst 44243500 # number of overall miss cycles
759system.cpu0.icache.overall_miss_latency::total 44243500 # number of overall miss cycles
760system.cpu0.icache.ReadReq_accesses::cpu0.inst 7997 # number of ReadReq accesses(hits+misses)
761system.cpu0.icache.ReadReq_accesses::total 7997 # number of ReadReq accesses(hits+misses)
762system.cpu0.icache.demand_accesses::cpu0.inst 7997 # number of demand (read+write) accesses
763system.cpu0.icache.demand_accesses::total 7997 # number of demand (read+write) accesses
764system.cpu0.icache.overall_accesses::cpu0.inst 7997 # number of overall (read+write) accesses
765system.cpu0.icache.overall_accesses::total 7997 # number of overall (read+write) accesses
766system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117419 # miss rate for ReadReq accesses
767system.cpu0.icache.ReadReq_miss_rate::total 0.117419 # miss rate for ReadReq accesses
768system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117419 # miss rate for demand accesses
769system.cpu0.icache.demand_miss_rate::total 0.117419 # miss rate for demand accesses
770system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117419 # miss rate for overall accesses
771system.cpu0.icache.overall_miss_rate::total 0.117419 # miss rate for overall accesses
772system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381 # average ReadReq miss latency
773system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381 # average ReadReq miss latency
774system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency
775system.cpu0.icache.demand_avg_miss_latency::total 47117.678381 # average overall miss latency
776system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency
777system.cpu0.icache.overall_avg_miss_latency::total 47117.678381 # average overall miss latency

777system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
778system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
779system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked
780system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
781system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked
782system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

778system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
779system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
780system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked
781system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
782system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked
783system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

783system.cpu0.icache.writebacks::writebacks 394 # number of writebacks
784system.cpu0.icache.writebacks::total 394 # number of writebacks
785system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits
786system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
787system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits
788system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits
789system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits
790system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits
791system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses
792system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses
793system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses
794system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses
795system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses
796system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses
797system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles
798system.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles
799system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles
800system.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles
801system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles
802system.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles
803system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses
804system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses
805system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses
806system.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses
807system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses
808system.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses
809system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency
810system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency
811system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency
812system.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency
813system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency
814system.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency
815system.cpu1.branchPred.lookups 70381 # Number of BP lookups
816system.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted
817system.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect
818system.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups

784system.cpu0.icache.writebacks::writebacks 413 # number of writebacks
785system.cpu0.icache.writebacks::total 413 # number of writebacks
786system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 226 # number of ReadReq MSHR hits
787system.cpu0.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits
788system.cpu0.icache.demand_mshr_hits::cpu0.inst 226 # number of demand (read+write) MSHR hits
789system.cpu0.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits
790system.cpu0.icache.overall_mshr_hits::cpu0.inst 226 # number of overall MSHR hits
791system.cpu0.icache.overall_mshr_hits::total 226 # number of overall MSHR hits
792system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 713 # number of ReadReq MSHR misses
793system.cpu0.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses
794system.cpu0.icache.demand_mshr_misses::cpu0.inst 713 # number of demand (read+write) MSHR misses
795system.cpu0.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses
796system.cpu0.icache.overall_mshr_misses::cpu0.inst 713 # number of overall MSHR misses
797system.cpu0.icache.overall_mshr_misses::total 713 # number of overall MSHR misses
798system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34164500 # number of ReadReq MSHR miss cycles
799system.cpu0.icache.ReadReq_mshr_miss_latency::total 34164500 # number of ReadReq MSHR miss cycles
800system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34164500 # number of demand (read+write) MSHR miss cycles
801system.cpu0.icache.demand_mshr_miss_latency::total 34164500 # number of demand (read+write) MSHR miss cycles
802system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34164500 # number of overall MSHR miss cycles
803system.cpu0.icache.overall_mshr_miss_latency::total 34164500 # number of overall MSHR miss cycles
804system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for ReadReq accesses
805system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089158 # mshr miss rate for ReadReq accesses
806system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for demand accesses
807system.cpu0.icache.demand_mshr_miss_rate::total 0.089158 # mshr miss rate for demand accesses
808system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for overall accesses
809system.cpu0.icache.overall_mshr_miss_rate::total 0.089158 # mshr miss rate for overall accesses
810system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average ReadReq mshr miss latency
811system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790 # average ReadReq mshr miss latency
812system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency
813system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency
814system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency
815system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency
816system.cpu1.branchPred.lookups 73042 # Number of BP lookups
817system.cpu1.branchPred.condPredicted 65659 # Number of conditional branches predicted
818system.cpu1.branchPred.condIncorrect 2238 # Number of conditional branches incorrect
819system.cpu1.branchPred.BTBLookups 64943 # Number of BTB lookups

819system.cpu1.branchPred.BTBHits 0 # Number of BTB hits
820system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
821system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

820system.cpu1.branchPred.BTBHits 0 # Number of BTB hits
821system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
822system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

822system.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target.

823system.cpu1.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target.

823system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

824system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

824system.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups.
825system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits.
826system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses.
827system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches.
828system.cpu1.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
829system.cpu1.numCycles 193493 # number of cpu cycles simulated

825system.cpu1.branchPred.indirectLookups 64943 # Number of indirect predictor lookups.
826system.cpu1.branchPred.indirectHits 55241 # Number of indirect target hits.
827system.cpu1.branchPred.indirectMisses 9702 # Number of indirect misses.
828system.cpu1.branchPredindirectMispredicted 1128 # Number of mispredicted indirect branches.
829system.cpu1.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
830system.cpu1.numCycles 192502 # number of cpu cycles simulated

830system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
831system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

831system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
832system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

832system.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss
833system.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed
834system.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered
835system.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken
836system.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked
837system.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing

833system.cpu1.fetch.icacheStallCycles 33710 # Number of cycles fetch is stalled on an Icache miss
834system.cpu1.fetch.Insts 406560 # Number of instructions fetch has processed
835system.cpu1.fetch.Branches 73042 # Number of branches that fetch encountered
836system.cpu1.fetch.predictedBranches 57230 # Number of branches that fetch has predicted taken
837system.cpu1.fetch.Cycles 148689 # Number of cycles fetch has run and was not squashing or blocked
838system.cpu1.fetch.SquashCycles 4633 # Number of cycles fetch has spent squashing

838system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
839system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

839system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
840system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

840system.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps

841system.cpu1.fetch.PendingTrapStallCycles 1669 # Number of stall cycles due to pending traps

841system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR

842system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR

842system.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched
843system.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed
844system.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total)
845system.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total)
846system.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total)

843system.cpu1.fetch.CacheLines 22180 # Number of cache lines fetched
844system.cpu1.fetch.IcacheSquashes 918 # Number of outstanding Icache misses that were squashed
845system.cpu1.fetch.rateDist::samples 186413 # Number of instructions fetched each cycle (Total)
846system.cpu1.fetch.rateDist::mean 2.180964 # Number of instructions fetched each cycle (Total)
847system.cpu1.fetch.rateDist::stdev 2.381342 # Number of instructions fetched each cycle (Total)

847system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

848system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

848system.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total)
849system.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total)
850system.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total)
851system.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total)
852system.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total)
853system.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total)
854system.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total)
855system.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total)
856system.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total)

849system.cpu1.fetch.rateDist::0 54977 29.49% 29.49% # Number of instructions fetched each cycle (Total)
850system.cpu1.fetch.rateDist::1 63721 34.18% 63.67% # Number of instructions fetched each cycle (Total)
851system.cpu1.fetch.rateDist::2 5493 2.95% 66.62% # Number of instructions fetched each cycle (Total)
852system.cpu1.fetch.rateDist::3 3499 1.88% 68.50% # Number of instructions fetched each cycle (Total)
853system.cpu1.fetch.rateDist::4 651 0.35% 68.85% # Number of instructions fetched each cycle (Total)
854system.cpu1.fetch.rateDist::5 47493 25.48% 94.32% # Number of instructions fetched each cycle (Total)
855system.cpu1.fetch.rateDist::6 995 0.53% 94.86% # Number of instructions fetched each cycle (Total)
856system.cpu1.fetch.rateDist::7 1355 0.73% 95.59% # Number of instructions fetched each cycle (Total)
857system.cpu1.fetch.rateDist::8 8229 4.41% 100.00% # Number of instructions fetched each cycle (Total)

857system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
858system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
859system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

858system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
859system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
860system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

860system.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total)
861system.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle
862system.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle
863system.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle
864system.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked
865system.cpu1.decode.RunCycles 103585 # Number of cycles decode is running
866system.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking
867system.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing
868system.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode
869system.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing
870system.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle
871system.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking
872system.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst
873system.cpu1.rename.RunCycles 104390 # Number of cycles rename is running
874system.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking
875system.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename
876system.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full
877system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full

861system.cpu1.fetch.rateDist::total 186413 # Number of instructions fetched each cycle (Total)
862system.cpu1.fetch.branchRate 0.379435 # Number of branch fetches per cycle
863system.cpu1.fetch.rate 2.111978 # Number of inst fetches per cycle
864system.cpu1.decode.IdleCycles 22012 # Number of cycles decode is idle
865system.cpu1.decode.BlockedCycles 48189 # Number of cycles decode is blocked
866system.cpu1.decode.RunCycles 110683 # Number of cycles decode is running
867system.cpu1.decode.UnblockCycles 3203 # Number of cycles decode is unblocking
868system.cpu1.decode.SquashCycles 2316 # Number of cycles decode is squashing
869system.cpu1.decode.DecodedInsts 375249 # Number of instructions handled by decode
870system.cpu1.rename.SquashCycles 2316 # Number of cycles rename is squashing
871system.cpu1.rename.IdleCycles 23003 # Number of cycles rename is idle
872system.cpu1.rename.BlockCycles 21046 # Number of cycles rename is blocking
873system.cpu1.rename.serializeStallCycles 13565 # count of cycles rename stalled for serializing inst
874system.cpu1.rename.RunCycles 110960 # Number of cycles rename is running
875system.cpu1.rename.UnblockCycles 15513 # Number of cycles rename is unblocking
876system.cpu1.rename.RenamedInsts 369118 # Number of instructions processed by rename
877system.cpu1.rename.IQFullEvents 12808 # Number of times rename has blocked due to IQ full
878system.cpu1.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full

878system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers

879system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers

879system.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed
880system.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made
881system.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups
882system.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups
883system.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed
884system.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing
885system.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed
886system.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed
887system.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer
888system.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit.
889system.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit.
890system.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads.
891system.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores.
892system.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec)
893system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ
894system.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued
895system.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
896system.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling
897system.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph
898system.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed
899system.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle
900system.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle
901system.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle

880system.cpu1.rename.RenamedOperands 260404 # Number of destination operands rename has renamed
881system.cpu1.rename.RenameLookups 717496 # Number of register rename lookups that rename has made
882system.cpu1.rename.int_rename_lookups 555302 # Number of integer rename lookups
883system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups
884system.cpu1.rename.CommittedMaps 234261 # Number of HB maps that are committed
885system.cpu1.rename.UndoneMaps 26143 # Number of HB maps that are undone due to squashing
886system.cpu1.rename.serializingInsts 1622 # count of serializing insts renamed
887system.cpu1.rename.tempSerializingInsts 1759 # count of temporary serializing insts renamed
888system.cpu1.rename.skidInsts 20875 # count of insts added to the skid buffer
889system.cpu1.memDep0.insertedLoads 105786 # Number of loads inserted to the mem dependence unit.
890system.cpu1.memDep0.insertedStores 51568 # Number of stores inserted to the mem dependence unit.
891system.cpu1.memDep0.conflictingLoads 49714 # Number of conflicting loads.
892system.cpu1.memDep0.conflictingStores 45358 # Number of conflicting stores.
893system.cpu1.iq.iqInstsAdded 305985 # Number of instructions added to the IQ (excludes non-spec)
894system.cpu1.iq.iqNonSpecInstsAdded 5880 # Number of non-speculative instructions added to the IQ
895system.cpu1.iq.iqInstsIssued 304555 # Number of instructions issued
896system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued
897system.cpu1.iq.iqSquashedInstsExamined 23105 # Number of squashed instructions iterated over during squash; mainly for profiling
898system.cpu1.iq.iqSquashedOperandsExamined 18122 # Number of squashed operands that are examined and possibly removed from graph
899system.cpu1.iq.iqSquashedNonSpecRemoved 1124 # Number of squashed non-spec instructions that were removed
900system.cpu1.iq.issued_per_cycle::samples 186413 # Number of insts issued each cycle
901system.cpu1.iq.issued_per_cycle::mean 1.633765 # Number of insts issued each cycle
902system.cpu1.iq.issued_per_cycle::stdev 1.368784 # Number of insts issued each cycle

902system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

903system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

903system.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle
904system.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle
905system.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle
906system.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle
907system.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle
908system.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle
909system.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle
910system.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle
911system.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle

904system.cpu1.iq.issued_per_cycle::0 59464 31.90% 31.90% # Number of insts issued each cycle
905system.cpu1.iq.issued_per_cycle::1 19554 10.49% 42.39% # Number of insts issued each cycle
906system.cpu1.iq.issued_per_cycle::2 50315 26.99% 69.38% # Number of insts issued each cycle
907system.cpu1.iq.issued_per_cycle::3 50093 26.87% 96.25% # Number of insts issued each cycle
908system.cpu1.iq.issued_per_cycle::4 3572 1.92% 98.17% # Number of insts issued each cycle
909system.cpu1.iq.issued_per_cycle::5 1698 0.91% 99.08% # Number of insts issued each cycle
910system.cpu1.iq.issued_per_cycle::6 1008 0.54% 99.62% # Number of insts issued each cycle
911system.cpu1.iq.issued_per_cycle::7 406 0.22% 99.84% # Number of insts issued each cycle
912system.cpu1.iq.issued_per_cycle::8 303 0.16% 100.00% # Number of insts issued each cycle

912system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
913system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
914system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

913system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
914system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
915system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

915system.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle

916system.cpu1.iq.issued_per_cycle::total 186413 # Number of insts issued each cycle

916system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

917system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

917system.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available
918system.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available
919system.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available
920system.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available
921system.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available
922system.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available
923system.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available
924system.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available
925system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available
926system.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available
927system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available
928system.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available
929system.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available
930system.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available
931system.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available
932system.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available
933system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available
934system.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available
935system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available
936system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available
937system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available
938system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available
939system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available
940system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available
941system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available
942system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available
943system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available
944system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available
945system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available
946system.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available
947system.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available

918system.cpu1.iq.fu_full::IntAlu 182 38.89% 38.89% # attempts to use FU when none available
919system.cpu1.iq.fu_full::IntMult 0 0.00% 38.89% # attempts to use FU when none available
920system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.89% # attempts to use FU when none available
921system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.89% # attempts to use FU when none available
922system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.89% # attempts to use FU when none available
923system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.89% # attempts to use FU when none available
924system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.89% # attempts to use FU when none available
925system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.89% # attempts to use FU when none available
926system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.89% # attempts to use FU when none available
927system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.89% # attempts to use FU when none available
928system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.89% # attempts to use FU when none available
929system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.89% # attempts to use FU when none available
930system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.89% # attempts to use FU when none available
931system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.89% # attempts to use FU when none available
932system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.89% # attempts to use FU when none available
933system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.89% # attempts to use FU when none available
934system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.89% # attempts to use FU when none available
935system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.89% # attempts to use FU when none available
936system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.89% # attempts to use FU when none available
937system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.89% # attempts to use FU when none available
938system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.89% # attempts to use FU when none available
939system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.89% # attempts to use FU when none available
940system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.89% # attempts to use FU when none available
941system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.89% # attempts to use FU when none available
942system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.89% # attempts to use FU when none available
943system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.89% # attempts to use FU when none available
944system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.89% # attempts to use FU when none available
945system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.89% # attempts to use FU when none available
946system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.89% # attempts to use FU when none available
947system.cpu1.iq.fu_full::MemRead 58 12.39% 51.28% # attempts to use FU when none available
948system.cpu1.iq.fu_full::MemWrite 228 48.72% 100.00% # attempts to use FU when none available

948system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
949system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
950system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

949system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
950system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
951system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

951system.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued
952system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
953system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
954system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
955system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
956system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
957system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
958system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
959system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
960system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
961system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
962system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
963system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
964system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
965system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
966system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
967system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
968system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
969system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
970system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
971system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
972system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
973system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
974system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
975system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
976system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
977system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
978system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
979system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
980system.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued
981system.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued

952system.cpu1.iq.FU_type_0::IntAlu 145063 47.63% 47.63% # Type of FU issued
953system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.63% # Type of FU issued
954system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.63% # Type of FU issued
955system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.63% # Type of FU issued
956system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.63% # Type of FU issued
957system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.63% # Type of FU issued
958system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.63% # Type of FU issued
959system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.63% # Type of FU issued
960system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.63% # Type of FU issued
961system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.63% # Type of FU issued
962system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.63% # Type of FU issued
963system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.63% # Type of FU issued
964system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.63% # Type of FU issued
965system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.63% # Type of FU issued
966system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.63% # Type of FU issued
967system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.63% # Type of FU issued
968system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.63% # Type of FU issued
969system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.63% # Type of FU issued
970system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.63% # Type of FU issued
971system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.63% # Type of FU issued
972system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.63% # Type of FU issued
973system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.63% # Type of FU issued
974system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.63% # Type of FU issued
975system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.63% # Type of FU issued
976system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.63% # Type of FU issued
977system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.63% # Type of FU issued
978system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.63% # Type of FU issued
979system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.63% # Type of FU issued
980system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.63% # Type of FU issued
981system.cpu1.iq.FU_type_0::MemRead 108861 35.74% 83.38% # Type of FU issued
982system.cpu1.iq.FU_type_0::MemWrite 50631 16.62% 100.00% # Type of FU issued

982system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
983system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

983system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
984system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

984system.cpu1.iq.FU_type_0::total 288395 # Type of FU issued
985system.cpu1.iq.rate 1.490467 # Inst issue rate
986system.cpu1.iq.fu_busy_cnt 499 # FU busy when requested
987system.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst)
988system.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads
989system.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes
990system.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses

985system.cpu1.iq.FU_type_0::total 304555 # Type of FU issued
986system.cpu1.iq.rate 1.582087 # Inst issue rate
987system.cpu1.iq.fu_busy_cnt 468 # FU busy when requested
988system.cpu1.iq.fu_busy_rate 0.001537 # FU busy rate (busy events/executed inst)
989system.cpu1.iq.int_inst_queue_reads 796075 # Number of integer instruction queue reads
990system.cpu1.iq.int_inst_queue_writes 334945 # Number of integer instruction queue writes
991system.cpu1.iq.int_inst_queue_wakeup_accesses 300973 # Number of integer instruction queue wakeup accesses

991system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

992system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

992system.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes

993system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes

993system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

994system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

994system.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses

995system.cpu1.iq.int_alu_accesses 305023 # Number of integer alu accesses

995system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses

996system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses

996system.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores

997system.cpu1.iew.lsq.thread0.forwLoads 45252 # Number of loads that had data forwarded from stores

997system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

998system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

998system.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed
999system.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed
1000system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
1001system.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed

999system.cpu1.iew.lsq.thread0.squashedLoads 4194 # Number of loads squashed
1000system.cpu1.iew.lsq.thread0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed
1001system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
1002system.cpu1.iew.lsq.thread0.squashedStores 2536 # Number of stores squashed

1002system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1003system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1004system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1005system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1006system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1003system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1004system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1005system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1006system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1007system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1007system.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing
1008system.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking

1008system.cpu1.iew.iewSquashCycles 2316 # Number of cycles IEW is squashing
1009system.cpu1.iew.iewBlockCycles 6366 # Number of cycles IEW is blocking

1009system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking

1010system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking

1010system.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ
1011system.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch
1012system.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions
1013system.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions
1014system.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions
1015system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall

1011system.cpu1.iew.iewDispatchedInsts 362764 # Number of instructions dispatched to IQ
1012system.cpu1.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
1013system.cpu1.iew.iewDispLoadInsts 105786 # Number of dispatched load instructions
1014system.cpu1.iew.iewDispStoreInsts 51568 # Number of dispatched store instructions
1015system.cpu1.iew.iewDispNonSpecInsts 1528 # Number of dispatched non-speculative instructions
1016system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall

1016system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1017system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1017system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
1018system.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
1019system.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly
1020system.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute
1021system.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions
1022system.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed
1023system.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute

1018system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
1019system.cpu1.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
1020system.cpu1.iew.predictedNotTakenIncorrect 2397 # Number of branches that were predicted not taken incorrectly
1021system.cpu1.iew.branchMispredicts 2840 # Number of branch mispredicts detected at execute
1022system.cpu1.iew.iewExecutedInsts 302276 # Number of executed instructions
1023system.cpu1.iew.iewExecLoadInsts 104291 # Number of load instructions executed
1024system.cpu1.iew.iewExecSquashedInsts 2279 # Number of squashed instructions skipped in execute

1024system.cpu1.iew.exec_swp 0 # number of swp insts executed

1025system.cpu1.iew.exec_swp 0 # number of swp insts executed

1025system.cpu1.iew.exec_nop 47948 # number of nop insts executed
1026system.cpu1.iew.exec_refs 144318 # number of memory reference insts executed
1027system.cpu1.iew.exec_branches 58093 # Number of branches executed
1028system.cpu1.iew.exec_stores 46617 # Number of stores executed
1029system.cpu1.iew.exec_rate 1.477103 # Inst execution rate
1030system.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit
1031system.cpu1.iew.wb_count 284383 # cumulative count of insts written-back
1032system.cpu1.iew.wb_producers 161989 # num instructions producing a value
1033system.cpu1.iew.wb_consumers 169394 # num instructions consuming a value
1034system.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle
1035system.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back
1036system.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit
1037system.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards
1038system.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted
1039system.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle
1040system.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle
1041system.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle

1026system.cpu1.iew.exec_nop 50899 # number of nop insts executed
1027system.cpu1.iew.exec_refs 154635 # number of memory reference insts executed
1028system.cpu1.iew.exec_branches 61121 # Number of branches executed
1029system.cpu1.iew.exec_stores 50344 # Number of stores executed
1030system.cpu1.iew.exec_rate 1.570249 # Inst execution rate
1031system.cpu1.iew.wb_sent 301460 # cumulative count of insts sent to commit
1032system.cpu1.iew.wb_count 300973 # cumulative count of insts written-back
1033system.cpu1.iew.wb_producers 172395 # num instructions producing a value
1034system.cpu1.iew.wb_consumers 179828 # num instructions consuming a value
1035system.cpu1.iew.wb_rate 1.563480 # insts written-back per cycle
1036system.cpu1.iew.wb_fanout 0.958666 # average fanout of values written-back
1037system.cpu1.commit.commitSquashedInsts 24140 # The number of squashed insts skipped by commit
1038system.cpu1.commit.commitNonSpecStalls 4756 # The number of times commit has been forced to stall to communicate backwards
1039system.cpu1.commit.branchMispredicts 2238 # The number of times a branch was mispredicted
1040system.cpu1.commit.committed_per_cycle::samples 181815 # Number of insts commited each cycle
1041system.cpu1.commit.committed_per_cycle::mean 1.862272 # Number of insts commited each cycle
1042system.cpu1.commit.committed_per_cycle::stdev 2.110451 # Number of insts commited each cycle

1042system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1043system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1043system.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle
1044system.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle
1045system.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle
1046system.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle
1047system.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle
1048system.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle
1049system.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle
1050system.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle
1051system.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle

1044system.cpu1.commit.committed_per_cycle::0 63682 35.03% 35.03% # Number of insts commited each cycle
1045system.cpu1.commit.committed_per_cycle::1 57506 31.63% 66.65% # Number of insts commited each cycle
1046system.cpu1.commit.committed_per_cycle::2 5445 2.99% 69.65% # Number of insts commited each cycle
1047system.cpu1.commit.committed_per_cycle::3 5412 2.98% 72.63% # Number of insts commited each cycle
1048system.cpu1.commit.committed_per_cycle::4 1312 0.72% 73.35% # Number of insts commited each cycle
1049system.cpu1.commit.committed_per_cycle::5 45472 25.01% 98.36% # Number of insts commited each cycle
1050system.cpu1.commit.committed_per_cycle::6 770 0.42% 98.78% # Number of insts commited each cycle
1051system.cpu1.commit.committed_per_cycle::7 999 0.55% 99.33% # Number of insts commited each cycle
1052system.cpu1.commit.committed_per_cycle::8 1217 0.67% 100.00% # Number of insts commited each cycle

1052system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1053system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1054system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1053system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1054system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1055system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1055system.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle
1056system.cpu1.commit.committedInsts 318993 # Number of instructions committed
1057system.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed

1056system.cpu1.commit.committed_per_cycle::total 181815 # Number of insts commited each cycle
1057system.cpu1.commit.committedInsts 338589 # Number of instructions committed
1058system.cpu1.commit.committedOps 338589 # Number of ops (including micro ops) committed

1058system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

1059system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

1059system.cpu1.commit.refs 140209 # Number of memory references committed
1060system.cpu1.commit.loads 94853 # Number of loads committed
1061system.cpu1.commit.membars 4659 # Number of memory barriers committed
1062system.cpu1.commit.branches 55980 # Number of branches committed

1060system.cpu1.commit.refs 150624 # Number of memory references committed
1061system.cpu1.commit.loads 101592 # Number of loads committed
1062system.cpu1.commit.membars 4041 # Number of memory barriers committed
1063system.cpu1.commit.branches 59040 # Number of branches committed

1063system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.

1064system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.

1064system.cpu1.commit.int_insts 218308 # Number of committed integer instructions.

1065system.cpu1.commit.int_insts 231783 # Number of committed integer instructions.

1065system.cpu1.commit.function_calls 322 # Number of function calls committed.

1066system.cpu1.commit.function_calls 322 # Number of function calls committed.

1066system.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction
1067system.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction
1068system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction
1069system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction
1070system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction
1071system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction
1072system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction
1073system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction
1074system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction
1075system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction
1076system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction
1077system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction
1078system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction
1079system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction
1080system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction
1081system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction
1082system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction
1083system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction
1084system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction
1085system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction
1086system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction
1087system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction
1088system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction
1089system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction
1090system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction
1091system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction
1092system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction
1093system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction
1094system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction
1095system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction
1096system.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction
1097system.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction

1067system.cpu1.commit.op_class_0::No_OpClass 49829 14.72% 14.72% # Class of committed instruction
1068system.cpu1.commit.op_class_0::IntAlu 134095 39.60% 54.32% # Class of committed instruction
1069system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.32% # Class of committed instruction
1070system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.32% # Class of committed instruction
1071system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.32% # Class of committed instruction
1072system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.32% # Class of committed instruction
1073system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.32% # Class of committed instruction
1074system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.32% # Class of committed instruction
1075system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.32% # Class of committed instruction
1076system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.32% # Class of committed instruction
1077system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.32% # Class of committed instruction
1078system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.32% # Class of committed instruction
1079system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.32% # Class of committed instruction
1080system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.32% # Class of committed instruction
1081system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.32% # Class of committed instruction
1082system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.32% # Class of committed instruction
1083system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.32% # Class of committed instruction
1084system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.32% # Class of committed instruction
1085system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.32% # Class of committed instruction
1086system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.32% # Class of committed instruction
1087system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.32% # Class of committed instruction
1088system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.32% # Class of committed instruction
1089system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.32% # Class of committed instruction
1090system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.32% # Class of committed instruction
1091system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.32% # Class of committed instruction
1092system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.32% # Class of committed instruction
1093system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.32% # Class of committed instruction
1094system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.32% # Class of committed instruction
1095system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.32% # Class of committed instruction
1096system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.32% # Class of committed instruction
1097system.cpu1.commit.op_class_0::MemRead 105633 31.20% 85.52% # Class of committed instruction
1098system.cpu1.commit.op_class_0::MemWrite 49032 14.48% 100.00% # Class of committed instruction

1098system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1099system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1099system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1100system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1100system.cpu1.commit.op_class_0::total 318993 # Class of committed instruction
1101system.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached
1102system.cpu1.rob.rob_reads 524909 # The number of ROB reads
1103system.cpu1.rob.rob_writes 693389 # The number of ROB writes
1104system.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
1105system.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling

1101system.cpu1.commit.op_class_0::total 338589 # Class of committed instruction
1102system.cpu1.commit.bw_lim_events 1217 # number cycles where commit BW limit reached
1103system.cpu1.rob.rob_reads 542741 # The number of ROB reads
1104system.cpu1.rob.rob_writes 730091 # The number of ROB writes
1105system.cpu1.timesIdled 236 # Number of times that the entire CPU went into an idle state and unscheduled itself
1106system.cpu1.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling

1106system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

1107system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

1107system.cpu1.committedInsts 267566 # Number of Instructions Simulated
1108system.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated
1109system.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction
1110system.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads
1111system.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle
1112system.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads
1113system.cpu1.int_regfile_reads 496242 # number of integer regfile reads
1114system.cpu1.int_regfile_writes 230976 # number of integer regfile writes

1108system.cpu1.committedInsts 284719 # Number of Instructions Simulated
1109system.cpu1.committedOps 284719 # Number of Ops (including micro ops) Simulated
1110system.cpu1.cpi 0.676112 # CPI: Cycles Per Instruction
1111system.cpu1.cpi_total 0.676112 # CPI: Total CPI of All Threads
1112system.cpu1.ipc 1.479044 # IPC: Instructions Per Cycle
1113system.cpu1.ipc_total 1.479044 # IPC: Total IPC of All Threads
1114system.cpu1.int_regfile_reads 527704 # number of integer regfile reads
1115system.cpu1.int_regfile_writes 245054 # number of integer regfile writes

1115system.cpu1.fp_regfile_writes 64 # number of floating regfile writes

1116system.cpu1.fp_regfile_writes 64 # number of floating regfile writes

1116system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads

1117system.cpu1.misc_regfile_reads 156484 # number of misc regfile reads

1117system.cpu1.misc_regfile_writes 648 # number of misc regfile writes

1118system.cpu1.misc_regfile_writes 648 # number of misc regfile writes

1118system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

1119system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

1119system.cpu1.dcache.tags.replacements 0 # number of replacements

1120system.cpu1.dcache.tags.replacements 0 # number of replacements

1120system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use
1121system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks.
1122system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
1123system.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks.

1121system.cpu1.dcache.tags.tagsinuse 26.869792 # Cycle average of tags in use
1122system.cpu1.dcache.tags.total_refs 56025 # Total number of references to valid blocks.
1123system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1124system.cpu1.dcache.tags.avg_refs 1931.896552 # Average number of references to valid blocks.

1124system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1125system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1125system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor
1126system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy
1127system.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy
1128system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
1129system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
1130system.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
1131system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
1132system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
1133system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses
1134system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses
1135system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1136system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits
1137system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits
1138system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits
1139system.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits
1140system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
1141system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1142system.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits
1143system.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits
1144system.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits
1145system.cpu1.dcache.overall_hits::total 100708 # number of overall hits

1126system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.869792 # Average occupied blocks per requestor
1127system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052480 # Average percentage of cache occupancy
1128system.cpu1.dcache.tags.occ_percent::total 0.052480 # Average percentage of cache occupancy
1129system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1130system.cpu1.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
1131system.cpu1.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
1132system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1133system.cpu1.dcache.tags.tag_accesses 432447 # Number of tag accesses
1134system.cpu1.dcache.tags.data_accesses 432447 # Number of data accesses
1135system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1136system.cpu1.dcache.ReadReq_hits::cpu1.data 58508 # number of ReadReq hits
1137system.cpu1.dcache.ReadReq_hits::total 58508 # number of ReadReq hits
1138system.cpu1.dcache.WriteReq_hits::cpu1.data 48814 # number of WriteReq hits
1139system.cpu1.dcache.WriteReq_hits::total 48814 # number of WriteReq hits
1140system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
1141system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
1142system.cpu1.dcache.demand_hits::cpu1.data 107322 # number of demand (read+write) hits
1143system.cpu1.dcache.demand_hits::total 107322 # number of demand (read+write) hits
1144system.cpu1.dcache.overall_hits::cpu1.data 107322 # number of overall hits
1145system.cpu1.dcache.overall_hits::total 107322 # number of overall hits

1146system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses
1147system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses

1148system.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses
1149system.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses

1148system.cpu1.dcache.WriteReq_misses::cpu1.data 149 # number of WriteReq misses
1149system.cpu1.dcache.WriteReq_misses::total 149 # number of WriteReq misses

1150system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses
1151system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses

1152system.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses
1153system.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses
1154system.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses
1155system.cpu1.dcache.overall_misses::total 653 # number of overall misses
1156system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles
1157system.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles
1158system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles
1159system.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles
1160system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles
1161system.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles
1162system.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles
1163system.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles
1164system.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles
1165system.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles
1166system.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses)
1167system.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses)
1168system.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses)
1169system.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses)
1170system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
1171system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
1172system.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses
1173system.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses
1174system.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses
1175system.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses
1176system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses
1177system.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses
1178system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses
1179system.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses
1180system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses
1181system.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses
1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses
1183system.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses
1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses
1185system.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses
1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency
1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency
1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency
1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency
1190system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency
1191system.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency
1192system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency
1193system.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency
1194system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency
1195system.cpu1.dcache.overall_avg_miss_latency::total 19893.568147 # average overall miss latency

1152system.cpu1.dcache.demand_misses::cpu1.data 656 # number of demand (read+write) misses
1153system.cpu1.dcache.demand_misses::total 656 # number of demand (read+write) misses
1154system.cpu1.dcache.overall_misses::cpu1.data 656 # number of overall misses
1155system.cpu1.dcache.overall_misses::total 656 # number of overall misses
1156system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4815500 # number of ReadReq miss cycles
1157system.cpu1.dcache.ReadReq_miss_latency::total 4815500 # number of ReadReq miss cycles
1158system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3532500 # number of WriteReq miss cycles
1159system.cpu1.dcache.WriteReq_miss_latency::total 3532500 # number of WriteReq miss cycles
1160system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 364000 # number of SwapReq miss cycles
1161system.cpu1.dcache.SwapReq_miss_latency::total 364000 # number of SwapReq miss cycles
1162system.cpu1.dcache.demand_miss_latency::cpu1.data 8348000 # number of demand (read+write) miss cycles
1163system.cpu1.dcache.demand_miss_latency::total 8348000 # number of demand (read+write) miss cycles
1164system.cpu1.dcache.overall_miss_latency::cpu1.data 8348000 # number of overall miss cycles
1165system.cpu1.dcache.overall_miss_latency::total 8348000 # number of overall miss cycles
1166system.cpu1.dcache.ReadReq_accesses::cpu1.data 59015 # number of ReadReq accesses(hits+misses)
1167system.cpu1.dcache.ReadReq_accesses::total 59015 # number of ReadReq accesses(hits+misses)
1168system.cpu1.dcache.WriteReq_accesses::cpu1.data 48963 # number of WriteReq accesses(hits+misses)
1169system.cpu1.dcache.WriteReq_accesses::total 48963 # number of WriteReq accesses(hits+misses)
1170system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
1171system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
1172system.cpu1.dcache.demand_accesses::cpu1.data 107978 # number of demand (read+write) accesses
1173system.cpu1.dcache.demand_accesses::total 107978 # number of demand (read+write) accesses
1174system.cpu1.dcache.overall_accesses::cpu1.data 107978 # number of overall (read+write) accesses
1175system.cpu1.dcache.overall_accesses::total 107978 # number of overall (read+write) accesses
1176system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008591 # miss rate for ReadReq accesses
1177system.cpu1.dcache.ReadReq_miss_rate::total 0.008591 # miss rate for ReadReq accesses
1178system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003043 # miss rate for WriteReq accesses
1179system.cpu1.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses
1180system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.840580 # miss rate for SwapReq accesses
1181system.cpu1.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses
1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006075 # miss rate for demand accesses
1183system.cpu1.dcache.demand_miss_rate::total 0.006075 # miss rate for demand accesses
1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006075 # miss rate for overall accesses
1185system.cpu1.dcache.overall_miss_rate::total 0.006075 # miss rate for overall accesses
1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 9498.027613 # average ReadReq miss latency
1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 9498.027613 # average ReadReq miss latency
1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691 # average WriteReq miss latency
1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691 # average WriteReq miss latency
1190system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6275.862069 # average SwapReq miss latency
1191system.cpu1.dcache.SwapReq_avg_miss_latency::total 6275.862069 # average SwapReq miss latency
1192system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency
1193system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756 # average overall miss latency
1194system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency
1195system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756 # average overall miss latency

1196system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1197system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1198system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1199system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1200system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1201system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1202system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341 # number of ReadReq MSHR hits
1203system.cpu1.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits
1204system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 40 # number of WriteReq MSHR hits
1205system.cpu1.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits
1206system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 2 # number of SwapReq MSHR hits
1207system.cpu1.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits
1208system.cpu1.dcache.demand_mshr_hits::cpu1.data 381 # number of demand (read+write) MSHR hits
1209system.cpu1.dcache.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits
1210system.cpu1.dcache.overall_mshr_hits::cpu1.data 381 # number of overall MSHR hits
1211system.cpu1.dcache.overall_mshr_hits::total 381 # number of overall MSHR hits
1212system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses
1213system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses

1202system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits
1203system.cpu1.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits
1204system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits
1205system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits
1206system.cpu1.dcache.demand_mshr_hits::cpu1.data 387 # number of demand (read+write) MSHR hits
1207system.cpu1.dcache.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits
1208system.cpu1.dcache.overall_mshr_hits::cpu1.data 387 # number of overall MSHR hits
1209system.cpu1.dcache.overall_mshr_hits::total 387 # number of overall MSHR hits
1210system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses
1211system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses

1214system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
1215system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses

1212system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
1213system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses

1216system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
1217system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
1218system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses
1219system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
1220system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses
1221system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
1222system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2098000 # number of ReadReq MSHR miss cycles
1223system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles
1224system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1657500 # number of WriteReq MSHR miss cycles
1225system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1657500 # number of WriteReq MSHR miss cycles
1226system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 738000 # number of SwapReq MSHR miss cycles
1227system.cpu1.dcache.SwapReq_mshr_miss_latency::total 738000 # number of SwapReq MSHR miss cycles
1228system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3755500 # number of demand (read+write) MSHR miss cycles
1229system.cpu1.dcache.demand_mshr_miss_latency::total 3755500 # number of demand (read+write) MSHR miss cycles
1230system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3755500 # number of overall MSHR miss cycles
1231system.cpu1.dcache.overall_mshr_miss_latency::total 3755500 # number of overall MSHR miss cycles
1232system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002960 # mshr miss rate for ReadReq accesses
1233system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002960 # mshr miss rate for ReadReq accesses
1234system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002341 # mshr miss rate for WriteReq accesses
1235system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002341 # mshr miss rate for WriteReq accesses
1236system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses
1237system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses
1238system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for demand accesses
1239system.cpu1.dcache.demand_mshr_miss_rate::total 0.002683 # mshr miss rate for demand accesses
1240system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for overall accesses
1241system.cpu1.dcache.overall_mshr_miss_rate::total 0.002683 # mshr miss rate for overall accesses
1242system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12638.554217 # average ReadReq mshr miss latency
1243system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12638.554217 # average ReadReq mshr miss latency
1244system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15636.792453 # average WriteReq mshr miss latency
1245system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15636.792453 # average WriteReq mshr miss latency
1246system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 13178.571429 # average SwapReq mshr miss latency
1247system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 13178.571429 # average SwapReq mshr miss latency
1248system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency
1249system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency
1250system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency
1251system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency
1252system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1253system.cpu1.icache.tags.replacements 579 # number of replacements
1254system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use
1255system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks.
1256system.cpu1.icache.tags.sampled_refs 713 # Sample count of references to valid blocks.
1257system.cpu1.icache.tags.avg_refs 31.784011 # Average number of references to valid blocks.

1214system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses
1215system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
1216system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses
1217system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
1218system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses
1219system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
1220system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1494500 # number of ReadReq MSHR miss cycles
1221system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1494500 # number of ReadReq MSHR miss cycles
1222system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1455500 # number of WriteReq MSHR miss cycles
1223system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1455500 # number of WriteReq MSHR miss cycles
1224system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 306000 # number of SwapReq MSHR miss cycles
1225system.cpu1.dcache.SwapReq_mshr_miss_latency::total 306000 # number of SwapReq MSHR miss cycles
1226system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2950000 # number of demand (read+write) MSHR miss cycles
1227system.cpu1.dcache.demand_mshr_miss_latency::total 2950000 # number of demand (read+write) MSHR miss cycles
1228system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2950000 # number of overall MSHR miss cycles
1229system.cpu1.dcache.overall_mshr_miss_latency::total 2950000 # number of overall MSHR miss cycles
1230system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002762 # mshr miss rate for ReadReq accesses
1231system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002762 # mshr miss rate for ReadReq accesses
1232system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002165 # mshr miss rate for WriteReq accesses
1233system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002165 # mshr miss rate for WriteReq accesses
1234system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.840580 # mshr miss rate for SwapReq accesses
1235system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses
1236system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for demand accesses
1237system.cpu1.dcache.demand_mshr_miss_rate::total 0.002491 # mshr miss rate for demand accesses
1238system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for overall accesses
1239system.cpu1.dcache.overall_mshr_miss_rate::total 0.002491 # mshr miss rate for overall accesses
1240system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9168.711656 # average ReadReq mshr miss latency
1241system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9168.711656 # average ReadReq mshr miss latency
1242system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075 # average WriteReq mshr miss latency
1243system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075 # average WriteReq mshr miss latency
1244system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5275.862069 # average SwapReq mshr miss latency
1245system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5275.862069 # average SwapReq mshr miss latency
1246system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency
1247system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency
1248system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency
1249system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency
1250system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1251system.cpu1.icache.tags.replacements 556 # number of replacements
1252system.cpu1.icache.tags.tagsinuse 97.374754 # Cycle average of tags in use
1253system.cpu1.icache.tags.total_refs 21335 # Total number of references to valid blocks.
1254system.cpu1.icache.tags.sampled_refs 687 # Sample count of references to valid blocks.
1255system.cpu1.icache.tags.avg_refs 31.055313 # Average number of references to valid blocks.

1258system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1256system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1259system.cpu1.icache.tags.occ_blocks::cpu1.inst 98.515696 # Average occupied blocks per requestor
1260system.cpu1.icache.tags.occ_percent::cpu1.inst 0.192413 # Average percentage of cache occupancy
1261system.cpu1.icache.tags.occ_percent::total 0.192413 # Average percentage of cache occupancy
1262system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
1263system.cpu1.icache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
1264system.cpu1.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
1265system.cpu1.icache.tags.age_task_id_blocks_1024::2 8 # Occupied blocks per task id
1266system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id
1267system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses
1268system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses
1269system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1270system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits
1271system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits
1272system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits
1273system.cpu1.icache.demand_hits::total 22662 # number of demand (read+write) hits
1274system.cpu1.icache.overall_hits::cpu1.inst 22662 # number of overall hits
1275system.cpu1.icache.overall_hits::total 22662 # number of overall hits
1276system.cpu1.icache.ReadReq_misses::cpu1.inst 870 # number of ReadReq misses
1277system.cpu1.icache.ReadReq_misses::total 870 # number of ReadReq misses
1278system.cpu1.icache.demand_misses::cpu1.inst 870 # number of demand (read+write) misses
1279system.cpu1.icache.demand_misses::total 870 # number of demand (read+write) misses
1280system.cpu1.icache.overall_misses::cpu1.inst 870 # number of overall misses
1281system.cpu1.icache.overall_misses::total 870 # number of overall misses
1282system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19533000 # number of ReadReq miss cycles
1283system.cpu1.icache.ReadReq_miss_latency::total 19533000 # number of ReadReq miss cycles
1284system.cpu1.icache.demand_miss_latency::cpu1.inst 19533000 # number of demand (read+write) miss cycles
1285system.cpu1.icache.demand_miss_latency::total 19533000 # number of demand (read+write) miss cycles
1286system.cpu1.icache.overall_miss_latency::cpu1.inst 19533000 # number of overall miss cycles
1287system.cpu1.icache.overall_miss_latency::total 19533000 # number of overall miss cycles
1288system.cpu1.icache.ReadReq_accesses::cpu1.inst 23532 # number of ReadReq accesses(hits+misses)
1289system.cpu1.icache.ReadReq_accesses::total 23532 # number of ReadReq accesses(hits+misses)
1290system.cpu1.icache.demand_accesses::cpu1.inst 23532 # number of demand (read+write) accesses
1291system.cpu1.icache.demand_accesses::total 23532 # number of demand (read+write) accesses
1292system.cpu1.icache.overall_accesses::cpu1.inst 23532 # number of overall (read+write) accesses
1293system.cpu1.icache.overall_accesses::total 23532 # number of overall (read+write) accesses
1294system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036971 # miss rate for ReadReq accesses
1295system.cpu1.icache.ReadReq_miss_rate::total 0.036971 # miss rate for ReadReq accesses
1296system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036971 # miss rate for demand accesses
1297system.cpu1.icache.demand_miss_rate::total 0.036971 # miss rate for demand accesses
1298system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036971 # miss rate for overall accesses
1299system.cpu1.icache.overall_miss_rate::total 0.036971 # miss rate for overall accesses
1300system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22451.724138 # average ReadReq miss latency
1301system.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency
1302system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency
1303system.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency
1304system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency
1305system.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency

1257system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.374754 # Average occupied blocks per requestor
1258system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190185 # Average percentage of cache occupancy
1259system.cpu1.icache.tags.occ_percent::total 0.190185 # Average percentage of cache occupancy
1260system.cpu1.icache.tags.occ_task_id_blocks::1024 131 # Occupied blocks per task id
1261system.cpu1.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
1262system.cpu1.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
1263system.cpu1.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
1264system.cpu1.icache.tags.occ_task_id_percent::1024 0.255859 # Percentage of cache occupancy per task id
1265system.cpu1.icache.tags.tag_accesses 22867 # Number of tag accesses
1266system.cpu1.icache.tags.data_accesses 22867 # Number of data accesses
1267system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1268system.cpu1.icache.ReadReq_hits::cpu1.inst 21335 # number of ReadReq hits
1269system.cpu1.icache.ReadReq_hits::total 21335 # number of ReadReq hits
1270system.cpu1.icache.demand_hits::cpu1.inst 21335 # number of demand (read+write) hits
1271system.cpu1.icache.demand_hits::total 21335 # number of demand (read+write) hits
1272system.cpu1.icache.overall_hits::cpu1.inst 21335 # number of overall hits
1273system.cpu1.icache.overall_hits::total 21335 # number of overall hits
1274system.cpu1.icache.ReadReq_misses::cpu1.inst 845 # number of ReadReq misses
1275system.cpu1.icache.ReadReq_misses::total 845 # number of ReadReq misses
1276system.cpu1.icache.demand_misses::cpu1.inst 845 # number of demand (read+write) misses
1277system.cpu1.icache.demand_misses::total 845 # number of demand (read+write) misses
1278system.cpu1.icache.overall_misses::cpu1.inst 845 # number of overall misses
1279system.cpu1.icache.overall_misses::total 845 # number of overall misses
1280system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 18952000 # number of ReadReq miss cycles
1281system.cpu1.icache.ReadReq_miss_latency::total 18952000 # number of ReadReq miss cycles
1282system.cpu1.icache.demand_miss_latency::cpu1.inst 18952000 # number of demand (read+write) miss cycles
1283system.cpu1.icache.demand_miss_latency::total 18952000 # number of demand (read+write) miss cycles
1284system.cpu1.icache.overall_miss_latency::cpu1.inst 18952000 # number of overall miss cycles
1285system.cpu1.icache.overall_miss_latency::total 18952000 # number of overall miss cycles
1286system.cpu1.icache.ReadReq_accesses::cpu1.inst 22180 # number of ReadReq accesses(hits+misses)
1287system.cpu1.icache.ReadReq_accesses::total 22180 # number of ReadReq accesses(hits+misses)
1288system.cpu1.icache.demand_accesses::cpu1.inst 22180 # number of demand (read+write) accesses
1289system.cpu1.icache.demand_accesses::total 22180 # number of demand (read+write) accesses
1290system.cpu1.icache.overall_accesses::cpu1.inst 22180 # number of overall (read+write) accesses
1291system.cpu1.icache.overall_accesses::total 22180 # number of overall (read+write) accesses
1292system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038097 # miss rate for ReadReq accesses
1293system.cpu1.icache.ReadReq_miss_rate::total 0.038097 # miss rate for ReadReq accesses
1294system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038097 # miss rate for demand accesses
1295system.cpu1.icache.demand_miss_rate::total 0.038097 # miss rate for demand accesses
1296system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038097 # miss rate for overall accesses
1297system.cpu1.icache.overall_miss_rate::total 0.038097 # miss rate for overall accesses
1298system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367 # average ReadReq miss latency
1299system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367 # average ReadReq miss latency
1300system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency
1301system.cpu1.icache.demand_avg_miss_latency::total 22428.402367 # average overall miss latency
1302system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency
1303system.cpu1.icache.overall_avg_miss_latency::total 22428.402367 # average overall miss latency

1306system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked
1307system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1308system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked
1309system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1310system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked
1311system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1304system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked
1305system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1306system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked
1307system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1308system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked
1309system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1312system.cpu1.icache.writebacks::writebacks 579 # number of writebacks
1313system.cpu1.icache.writebacks::total 579 # number of writebacks
1314system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits
1315system.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits
1316system.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits
1317system.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits
1318system.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits
1319system.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits
1320system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses
1321system.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses
1322system.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses
1323system.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses
1324system.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses
1325system.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses
1326system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles
1327system.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles
1328system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles
1329system.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles
1330system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles
1331system.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles
1332system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses
1333system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses
1334system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses
1335system.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses
1336system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses
1337system.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses
1338system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency
1339system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency
1340system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency
1341system.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency
1342system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency
1343system.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency
1344system.cpu2.branchPred.lookups 63667 # Number of BP lookups
1345system.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted
1346system.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect
1347system.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups

1310system.cpu1.icache.writebacks::writebacks 556 # number of writebacks
1311system.cpu1.icache.writebacks::total 556 # number of writebacks
1312system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 # number of ReadReq MSHR hits
1313system.cpu1.icache.ReadReq_mshr_hits::total 158 # number of ReadReq MSHR hits
1314system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 # number of demand (read+write) MSHR hits
1315system.cpu1.icache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits
1316system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 # number of overall MSHR hits
1317system.cpu1.icache.overall_mshr_hits::total 158 # number of overall MSHR hits
1318system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 687 # number of ReadReq MSHR misses
1319system.cpu1.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses
1320system.cpu1.icache.demand_mshr_misses::cpu1.inst 687 # number of demand (read+write) MSHR misses
1321system.cpu1.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses
1322system.cpu1.icache.overall_mshr_misses::cpu1.inst 687 # number of overall MSHR misses
1323system.cpu1.icache.overall_mshr_misses::total 687 # number of overall MSHR misses
1324system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 14723000 # number of ReadReq MSHR miss cycles
1325system.cpu1.icache.ReadReq_mshr_miss_latency::total 14723000 # number of ReadReq MSHR miss cycles
1326system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 14723000 # number of demand (read+write) MSHR miss cycles
1327system.cpu1.icache.demand_mshr_miss_latency::total 14723000 # number of demand (read+write) MSHR miss cycles
1328system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 14723000 # number of overall MSHR miss cycles
1329system.cpu1.icache.overall_mshr_miss_latency::total 14723000 # number of overall MSHR miss cycles
1330system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for ReadReq accesses
1331system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030974 # mshr miss rate for ReadReq accesses
1332system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for demand accesses
1333system.cpu1.icache.demand_mshr_miss_rate::total 0.030974 # mshr miss rate for demand accesses
1334system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for overall accesses
1335system.cpu1.icache.overall_mshr_miss_rate::total 0.030974 # mshr miss rate for overall accesses
1336system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average ReadReq mshr miss latency
1337system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806 # average ReadReq mshr miss latency
1338system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency
1339system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency
1340system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency
1341system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency
1342system.cpu2.branchPred.lookups 66096 # Number of BP lookups
1343system.cpu2.branchPred.condPredicted 57926 # Number of conditional branches predicted
1344system.cpu2.branchPred.condIncorrect 2486 # Number of conditional branches incorrect
1345system.cpu2.branchPred.BTBLookups 57464 # Number of BTB lookups

1348system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
1349system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1350system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1346system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
1347system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1348system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1351system.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target.

1349system.cpu2.branchPred.usedRAS 2115 # Number of times the RAS was used to get a target.

1352system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1350system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1353system.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups.
1354system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits.
1355system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses.
1356system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches.
1357system.cpu2.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
1358system.cpu2.numCycles 193104 # number of cpu cycles simulated

1351system.cpu2.branchPred.indirectLookups 57464 # Number of indirect predictor lookups.
1352system.cpu2.branchPred.indirectHits 46751 # Number of indirect target hits.
1353system.cpu2.branchPred.indirectMisses 10713 # Number of indirect misses.
1354system.cpu2.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches.
1355system.cpu2.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
1356system.cpu2.numCycles 192112 # number of cpu cycles simulated

1359system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1360system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed

1357system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1358system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed

1361system.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss
1362system.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed
1363system.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered
1364system.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken
1365system.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked
1366system.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing

1359system.cpu2.fetch.icacheStallCycles 39817 # Number of cycles fetch is stalled on an Icache miss
1360system.cpu2.fetch.Insts 356778 # Number of instructions fetch has processed
1361system.cpu2.fetch.Branches 66096 # Number of branches that fetch encountered
1362system.cpu2.fetch.predictedBranches 48866 # Number of branches that fetch has predicted taken
1363system.cpu2.fetch.Cycles 146191 # Number of cycles fetch has run and was not squashing or blocked
1364system.cpu2.fetch.SquashCycles 5129 # Number of cycles fetch has spent squashing

1367system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1368system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1365system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1366system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1369system.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps
1370system.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR
1371system.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched
1372system.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed
1373system.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total)
1374system.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total)
1375system.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total)

1367system.cpu2.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps
1368system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR
1369system.cpu2.fetch.CacheLines 28579 # Number of cache lines fetched
1370system.cpu2.fetch.IcacheSquashes 972 # Number of outstanding Icache misses that were squashed
1371system.cpu2.fetch.rateDist::samples 190509 # Number of instructions fetched each cycle (Total)
1372system.cpu2.fetch.rateDist::mean 1.872762 # Number of instructions fetched each cycle (Total)
1373system.cpu2.fetch.rateDist::stdev 2.344982 # Number of instructions fetched each cycle (Total)

1376system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1374system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1377system.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total)
1378system.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total)
1379system.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total)
1380system.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total)
1381system.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total)
1382system.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total)
1383system.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total)
1384system.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total)
1385system.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total)

1375system.cpu2.fetch.rateDist::0 72004 37.80% 37.80% # Number of instructions fetched each cycle (Total)
1376system.cpu2.fetch.rateDist::1 58377 30.64% 68.44% # Number of instructions fetched each cycle (Total)
1377system.cpu2.fetch.rateDist::2 8422 4.42% 72.86% # Number of instructions fetched each cycle (Total)
1378system.cpu2.fetch.rateDist::3 3406 1.79% 74.65% # Number of instructions fetched each cycle (Total)
1379system.cpu2.fetch.rateDist::4 670 0.35% 75.00% # Number of instructions fetched each cycle (Total)
1380system.cpu2.fetch.rateDist::5 36267 19.04% 94.04% # Number of instructions fetched each cycle (Total)
1381system.cpu2.fetch.rateDist::6 1053 0.55% 94.59% # Number of instructions fetched each cycle (Total)
1382system.cpu2.fetch.rateDist::7 1474 0.77% 95.36% # Number of instructions fetched each cycle (Total)
1383system.cpu2.fetch.rateDist::8 8836 4.64% 100.00% # Number of instructions fetched each cycle (Total)

1386system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1387system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1388system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1384system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1385system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1386system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1389system.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total)
1390system.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle
1391system.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle
1392system.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle
1393system.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked
1394system.cpu2.decode.RunCycles 84446 # Number of cycles decode is running
1395system.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking
1396system.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing
1397system.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode
1398system.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing
1399system.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle
1400system.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking
1401system.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst
1402system.cpu2.rename.RunCycles 85216 # Number of cycles rename is running
1403system.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking
1404system.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename
1405system.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full

1387system.cpu2.fetch.rateDist::total 190509 # Number of instructions fetched each cycle (Total)
1388system.cpu2.fetch.branchRate 0.344049 # Number of branch fetches per cycle
1389system.cpu2.fetch.rate 1.857135 # Number of inst fetches per cycle
1390system.cpu2.decode.IdleCycles 22990 # Number of cycles decode is idle
1391system.cpu2.decode.BlockedCycles 70899 # Number of cycles decode is blocked
1392system.cpu2.decode.RunCycles 89451 # Number of cycles decode is running
1393system.cpu2.decode.UnblockCycles 4595 # Number of cycles decode is unblocking
1394system.cpu2.decode.SquashCycles 2564 # Number of cycles decode is squashing
1395system.cpu2.decode.DecodedInsts 324452 # Number of instructions handled by decode
1396system.cpu2.rename.SquashCycles 2564 # Number of cycles rename is squashing
1397system.cpu2.rename.IdleCycles 24019 # Number of cycles rename is idle
1398system.cpu2.rename.BlockCycles 34614 # Number of cycles rename is blocking
1399system.cpu2.rename.serializeStallCycles 13407 # count of cycles rename stalled for serializing inst
1400system.cpu2.rename.RunCycles 89996 # Number of cycles rename is running
1401system.cpu2.rename.UnblockCycles 25899 # Number of cycles rename is unblocking
1402system.cpu2.rename.RenamedInsts 317685 # Number of instructions processed by rename
1403system.cpu2.rename.IQFullEvents 22128 # Number of times rename has blocked due to IQ full

1406system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
1407system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers

1404system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
1405system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers

1408system.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed
1409system.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made
1410system.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups
1411system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups
1412system.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed
1413system.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing
1414system.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed
1415system.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed
1416system.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer
1417system.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit.
1418system.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit.
1419system.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads.
1420system.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores.
1421system.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec)
1422system.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ
1423system.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued
1424system.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued
1425system.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling
1426system.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph
1427system.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed
1428system.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle
1429system.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle
1430system.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle

1406system.cpu2.rename.RenamedOperands 221990 # Number of destination operands rename has renamed
1407system.cpu2.rename.RenameLookups 601950 # Number of register rename lookups that rename has made
1408system.cpu2.rename.int_rename_lookups 469192 # Number of integer rename lookups
1409system.cpu2.rename.fp_rename_lookups 40 # Number of floating rename lookups
1410system.cpu2.rename.CommittedMaps 192480 # Number of HB maps that are committed
1411system.cpu2.rename.UndoneMaps 29510 # Number of HB maps that are undone due to squashing
1412system.cpu2.rename.serializingInsts 1686 # count of serializing insts renamed
1413system.cpu2.rename.tempSerializingInsts 1819 # count of temporary serializing insts renamed
1414system.cpu2.rename.skidInsts 31415 # count of insts added to the skid buffer
1415system.cpu2.memDep0.insertedLoads 86703 # Number of loads inserted to the mem dependence unit.
1416system.cpu2.memDep0.insertedStores 40578 # Number of stores inserted to the mem dependence unit.
1417system.cpu2.memDep0.conflictingLoads 41384 # Number of conflicting loads.
1418system.cpu2.memDep0.conflictingStores 34173 # Number of conflicting stores.
1419system.cpu2.iq.iqInstsAdded 258235 # Number of instructions added to the IQ (excludes non-spec)
1420system.cpu2.iq.iqNonSpecInstsAdded 8782 # Number of non-speculative instructions added to the IQ
1421system.cpu2.iq.iqInstsIssued 258833 # Number of instructions issued
1422system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
1423system.cpu2.iq.iqSquashedInstsExamined 25653 # Number of squashed instructions iterated over during squash; mainly for profiling
1424system.cpu2.iq.iqSquashedOperandsExamined 20039 # Number of squashed operands that are examined and possibly removed from graph
1425system.cpu2.iq.iqSquashedNonSpecRemoved 1265 # Number of squashed non-spec instructions that were removed
1426system.cpu2.iq.issued_per_cycle::samples 190509 # Number of insts issued each cycle
1427system.cpu2.iq.issued_per_cycle::mean 1.358639 # Number of insts issued each cycle
1428system.cpu2.iq.issued_per_cycle::stdev 1.384430 # Number of insts issued each cycle

1431system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1429system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1432system.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle
1433system.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle
1434system.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle
1435system.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle
1436system.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle
1437system.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle
1438system.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle
1439system.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle
1440system.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle

1430system.cpu2.iq.issued_per_cycle::0 76931 40.38% 40.38% # Number of insts issued each cycle
1431system.cpu2.iq.issued_per_cycle::1 28046 14.72% 55.10% # Number of insts issued each cycle
1432system.cpu2.iq.issued_per_cycle::2 39341 20.65% 75.75% # Number of insts issued each cycle
1433system.cpu2.iq.issued_per_cycle::3 39028 20.49% 96.24% # Number of insts issued each cycle
1434system.cpu2.iq.issued_per_cycle::4 3604 1.89% 98.13% # Number of insts issued each cycle
1435system.cpu2.iq.issued_per_cycle::5 1759 0.92% 99.06% # Number of insts issued each cycle
1436system.cpu2.iq.issued_per_cycle::6 1073 0.56% 99.62% # Number of insts issued each cycle
1437system.cpu2.iq.issued_per_cycle::7 444 0.23% 99.85% # Number of insts issued each cycle
1438system.cpu2.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle

1441system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1442system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1443system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1439system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1440system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1441system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1444system.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle

1442system.cpu2.iq.issued_per_cycle::total 190509 # Number of insts issued each cycle

1445system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1443system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1446system.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available
1447system.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available
1448system.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available
1449system.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available
1450system.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available
1451system.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available
1452system.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available
1453system.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available
1454system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
1455system.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available
1456system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available
1457system.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available
1458system.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available
1459system.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available
1460system.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available
1461system.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available
1462system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available
1463system.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available
1464system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available
1465system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available
1466system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available
1467system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available
1468system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available
1469system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available
1470system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available
1471system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available
1472system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available
1473system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available
1474system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
1475system.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available
1476system.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available

1444system.cpu2.iq.fu_full::IntAlu 204 42.15% 42.15% # attempts to use FU when none available
1445system.cpu2.iq.fu_full::IntMult 0 0.00% 42.15% # attempts to use FU when none available
1446system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.15% # attempts to use FU when none available
1447system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.15% # attempts to use FU when none available
1448system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.15% # attempts to use FU when none available
1449system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.15% # attempts to use FU when none available
1450system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.15% # attempts to use FU when none available
1451system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.15% # attempts to use FU when none available
1452system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.15% # attempts to use FU when none available
1453system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.15% # attempts to use FU when none available
1454system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.15% # attempts to use FU when none available
1455system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.15% # attempts to use FU when none available
1456system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.15% # attempts to use FU when none available
1457system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.15% # attempts to use FU when none available
1458system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.15% # attempts to use FU when none available
1459system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.15% # attempts to use FU when none available
1460system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.15% # attempts to use FU when none available
1461system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.15% # attempts to use FU when none available
1462system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.15% # attempts to use FU when none available
1463system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.15% # attempts to use FU when none available
1464system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.15% # attempts to use FU when none available
1465system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.15% # attempts to use FU when none available
1466system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.15% # attempts to use FU when none available
1467system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.15% # attempts to use FU when none available
1468system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.15% # attempts to use FU when none available
1469system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.15% # attempts to use FU when none available
1470system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.15% # attempts to use FU when none available
1471system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.15% # attempts to use FU when none available
1472system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.15% # attempts to use FU when none available
1473system.cpu2.iq.fu_full::MemRead 51 10.54% 52.69% # attempts to use FU when none available
1474system.cpu2.iq.fu_full::MemWrite 229 47.31% 100.00% # attempts to use FU when none available

1477system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1478system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1479system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1475system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1476system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1477system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1480system.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued
1481system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued
1482system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued
1483system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued
1484system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued
1485system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued
1486system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued
1487system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued
1488system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued
1489system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued
1490system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued
1491system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued
1492system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued
1493system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued
1494system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued
1495system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued
1496system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued
1497system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued
1498system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued
1499system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued
1500system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued
1501system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued
1502system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued
1503system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued
1504system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued
1505system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued
1506system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued
1507system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued
1508system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued
1509system.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued
1510system.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued

1478system.cpu2.iq.FU_type_0::IntAlu 126867 49.02% 49.02% # Type of FU issued
1479system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.02% # Type of FU issued
1480system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.02% # Type of FU issued
1481system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.02% # Type of FU issued
1482system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.02% # Type of FU issued
1483system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.02% # Type of FU issued
1484system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.02% # Type of FU issued
1485system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.02% # Type of FU issued
1486system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.02% # Type of FU issued
1487system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.02% # Type of FU issued
1488system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.02% # Type of FU issued
1489system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.02% # Type of FU issued
1490system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.02% # Type of FU issued
1491system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.02% # Type of FU issued
1492system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.02% # Type of FU issued
1493system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.02% # Type of FU issued
1494system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.02% # Type of FU issued
1495system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.02% # Type of FU issued
1496system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.02% # Type of FU issued
1497system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.02% # Type of FU issued
1498system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.02% # Type of FU issued
1499system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.02% # Type of FU issued
1500system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.02% # Type of FU issued
1501system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.02% # Type of FU issued
1502system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.02% # Type of FU issued
1503system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.02% # Type of FU issued
1504system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.02% # Type of FU issued
1505system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.02% # Type of FU issued
1506system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.02% # Type of FU issued
1507system.cpu2.iq.FU_type_0::MemRead 92395 35.70% 84.71% # Type of FU issued
1508system.cpu2.iq.FU_type_0::MemWrite 39571 15.29% 100.00% # Type of FU issued

1511system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1512system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1509system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1510system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1513system.cpu2.iq.FU_type_0::total 247097 # Type of FU issued
1514system.cpu2.iq.rate 1.279606 # Inst issue rate
1515system.cpu2.iq.fu_busy_cnt 498 # FU busy when requested
1516system.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst)
1517system.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads
1518system.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes
1519system.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses

1511system.cpu2.iq.FU_type_0::total 258833 # Type of FU issued
1512system.cpu2.iq.rate 1.347303 # Inst issue rate
1513system.cpu2.iq.fu_busy_cnt 484 # FU busy when requested
1514system.cpu2.iq.fu_busy_rate 0.001870 # FU busy rate (busy events/executed inst)
1515system.cpu2.iq.int_inst_queue_reads 708742 # Number of integer instruction queue reads
1516system.cpu2.iq.int_inst_queue_writes 292626 # Number of integer instruction queue writes
1517system.cpu2.iq.int_inst_queue_wakeup_accesses 254835 # Number of integer instruction queue wakeup accesses

1520system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

1518system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

1521system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes

1519system.cpu2.iq.fp_inst_queue_writes 80 # Number of floating instruction queue writes

1522system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1520system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1523system.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses

1521system.cpu2.iq.int_alu_accesses 259317 # Number of integer alu accesses

1524system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1522system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1525system.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores

1523system.cpu2.iew.lsq.thread0.forwLoads 34129 # Number of loads that had data forwarded from stores

1526system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1524system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1527system.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed

1525system.cpu2.iew.lsq.thread0.squashedLoads 4624 # Number of loads squashed

1528system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed

1526system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed

1529system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
1530system.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed

1527system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations
1528system.cpu2.iew.lsq.thread0.squashedStores 2677 # Number of stores squashed

1531system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1532system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1533system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1534system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1535system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1529system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1530system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1531system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1532system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1533system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1536system.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing
1537system.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking
1538system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
1539system.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ
1540system.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch
1541system.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions
1542system.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions
1543system.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions

1534system.cpu2.iew.iewSquashCycles 2564 # Number of cycles IEW is squashing
1535system.cpu2.iew.iewBlockCycles 9290 # Number of cycles IEW is blocking
1536system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
1537system.cpu2.iew.iewDispatchedInsts 309688 # Number of instructions dispatched to IQ
1538system.cpu2.iew.iewDispSquashedInsts 288 # Number of squashed instructions skipped by dispatch
1539system.cpu2.iew.iewDispLoadInsts 86703 # Number of dispatched load instructions
1540system.cpu2.iew.iewDispStoreInsts 40578 # Number of dispatched store instructions
1541system.cpu2.iew.iewDispNonSpecInsts 1561 # Number of dispatched non-speculative instructions

1544system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
1545system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1542system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
1543system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1546system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations
1547system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
1548system.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly
1549system.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute
1550system.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions
1551system.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed
1552system.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute

1544system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations
1545system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
1546system.cpu2.iew.predictedNotTakenIncorrect 2684 # Number of branches that were predicted not taken incorrectly
1547system.cpu2.iew.branchMispredicts 3127 # Number of branch mispredicts detected at execute
1548system.cpu2.iew.iewExecutedInsts 256258 # Number of executed instructions
1549system.cpu2.iew.iewExecLoadInsts 85016 # Number of load instructions executed
1550system.cpu2.iew.iewExecSquashedInsts 2575 # Number of squashed instructions skipped in execute

1553system.cpu2.iew.exec_swp 0 # number of swp insts executed

1551system.cpu2.iew.exec_swp 0 # number of swp insts executed

1554system.cpu2.iew.exec_nop 40599 # number of nop insts executed
1555system.cpu2.iew.exec_refs 117071 # number of memory reference insts executed
1556system.cpu2.iew.exec_branches 50931 # Number of branches executed
1557system.cpu2.iew.exec_stores 36741 # Number of stores executed
1558system.cpu2.iew.exec_rate 1.266473 # Inst execution rate
1559system.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit
1560system.cpu2.iew.wb_count 243170 # cumulative count of insts written-back
1561system.cpu2.iew.wb_producers 134852 # num instructions producing a value
1562system.cpu2.iew.wb_consumers 142392 # num instructions consuming a value
1563system.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle
1564system.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back
1565system.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit
1566system.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards
1567system.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted
1568system.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle
1569system.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle
1570system.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle

1552system.cpu2.iew.exec_nop 42671 # number of nop insts executed
1553system.cpu2.iew.exec_refs 124288 # number of memory reference insts executed
1554system.cpu2.iew.exec_branches 53042 # Number of branches executed
1555system.cpu2.iew.exec_stores 39272 # Number of stores executed
1556system.cpu2.iew.exec_rate 1.333899 # Inst execution rate
1557system.cpu2.iew.wb_sent 255341 # cumulative count of insts sent to commit
1558system.cpu2.iew.wb_count 254835 # cumulative count of insts written-back
1559system.cpu2.iew.wb_producers 142252 # num instructions producing a value
1560system.cpu2.iew.wb_consumers 149928 # num instructions consuming a value
1561system.cpu2.iew.wb_rate 1.326492 # insts written-back per cycle
1562system.cpu2.iew.wb_fanout 0.948802 # average fanout of values written-back
1563system.cpu2.commit.commitSquashedInsts 26847 # The number of squashed insts skipped by commit
1564system.cpu2.commit.commitNonSpecStalls 7517 # The number of times commit has been forced to stall to communicate backwards
1565system.cpu2.commit.branchMispredicts 2486 # The number of times a branch was mispredicted
1566system.cpu2.commit.committed_per_cycle::samples 185379 # Number of insts commited each cycle
1567system.cpu2.commit.committed_per_cycle::mean 1.525604 # Number of insts commited each cycle
1568system.cpu2.commit.committed_per_cycle::stdev 2.006612 # Number of insts commited each cycle

1571system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1569system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1572system.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle
1573system.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle
1574system.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle
1575system.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle
1576system.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle
1577system.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle
1578system.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle
1579system.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle
1580system.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle

1570system.cpu2.commit.committed_per_cycle::0 83888 45.25% 45.25% # Number of insts commited each cycle
1571system.cpu2.commit.committed_per_cycle::1 49216 26.55% 71.80% # Number of insts commited each cycle
1572system.cpu2.commit.committed_per_cycle::2 5545 2.99% 74.79% # Number of insts commited each cycle
1573system.cpu2.commit.committed_per_cycle::3 8151 4.40% 79.19% # Number of insts commited each cycle
1574system.cpu2.commit.committed_per_cycle::4 1274 0.69% 79.88% # Number of insts commited each cycle
1575system.cpu2.commit.committed_per_cycle::5 34338 18.52% 98.40% # Number of insts commited each cycle
1576system.cpu2.commit.committed_per_cycle::6 700 0.38% 98.78% # Number of insts commited each cycle
1577system.cpu2.commit.committed_per_cycle::7 1066 0.58% 99.35% # Number of insts commited each cycle
1578system.cpu2.commit.committed_per_cycle::8 1201 0.65% 100.00% # Number of insts commited each cycle

1581system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1582system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1583system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1579system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1580system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1581system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1584system.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle
1585system.cpu2.commit.committedInsts 269325 # Number of instructions committed
1586system.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed

1582system.cpu2.commit.committed_per_cycle::total 185379 # Number of insts commited each cycle
1583system.cpu2.commit.committedInsts 282815 # Number of instructions committed
1584system.cpu2.commit.committedOps 282815 # Number of ops (including micro ops) committed

1587system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1585system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1588system.cpu2.commit.refs 112812 # Number of memory references committed
1589system.cpu2.commit.loads 77446 # Number of loads committed
1590system.cpu2.commit.membars 7225 # Number of memory barriers committed
1591system.cpu2.commit.branches 48554 # Number of branches committed

1586system.cpu2.commit.refs 119980 # Number of memory references committed
1587system.cpu2.commit.loads 82079 # Number of loads committed
1588system.cpu2.commit.membars 6800 # Number of memory barriers committed
1589system.cpu2.commit.branches 50664 # Number of branches committed

1592system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1590system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1593system.cpu2.commit.int_insts 183489 # Number of committed integer instructions.

1591system.cpu2.commit.int_insts 192763 # Number of committed integer instructions.

1594system.cpu2.commit.function_calls 322 # Number of function calls committed.

1592system.cpu2.commit.function_calls 322 # Number of function calls committed.

1595system.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction
1596system.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction
1597system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction
1598system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction
1599system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction
1600system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction
1601system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction
1602system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction
1603system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction
1604system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction
1605system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction
1606system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction
1607system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction
1608system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction
1609system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction
1610system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction
1611system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction
1612system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction
1613system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction
1614system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction
1615system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction
1616system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction
1617system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction
1618system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction
1619system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction
1620system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction
1621system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction
1622system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction
1623system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction
1624system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction
1625system.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction
1626system.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction

1593system.cpu2.commit.op_class_0::No_OpClass 41451 14.66% 14.66% # Class of committed instruction
1594system.cpu2.commit.op_class_0::IntAlu 114584 40.52% 55.17% # Class of committed instruction
1595system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.17% # Class of committed instruction
1596system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.17% # Class of committed instruction
1597system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.17% # Class of committed instruction
1598system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.17% # Class of committed instruction
1599system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.17% # Class of committed instruction
1600system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.17% # Class of committed instruction
1601system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.17% # Class of committed instruction
1602system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.17% # Class of committed instruction
1603system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.17% # Class of committed instruction
1604system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.17% # Class of committed instruction
1605system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.17% # Class of committed instruction
1606system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.17% # Class of committed instruction
1607system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.17% # Class of committed instruction
1608system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.17% # Class of committed instruction
1609system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.17% # Class of committed instruction
1610system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.17% # Class of committed instruction
1611system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.17% # Class of committed instruction
1612system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.17% # Class of committed instruction
1613system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.17% # Class of committed instruction
1614system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.17% # Class of committed instruction
1615system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.17% # Class of committed instruction
1616system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.17% # Class of committed instruction
1617system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.17% # Class of committed instruction
1618system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.17% # Class of committed instruction
1619system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.17% # Class of committed instruction
1620system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.17% # Class of committed instruction
1621system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.17% # Class of committed instruction
1622system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.17% # Class of committed instruction
1623system.cpu2.commit.op_class_0::MemRead 88879 31.43% 86.60% # Class of committed instruction
1624system.cpu2.commit.op_class_0::MemWrite 37901 13.40% 100.00% # Class of committed instruction

1627system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1628system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1625system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1626system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1629system.cpu2.commit.op_class_0::total 269325 # Class of committed instruction
1630system.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached
1631system.cpu2.rob.rob_reads 480143 # The number of ROB reads
1632system.cpu2.rob.rob_writes 596277 # The number of ROB writes
1633system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
1634system.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling

1627system.cpu2.commit.op_class_0::total 282815 # Class of committed instruction
1628system.cpu2.commit.bw_lim_events 1201 # number cycles where commit BW limit reached
1629system.cpu2.rob.rob_reads 493254 # The number of ROB reads
1630system.cpu2.rob.rob_writes 624500 # The number of ROB writes
1631system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
1632system.cpu2.idleCycles 1603 # Total number of cycles that the CPU has spent unscheduled due to idling

1635system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

1633system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

1636system.cpu2.committedInsts 222755 # Number of Instructions Simulated
1637system.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated
1638system.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction
1639system.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads
1640system.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle
1641system.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads
1642system.cpu2.int_regfile_reads 415553 # number of integer regfile reads
1643system.cpu2.int_regfile_writes 194388 # number of integer regfile writes

1634system.cpu2.committedInsts 234564 # Number of Instructions Simulated
1635system.cpu2.committedOps 234564 # Number of Ops (including micro ops) Simulated
1636system.cpu2.cpi 0.819017 # CPI: Cycles Per Instruction
1637system.cpu2.cpi_total 0.819017 # CPI: Total CPI of All Threads
1638system.cpu2.ipc 1.220975 # IPC: Instructions Per Cycle
1639system.cpu2.ipc_total 1.220975 # IPC: Total IPC of All Threads
1640system.cpu2.int_regfile_reads 437605 # number of integer regfile reads
1641system.cpu2.int_regfile_writes 204427 # number of integer regfile writes

1644system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1642system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1645system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads

1643system.cpu2.misc_regfile_reads 126238 # number of misc regfile reads

1646system.cpu2.misc_regfile_writes 648 # number of misc regfile writes

1644system.cpu2.misc_regfile_writes 648 # number of misc regfile writes

1647system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

1645system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

1648system.cpu2.dcache.tags.replacements 0 # number of replacements

1646system.cpu2.dcache.tags.replacements 0 # number of replacements

1649system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use
1650system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks.

1647system.cpu2.dcache.tags.tagsinuse 26.114184 # Cycle average of tags in use
1648system.cpu2.dcache.tags.total_refs 45075 # Total number of references to valid blocks.

1651system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.

1649system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.

1652system.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks.

1650system.cpu2.dcache.tags.avg_refs 1502.500000 # Average number of references to valid blocks.

1653system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1651system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1654system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor
1655system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy
1656system.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy

1652system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.114184 # Average occupied blocks per requestor
1653system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051004 # Average percentage of cache occupancy
1654system.cpu2.dcache.tags.occ_percent::total 0.051004 # Average percentage of cache occupancy

1657system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id

1655system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id

1658system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
1659system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
1660system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id

1656system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id

1661system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id

1657system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id

1662system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses
1663system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses
1664system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1665system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits
1666system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits
1667system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits
1668system.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits

1658system.cpu2.dcache.tags.tag_accesses 355312 # Number of tag accesses
1659system.cpu2.dcache.tags.data_accesses 355312 # Number of data accesses
1660system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1661system.cpu2.dcache.ReadReq_hits::cpu2.data 50364 # number of ReadReq hits
1662system.cpu2.dcache.ReadReq_hits::total 50364 # number of ReadReq hits
1663system.cpu2.dcache.WriteReq_hits::cpu2.data 37691 # number of WriteReq hits
1664system.cpu2.dcache.WriteReq_hits::total 37691 # number of WriteReq hits

1669system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
1670system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits

1665system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
1666system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits

1671system.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits
1672system.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits
1673system.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits
1674system.cpu2.dcache.overall_hits::total 83369 # number of overall hits
1675system.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses
1676system.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses
1677system.cpu2.dcache.WriteReq_misses::cpu2.data 145 # number of WriteReq misses
1678system.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses
1679system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
1680system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
1681system.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses
1682system.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses
1683system.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses
1684system.cpu2.dcache.overall_misses::total 645 # number of overall misses
1685system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles
1686system.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles
1687system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3144500 # number of WriteReq miss cycles
1688system.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles
1689system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles
1690system.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles
1691system.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles
1692system.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles
1693system.cpu2.dcache.overall_miss_latency::cpu2.data 11308000 # number of overall miss cycles
1694system.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles
1695system.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses)
1696system.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses)
1697system.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses)
1698system.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses)
1699system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses)
1700system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
1701system.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses
1702system.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses
1703system.cpu2.dcache.overall_accesses::cpu2.data 84014 # number of overall (read+write) accesses
1704system.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses
1705system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses
1706system.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses
1707system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses
1708system.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses
1709system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.805970 # miss rate for SwapReq accesses
1710system.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses
1711system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007677 # miss rate for demand accesses
1712system.cpu2.dcache.demand_miss_rate::total 0.007677 # miss rate for demand accesses
1713system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007677 # miss rate for overall accesses
1714system.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses
1715system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency
1716system.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency
1717system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency
1718system.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency
1719system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency
1720system.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency
1721system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency
1722system.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency
1723system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency
1724system.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency

1667system.cpu2.dcache.demand_hits::cpu2.data 88055 # number of demand (read+write) hits
1668system.cpu2.dcache.demand_hits::total 88055 # number of demand (read+write) hits
1669system.cpu2.dcache.overall_hits::cpu2.data 88055 # number of overall hits
1670system.cpu2.dcache.overall_hits::total 88055 # number of overall hits
1671system.cpu2.dcache.ReadReq_misses::cpu2.data 498 # number of ReadReq misses
1672system.cpu2.dcache.ReadReq_misses::total 498 # number of ReadReq misses
1673system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
1674system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
1675system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
1676system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
1677system.cpu2.dcache.demand_misses::cpu2.data 637 # number of demand (read+write) misses
1678system.cpu2.dcache.demand_misses::total 637 # number of demand (read+write) misses
1679system.cpu2.dcache.overall_misses::cpu2.data 637 # number of overall misses
1680system.cpu2.dcache.overall_misses::total 637 # number of overall misses
1681system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3990000 # number of ReadReq miss cycles
1682system.cpu2.dcache.ReadReq_miss_latency::total 3990000 # number of ReadReq miss cycles
1683system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2835500 # number of WriteReq miss cycles
1684system.cpu2.dcache.WriteReq_miss_latency::total 2835500 # number of WriteReq miss cycles
1685system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 366500 # number of SwapReq miss cycles
1686system.cpu2.dcache.SwapReq_miss_latency::total 366500 # number of SwapReq miss cycles
1687system.cpu2.dcache.demand_miss_latency::cpu2.data 6825500 # number of demand (read+write) miss cycles
1688system.cpu2.dcache.demand_miss_latency::total 6825500 # number of demand (read+write) miss cycles
1689system.cpu2.dcache.overall_miss_latency::cpu2.data 6825500 # number of overall miss cycles
1690system.cpu2.dcache.overall_miss_latency::total 6825500 # number of overall miss cycles
1691system.cpu2.dcache.ReadReq_accesses::cpu2.data 50862 # number of ReadReq accesses(hits+misses)
1692system.cpu2.dcache.ReadReq_accesses::total 50862 # number of ReadReq accesses(hits+misses)
1693system.cpu2.dcache.WriteReq_accesses::cpu2.data 37830 # number of WriteReq accesses(hits+misses)
1694system.cpu2.dcache.WriteReq_accesses::total 37830 # number of WriteReq accesses(hits+misses)
1695system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
1696system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1697system.cpu2.dcache.demand_accesses::cpu2.data 88692 # number of demand (read+write) accesses
1698system.cpu2.dcache.demand_accesses::total 88692 # number of demand (read+write) accesses
1699system.cpu2.dcache.overall_accesses::cpu2.data 88692 # number of overall (read+write) accesses
1700system.cpu2.dcache.overall_accesses::total 88692 # number of overall (read+write) accesses
1701system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009791 # miss rate for ReadReq accesses
1702system.cpu2.dcache.ReadReq_miss_rate::total 0.009791 # miss rate for ReadReq accesses
1703system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003674 # miss rate for WriteReq accesses
1704system.cpu2.dcache.WriteReq_miss_rate::total 0.003674 # miss rate for WriteReq accesses
1705system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses
1706system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
1707system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007182 # miss rate for demand accesses
1708system.cpu2.dcache.demand_miss_rate::total 0.007182 # miss rate for demand accesses
1709system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007182 # miss rate for overall accesses
1710system.cpu2.dcache.overall_miss_rate::total 0.007182 # miss rate for overall accesses
1711system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8012.048193 # average ReadReq miss latency
1712system.cpu2.dcache.ReadReq_avg_miss_latency::total 8012.048193 # average ReadReq miss latency
1713system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576 # average WriteReq miss latency
1714system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576 # average WriteReq miss latency
1715system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6318.965517 # average SwapReq miss latency
1716system.cpu2.dcache.SwapReq_avg_miss_latency::total 6318.965517 # average SwapReq miss latency
1717system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency
1718system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644 # average overall miss latency
1719system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency
1720system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644 # average overall miss latency

1725system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1726system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1727system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1728system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1729system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1730system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1721system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1722system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1723system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1724system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1725system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1726system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1731system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 338 # number of ReadReq MSHR hits
1732system.cpu2.dcache.ReadReq_mshr_hits::total 338 # number of ReadReq MSHR hits
1733system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 39 # number of WriteReq MSHR hits
1734system.cpu2.dcache.WriteReq_mshr_hits::total 39 # number of WriteReq MSHR hits
1735system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 2 # number of SwapReq MSHR hits
1736system.cpu2.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits
1737system.cpu2.dcache.demand_mshr_hits::cpu2.data 377 # number of demand (read+write) MSHR hits
1738system.cpu2.dcache.demand_mshr_hits::total 377 # number of demand (read+write) MSHR hits
1739system.cpu2.dcache.overall_mshr_hits::cpu2.data 377 # number of overall MSHR hits
1740system.cpu2.dcache.overall_mshr_hits::total 377 # number of overall MSHR hits
1741system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
1742system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
1743system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
1744system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
1745system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses
1746system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
1747system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
1748system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
1749system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
1750system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
1751system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1730500 # number of ReadReq MSHR miss cycles
1752system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1730500 # number of ReadReq MSHR miss cycles
1753system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1679500 # number of WriteReq MSHR miss cycles
1754system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1679500 # number of WriteReq MSHR miss cycles
1755system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 752000 # number of SwapReq MSHR miss cycles
1756system.cpu2.dcache.SwapReq_mshr_miss_latency::total 752000 # number of SwapReq MSHR miss cycles
1757system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3410000 # number of demand (read+write) MSHR miss cycles
1758system.cpu2.dcache.demand_mshr_miss_latency::total 3410000 # number of demand (read+write) MSHR miss cycles
1759system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3410000 # number of overall MSHR miss cycles
1760system.cpu2.dcache.overall_mshr_miss_latency::total 3410000 # number of overall MSHR miss cycles
1761system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003325 # mshr miss rate for ReadReq accesses
1762system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003325 # mshr miss rate for ReadReq accesses
1763system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003003 # mshr miss rate for WriteReq accesses
1764system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003003 # mshr miss rate for WriteReq accesses
1765system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.776119 # mshr miss rate for SwapReq accesses
1766system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses
1767system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for demand accesses
1768system.cpu2.dcache.demand_mshr_miss_rate::total 0.003190 # mshr miss rate for demand accesses
1769system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for overall accesses
1770system.cpu2.dcache.overall_mshr_miss_rate::total 0.003190 # mshr miss rate for overall accesses
1771system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10682.098765 # average ReadReq mshr miss latency
1772system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10682.098765 # average ReadReq mshr miss latency
1773system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15844.339623 # average WriteReq mshr miss latency
1774system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15844.339623 # average WriteReq mshr miss latency
1775system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14461.538462 # average SwapReq mshr miss latency
1776system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14461.538462 # average SwapReq mshr miss latency
1777system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency
1778system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency
1779system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency
1780system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency
1781system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1782system.cpu2.icache.tags.replacements 598 # number of replacements
1783system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use
1784system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks.
1785system.cpu2.icache.tags.sampled_refs 733 # Sample count of references to valid blocks.
1786system.cpu2.icache.tags.avg_refs 38.968622 # Average number of references to valid blocks.

1727system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 331 # number of ReadReq MSHR hits
1728system.cpu2.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits
1729system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
1730system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
1731system.cpu2.dcache.demand_mshr_hits::cpu2.data 365 # number of demand (read+write) MSHR hits
1732system.cpu2.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits
1733system.cpu2.dcache.overall_mshr_hits::cpu2.data 365 # number of overall MSHR hits
1734system.cpu2.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits
1735system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 167 # number of ReadReq MSHR misses
1736system.cpu2.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
1737system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
1738system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
1739system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
1740system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
1741system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses
1742system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
1743system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses
1744system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses
1745system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1193000 # number of ReadReq MSHR miss cycles
1746system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1193000 # number of ReadReq MSHR miss cycles
1747system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1388000 # number of WriteReq MSHR miss cycles
1748system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1388000 # number of WriteReq MSHR miss cycles
1749system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 308500 # number of SwapReq MSHR miss cycles
1750system.cpu2.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles
1751system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2581000 # number of demand (read+write) MSHR miss cycles
1752system.cpu2.dcache.demand_mshr_miss_latency::total 2581000 # number of demand (read+write) MSHR miss cycles
1753system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2581000 # number of overall MSHR miss cycles
1754system.cpu2.dcache.overall_mshr_miss_latency::total 2581000 # number of overall MSHR miss cycles
1755system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003283 # mshr miss rate for ReadReq accesses
1756system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003283 # mshr miss rate for ReadReq accesses
1757system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002776 # mshr miss rate for WriteReq accesses
1758system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002776 # mshr miss rate for WriteReq accesses
1759system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses
1760system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
1761system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for demand accesses
1762system.cpu2.dcache.demand_mshr_miss_rate::total 0.003067 # mshr miss rate for demand accesses
1763system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for overall accesses
1764system.cpu2.dcache.overall_mshr_miss_rate::total 0.003067 # mshr miss rate for overall accesses
1765system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7143.712575 # average ReadReq mshr miss latency
1766system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7143.712575 # average ReadReq mshr miss latency
1767system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619 # average WriteReq mshr miss latency
1768system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619 # average WriteReq mshr miss latency
1769system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5318.965517 # average SwapReq mshr miss latency
1770system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5318.965517 # average SwapReq mshr miss latency
1771system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency
1772system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency
1773system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency
1774system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency
1775system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1776system.cpu2.icache.tags.replacements 578 # number of replacements
1777system.cpu2.icache.tags.tagsinuse 95.404705 # Cycle average of tags in use
1778system.cpu2.icache.tags.total_refs 27742 # Total number of references to valid blocks.
1779system.cpu2.icache.tags.sampled_refs 710 # Sample count of references to valid blocks.
1780system.cpu2.icache.tags.avg_refs 39.073239 # Average number of references to valid blocks.

1787system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1781system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1788system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.853337 # Average occupied blocks per requestor
1789system.cpu2.icache.tags.occ_percent::cpu2.inst 0.187214 # Average percentage of cache occupancy
1790system.cpu2.icache.tags.occ_percent::total 0.187214 # Average percentage of cache occupancy
1791system.cpu2.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
1792system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
1793system.cpu2.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
1794system.cpu2.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
1795system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id
1796system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses
1797system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses
1798system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
1799system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits
1800system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits
1801system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits
1802system.cpu2.icache.demand_hits::total 28564 # number of demand (read+write) hits
1803system.cpu2.icache.overall_hits::cpu2.inst 28564 # number of overall hits
1804system.cpu2.icache.overall_hits::total 28564 # number of overall hits
1805system.cpu2.icache.ReadReq_misses::cpu2.inst 852 # number of ReadReq misses
1806system.cpu2.icache.ReadReq_misses::total 852 # number of ReadReq misses
1807system.cpu2.icache.demand_misses::cpu2.inst 852 # number of demand (read+write) misses
1808system.cpu2.icache.demand_misses::total 852 # number of demand (read+write) misses
1809system.cpu2.icache.overall_misses::cpu2.inst 852 # number of overall misses
1810system.cpu2.icache.overall_misses::total 852 # number of overall misses
1811system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12789500 # number of ReadReq miss cycles
1812system.cpu2.icache.ReadReq_miss_latency::total 12789500 # number of ReadReq miss cycles
1813system.cpu2.icache.demand_miss_latency::cpu2.inst 12789500 # number of demand (read+write) miss cycles
1814system.cpu2.icache.demand_miss_latency::total 12789500 # number of demand (read+write) miss cycles
1815system.cpu2.icache.overall_miss_latency::cpu2.inst 12789500 # number of overall miss cycles
1816system.cpu2.icache.overall_miss_latency::total 12789500 # number of overall miss cycles
1817system.cpu2.icache.ReadReq_accesses::cpu2.inst 29416 # number of ReadReq accesses(hits+misses)
1818system.cpu2.icache.ReadReq_accesses::total 29416 # number of ReadReq accesses(hits+misses)
1819system.cpu2.icache.demand_accesses::cpu2.inst 29416 # number of demand (read+write) accesses
1820system.cpu2.icache.demand_accesses::total 29416 # number of demand (read+write) accesses
1821system.cpu2.icache.overall_accesses::cpu2.inst 29416 # number of overall (read+write) accesses
1822system.cpu2.icache.overall_accesses::total 29416 # number of overall (read+write) accesses
1823system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028964 # miss rate for ReadReq accesses
1824system.cpu2.icache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses
1825system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028964 # miss rate for demand accesses
1826system.cpu2.icache.demand_miss_rate::total 0.028964 # miss rate for demand accesses
1827system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028964 # miss rate for overall accesses
1828system.cpu2.icache.overall_miss_rate::total 0.028964 # miss rate for overall accesses
1829system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15011.150235 # average ReadReq miss latency
1830system.cpu2.icache.ReadReq_avg_miss_latency::total 15011.150235 # average ReadReq miss latency
1831system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency
1832system.cpu2.icache.demand_avg_miss_latency::total 15011.150235 # average overall miss latency
1833system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency
1834system.cpu2.icache.overall_avg_miss_latency::total 15011.150235 # average overall miss latency
1835system.cpu2.icache.blocked_cycles::no_mshrs 111 # number of cycles access was blocked

1782system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.404705 # Average occupied blocks per requestor
1783system.cpu2.icache.tags.occ_percent::cpu2.inst 0.186337 # Average percentage of cache occupancy
1784system.cpu2.icache.tags.occ_percent::total 0.186337 # Average percentage of cache occupancy
1785system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id
1786system.cpu2.icache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
1787system.cpu2.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
1788system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id
1789system.cpu2.icache.tags.tag_accesses 29289 # Number of tag accesses
1790system.cpu2.icache.tags.data_accesses 29289 # Number of data accesses
1791system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
1792system.cpu2.icache.ReadReq_hits::cpu2.inst 27742 # number of ReadReq hits
1793system.cpu2.icache.ReadReq_hits::total 27742 # number of ReadReq hits
1794system.cpu2.icache.demand_hits::cpu2.inst 27742 # number of demand (read+write) hits
1795system.cpu2.icache.demand_hits::total 27742 # number of demand (read+write) hits
1796system.cpu2.icache.overall_hits::cpu2.inst 27742 # number of overall hits
1797system.cpu2.icache.overall_hits::total 27742 # number of overall hits
1798system.cpu2.icache.ReadReq_misses::cpu2.inst 837 # number of ReadReq misses
1799system.cpu2.icache.ReadReq_misses::total 837 # number of ReadReq misses
1800system.cpu2.icache.demand_misses::cpu2.inst 837 # number of demand (read+write) misses
1801system.cpu2.icache.demand_misses::total 837 # number of demand (read+write) misses
1802system.cpu2.icache.overall_misses::cpu2.inst 837 # number of overall misses
1803system.cpu2.icache.overall_misses::total 837 # number of overall misses
1804system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12852000 # number of ReadReq miss cycles
1805system.cpu2.icache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles
1806system.cpu2.icache.demand_miss_latency::cpu2.inst 12852000 # number of demand (read+write) miss cycles
1807system.cpu2.icache.demand_miss_latency::total 12852000 # number of demand (read+write) miss cycles
1808system.cpu2.icache.overall_miss_latency::cpu2.inst 12852000 # number of overall miss cycles
1809system.cpu2.icache.overall_miss_latency::total 12852000 # number of overall miss cycles
1810system.cpu2.icache.ReadReq_accesses::cpu2.inst 28579 # number of ReadReq accesses(hits+misses)
1811system.cpu2.icache.ReadReq_accesses::total 28579 # number of ReadReq accesses(hits+misses)
1812system.cpu2.icache.demand_accesses::cpu2.inst 28579 # number of demand (read+write) accesses
1813system.cpu2.icache.demand_accesses::total 28579 # number of demand (read+write) accesses
1814system.cpu2.icache.overall_accesses::cpu2.inst 28579 # number of overall (read+write) accesses
1815system.cpu2.icache.overall_accesses::total 28579 # number of overall (read+write) accesses
1816system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029287 # miss rate for ReadReq accesses
1817system.cpu2.icache.ReadReq_miss_rate::total 0.029287 # miss rate for ReadReq accesses
1818system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029287 # miss rate for demand accesses
1819system.cpu2.icache.demand_miss_rate::total 0.029287 # miss rate for demand accesses
1820system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029287 # miss rate for overall accesses
1821system.cpu2.icache.overall_miss_rate::total 0.029287 # miss rate for overall accesses
1822system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710 # average ReadReq miss latency
1823system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710 # average ReadReq miss latency
1824system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency
1825system.cpu2.icache.demand_avg_miss_latency::total 15354.838710 # average overall miss latency
1826system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency
1827system.cpu2.icache.overall_avg_miss_latency::total 15354.838710 # average overall miss latency
1828system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked

1836system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1829system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1837system.cpu2.icache.blocked::no_mshrs 5 # number of cycles access was blocked

1830system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked

1838system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked

1831system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked

1839system.cpu2.icache.avg_blocked_cycles::no_mshrs 22.200000 # average number of cycles each access was blocked

1832system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked

1840system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1833system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1841system.cpu2.icache.writebacks::writebacks 598 # number of writebacks
1842system.cpu2.icache.writebacks::total 598 # number of writebacks
1843system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 119 # number of ReadReq MSHR hits
1844system.cpu2.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
1845system.cpu2.icache.demand_mshr_hits::cpu2.inst 119 # number of demand (read+write) MSHR hits
1846system.cpu2.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits
1847system.cpu2.icache.overall_mshr_hits::cpu2.inst 119 # number of overall MSHR hits
1848system.cpu2.icache.overall_mshr_hits::total 119 # number of overall MSHR hits
1849system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 733 # number of ReadReq MSHR misses
1850system.cpu2.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
1851system.cpu2.icache.demand_mshr_misses::cpu2.inst 733 # number of demand (read+write) MSHR misses
1852system.cpu2.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
1853system.cpu2.icache.overall_mshr_misses::cpu2.inst 733 # number of overall MSHR misses
1854system.cpu2.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
1855system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10899500 # number of ReadReq MSHR miss cycles
1856system.cpu2.icache.ReadReq_mshr_miss_latency::total 10899500 # number of ReadReq MSHR miss cycles
1857system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10899500 # number of demand (read+write) MSHR miss cycles
1858system.cpu2.icache.demand_mshr_miss_latency::total 10899500 # number of demand (read+write) MSHR miss cycles
1859system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10899500 # number of overall MSHR miss cycles
1860system.cpu2.icache.overall_mshr_miss_latency::total 10899500 # number of overall MSHR miss cycles
1861system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for ReadReq accesses
1862system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024918 # mshr miss rate for ReadReq accesses
1863system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for demand accesses
1864system.cpu2.icache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
1865system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for overall accesses
1866system.cpu2.icache.overall_mshr_miss_rate::total 0.024918 # mshr miss rate for overall accesses
1867system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average ReadReq mshr miss latency
1868system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency
1869system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency
1870system.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency
1871system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency
1872system.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency
1873system.cpu3.branchPred.lookups 61800 # Number of BP lookups
1874system.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted
1875system.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect
1876system.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups

1834system.cpu2.icache.writebacks::writebacks 578 # number of writebacks
1835system.cpu2.icache.writebacks::total 578 # number of writebacks
1836system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 127 # number of ReadReq MSHR hits
1837system.cpu2.icache.ReadReq_mshr_hits::total 127 # number of ReadReq MSHR hits
1838system.cpu2.icache.demand_mshr_hits::cpu2.inst 127 # number of demand (read+write) MSHR hits
1839system.cpu2.icache.demand_mshr_hits::total 127 # number of demand (read+write) MSHR hits
1840system.cpu2.icache.overall_mshr_hits::cpu2.inst 127 # number of overall MSHR hits
1841system.cpu2.icache.overall_mshr_hits::total 127 # number of overall MSHR hits
1842system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 710 # number of ReadReq MSHR misses
1843system.cpu2.icache.ReadReq_mshr_misses::total 710 # number of ReadReq MSHR misses
1844system.cpu2.icache.demand_mshr_misses::cpu2.inst 710 # number of demand (read+write) MSHR misses
1845system.cpu2.icache.demand_mshr_misses::total 710 # number of demand (read+write) MSHR misses
1846system.cpu2.icache.overall_mshr_misses::cpu2.inst 710 # number of overall MSHR misses
1847system.cpu2.icache.overall_mshr_misses::total 710 # number of overall MSHR misses
1848system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10853000 # number of ReadReq MSHR miss cycles
1849system.cpu2.icache.ReadReq_mshr_miss_latency::total 10853000 # number of ReadReq MSHR miss cycles
1850system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10853000 # number of demand (read+write) MSHR miss cycles
1851system.cpu2.icache.demand_mshr_miss_latency::total 10853000 # number of demand (read+write) MSHR miss cycles
1852system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10853000 # number of overall MSHR miss cycles
1853system.cpu2.icache.overall_mshr_miss_latency::total 10853000 # number of overall MSHR miss cycles
1854system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for ReadReq accesses
1855system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024843 # mshr miss rate for ReadReq accesses
1856system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for demand accesses
1857system.cpu2.icache.demand_mshr_miss_rate::total 0.024843 # mshr miss rate for demand accesses
1858system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for overall accesses
1859system.cpu2.icache.overall_mshr_miss_rate::total 0.024843 # mshr miss rate for overall accesses
1860system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average ReadReq mshr miss latency
1861system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493 # average ReadReq mshr miss latency
1862system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency
1863system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency
1864system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency
1865system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency
1866system.cpu3.branchPred.lookups 58058 # Number of BP lookups
1867system.cpu3.branchPred.condPredicted 50256 # Number of conditional branches predicted
1868system.cpu3.branchPred.condIncorrect 2406 # Number of conditional branches incorrect
1869system.cpu3.branchPred.BTBLookups 50211 # Number of BTB lookups

1877system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
1878system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1879system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1870system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
1871system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1872system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage

1880system.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target.

1873system.cpu3.branchPred.usedRAS 1984 # Number of times the RAS was used to get a target.

1881system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1874system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1882system.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups.
1883system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits.
1884system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses.
1885system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches.
1886system.cpu3.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
1887system.cpu3.numCycles 192748 # number of cpu cycles simulated

1875system.cpu3.branchPred.indirectLookups 50211 # Number of indirect predictor lookups.
1876system.cpu3.branchPred.indirectHits 39339 # Number of indirect target hits.
1877system.cpu3.branchPred.indirectMisses 10872 # Number of indirect misses.
1878system.cpu3.branchPredindirectMispredicted 1290 # Number of mispredicted indirect branches.
1879system.cpu3.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
1880system.cpu3.numCycles 191755 # number of cpu cycles simulated

1888system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1889system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed

1881system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1882system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed

1890system.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss
1891system.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed
1892system.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered
1893system.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken
1894system.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked
1895system.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing

1883system.cpu3.fetch.icacheStallCycles 44345 # Number of cycles fetch is stalled on an Icache miss
1884system.cpu3.fetch.Insts 305380 # Number of instructions fetch has processed
1885system.cpu3.fetch.Branches 58058 # Number of branches that fetch encountered
1886system.cpu3.fetch.predictedBranches 41323 # Number of branches that fetch has predicted taken
1887system.cpu3.fetch.Cycles 141573 # Number of cycles fetch has run and was not squashing or blocked
1888system.cpu3.fetch.SquashCycles 4965 # Number of cycles fetch has spent squashing

1896system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1897system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1889system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1890system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1898system.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps
1899system.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched
1900system.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed
1901system.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total)
1902system.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total)
1903system.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total)

1891system.cpu3.fetch.PendingTrapStallCycles 1720 # Number of stall cycles due to pending traps
1892system.cpu3.fetch.CacheLines 32940 # Number of cache lines fetched
1893system.cpu3.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed
1894system.cpu3.fetch.rateDist::samples 190133 # Number of instructions fetched each cycle (Total)
1895system.cpu3.fetch.rateDist::mean 1.606139 # Number of instructions fetched each cycle (Total)
1896system.cpu3.fetch.rateDist::stdev 2.261267 # Number of instructions fetched each cycle (Total)

1904system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1897system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1905system.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total)
1906system.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total)
1907system.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total)
1908system.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total)
1909system.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total)
1910system.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total)
1911system.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total)
1912system.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total)
1913system.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total)

1898system.cpu3.fetch.rateDist::0 84706 44.55% 44.55% # Number of instructions fetched each cycle (Total)
1899system.cpu3.fetch.rateDist::1 53051 27.90% 72.45% # Number of instructions fetched each cycle (Total)
1900system.cpu3.fetch.rateDist::2 10689 5.62% 78.07% # Number of instructions fetched each cycle (Total)
1901system.cpu3.fetch.rateDist::3 3433 1.81% 79.88% # Number of instructions fetched each cycle (Total)
1902system.cpu3.fetch.rateDist::4 679 0.36% 80.24% # Number of instructions fetched each cycle (Total)
1903system.cpu3.fetch.rateDist::5 26352 13.86% 94.10% # Number of instructions fetched each cycle (Total)
1904system.cpu3.fetch.rateDist::6 1085 0.57% 94.67% # Number of instructions fetched each cycle (Total)
1905system.cpu3.fetch.rateDist::7 1438 0.76% 95.42% # Number of instructions fetched each cycle (Total)
1906system.cpu3.fetch.rateDist::8 8700 4.58% 100.00% # Number of instructions fetched each cycle (Total)

1914system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1915system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1916system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1907system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1908system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1909system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1917system.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total)
1918system.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle
1919system.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle
1920system.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle
1921system.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked
1922system.cpu3.decode.RunCycles 79630 # Number of cycles decode is running
1923system.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking
1924system.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing
1925system.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode
1926system.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing
1927system.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle
1928system.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking
1929system.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst
1930system.cpu3.rename.RunCycles 80471 # Number of cycles rename is running
1931system.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking
1932system.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename
1933system.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full
1934system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
1935system.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed
1936system.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made
1937system.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups
1938system.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups
1939system.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed
1940system.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing
1941system.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed
1942system.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed
1943system.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer
1944system.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit.
1945system.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit.
1946system.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads.
1947system.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores.
1948system.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec)
1949system.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ
1950system.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued
1951system.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued
1952system.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling
1953system.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph
1954system.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed
1955system.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle
1956system.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle
1957system.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle

1910system.cpu3.fetch.rateDist::total 190133 # Number of instructions fetched each cycle (Total)
1911system.cpu3.fetch.branchRate 0.302772 # Number of branch fetches per cycle
1912system.cpu3.fetch.rate 1.592553 # Number of inst fetches per cycle
1913system.cpu3.decode.IdleCycles 22846 # Number of cycles decode is idle
1914system.cpu3.decode.BlockedCycles 89002 # Number of cycles decode is blocked
1915system.cpu3.decode.RunCycles 70141 # Number of cycles decode is running
1916system.cpu3.decode.UnblockCycles 5652 # Number of cycles decode is unblocking
1917system.cpu3.decode.SquashCycles 2482 # Number of cycles decode is squashing
1918system.cpu3.decode.DecodedInsts 273868 # Number of instructions handled by decode
1919system.cpu3.rename.SquashCycles 2482 # Number of cycles rename is squashing
1920system.cpu3.rename.IdleCycles 23847 # Number of cycles rename is idle
1921system.cpu3.rename.BlockCycles 45287 # Number of cycles rename is blocking
1922system.cpu3.rename.serializeStallCycles 13384 # count of cycles rename stalled for serializing inst
1923system.cpu3.rename.RunCycles 70737 # Number of cycles rename is running
1924system.cpu3.rename.UnblockCycles 34386 # Number of cycles rename is unblocking
1925system.cpu3.rename.RenamedInsts 267452 # Number of instructions processed by rename
1926system.cpu3.rename.IQFullEvents 29592 # Number of times rename has blocked due to IQ full
1927system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
1928system.cpu3.rename.RenamedOperands 184677 # Number of destination operands rename has renamed
1929system.cpu3.rename.RenameLookups 492576 # Number of register rename lookups that rename has made
1930system.cpu3.rename.int_rename_lookups 387264 # Number of integer rename lookups
1931system.cpu3.rename.fp_rename_lookups 20 # Number of floating rename lookups
1932system.cpu3.rename.CommittedMaps 155405 # Number of HB maps that are committed
1933system.cpu3.rename.UndoneMaps 29272 # Number of HB maps that are undone due to squashing
1934system.cpu3.rename.serializingInsts 1682 # count of serializing insts renamed
1935system.cpu3.rename.tempSerializingInsts 1811 # count of temporary serializing insts renamed
1936system.cpu3.rename.skidInsts 39856 # count of insts added to the skid buffer
1937system.cpu3.memDep0.insertedLoads 69050 # Number of loads inserted to the mem dependence unit.
1938system.cpu3.memDep0.insertedStores 30771 # Number of stores inserted to the mem dependence unit.
1939system.cpu3.memDep0.conflictingLoads 33750 # Number of conflicting loads.
1940system.cpu3.memDep0.conflictingStores 24332 # Number of conflicting stores.
1941system.cpu3.iq.iqInstsAdded 213083 # Number of instructions added to the IQ (excludes non-spec)
1942system.cpu3.iq.iqNonSpecInstsAdded 11008 # Number of non-speculative instructions added to the IQ
1943system.cpu3.iq.iqInstsIssued 216315 # Number of instructions issued
1944system.cpu3.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
1945system.cpu3.iq.iqSquashedInstsExamined 25213 # Number of squashed instructions iterated over during squash; mainly for profiling
1946system.cpu3.iq.iqSquashedOperandsExamined 19048 # Number of squashed operands that are examined and possibly removed from graph
1947system.cpu3.iq.iqSquashedNonSpecRemoved 1289 # Number of squashed non-spec instructions that were removed
1948system.cpu3.iq.issued_per_cycle::samples 190133 # Number of insts issued each cycle
1949system.cpu3.iq.issued_per_cycle::mean 1.137704 # Number of insts issued each cycle
1950system.cpu3.iq.issued_per_cycle::stdev 1.357547 # Number of insts issued each cycle

1958system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1951system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1959system.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle
1960system.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle
1961system.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle
1962system.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle
1963system.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle
1964system.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle
1965system.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle
1966system.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle
1967system.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle

1952system.cpu3.iq.issued_per_cycle::0 89784 47.22% 47.22% # Number of insts issued each cycle
1953system.cpu3.iq.issued_per_cycle::1 34463 18.13% 65.35% # Number of insts issued each cycle
1954system.cpu3.iq.issued_per_cycle::2 29348 15.44% 80.78% # Number of insts issued each cycle
1955system.cpu3.iq.issued_per_cycle::3 29336 15.43% 96.21% # Number of insts issued each cycle
1956system.cpu3.iq.issued_per_cycle::4 3681 1.94% 98.15% # Number of insts issued each cycle
1957system.cpu3.iq.issued_per_cycle::5 1744 0.92% 99.07% # Number of insts issued each cycle
1958system.cpu3.iq.issued_per_cycle::6 1040 0.55% 99.61% # Number of insts issued each cycle
1959system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.84% # Number of insts issued each cycle
1960system.cpu3.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle

1968system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1969system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1970system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1961system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1962system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1963system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1971system.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle

1964system.cpu3.iq.issued_per_cycle::total 190133 # Number of insts issued each cycle

1972system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1965system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1973system.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available
1974system.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available
1975system.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available
1976system.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available
1977system.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available
1978system.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available
1979system.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available
1980system.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available
1981system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available
1982system.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available
1983system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available
1984system.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available
1985system.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available
1986system.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available
1987system.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available
1988system.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available
1989system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available
1990system.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available
1991system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available
1992system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available
1993system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available
1994system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available
1995system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available
1996system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available
1997system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available
1998system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available
1999system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available
2000system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available
2001system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available
2002system.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available
2003system.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available

1966system.cpu3.iq.fu_full::IntAlu 189 39.38% 39.38% # attempts to use FU when none available
1967system.cpu3.iq.fu_full::IntMult 0 0.00% 39.38% # attempts to use FU when none available
1968system.cpu3.iq.fu_full::IntDiv 0 0.00% 39.38% # attempts to use FU when none available
1969system.cpu3.iq.fu_full::FloatAdd 0 0.00% 39.38% # attempts to use FU when none available
1970system.cpu3.iq.fu_full::FloatCmp 0 0.00% 39.38% # attempts to use FU when none available
1971system.cpu3.iq.fu_full::FloatCvt 0 0.00% 39.38% # attempts to use FU when none available
1972system.cpu3.iq.fu_full::FloatMult 0 0.00% 39.38% # attempts to use FU when none available
1973system.cpu3.iq.fu_full::FloatDiv 0 0.00% 39.38% # attempts to use FU when none available
1974system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 39.38% # attempts to use FU when none available
1975system.cpu3.iq.fu_full::SimdAdd 0 0.00% 39.38% # attempts to use FU when none available
1976system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 39.38% # attempts to use FU when none available
1977system.cpu3.iq.fu_full::SimdAlu 0 0.00% 39.38% # attempts to use FU when none available
1978system.cpu3.iq.fu_full::SimdCmp 0 0.00% 39.38% # attempts to use FU when none available
1979system.cpu3.iq.fu_full::SimdCvt 0 0.00% 39.38% # attempts to use FU when none available
1980system.cpu3.iq.fu_full::SimdMisc 0 0.00% 39.38% # attempts to use FU when none available
1981system.cpu3.iq.fu_full::SimdMult 0 0.00% 39.38% # attempts to use FU when none available
1982system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 39.38% # attempts to use FU when none available
1983system.cpu3.iq.fu_full::SimdShift 0 0.00% 39.38% # attempts to use FU when none available
1984system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 39.38% # attempts to use FU when none available
1985system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 39.38% # attempts to use FU when none available
1986system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 39.38% # attempts to use FU when none available
1987system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 39.38% # attempts to use FU when none available
1988system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 39.38% # attempts to use FU when none available
1989system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 39.38% # attempts to use FU when none available
1990system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 39.38% # attempts to use FU when none available
1991system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 39.38% # attempts to use FU when none available
1992system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 39.38% # attempts to use FU when none available
1993system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.38% # attempts to use FU when none available
1994system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 39.38% # attempts to use FU when none available
1995system.cpu3.iq.fu_full::MemRead 53 11.04% 50.42% # attempts to use FU when none available
1996system.cpu3.iq.fu_full::MemWrite 238 49.58% 100.00% # attempts to use FU when none available

2004system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2005system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2006system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1997system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1998system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1999system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

2007system.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued
2008system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued
2009system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued
2010system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued
2011system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued
2012system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued
2013system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued
2014system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued
2015system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued
2016system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued
2017system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued
2018system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued
2019system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued
2020system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued
2021system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued
2022system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued
2023system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued
2024system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued
2025system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued
2026system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued
2027system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued
2028system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued
2029system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued
2030system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued
2031system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued
2032system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued
2033system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued
2034system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued
2035system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued
2036system.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued
2037system.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued

2000system.cpu3.iq.FU_type_0::IntAlu 109511 50.63% 50.63% # Type of FU issued
2001system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.63% # Type of FU issued
2002system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.63% # Type of FU issued
2003system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.63% # Type of FU issued
2004system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.63% # Type of FU issued
2005system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.63% # Type of FU issued
2006system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.63% # Type of FU issued
2007system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.63% # Type of FU issued
2008system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.63% # Type of FU issued
2009system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.63% # Type of FU issued
2010system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.63% # Type of FU issued
2011system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.63% # Type of FU issued
2012system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.63% # Type of FU issued
2013system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.63% # Type of FU issued
2014system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.63% # Type of FU issued
2015system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.63% # Type of FU issued
2016system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.63% # Type of FU issued
2017system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.63% # Type of FU issued
2018system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.63% # Type of FU issued
2019system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.63% # Type of FU issued
2020system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.63% # Type of FU issued
2021system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.63% # Type of FU issued
2022system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.63% # Type of FU issued
2023system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.63% # Type of FU issued
2024system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.63% # Type of FU issued
2025system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.63% # Type of FU issued
2026system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.63% # Type of FU issued
2027system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.63% # Type of FU issued
2028system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.63% # Type of FU issued
2029system.cpu3.iq.FU_type_0::MemRead 77010 35.60% 86.23% # Type of FU issued
2030system.cpu3.iq.FU_type_0::MemWrite 29794 13.77% 100.00% # Type of FU issued

2038system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2039system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

2031system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2032system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

2040system.cpu3.iq.FU_type_0::total 236528 # Type of FU issued
2041system.cpu3.iq.rate 1.227136 # Inst issue rate
2042system.cpu3.iq.fu_busy_cnt 461 # FU busy when requested
2043system.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst)
2044system.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads
2045system.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes
2046system.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses

2033system.cpu3.iq.FU_type_0::total 216315 # Type of FU issued
2034system.cpu3.iq.rate 1.128080 # Inst issue rate
2035system.cpu3.iq.fu_busy_cnt 480 # FU busy when requested
2036system.cpu3.iq.fu_busy_rate 0.002219 # FU busy rate (busy events/executed inst)
2037system.cpu3.iq.int_inst_queue_reads 623296 # Number of integer instruction queue reads
2038system.cpu3.iq.int_inst_queue_writes 249298 # Number of integer instruction queue writes
2039system.cpu3.iq.int_inst_queue_wakeup_accesses 212257 # Number of integer instruction queue wakeup accesses

2047system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

2040system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads

2048system.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes

2041system.cpu3.iq.fp_inst_queue_writes 40 # Number of floating instruction queue writes

2049system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

2042system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

2050system.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses

2043system.cpu3.iq.int_alu_accesses 216795 # Number of integer alu accesses

2051system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses

2044system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses

2052system.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores

2045system.cpu3.iew.lsq.thread0.forwLoads 24283 # Number of loads that had data forwarded from stores

2053system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

2046system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

2054system.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed
2055system.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
2056system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
2057system.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed

2047system.cpu3.iew.lsq.thread0.squashedLoads 4403 # Number of loads squashed
2048system.cpu3.iew.lsq.thread0.ignoredResponses 27 # Number of memory responses ignored because the instruction is squashed
2049system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
2050system.cpu3.iew.lsq.thread0.squashedStores 2689 # Number of stores squashed

2058system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2059system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2060system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2061system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2062system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle

2051system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2052system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2053system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2054system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2055system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle

2063system.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing
2064system.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking
2065system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
2066system.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ
2067system.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch
2068system.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions
2069system.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions
2070system.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions
2071system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall

2056system.cpu3.iew.iewSquashCycles 2482 # Number of cycles IEW is squashing
2057system.cpu3.iew.iewBlockCycles 11408 # Number of cycles IEW is blocking
2058system.cpu3.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
2059system.cpu3.iew.iewDispatchedInsts 259073 # Number of instructions dispatched to IQ
2060system.cpu3.iew.iewDispSquashedInsts 473 # Number of squashed instructions skipped by dispatch
2061system.cpu3.iew.iewDispLoadInsts 69050 # Number of dispatched load instructions
2062system.cpu3.iew.iewDispStoreInsts 30771 # Number of dispatched store instructions
2063system.cpu3.iew.iewDispNonSpecInsts 1541 # Number of dispatched non-speculative instructions
2064system.cpu3.iew.iewIQFullEvents 26 # Number of times the IQ has become full, causing a stall

2072system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

2065system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

2073system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations
2074system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly
2075system.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly
2076system.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute
2077system.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions
2078system.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed
2079system.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute

2066system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
2067system.cpu3.iew.predictedTakenIncorrect 490 # Number of branches that were predicted taken incorrectly
2068system.cpu3.iew.predictedNotTakenIncorrect 2580 # Number of branches that were predicted not taken incorrectly
2069system.cpu3.iew.branchMispredicts 3070 # Number of branch mispredicts detected at execute
2070system.cpu3.iew.iewExecutedInsts 213662 # Number of executed instructions
2071system.cpu3.iew.iewExecLoadInsts 67471 # Number of load instructions executed
2072system.cpu3.iew.iewExecSquashedInsts 2653 # Number of squashed instructions skipped in execute

2080system.cpu3.iew.exec_swp 0 # number of swp insts executed

2073system.cpu3.iew.exec_swp 0 # number of swp insts executed

2081system.cpu3.iew.exec_nop 38771 # number of nop insts executed
2082system.cpu3.iew.exec_refs 110309 # number of memory reference insts executed
2083system.cpu3.iew.exec_branches 49060 # Number of branches executed
2084system.cpu3.iew.exec_stores 34297 # Number of stores executed
2085system.cpu3.iew.exec_rate 1.213725 # Inst execution rate
2086system.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit
2087system.cpu3.iew.wb_count 232596 # cumulative count of insts written-back
2088system.cpu3.iew.wb_producers 128296 # num instructions producing a value
2089system.cpu3.iew.wb_consumers 135910 # num instructions consuming a value
2090system.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle
2091system.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back
2092system.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit
2093system.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards
2094system.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted
2095system.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle
2096system.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle
2097system.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle

2074system.cpu3.iew.exec_nop 34982 # number of nop insts executed
2075system.cpu3.iew.exec_refs 96956 # number of memory reference insts executed
2076system.cpu3.iew.exec_branches 45328 # Number of branches executed
2077system.cpu3.iew.exec_stores 29485 # Number of stores executed
2078system.cpu3.iew.exec_rate 1.114245 # Inst execution rate
2079system.cpu3.iew.wb_sent 212766 # cumulative count of insts sent to commit
2080system.cpu3.iew.wb_count 212257 # cumulative count of insts written-back
2081system.cpu3.iew.wb_producers 115033 # num instructions producing a value
2082system.cpu3.iew.wb_consumers 122695 # num instructions consuming a value
2083system.cpu3.iew.wb_rate 1.106918 # insts written-back per cycle
2084system.cpu3.iew.wb_fanout 0.937552 # average fanout of values written-back
2085system.cpu3.commit.commitSquashedInsts 26335 # The number of squashed insts skipped by commit
2086system.cpu3.commit.commitNonSpecStalls 9719 # The number of times commit has been forced to stall to communicate backwards
2087system.cpu3.commit.branchMispredicts 2406 # The number of times a branch was mispredicted
2088system.cpu3.commit.committed_per_cycle::samples 185183 # Number of insts commited each cycle
2089system.cpu3.commit.committed_per_cycle::mean 1.256660 # Number of insts commited each cycle
2090system.cpu3.commit.committed_per_cycle::stdev 1.878907 # Number of insts commited each cycle

2098system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2091system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2099system.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle
2100system.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle
2101system.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle
2102system.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle
2103system.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle
2104system.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle
2105system.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle
2106system.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle
2107system.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle

2092system.cpu3.commit.committed_per_cycle::0 99076 53.50% 53.50% # Number of insts commited each cycle
2093system.cpu3.commit.committed_per_cycle::1 41559 22.44% 75.94% # Number of insts commited each cycle
2094system.cpu3.commit.committed_per_cycle::2 5388 2.91% 78.85% # Number of insts commited each cycle
2095system.cpu3.commit.committed_per_cycle::3 10319 5.57% 84.43% # Number of insts commited each cycle
2096system.cpu3.commit.committed_per_cycle::4 1252 0.68% 85.10% # Number of insts commited each cycle
2097system.cpu3.commit.committed_per_cycle::5 24567 13.27% 98.37% # Number of insts commited each cycle
2098system.cpu3.commit.committed_per_cycle::6 787 0.42% 98.79% # Number of insts commited each cycle
2099system.cpu3.commit.committed_per_cycle::7 1025 0.55% 99.35% # Number of insts commited each cycle
2100system.cpu3.commit.committed_per_cycle::8 1210 0.65% 100.00% # Number of insts commited each cycle

2108system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2109system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2110system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2101system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2102system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2103system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2111system.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle
2112system.cpu3.commit.committedInsts 257514 # Number of instructions committed
2113system.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed

2104system.cpu3.commit.committed_per_cycle::total 185183 # Number of insts commited each cycle
2105system.cpu3.commit.committedInsts 232712 # Number of instructions committed
2106system.cpu3.commit.committedOps 232712 # Number of ops (including micro ops) committed

2114system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed

2107system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed

2115system.cpu3.commit.refs 106267 # Number of memory references committed
2116system.cpu3.commit.loads 73290 # Number of loads committed
2117system.cpu3.commit.membars 7865 # Number of memory barriers committed
2118system.cpu3.commit.branches 46801 # Number of branches committed

2108system.cpu3.commit.refs 92729 # Number of memory references committed
2109system.cpu3.commit.loads 64647 # Number of loads committed
2110system.cpu3.commit.membars 9005 # Number of memory barriers committed
2111system.cpu3.commit.branches 43044 # Number of branches committed

2119system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.

2112system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.

2120system.cpu3.commit.int_insts 175188 # Number of committed integer instructions.

2113system.cpu3.commit.int_insts 157897 # Number of committed integer instructions.

2121system.cpu3.commit.function_calls 322 # Number of function calls committed.

2114system.cpu3.commit.function_calls 322 # Number of function calls committed.

2122system.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction
2123system.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction
2124system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction
2125system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction
2126system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction
2127system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction
2128system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction
2129system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction
2130system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction
2131system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction
2132system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction
2133system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction
2134system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction
2135system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction
2136system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction
2137system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction
2138system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction
2139system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction
2140system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction
2141system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction
2142system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction
2143system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction
2144system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction
2145system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction
2146system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction
2147system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction
2148system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction
2149system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction
2150system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction
2151system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction
2152system.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction
2153system.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction

2115system.cpu3.commit.op_class_0::No_OpClass 33834 14.54% 14.54% # Class of committed instruction
2116system.cpu3.commit.op_class_0::IntAlu 97144 41.74% 56.28% # Class of committed instruction
2117system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.28% # Class of committed instruction
2118system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.28% # Class of committed instruction
2119system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.28% # Class of committed instruction
2120system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.28% # Class of committed instruction
2121system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.28% # Class of committed instruction
2122system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.28% # Class of committed instruction
2123system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.28% # Class of committed instruction
2124system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.28% # Class of committed instruction
2125system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.28% # Class of committed instruction
2126system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.28% # Class of committed instruction
2127system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.28% # Class of committed instruction
2128system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.28% # Class of committed instruction
2129system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.28% # Class of committed instruction
2130system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.28% # Class of committed instruction
2131system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.28% # Class of committed instruction
2132system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.28% # Class of committed instruction
2133system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.28% # Class of committed instruction
2134system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.28% # Class of committed instruction
2135system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.28% # Class of committed instruction
2136system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.28% # Class of committed instruction
2137system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.28% # Class of committed instruction
2138system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.28% # Class of committed instruction
2139system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.28% # Class of committed instruction
2140system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.28% # Class of committed instruction
2141system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.28% # Class of committed instruction
2142system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.28% # Class of committed instruction
2143system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.28% # Class of committed instruction
2144system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.28% # Class of committed instruction
2145system.cpu3.commit.op_class_0::MemRead 73652 31.65% 87.93% # Class of committed instruction
2146system.cpu3.commit.op_class_0::MemWrite 28082 12.07% 100.00% # Class of committed instruction

2154system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2155system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2147system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2148system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2156system.cpu3.commit.op_class_0::total 257514 # Class of committed instruction
2157system.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached
2158system.cpu3.rob.rob_reads 467769 # The number of ROB reads
2159system.cpu3.rob.rob_writes 571412 # The number of ROB writes
2160system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
2161system.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling

2149system.cpu3.commit.op_class_0::total 232712 # Class of committed instruction
2150system.cpu3.commit.bw_lim_events 1210 # number cycles where commit BW limit reached
2151system.cpu3.rob.rob_reads 442434 # The number of ROB reads
2152system.cpu3.rob.rob_writes 523106 # The number of ROB writes
2153system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
2154system.cpu3.idleCycles 1622 # Total number of cycles that the CPU has spent unscheduled due to idling

2162system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

2155system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt

2163system.cpu3.committedInsts 212061 # Number of Instructions Simulated
2164system.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated
2165system.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction
2166system.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads
2167system.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle
2168system.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads
2169system.cpu3.int_regfile_reads 395124 # number of integer regfile reads
2170system.cpu3.int_regfile_writes 185063 # number of integer regfile writes

2156system.cpu3.committedInsts 189873 # Number of Instructions Simulated
2157system.cpu3.committedOps 189873 # Number of Ops (including micro ops) Simulated
2158system.cpu3.cpi 1.009912 # CPI: Cycles Per Instruction
2159system.cpu3.cpi_total 1.009912 # CPI: Total CPI of All Threads
2160system.cpu3.ipc 0.990185 # IPC: Instructions Per Cycle
2161system.cpu3.ipc_total 0.990185 # IPC: Total IPC of All Threads
2162system.cpu3.int_regfile_reads 355771 # number of integer regfile reads
2163system.cpu3.int_regfile_writes 167240 # number of integer regfile writes

2171system.cpu3.fp_regfile_writes 64 # number of floating regfile writes

2164system.cpu3.fp_regfile_writes 64 # number of floating regfile writes

2172system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads

2165system.cpu3.misc_regfile_reads 98845 # number of misc regfile reads

2173system.cpu3.misc_regfile_writes 648 # number of misc regfile writes

2166system.cpu3.misc_regfile_writes 648 # number of misc regfile writes

2174system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

2167system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

2175system.cpu3.dcache.tags.replacements 0 # number of replacements

2168system.cpu3.dcache.tags.replacements 0 # number of replacements

2176system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use
2177system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks.
2178system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
2179system.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks.

2169system.cpu3.dcache.tags.tagsinuse 24.519752 # Cycle average of tags in use
2170system.cpu3.dcache.tags.total_refs 35385 # Total number of references to valid blocks.
2171system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
2172system.cpu3.dcache.tags.avg_refs 1179.500000 # Average number of references to valid blocks.

2180system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2173system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2181system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.465247 # Average occupied blocks per requestor
2182system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047784 # Average percentage of cache occupancy
2183system.cpu3.dcache.tags.occ_percent::total 0.047784 # Average percentage of cache occupancy
2184system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
2185system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
2186system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
2187system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
2188system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses
2189system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses
2190system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
2191system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits
2192system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits
2193system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits
2194system.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits
2195system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
2196system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
2197system.cpu3.dcache.demand_hits::cpu3.data 79122 # number of demand (read+write) hits
2198system.cpu3.dcache.demand_hits::total 79122 # number of demand (read+write) hits
2199system.cpu3.dcache.overall_hits::cpu3.data 79122 # number of overall hits
2200system.cpu3.dcache.overall_hits::total 79122 # number of overall hits
2201system.cpu3.dcache.ReadReq_misses::cpu3.data 454 # number of ReadReq misses
2202system.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses

2174system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.519752 # Average occupied blocks per requestor
2175system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047890 # Average percentage of cache occupancy
2176system.cpu3.dcache.tags.occ_percent::total 0.047890 # Average percentage of cache occupancy
2177system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
2178system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
2179system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
2180system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
2181system.cpu3.dcache.tags.tag_accesses 285185 # Number of tag accesses
2182system.cpu3.dcache.tags.data_accesses 285185 # Number of data accesses
2183system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
2184system.cpu3.dcache.ReadReq_hits::cpu3.data 42713 # number of ReadReq hits
2185system.cpu3.dcache.ReadReq_hits::total 42713 # number of ReadReq hits
2186system.cpu3.dcache.WriteReq_hits::cpu3.data 27877 # number of WriteReq hits
2187system.cpu3.dcache.WriteReq_hits::total 27877 # number of WriteReq hits
2188system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits
2189system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits
2190system.cpu3.dcache.demand_hits::cpu3.data 70590 # number of demand (read+write) hits
2191system.cpu3.dcache.demand_hits::total 70590 # number of demand (read+write) hits
2192system.cpu3.dcache.overall_hits::cpu3.data 70590 # number of overall hits
2193system.cpu3.dcache.overall_hits::total 70590 # number of overall hits
2194system.cpu3.dcache.ReadReq_misses::cpu3.data 439 # number of ReadReq misses
2195system.cpu3.dcache.ReadReq_misses::total 439 # number of ReadReq misses

2203system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses
2204system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses

2196system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses
2197system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses

2205system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses
2206system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses
2207system.cpu3.dcache.demand_misses::cpu3.data 591 # number of demand (read+write) misses
2208system.cpu3.dcache.demand_misses::total 591 # number of demand (read+write) misses
2209system.cpu3.dcache.overall_misses::cpu3.data 591 # number of overall misses
2210system.cpu3.dcache.overall_misses::total 591 # number of overall misses
2211system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 6996500 # number of ReadReq miss cycles
2212system.cpu3.dcache.ReadReq_miss_latency::total 6996500 # number of ReadReq miss cycles
2213system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2957500 # number of WriteReq miss cycles
2214system.cpu3.dcache.WriteReq_miss_latency::total 2957500 # number of WriteReq miss cycles
2215system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 770500 # number of SwapReq miss cycles
2216system.cpu3.dcache.SwapReq_miss_latency::total 770500 # number of SwapReq miss cycles
2217system.cpu3.dcache.demand_miss_latency::cpu3.data 9954000 # number of demand (read+write) miss cycles
2218system.cpu3.dcache.demand_miss_latency::total 9954000 # number of demand (read+write) miss cycles
2219system.cpu3.dcache.overall_miss_latency::cpu3.data 9954000 # number of overall miss cycles
2220system.cpu3.dcache.overall_miss_latency::total 9954000 # number of overall miss cycles
2221system.cpu3.dcache.ReadReq_accesses::cpu3.data 46807 # number of ReadReq accesses(hits+misses)
2222system.cpu3.dcache.ReadReq_accesses::total 46807 # number of ReadReq accesses(hits+misses)
2223system.cpu3.dcache.WriteReq_accesses::cpu3.data 32906 # number of WriteReq accesses(hits+misses)
2224system.cpu3.dcache.WriteReq_accesses::total 32906 # number of WriteReq accesses(hits+misses)
2225system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
2226system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
2227system.cpu3.dcache.demand_accesses::cpu3.data 79713 # number of demand (read+write) accesses
2228system.cpu3.dcache.demand_accesses::total 79713 # number of demand (read+write) accesses
2229system.cpu3.dcache.overall_accesses::cpu3.data 79713 # number of overall (read+write) accesses
2230system.cpu3.dcache.overall_accesses::total 79713 # number of overall (read+write) accesses
2231system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009699 # miss rate for ReadReq accesses
2232system.cpu3.dcache.ReadReq_miss_rate::total 0.009699 # miss rate for ReadReq accesses
2233system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004163 # miss rate for WriteReq accesses
2234system.cpu3.dcache.WriteReq_miss_rate::total 0.004163 # miss rate for WriteReq accesses
2235system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses
2236system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses
2237system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007414 # miss rate for demand accesses
2238system.cpu3.dcache.demand_miss_rate::total 0.007414 # miss rate for demand accesses
2239system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007414 # miss rate for overall accesses
2240system.cpu3.dcache.overall_miss_rate::total 0.007414 # miss rate for overall accesses
2241system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15410.792952 # average ReadReq miss latency
2242system.cpu3.dcache.ReadReq_avg_miss_latency::total 15410.792952 # average ReadReq miss latency
2243system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21587.591241 # average WriteReq miss latency
2244system.cpu3.dcache.WriteReq_avg_miss_latency::total 21587.591241 # average WriteReq miss latency
2245system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 13758.928571 # average SwapReq miss latency
2246system.cpu3.dcache.SwapReq_avg_miss_latency::total 13758.928571 # average SwapReq miss latency
2247system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency
2248system.cpu3.dcache.demand_avg_miss_latency::total 16842.639594 # average overall miss latency
2249system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency
2250system.cpu3.dcache.overall_avg_miss_latency::total 16842.639594 # average overall miss latency

2198system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
2199system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
2200system.cpu3.dcache.demand_misses::cpu3.data 576 # number of demand (read+write) misses
2201system.cpu3.dcache.demand_misses::total 576 # number of demand (read+write) misses
2202system.cpu3.dcache.overall_misses::cpu3.data 576 # number of overall misses
2203system.cpu3.dcache.overall_misses::total 576 # number of overall misses
2204system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3185500 # number of ReadReq miss cycles
2205system.cpu3.dcache.ReadReq_miss_latency::total 3185500 # number of ReadReq miss cycles
2206system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2743000 # number of WriteReq miss cycles
2207system.cpu3.dcache.WriteReq_miss_latency::total 2743000 # number of WriteReq miss cycles
2208system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 334000 # number of SwapReq miss cycles
2209system.cpu3.dcache.SwapReq_miss_latency::total 334000 # number of SwapReq miss cycles
2210system.cpu3.dcache.demand_miss_latency::cpu3.data 5928500 # number of demand (read+write) miss cycles
2211system.cpu3.dcache.demand_miss_latency::total 5928500 # number of demand (read+write) miss cycles
2212system.cpu3.dcache.overall_miss_latency::cpu3.data 5928500 # number of overall miss cycles
2213system.cpu3.dcache.overall_miss_latency::total 5928500 # number of overall miss cycles
2214system.cpu3.dcache.ReadReq_accesses::cpu3.data 43152 # number of ReadReq accesses(hits+misses)
2215system.cpu3.dcache.ReadReq_accesses::total 43152 # number of ReadReq accesses(hits+misses)
2216system.cpu3.dcache.WriteReq_accesses::cpu3.data 28014 # number of WriteReq accesses(hits+misses)
2217system.cpu3.dcache.WriteReq_accesses::total 28014 # number of WriteReq accesses(hits+misses)
2218system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses)
2219system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
2220system.cpu3.dcache.demand_accesses::cpu3.data 71166 # number of demand (read+write) accesses
2221system.cpu3.dcache.demand_accesses::total 71166 # number of demand (read+write) accesses
2222system.cpu3.dcache.overall_accesses::cpu3.data 71166 # number of overall (read+write) accesses
2223system.cpu3.dcache.overall_accesses::total 71166 # number of overall (read+write) accesses
2224system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010173 # miss rate for ReadReq accesses
2225system.cpu3.dcache.ReadReq_miss_rate::total 0.010173 # miss rate for ReadReq accesses
2226system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004890 # miss rate for WriteReq accesses
2227system.cpu3.dcache.WriteReq_miss_rate::total 0.004890 # miss rate for WriteReq accesses
2228system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.764706 # miss rate for SwapReq accesses
2229system.cpu3.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses
2230system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008094 # miss rate for demand accesses
2231system.cpu3.dcache.demand_miss_rate::total 0.008094 # miss rate for demand accesses
2232system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008094 # miss rate for overall accesses
2233system.cpu3.dcache.overall_miss_rate::total 0.008094 # miss rate for overall accesses
2234system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7256.264237 # average ReadReq miss latency
2235system.cpu3.dcache.ReadReq_avg_miss_latency::total 7256.264237 # average ReadReq miss latency
2236system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810 # average WriteReq miss latency
2237system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810 # average WriteReq miss latency
2238system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6423.076923 # average SwapReq miss latency
2239system.cpu3.dcache.SwapReq_avg_miss_latency::total 6423.076923 # average SwapReq miss latency
2240system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency
2241system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722 # average overall miss latency
2242system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency
2243system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722 # average overall miss latency

2251system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2252system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2253system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2254system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2255system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2256system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2244system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2245system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2246system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2247system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2248system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2249system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2257system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 292 # number of ReadReq MSHR hits
2258system.cpu3.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits
2259system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits
2260system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
2261system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 3 # number of SwapReq MSHR hits
2262system.cpu3.dcache.SwapReq_mshr_hits::total 3 # number of SwapReq MSHR hits
2263system.cpu3.dcache.demand_mshr_hits::cpu3.data 327 # number of demand (read+write) MSHR hits
2264system.cpu3.dcache.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits
2265system.cpu3.dcache.overall_mshr_hits::cpu3.data 327 # number of overall MSHR hits
2266system.cpu3.dcache.overall_mshr_hits::total 327 # number of overall MSHR hits
2267system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 # number of ReadReq MSHR misses
2268system.cpu3.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
2269system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses
2270system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
2271system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses
2272system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses
2273system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses
2274system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses
2275system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses
2276system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
2277system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1605500 # number of ReadReq MSHR miss cycles
2278system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1605500 # number of ReadReq MSHR miss cycles
2279system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1601500 # number of WriteReq MSHR miss cycles
2280system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1601500 # number of WriteReq MSHR miss cycles
2281system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 714500 # number of SwapReq MSHR miss cycles
2282system.cpu3.dcache.SwapReq_mshr_miss_latency::total 714500 # number of SwapReq MSHR miss cycles
2283system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3207000 # number of demand (read+write) MSHR miss cycles
2284system.cpu3.dcache.demand_mshr_miss_latency::total 3207000 # number of demand (read+write) MSHR miss cycles
2285system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3207000 # number of overall MSHR miss cycles
2286system.cpu3.dcache.overall_mshr_miss_latency::total 3207000 # number of overall MSHR miss cycles
2287system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses
2288system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses
2289system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses
2290system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003100 # mshr miss rate for WriteReq accesses
2291system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.746479 # mshr miss rate for SwapReq accesses
2292system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SwapReq accesses
2293system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses
2294system.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses
2295system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for overall accesses
2296system.cpu3.dcache.overall_mshr_miss_rate::total 0.003312 # mshr miss rate for overall accesses
2297system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9910.493827 # average ReadReq mshr miss latency
2298system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9910.493827 # average ReadReq mshr miss latency
2299system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15700.980392 # average WriteReq mshr miss latency
2300system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15700.980392 # average WriteReq mshr miss latency
2301system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 13481.132075 # average SwapReq mshr miss latency
2302system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 13481.132075 # average SwapReq mshr miss latency
2303system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency
2304system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency
2305system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency
2306system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency
2307system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
2308system.cpu3.icache.tags.replacements 563 # number of replacements
2309system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use
2310system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks.
2311system.cpu3.icache.tags.sampled_refs 701 # Sample count of references to valid blocks.
2312system.cpu3.icache.tags.avg_refs 42.105563 # Average number of references to valid blocks.

2250system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 281 # number of ReadReq MSHR hits
2251system.cpu3.dcache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits
2252system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits
2253system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
2254system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits
2255system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits
2256system.cpu3.dcache.demand_mshr_hits::cpu3.data 314 # number of demand (read+write) MSHR hits
2257system.cpu3.dcache.demand_mshr_hits::total 314 # number of demand (read+write) MSHR hits
2258system.cpu3.dcache.overall_mshr_hits::cpu3.data 314 # number of overall MSHR hits
2259system.cpu3.dcache.overall_mshr_hits::total 314 # number of overall MSHR hits
2260system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses
2261system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
2262system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
2263system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
2264system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
2265system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
2266system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses
2267system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
2268system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses
2269system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
2270system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1084000 # number of ReadReq MSHR miss cycles
2271system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1084000 # number of ReadReq MSHR miss cycles
2272system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1390500 # number of WriteReq MSHR miss cycles
2273system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1390500 # number of WriteReq MSHR miss cycles
2274system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 282000 # number of SwapReq MSHR miss cycles
2275system.cpu3.dcache.SwapReq_mshr_miss_latency::total 282000 # number of SwapReq MSHR miss cycles
2276system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2474500 # number of demand (read+write) MSHR miss cycles
2277system.cpu3.dcache.demand_mshr_miss_latency::total 2474500 # number of demand (read+write) MSHR miss cycles
2278system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2474500 # number of overall MSHR miss cycles
2279system.cpu3.dcache.overall_mshr_miss_latency::total 2474500 # number of overall MSHR miss cycles
2280system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses
2281system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses
2282system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for WriteReq accesses
2283system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003712 # mshr miss rate for WriteReq accesses
2284system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.750000 # mshr miss rate for SwapReq accesses
2285system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses
2286system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for demand accesses
2287system.cpu3.dcache.demand_mshr_miss_rate::total 0.003682 # mshr miss rate for demand accesses
2288system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for overall accesses
2289system.cpu3.dcache.overall_mshr_miss_rate::total 0.003682 # mshr miss rate for overall accesses
2290system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6860.759494 # average ReadReq mshr miss latency
2291system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6860.759494 # average ReadReq mshr miss latency
2292system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13370.192308 # average WriteReq mshr miss latency
2293system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308 # average WriteReq mshr miss latency
2294system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5529.411765 # average SwapReq mshr miss latency
2295system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5529.411765 # average SwapReq mshr miss latency
2296system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency
2297system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency
2298system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency
2299system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency
2300system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
2301system.cpu3.icache.tags.replacements 578 # number of replacements
2302system.cpu3.icache.tags.tagsinuse 92.680953 # Cycle average of tags in use
2303system.cpu3.icache.tags.total_refs 32101 # Total number of references to valid blocks.
2304system.cpu3.icache.tags.sampled_refs 713 # Sample count of references to valid blocks.
2305system.cpu3.icache.tags.avg_refs 45.022440 # Average number of references to valid blocks.

2313system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2306system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2314system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.764815 # Average occupied blocks per requestor
2315system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183134 # Average percentage of cache occupancy
2316system.cpu3.icache.tags.occ_percent::total 0.183134 # Average percentage of cache occupancy
2317system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
2318system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

2307system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.680953 # Average occupied blocks per requestor
2308system.cpu3.icache.tags.occ_percent::cpu3.inst 0.181017 # Average percentage of cache occupancy
2309system.cpu3.icache.tags.occ_percent::total 0.181017 # Average percentage of cache occupancy
2310system.cpu3.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
2311system.cpu3.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id

2319system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id

2312system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id

2320system.cpu3.icache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
2321system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id
2322system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses
2323system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses
2324system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
2325system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits
2326system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits
2327system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits
2328system.cpu3.icache.demand_hits::total 29516 # number of demand (read+write) hits
2329system.cpu3.icache.overall_hits::cpu3.inst 29516 # number of overall hits
2330system.cpu3.icache.overall_hits::total 29516 # number of overall hits
2331system.cpu3.icache.ReadReq_misses::cpu3.inst 821 # number of ReadReq misses
2332system.cpu3.icache.ReadReq_misses::total 821 # number of ReadReq misses
2333system.cpu3.icache.demand_misses::cpu3.inst 821 # number of demand (read+write) misses
2334system.cpu3.icache.demand_misses::total 821 # number of demand (read+write) misses
2335system.cpu3.icache.overall_misses::cpu3.inst 821 # number of overall misses
2336system.cpu3.icache.overall_misses::total 821 # number of overall misses
2337system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11709000 # number of ReadReq miss cycles
2338system.cpu3.icache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles
2339system.cpu3.icache.demand_miss_latency::cpu3.inst 11709000 # number of demand (read+write) miss cycles
2340system.cpu3.icache.demand_miss_latency::total 11709000 # number of demand (read+write) miss cycles
2341system.cpu3.icache.overall_miss_latency::cpu3.inst 11709000 # number of overall miss cycles
2342system.cpu3.icache.overall_miss_latency::total 11709000 # number of overall miss cycles
2343system.cpu3.icache.ReadReq_accesses::cpu3.inst 30337 # number of ReadReq accesses(hits+misses)
2344system.cpu3.icache.ReadReq_accesses::total 30337 # number of ReadReq accesses(hits+misses)
2345system.cpu3.icache.demand_accesses::cpu3.inst 30337 # number of demand (read+write) accesses
2346system.cpu3.icache.demand_accesses::total 30337 # number of demand (read+write) accesses
2347system.cpu3.icache.overall_accesses::cpu3.inst 30337 # number of overall (read+write) accesses
2348system.cpu3.icache.overall_accesses::total 30337 # number of overall (read+write) accesses
2349system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.027063 # miss rate for ReadReq accesses
2350system.cpu3.icache.ReadReq_miss_rate::total 0.027063 # miss rate for ReadReq accesses
2351system.cpu3.icache.demand_miss_rate::cpu3.inst 0.027063 # miss rate for demand accesses
2352system.cpu3.icache.demand_miss_rate::total 0.027063 # miss rate for demand accesses
2353system.cpu3.icache.overall_miss_rate::cpu3.inst 0.027063 # miss rate for overall accesses
2354system.cpu3.icache.overall_miss_rate::total 0.027063 # miss rate for overall accesses
2355system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14261.875761 # average ReadReq miss latency
2356system.cpu3.icache.ReadReq_avg_miss_latency::total 14261.875761 # average ReadReq miss latency
2357system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency
2358system.cpu3.icache.demand_avg_miss_latency::total 14261.875761 # average overall miss latency
2359system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency
2360system.cpu3.icache.overall_avg_miss_latency::total 14261.875761 # average overall miss latency

2313system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id
2314system.cpu3.icache.tags.tag_accesses 33653 # Number of tag accesses
2315system.cpu3.icache.tags.data_accesses 33653 # Number of data accesses
2316system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
2317system.cpu3.icache.ReadReq_hits::cpu3.inst 32101 # number of ReadReq hits
2318system.cpu3.icache.ReadReq_hits::total 32101 # number of ReadReq hits
2319system.cpu3.icache.demand_hits::cpu3.inst 32101 # number of demand (read+write) hits
2320system.cpu3.icache.demand_hits::total 32101 # number of demand (read+write) hits
2321system.cpu3.icache.overall_hits::cpu3.inst 32101 # number of overall hits
2322system.cpu3.icache.overall_hits::total 32101 # number of overall hits
2323system.cpu3.icache.ReadReq_misses::cpu3.inst 839 # number of ReadReq misses
2324system.cpu3.icache.ReadReq_misses::total 839 # number of ReadReq misses
2325system.cpu3.icache.demand_misses::cpu3.inst 839 # number of demand (read+write) misses
2326system.cpu3.icache.demand_misses::total 839 # number of demand (read+write) misses
2327system.cpu3.icache.overall_misses::cpu3.inst 839 # number of overall misses
2328system.cpu3.icache.overall_misses::total 839 # number of overall misses
2329system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11633500 # number of ReadReq miss cycles
2330system.cpu3.icache.ReadReq_miss_latency::total 11633500 # number of ReadReq miss cycles
2331system.cpu3.icache.demand_miss_latency::cpu3.inst 11633500 # number of demand (read+write) miss cycles
2332system.cpu3.icache.demand_miss_latency::total 11633500 # number of demand (read+write) miss cycles
2333system.cpu3.icache.overall_miss_latency::cpu3.inst 11633500 # number of overall miss cycles
2334system.cpu3.icache.overall_miss_latency::total 11633500 # number of overall miss cycles
2335system.cpu3.icache.ReadReq_accesses::cpu3.inst 32940 # number of ReadReq accesses(hits+misses)
2336system.cpu3.icache.ReadReq_accesses::total 32940 # number of ReadReq accesses(hits+misses)
2337system.cpu3.icache.demand_accesses::cpu3.inst 32940 # number of demand (read+write) accesses
2338system.cpu3.icache.demand_accesses::total 32940 # number of demand (read+write) accesses
2339system.cpu3.icache.overall_accesses::cpu3.inst 32940 # number of overall (read+write) accesses
2340system.cpu3.icache.overall_accesses::total 32940 # number of overall (read+write) accesses
2341system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.025471 # miss rate for ReadReq accesses
2342system.cpu3.icache.ReadReq_miss_rate::total 0.025471 # miss rate for ReadReq accesses
2343system.cpu3.icache.demand_miss_rate::cpu3.inst 0.025471 # miss rate for demand accesses
2344system.cpu3.icache.demand_miss_rate::total 0.025471 # miss rate for demand accesses
2345system.cpu3.icache.overall_miss_rate::cpu3.inst 0.025471 # miss rate for overall accesses
2346system.cpu3.icache.overall_miss_rate::total 0.025471 # miss rate for overall accesses
2347system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13865.911800 # average ReadReq miss latency
2348system.cpu3.icache.ReadReq_avg_miss_latency::total 13865.911800 # average ReadReq miss latency
2349system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency
2350system.cpu3.icache.demand_avg_miss_latency::total 13865.911800 # average overall miss latency
2351system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency
2352system.cpu3.icache.overall_avg_miss_latency::total 13865.911800 # average overall miss latency

2361system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2362system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2363system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2364system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2365system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2366system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2353system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2354system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2355system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2356system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2357system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2358system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2367system.cpu3.icache.writebacks::writebacks 563 # number of writebacks
2368system.cpu3.icache.writebacks::total 563 # number of writebacks
2369system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 120 # number of ReadReq MSHR hits
2370system.cpu3.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits
2371system.cpu3.icache.demand_mshr_hits::cpu3.inst 120 # number of demand (read+write) MSHR hits
2372system.cpu3.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits
2373system.cpu3.icache.overall_mshr_hits::cpu3.inst 120 # number of overall MSHR hits
2374system.cpu3.icache.overall_mshr_hits::total 120 # number of overall MSHR hits
2375system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 701 # number of ReadReq MSHR misses
2376system.cpu3.icache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses
2377system.cpu3.icache.demand_mshr_misses::cpu3.inst 701 # number of demand (read+write) MSHR misses
2378system.cpu3.icache.demand_mshr_misses::total 701 # number of demand (read+write) MSHR misses
2379system.cpu3.icache.overall_mshr_misses::cpu3.inst 701 # number of overall MSHR misses
2380system.cpu3.icache.overall_mshr_misses::total 701 # number of overall MSHR misses
2381system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10046500 # number of ReadReq MSHR miss cycles
2382system.cpu3.icache.ReadReq_mshr_miss_latency::total 10046500 # number of ReadReq MSHR miss cycles
2383system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10046500 # number of demand (read+write) MSHR miss cycles
2384system.cpu3.icache.demand_mshr_miss_latency::total 10046500 # number of demand (read+write) MSHR miss cycles
2385system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10046500 # number of overall MSHR miss cycles
2386system.cpu3.icache.overall_mshr_miss_latency::total 10046500 # number of overall MSHR miss cycles
2387system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for ReadReq accesses
2388system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023107 # mshr miss rate for ReadReq accesses
2389system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for demand accesses
2390system.cpu3.icache.demand_mshr_miss_rate::total 0.023107 # mshr miss rate for demand accesses
2391system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for overall accesses
2392system.cpu3.icache.overall_mshr_miss_rate::total 0.023107 # mshr miss rate for overall accesses
2393system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average ReadReq mshr miss latency
2394system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14331.669044 # average ReadReq mshr miss latency
2395system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency
2396system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency
2397system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency
2398system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency
2399system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

2359system.cpu3.icache.writebacks::writebacks 578 # number of writebacks
2360system.cpu3.icache.writebacks::total 578 # number of writebacks
2361system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # number of ReadReq MSHR hits
2362system.cpu3.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits
2363system.cpu3.icache.demand_mshr_hits::cpu3.inst 126 # number of demand (read+write) MSHR hits
2364system.cpu3.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits
2365system.cpu3.icache.overall_mshr_hits::cpu3.inst 126 # number of overall MSHR hits
2366system.cpu3.icache.overall_mshr_hits::total 126 # number of overall MSHR hits
2367system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 713 # number of ReadReq MSHR misses
2368system.cpu3.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses
2369system.cpu3.icache.demand_mshr_misses::cpu3.inst 713 # number of demand (read+write) MSHR misses
2370system.cpu3.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses
2371system.cpu3.icache.overall_mshr_misses::cpu3.inst 713 # number of overall MSHR misses
2372system.cpu3.icache.overall_mshr_misses::total 713 # number of overall MSHR misses
2373system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10107000 # number of ReadReq MSHR miss cycles
2374system.cpu3.icache.ReadReq_mshr_miss_latency::total 10107000 # number of ReadReq MSHR miss cycles
2375system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10107000 # number of demand (read+write) MSHR miss cycles
2376system.cpu3.icache.demand_mshr_miss_latency::total 10107000 # number of demand (read+write) MSHR miss cycles
2377system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10107000 # number of overall MSHR miss cycles
2378system.cpu3.icache.overall_mshr_miss_latency::total 10107000 # number of overall MSHR miss cycles
2379system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for ReadReq accesses
2380system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021645 # mshr miss rate for ReadReq accesses
2381system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for demand accesses
2382system.cpu3.icache.demand_mshr_miss_rate::total 0.021645 # mshr miss rate for demand accesses
2383system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for overall accesses
2384system.cpu3.icache.overall_mshr_miss_rate::total 0.021645 # mshr miss rate for overall accesses
2385system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average ReadReq mshr miss latency
2386system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14175.315568 # average ReadReq mshr miss latency
2387system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average overall mshr miss latency
2388system.cpu3.icache.demand_avg_mshr_miss_latency::total 14175.315568 # average overall mshr miss latency
2389system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average overall mshr miss latency
2390system.cpu3.icache.overall_avg_mshr_miss_latency::total 14175.315568 # average overall mshr miss latency
2391system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

2400system.l2c.tags.replacements 0 # number of replacements

2392system.l2c.tags.replacements 0 # number of replacements

2401system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use
2402system.l2c.tags.total_refs 3075 # Total number of references to valid blocks.
2403system.l2c.tags.sampled_refs 580 # Sample count of references to valid blocks.
2404system.l2c.tags.avg_refs 5.301724 # Average number of references to valid blocks.

2393system.l2c.tags.tagsinuse 567.287206 # Cycle average of tags in use
2394system.l2c.tags.total_refs 3156 # Total number of references to valid blocks.
2395system.l2c.tags.sampled_refs 709 # Sample count of references to valid blocks.
2396system.l2c.tags.avg_refs 4.451340 # Average number of references to valid blocks.

2405system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2397system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2406system.l2c.tags.occ_blocks::writebacks 0.808056 # Average occupied blocks per requestor
2407system.l2c.tags.occ_blocks::cpu0.inst 302.503225 # Average occupied blocks per requestor
2408system.l2c.tags.occ_blocks::cpu0.data 58.822483 # Average occupied blocks per requestor
2409system.l2c.tags.occ_blocks::cpu1.inst 70.101034 # Average occupied blocks per requestor
2410system.l2c.tags.occ_blocks::cpu1.data 5.583860 # Average occupied blocks per requestor
2411system.l2c.tags.occ_blocks::cpu2.inst 9.384250 # Average occupied blocks per requestor
2412system.l2c.tags.occ_blocks::cpu2.data 1.286758 # Average occupied blocks per requestor
2413system.l2c.tags.occ_blocks::cpu3.inst 5.637625 # Average occupied blocks per requestor
2414system.l2c.tags.occ_blocks::cpu3.data 1.160677 # Average occupied blocks per requestor
2415system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
2416system.l2c.tags.occ_percent::cpu0.inst 0.004616 # Average percentage of cache occupancy
2417system.l2c.tags.occ_percent::cpu0.data 0.000898 # Average percentage of cache occupancy
2418system.l2c.tags.occ_percent::cpu1.inst 0.001070 # Average percentage of cache occupancy
2419system.l2c.tags.occ_percent::cpu1.data 0.000085 # Average percentage of cache occupancy
2420system.l2c.tags.occ_percent::cpu2.inst 0.000143 # Average percentage of cache occupancy
2421system.l2c.tags.occ_percent::cpu2.data 0.000020 # Average percentage of cache occupancy
2422system.l2c.tags.occ_percent::cpu3.inst 0.000086 # Average percentage of cache occupancy
2423system.l2c.tags.occ_percent::cpu3.data 0.000018 # Average percentage of cache occupancy
2424system.l2c.tags.occ_percent::total 0.006947 # Average percentage of cache occupancy
2425system.l2c.tags.occ_task_id_blocks::1024 580 # Occupied blocks per task id
2426system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
2427system.l2c.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
2428system.l2c.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id
2429system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id
2430system.l2c.tags.tag_accesses 31874 # Number of tag accesses
2431system.l2c.tags.data_accesses 31874 # Number of data accesses
2432system.l2c.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states

2398system.l2c.tags.occ_blocks::cpu0.inst 303.185096 # Average occupied blocks per requestor
2399system.l2c.tags.occ_blocks::cpu0.data 145.120224 # Average occupied blocks per requestor
2400system.l2c.tags.occ_blocks::cpu1.inst 69.165941 # Average occupied blocks per requestor
2401system.l2c.tags.occ_blocks::cpu1.data 16.093016 # Average occupied blocks per requestor
2402system.l2c.tags.occ_blocks::cpu2.inst 8.947029 # Average occupied blocks per requestor
2403system.l2c.tags.occ_blocks::cpu2.data 10.727803 # Average occupied blocks per requestor
2404system.l2c.tags.occ_blocks::cpu3.inst 4.254567 # Average occupied blocks per requestor
2405system.l2c.tags.occ_blocks::cpu3.data 9.793531 # Average occupied blocks per requestor
2406system.l2c.tags.occ_percent::cpu0.inst 0.004626 # Average percentage of cache occupancy
2407system.l2c.tags.occ_percent::cpu0.data 0.002214 # Average percentage of cache occupancy
2408system.l2c.tags.occ_percent::cpu1.inst 0.001055 # Average percentage of cache occupancy
2409system.l2c.tags.occ_percent::cpu1.data 0.000246 # Average percentage of cache occupancy
2410system.l2c.tags.occ_percent::cpu2.inst 0.000137 # Average percentage of cache occupancy
2411system.l2c.tags.occ_percent::cpu2.data 0.000164 # Average percentage of cache occupancy
2412system.l2c.tags.occ_percent::cpu3.inst 0.000065 # Average percentage of cache occupancy
2413system.l2c.tags.occ_percent::cpu3.data 0.000149 # Average percentage of cache occupancy
2414system.l2c.tags.occ_percent::total 0.008656 # Average percentage of cache occupancy
2415system.l2c.tags.occ_task_id_blocks::1024 709 # Occupied blocks per task id
2416system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
2417system.l2c.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
2418system.l2c.tags.age_task_id_blocks_1024::2 487 # Occupied blocks per task id
2419system.l2c.tags.occ_task_id_percent::1024 0.010818 # Percentage of cache occupancy per task id
2420system.l2c.tags.tag_accesses 31781 # Number of tag accesses
2421system.l2c.tags.data_accesses 31781 # Number of data accesses
2422system.l2c.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states

2433system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
2434system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits

2423system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
2424system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits

2435system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits
2436system.l2c.WritebackClean_hits::total 709 # number of WritebackClean hits
2437system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2438system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
2439system.l2c.ReadCleanReq_hits::cpu0.inst 319 # number of ReadCleanReq hits
2440system.l2c.ReadCleanReq_hits::cpu1.inst 617 # number of ReadCleanReq hits
2441system.l2c.ReadCleanReq_hits::cpu2.inst 711 # number of ReadCleanReq hits
2442system.l2c.ReadCleanReq_hits::cpu3.inst 686 # number of ReadCleanReq hits
2443system.l2c.ReadCleanReq_hits::total 2333 # number of ReadCleanReq hits

2425system.l2c.WritebackClean_hits::writebacks 719 # number of WritebackClean hits
2426system.l2c.WritebackClean_hits::total 719 # number of WritebackClean hits
2427system.l2c.UpgradeReq_hits::cpu0.data 24 # number of UpgradeReq hits
2428system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits
2429system.l2c.UpgradeReq_hits::cpu2.data 22 # number of UpgradeReq hits
2430system.l2c.UpgradeReq_hits::cpu3.data 23 # number of UpgradeReq hits
2431system.l2c.UpgradeReq_hits::total 88 # number of UpgradeReq hits
2432system.l2c.ReadCleanReq_hits::cpu0.inst 334 # number of ReadCleanReq hits
2433system.l2c.ReadCleanReq_hits::cpu1.inst 594 # number of ReadCleanReq hits
2434system.l2c.ReadCleanReq_hits::cpu2.inst 687 # number of ReadCleanReq hits
2435system.l2c.ReadCleanReq_hits::cpu3.inst 700 # number of ReadCleanReq hits
2436system.l2c.ReadCleanReq_hits::total 2315 # number of ReadCleanReq hits

2444system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
2445system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
2446system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
2447system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
2448system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits

2437system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
2438system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
2439system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
2440system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
2441system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits

2449system.l2c.demand_hits::cpu0.inst 319 # number of demand (read+write) hits

2442system.l2c.demand_hits::cpu0.inst 334 # number of demand (read+write) hits

2450system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2443system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2451system.l2c.demand_hits::cpu1.inst 617 # number of demand (read+write) hits

2444system.l2c.demand_hits::cpu1.inst 594 # number of demand (read+write) hits

2452system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits

2445system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits

2453system.l2c.demand_hits::cpu2.inst 711 # number of demand (read+write) hits

2446system.l2c.demand_hits::cpu2.inst 687 # number of demand (read+write) hits

2454system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits

2447system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits

2455system.l2c.demand_hits::cpu3.inst 686 # number of demand (read+write) hits

2448system.l2c.demand_hits::cpu3.inst 700 # number of demand (read+write) hits

2456system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2449system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2457system.l2c.demand_hits::total 2365 # number of demand (read+write) hits
2458system.l2c.overall_hits::cpu0.inst 319 # number of overall hits

2450system.l2c.demand_hits::total 2347 # number of demand (read+write) hits
2451system.l2c.overall_hits::cpu0.inst 334 # number of overall hits

2459system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2452system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2460system.l2c.overall_hits::cpu1.inst 617 # number of overall hits

2453system.l2c.overall_hits::cpu1.inst 594 # number of overall hits

2461system.l2c.overall_hits::cpu1.data 5 # number of overall hits

2454system.l2c.overall_hits::cpu1.data 5 # number of overall hits

2462system.l2c.overall_hits::cpu2.inst 711 # number of overall hits

2455system.l2c.overall_hits::cpu2.inst 687 # number of overall hits

2463system.l2c.overall_hits::cpu2.data 11 # number of overall hits

2456system.l2c.overall_hits::cpu2.data 11 # number of overall hits

2464system.l2c.overall_hits::cpu3.inst 686 # number of overall hits

2457system.l2c.overall_hits::cpu3.inst 700 # number of overall hits

2465system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2458system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2466system.l2c.overall_hits::total 2365 # number of overall hits
2467system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses
2468system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses
2469system.l2c.UpgradeReq_misses::cpu2.data 24 # number of UpgradeReq misses
2470system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
2471system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses

2459system.l2c.overall_hits::total 2347 # number of overall hits

2472system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2473system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2474system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2475system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2476system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2460system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
2461system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2462system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
2463system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2464system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2477system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses
2478system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses
2479system.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses
2480system.l2c.ReadCleanReq_misses::cpu3.inst 15 # number of ReadCleanReq misses
2481system.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses

2465system.l2c.ReadCleanReq_misses::cpu0.inst 379 # number of ReadCleanReq misses
2466system.l2c.ReadCleanReq_misses::cpu1.inst 93 # number of ReadCleanReq misses
2467system.l2c.ReadCleanReq_misses::cpu2.inst 23 # number of ReadCleanReq misses
2468system.l2c.ReadCleanReq_misses::cpu3.inst 13 # number of ReadCleanReq misses
2469system.l2c.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses

2482system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses

2470system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses

2483system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses

2471system.l2c.ReadSharedReq_misses::cpu1.data 8 # number of ReadSharedReq misses

2484system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses
2485system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses

2472system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses
2473system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses

2486system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses
2487system.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses

2474system.l2c.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses
2475system.l2c.demand_misses::cpu0.inst 379 # number of demand (read+write) misses

2488system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses

2476system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses

2489system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses
2490system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses
2491system.l2c.demand_misses::cpu2.inst 22 # number of demand (read+write) misses

2477system.l2c.demand_misses::cpu1.inst 93 # number of demand (read+write) misses
2478system.l2c.demand_misses::cpu1.data 21 # number of demand (read+write) misses
2479system.l2c.demand_misses::cpu2.inst 23 # number of demand (read+write) misses

2492system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses

2480system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses

2493system.l2c.demand_misses::cpu3.inst 15 # number of demand (read+write) misses

2481system.l2c.demand_misses::cpu3.inst 13 # number of demand (read+write) misses

2494system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses

2482system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses

2495system.l2c.demand_misses::total 731 # number of demand (read+write) misses
2496system.l2c.overall_misses::cpu0.inst 377 # number of overall misses

2483system.l2c.demand_misses::total 728 # number of demand (read+write) misses
2484system.l2c.overall_misses::cpu0.inst 379 # number of overall misses

2497system.l2c.overall_misses::cpu0.data 170 # number of overall misses

2485system.l2c.overall_misses::cpu0.data 170 # number of overall misses

2498system.l2c.overall_misses::cpu1.inst 96 # number of overall misses
2499system.l2c.overall_misses::cpu1.data 22 # number of overall misses
2500system.l2c.overall_misses::cpu2.inst 22 # number of overall misses

2486system.l2c.overall_misses::cpu1.inst 93 # number of overall misses
2487system.l2c.overall_misses::cpu1.data 21 # number of overall misses
2488system.l2c.overall_misses::cpu2.inst 23 # number of overall misses

2501system.l2c.overall_misses::cpu2.data 15 # number of overall misses

2489system.l2c.overall_misses::cpu2.data 15 # number of overall misses

2502system.l2c.overall_misses::cpu3.inst 15 # number of overall misses

2490system.l2c.overall_misses::cpu3.inst 13 # number of overall misses

2503system.l2c.overall_misses::cpu3.data 14 # number of overall misses

2491system.l2c.overall_misses::cpu3.data 14 # number of overall misses

2504system.l2c.overall_misses::total 731 # number of overall misses
2505system.l2c.ReadExReq_miss_latency::cpu0.data 7826000 # number of ReadExReq miss cycles

2492system.l2c.overall_misses::total 728 # number of overall misses
2493system.l2c.ReadExReq_miss_latency::cpu0.data 7826500 # number of ReadExReq miss cycles

2506system.l2c.ReadExReq_miss_latency::cpu1.data 1039500 # number of ReadExReq miss cycles
2507system.l2c.ReadExReq_miss_latency::cpu2.data 940000 # number of ReadExReq miss cycles

2494system.l2c.ReadExReq_miss_latency::cpu1.data 1039500 # number of ReadExReq miss cycles
2495system.l2c.ReadExReq_miss_latency::cpu2.data 940000 # number of ReadExReq miss cycles

2508system.l2c.ReadExReq_miss_latency::cpu3.data 937500 # number of ReadExReq miss cycles

2496system.l2c.ReadExReq_miss_latency::cpu3.data 937000 # number of ReadExReq miss cycles

2509system.l2c.ReadExReq_miss_latency::total 10743000 # number of ReadExReq miss cycles

2497system.l2c.ReadExReq_miss_latency::total 10743000 # number of ReadExReq miss cycles

2510system.l2c.ReadCleanReq_miss_latency::cpu0.inst 29108500 # number of ReadCleanReq miss cycles
2511system.l2c.ReadCleanReq_miss_latency::cpu1.inst 7180500 # number of ReadCleanReq miss cycles
2512system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1748500 # number of ReadCleanReq miss cycles
2513system.l2c.ReadCleanReq_miss_latency::cpu3.inst 1200000 # number of ReadCleanReq miss cycles
2514system.l2c.ReadCleanReq_miss_latency::total 39237500 # number of ReadCleanReq miss cycles
2515system.l2c.ReadSharedReq_miss_latency::cpu0.data 6133500 # number of ReadSharedReq miss cycles
2516system.l2c.ReadSharedReq_miss_latency::cpu1.data 728000 # number of ReadSharedReq miss cycles
2517system.l2c.ReadSharedReq_miss_latency::cpu2.data 251500 # number of ReadSharedReq miss cycles
2518system.l2c.ReadSharedReq_miss_latency::cpu3.data 195000 # number of ReadSharedReq miss cycles
2519system.l2c.ReadSharedReq_miss_latency::total 7308000 # number of ReadSharedReq miss cycles
2520system.l2c.demand_miss_latency::cpu0.inst 29108500 # number of demand (read+write) miss cycles
2521system.l2c.demand_miss_latency::cpu0.data 13959500 # number of demand (read+write) miss cycles
2522system.l2c.demand_miss_latency::cpu1.inst 7180500 # number of demand (read+write) miss cycles
2523system.l2c.demand_miss_latency::cpu1.data 1767500 # number of demand (read+write) miss cycles
2524system.l2c.demand_miss_latency::cpu2.inst 1748500 # number of demand (read+write) miss cycles
2525system.l2c.demand_miss_latency::cpu2.data 1191500 # number of demand (read+write) miss cycles
2526system.l2c.demand_miss_latency::cpu3.inst 1200000 # number of demand (read+write) miss cycles
2527system.l2c.demand_miss_latency::cpu3.data 1132500 # number of demand (read+write) miss cycles
2528system.l2c.demand_miss_latency::total 57288500 # number of demand (read+write) miss cycles
2529system.l2c.overall_miss_latency::cpu0.inst 29108500 # number of overall miss cycles
2530system.l2c.overall_miss_latency::cpu0.data 13959500 # number of overall miss cycles
2531system.l2c.overall_miss_latency::cpu1.inst 7180500 # number of overall miss cycles
2532system.l2c.overall_miss_latency::cpu1.data 1767500 # number of overall miss cycles
2533system.l2c.overall_miss_latency::cpu2.inst 1748500 # number of overall miss cycles
2534system.l2c.overall_miss_latency::cpu2.data 1191500 # number of overall miss cycles
2535system.l2c.overall_miss_latency::cpu3.inst 1200000 # number of overall miss cycles
2536system.l2c.overall_miss_latency::cpu3.data 1132500 # number of overall miss cycles
2537system.l2c.overall_miss_latency::total 57288500 # number of overall miss cycles

2498system.l2c.ReadCleanReq_miss_latency::cpu0.inst 29388500 # number of ReadCleanReq miss cycles
2499system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6947000 # number of ReadCleanReq miss cycles
2500system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2007500 # number of ReadCleanReq miss cycles
2501system.l2c.ReadCleanReq_miss_latency::cpu3.inst 1084500 # number of ReadCleanReq miss cycles
2502system.l2c.ReadCleanReq_miss_latency::total 39427500 # number of ReadCleanReq miss cycles
2503system.l2c.ReadSharedReq_miss_latency::cpu0.data 6119500 # number of ReadSharedReq miss cycles
2504system.l2c.ReadSharedReq_miss_latency::cpu1.data 658500 # number of ReadSharedReq miss cycles
2505system.l2c.ReadSharedReq_miss_latency::cpu2.data 265000 # number of ReadSharedReq miss cycles
2506system.l2c.ReadSharedReq_miss_latency::cpu3.data 181000 # number of ReadSharedReq miss cycles
2507system.l2c.ReadSharedReq_miss_latency::total 7224000 # number of ReadSharedReq miss cycles
2508system.l2c.demand_miss_latency::cpu0.inst 29388500 # number of demand (read+write) miss cycles
2509system.l2c.demand_miss_latency::cpu0.data 13946000 # number of demand (read+write) miss cycles
2510system.l2c.demand_miss_latency::cpu1.inst 6947000 # number of demand (read+write) miss cycles
2511system.l2c.demand_miss_latency::cpu1.data 1698000 # number of demand (read+write) miss cycles
2512system.l2c.demand_miss_latency::cpu2.inst 2007500 # number of demand (read+write) miss cycles
2513system.l2c.demand_miss_latency::cpu2.data 1205000 # number of demand (read+write) miss cycles
2514system.l2c.demand_miss_latency::cpu3.inst 1084500 # number of demand (read+write) miss cycles
2515system.l2c.demand_miss_latency::cpu3.data 1118000 # number of demand (read+write) miss cycles
2516system.l2c.demand_miss_latency::total 57394500 # number of demand (read+write) miss cycles
2517system.l2c.overall_miss_latency::cpu0.inst 29388500 # number of overall miss cycles
2518system.l2c.overall_miss_latency::cpu0.data 13946000 # number of overall miss cycles
2519system.l2c.overall_miss_latency::cpu1.inst 6947000 # number of overall miss cycles
2520system.l2c.overall_miss_latency::cpu1.data 1698000 # number of overall miss cycles
2521system.l2c.overall_miss_latency::cpu2.inst 2007500 # number of overall miss cycles
2522system.l2c.overall_miss_latency::cpu2.data 1205000 # number of overall miss cycles
2523system.l2c.overall_miss_latency::cpu3.inst 1084500 # number of overall miss cycles
2524system.l2c.overall_miss_latency::cpu3.data 1118000 # number of overall miss cycles
2525system.l2c.overall_miss_latency::total 57394500 # number of overall miss cycles

2538system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
2539system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)

2526system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
2527system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)

2540system.l2c.WritebackClean_accesses::writebacks 709 # number of WritebackClean accesses(hits+misses)
2541system.l2c.WritebackClean_accesses::total 709 # number of WritebackClean accesses(hits+misses)

2528system.l2c.WritebackClean_accesses::writebacks 719 # number of WritebackClean accesses(hits+misses)
2529system.l2c.WritebackClean_accesses::total 719 # number of WritebackClean accesses(hits+misses)

2542system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses)

2530system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses)

2543system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses)
2544system.l2c.UpgradeReq_accesses::cpu2.data 24 # number of UpgradeReq accesses(hits+misses)
2545system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)

2531system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
2532system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses)
2533system.l2c.UpgradeReq_accesses::cpu3.data 23 # number of UpgradeReq accesses(hits+misses)

2546system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses)
2547system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2548system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2549system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2550system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2551system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2534system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses)
2535system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
2536system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2537system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
2538system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2539system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2552system.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses)
2553system.l2c.ReadCleanReq_accesses::cpu1.inst 713 # number of ReadCleanReq accesses(hits+misses)
2554system.l2c.ReadCleanReq_accesses::cpu2.inst 733 # number of ReadCleanReq accesses(hits+misses)
2555system.l2c.ReadCleanReq_accesses::cpu3.inst 701 # number of ReadCleanReq accesses(hits+misses)
2556system.l2c.ReadCleanReq_accesses::total 2843 # number of ReadCleanReq accesses(hits+misses)

2540system.l2c.ReadCleanReq_accesses::cpu0.inst 713 # number of ReadCleanReq accesses(hits+misses)
2541system.l2c.ReadCleanReq_accesses::cpu1.inst 687 # number of ReadCleanReq accesses(hits+misses)
2542system.l2c.ReadCleanReq_accesses::cpu2.inst 710 # number of ReadCleanReq accesses(hits+misses)
2543system.l2c.ReadCleanReq_accesses::cpu3.inst 713 # number of ReadCleanReq accesses(hits+misses)
2544system.l2c.ReadCleanReq_accesses::total 2823 # number of ReadCleanReq accesses(hits+misses)

2557system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses)

2545system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses)

2558system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses)

2546system.l2c.ReadSharedReq_accesses::cpu1.data 13 # number of ReadSharedReq accesses(hits+misses)

2559system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses)
2560system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses)

2547system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses)
2548system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses)

2561system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses)
2562system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses

2549system.l2c.ReadSharedReq_accesses::total 121 # number of ReadSharedReq accesses(hits+misses)
2550system.l2c.demand_accesses::cpu0.inst 713 # number of demand (read+write) accesses

2563system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses

2551system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses

2564system.l2c.demand_accesses::cpu1.inst 713 # number of demand (read+write) accesses
2565system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses
2566system.l2c.demand_accesses::cpu2.inst 733 # number of demand (read+write) accesses

2552system.l2c.demand_accesses::cpu1.inst 687 # number of demand (read+write) accesses
2553system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses
2554system.l2c.demand_accesses::cpu2.inst 710 # number of demand (read+write) accesses

2567system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses

2555system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses

2568system.l2c.demand_accesses::cpu3.inst 701 # number of demand (read+write) accesses

2556system.l2c.demand_accesses::cpu3.inst 713 # number of demand (read+write) accesses

2569system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses

2557system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses

2570system.l2c.demand_accesses::total 3096 # number of demand (read+write) accesses
2571system.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses

2558system.l2c.demand_accesses::total 3075 # number of demand (read+write) accesses
2559system.l2c.overall_accesses::cpu0.inst 713 # number of overall (read+write) accesses

2572system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses

2560system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses

2573system.l2c.overall_accesses::cpu1.inst 713 # number of overall (read+write) accesses
2574system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses
2575system.l2c.overall_accesses::cpu2.inst 733 # number of overall (read+write) accesses

2561system.l2c.overall_accesses::cpu1.inst 687 # number of overall (read+write) accesses
2562system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses
2563system.l2c.overall_accesses::cpu2.inst 710 # number of overall (read+write) accesses

2576system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses

2564system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses

2577system.l2c.overall_accesses::cpu3.inst 701 # number of overall (read+write) accesses

2565system.l2c.overall_accesses::cpu3.inst 713 # number of overall (read+write) accesses

2578system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses

2566system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses

2579system.l2c.overall_accesses::total 3096 # number of overall (read+write) accesses
2580system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses
2581system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2582system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2583system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
2584system.l2c.UpgradeReq_miss_rate::total 0.965909 # miss rate for UpgradeReq accesses

2567system.l2c.overall_accesses::total 3075 # number of overall (read+write) accesses

2585system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2586system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2587system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2588system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2589system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2568system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2569system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2570system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2571system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2572system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2590system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.541667 # miss rate for ReadCleanReq accesses
2591system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.134642 # miss rate for ReadCleanReq accesses
2592system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.030014 # miss rate for ReadCleanReq accesses
2593system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.021398 # miss rate for ReadCleanReq accesses
2594system.l2c.ReadCleanReq_miss_rate::total 0.179388 # miss rate for ReadCleanReq accesses

2573system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.531557 # miss rate for ReadCleanReq accesses
2574system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.135371 # miss rate for ReadCleanReq accesses
2575system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.032394 # miss rate for ReadCleanReq accesses
2576system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018233 # miss rate for ReadCleanReq accesses
2577system.l2c.ReadCleanReq_miss_rate::total 0.179950 # miss rate for ReadCleanReq accesses

2595system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses

2578system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses

2596system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses

2579system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadSharedReq accesses

2597system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses
2598system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses

2580system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses
2581system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses

2599system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses
2600system.l2c.demand_miss_rate::cpu0.inst 0.541667 # miss rate for demand accesses

2582system.l2c.ReadSharedReq_miss_rate::total 0.735537 # miss rate for ReadSharedReq accesses
2583system.l2c.demand_miss_rate::cpu0.inst 0.531557 # miss rate for demand accesses

2601system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses

2584system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses

2602system.l2c.demand_miss_rate::cpu1.inst 0.134642 # miss rate for demand accesses
2603system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses
2604system.l2c.demand_miss_rate::cpu2.inst 0.030014 # miss rate for demand accesses

2585system.l2c.demand_miss_rate::cpu1.inst 0.135371 # miss rate for demand accesses
2586system.l2c.demand_miss_rate::cpu1.data 0.807692 # miss rate for demand accesses
2587system.l2c.demand_miss_rate::cpu2.inst 0.032394 # miss rate for demand accesses

2605system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses

2588system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses

2606system.l2c.demand_miss_rate::cpu3.inst 0.021398 # miss rate for demand accesses

2589system.l2c.demand_miss_rate::cpu3.inst 0.018233 # miss rate for demand accesses

2607system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses

2590system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses

2608system.l2c.demand_miss_rate::total 0.236111 # miss rate for demand accesses
2609system.l2c.overall_miss_rate::cpu0.inst 0.541667 # miss rate for overall accesses

2591system.l2c.demand_miss_rate::total 0.236748 # miss rate for demand accesses
2592system.l2c.overall_miss_rate::cpu0.inst 0.531557 # miss rate for overall accesses

2610system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses

2593system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses

2611system.l2c.overall_miss_rate::cpu1.inst 0.134642 # miss rate for overall accesses
2612system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses
2613system.l2c.overall_miss_rate::cpu2.inst 0.030014 # miss rate for overall accesses

2594system.l2c.overall_miss_rate::cpu1.inst 0.135371 # miss rate for overall accesses
2595system.l2c.overall_miss_rate::cpu1.data 0.807692 # miss rate for overall accesses
2596system.l2c.overall_miss_rate::cpu2.inst 0.032394 # miss rate for overall accesses

2614system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses

2597system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses

2615system.l2c.overall_miss_rate::cpu3.inst 0.021398 # miss rate for overall accesses

2598system.l2c.overall_miss_rate::cpu3.inst 0.018233 # miss rate for overall accesses

2616system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses

2599system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses

2617system.l2c.overall_miss_rate::total 0.236111 # miss rate for overall accesses
2618system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83255.319149 # average ReadExReq miss latency

2600system.l2c.overall_miss_rate::total 0.236748 # miss rate for overall accesses
2601system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83260.638298 # average ReadExReq miss latency

2619system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462 # average ReadExReq miss latency
2620system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333 # average ReadExReq miss latency

2602system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462 # average ReadExReq miss latency
2603system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333 # average ReadExReq miss latency

2621system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78125 # average ReadExReq miss latency

2604system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78083.333333 # average ReadExReq miss latency

2622system.l2c.ReadExReq_avg_miss_latency::total 82007.633588 # average ReadExReq miss latency

2605system.l2c.ReadExReq_avg_miss_latency::total 82007.633588 # average ReadExReq miss latency

2623system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77210.875332 # average ReadCleanReq miss latency
2624system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74796.875000 # average ReadCleanReq miss latency
2625system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 79477.272727 # average ReadCleanReq miss latency
2626system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 80000 # average ReadCleanReq miss latency
2627system.l2c.ReadCleanReq_avg_miss_latency::total 76936.274510 # average ReadCleanReq miss latency
2628system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80703.947368 # average ReadSharedReq miss latency
2629system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80888.888889 # average ReadSharedReq miss latency
2630system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83833.333333 # average ReadSharedReq miss latency
2631system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 97500 # average ReadSharedReq miss latency
2632system.l2c.ReadSharedReq_avg_miss_latency::total 81200 # average ReadSharedReq miss latency
2633system.l2c.demand_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency
2634system.l2c.demand_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency
2635system.l2c.demand_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency
2636system.l2c.demand_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency
2637system.l2c.demand_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency
2638system.l2c.demand_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency
2639system.l2c.demand_avg_miss_latency::cpu3.inst 80000 # average overall miss latency
2640system.l2c.demand_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency
2641system.l2c.demand_avg_miss_latency::total 78370.041040 # average overall miss latency
2642system.l2c.overall_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency
2643system.l2c.overall_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency
2644system.l2c.overall_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency
2645system.l2c.overall_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency
2646system.l2c.overall_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency
2647system.l2c.overall_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency
2648system.l2c.overall_avg_miss_latency::cpu3.inst 80000 # average overall miss latency
2649system.l2c.overall_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency
2650system.l2c.overall_avg_miss_latency::total 78370.041040 # average overall miss latency

2606system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77542.216359 # average ReadCleanReq miss latency
2607system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74698.924731 # average ReadCleanReq miss latency
2608system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 87282.608696 # average ReadCleanReq miss latency
2609system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83423.076923 # average ReadCleanReq miss latency
2610system.l2c.ReadCleanReq_avg_miss_latency::total 77613.188976 # average ReadCleanReq miss latency
2611system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80519.736842 # average ReadSharedReq miss latency
2612system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82312.500000 # average ReadSharedReq miss latency
2613system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 88333.333333 # average ReadSharedReq miss latency
2614system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90500 # average ReadSharedReq miss latency
2615system.l2c.ReadSharedReq_avg_miss_latency::total 81168.539326 # average ReadSharedReq miss latency
2616system.l2c.demand_avg_miss_latency::cpu0.inst 77542.216359 # average overall miss latency
2617system.l2c.demand_avg_miss_latency::cpu0.data 82035.294118 # average overall miss latency
2618system.l2c.demand_avg_miss_latency::cpu1.inst 74698.924731 # average overall miss latency
2619system.l2c.demand_avg_miss_latency::cpu1.data 80857.142857 # average overall miss latency
2620system.l2c.demand_avg_miss_latency::cpu2.inst 87282.608696 # average overall miss latency
2621system.l2c.demand_avg_miss_latency::cpu2.data 80333.333333 # average overall miss latency
2622system.l2c.demand_avg_miss_latency::cpu3.inst 83423.076923 # average overall miss latency
2623system.l2c.demand_avg_miss_latency::cpu3.data 79857.142857 # average overall miss latency
2624system.l2c.demand_avg_miss_latency::total 78838.598901 # average overall miss latency
2625system.l2c.overall_avg_miss_latency::cpu0.inst 77542.216359 # average overall miss latency
2626system.l2c.overall_avg_miss_latency::cpu0.data 82035.294118 # average overall miss latency
2627system.l2c.overall_avg_miss_latency::cpu1.inst 74698.924731 # average overall miss latency
2628system.l2c.overall_avg_miss_latency::cpu1.data 80857.142857 # average overall miss latency
2629system.l2c.overall_avg_miss_latency::cpu2.inst 87282.608696 # average overall miss latency
2630system.l2c.overall_avg_miss_latency::cpu2.data 80333.333333 # average overall miss latency
2631system.l2c.overall_avg_miss_latency::cpu3.inst 83423.076923 # average overall miss latency
2632system.l2c.overall_avg_miss_latency::cpu3.data 79857.142857 # average overall miss latency
2633system.l2c.overall_avg_miss_latency::total 78838.598901 # average overall miss latency

2651system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2652system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2653system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2654system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2655system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2656system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2634system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2635system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2636system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2637system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2638system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2639system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2657system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits

2640system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits

2658system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits

2641system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits

2659system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits
2660system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits
2661system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits
2662system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits

2642system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 9 # number of ReadCleanReq MSHR hits
2643system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
2644system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
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2646system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits

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2665system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits
2666system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
2667system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits

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2649system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
2650system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits

2668system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits

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2671system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
2672system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses
2673system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses
2674system.l2c.UpgradeReq_mshr_misses::cpu2.data 24 # number of UpgradeReq MSHR misses
2675system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
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2652system.l2c.overall_mshr_hits::cpu2.inst 9 # number of overall MSHR hits
2653system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
2654system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits

2677system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
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2655system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
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2658system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
2659system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses

2682system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses
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2660system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 377 # number of ReadCleanReq MSHR misses
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2686system.l2c.ReadCleanReq_mshr_misses::total 493 # number of ReadCleanReq MSHR misses

2663system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 10 # number of ReadCleanReq MSHR misses
2664system.l2c.ReadCleanReq_mshr_misses::total 490 # number of ReadCleanReq MSHR misses

2687system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses

2665system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses

2688system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses

2666system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8 # number of ReadSharedReq MSHR misses

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2667system.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses
2668system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses

2691system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses
2692system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses

2669system.l2c.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses
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2693system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses

2671system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses

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2696system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses
2697system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses

2674system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses
2675system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses

2698system.l2c.demand_mshr_misses::cpu3.inst 11 # number of demand (read+write) MSHR misses

2676system.l2c.demand_mshr_misses::cpu3.inst 10 # number of demand (read+write) MSHR misses

2699system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses

2677system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses

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2678system.l2c.demand_mshr_misses::total 710 # number of demand (read+write) MSHR misses
2679system.l2c.overall_mshr_misses::cpu0.inst 377 # number of overall MSHR misses

2702system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses

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2681system.l2c.overall_mshr_misses::cpu1.inst 89 # number of overall MSHR misses
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2683system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses
2684system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses

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2708system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses

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2709system.l2c.overall_mshr_misses::total 714 # number of overall MSHR misses
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2711system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 400000 # number of UpgradeReq MSHR miss cycles
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2714system.l2c.UpgradeReq_mshr_miss_latency::total 1697500 # number of UpgradeReq MSHR miss cycles
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2687system.l2c.overall_mshr_misses::total 710 # number of overall MSHR misses
2688system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6886500 # number of ReadExReq MSHR miss cycles

2716system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 909500 # number of ReadExReq MSHR miss cycles
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2689system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 909500 # number of ReadExReq MSHR miss cycles
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2691system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 817000 # number of ReadExReq MSHR miss cycles

2719system.l2c.ReadExReq_mshr_miss_latency::total 9433000 # number of ReadExReq MSHR miss cycles

2692system.l2c.ReadExReq_mshr_miss_latency::total 9433000 # number of ReadExReq MSHR miss cycles

2720system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25321000 # number of ReadCleanReq MSHR miss cycles
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2724system.l2c.ReadCleanReq_mshr_miss_latency::total 33275500 # number of ReadCleanReq MSHR miss cycles
2725system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5373500 # number of ReadSharedReq MSHR miss cycles
2726system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 638000 # number of ReadSharedReq MSHR miss cycles
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2728system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 175000 # number of ReadSharedReq MSHR miss cycles
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2737system.l2c.demand_mshr_miss_latency::cpu3.data 992500 # number of demand (read+write) MSHR miss cycles
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2739system.l2c.overall_mshr_miss_latency::cpu0.inst 25321000 # number of overall MSHR miss cycles
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2742system.l2c.overall_mshr_miss_latency::cpu1.data 1547500 # number of overall MSHR miss cycles
2743system.l2c.overall_mshr_miss_latency::cpu2.inst 1080000 # number of overall MSHR miss cycles
2744system.l2c.overall_mshr_miss_latency::cpu2.data 1041500 # number of overall MSHR miss cycles
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2746system.l2c.overall_mshr_miss_latency::cpu3.data 992500 # number of overall MSHR miss cycles
2747system.l2c.overall_mshr_miss_latency::total 49116500 # number of overall MSHR miss cycles
2748system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses
2749system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2750system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2751system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
2752system.l2c.UpgradeReq_mshr_miss_rate::total 0.965909 # mshr miss rate for UpgradeReq accesses

2693system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25557000 # number of ReadCleanReq MSHR miss cycles
2694system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5847000 # number of ReadCleanReq MSHR miss cycles
2695system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1317000 # number of ReadCleanReq MSHR miss cycles
2696system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 764500 # number of ReadCleanReq MSHR miss cycles
2697system.l2c.ReadCleanReq_mshr_miss_latency::total 33485500 # number of ReadCleanReq MSHR miss cycles
2698system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5359500 # number of ReadSharedReq MSHR miss cycles
2699system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 578500 # number of ReadSharedReq MSHR miss cycles
2700system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 235000 # number of ReadSharedReq MSHR miss cycles
2701system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 161000 # number of ReadSharedReq MSHR miss cycles
2702system.l2c.ReadSharedReq_mshr_miss_latency::total 6334000 # number of ReadSharedReq MSHR miss cycles
2703system.l2c.demand_mshr_miss_latency::cpu0.inst 25557000 # number of demand (read+write) MSHR miss cycles
2704system.l2c.demand_mshr_miss_latency::cpu0.data 12246000 # number of demand (read+write) MSHR miss cycles
2705system.l2c.demand_mshr_miss_latency::cpu1.inst 5847000 # number of demand (read+write) MSHR miss cycles
2706system.l2c.demand_mshr_miss_latency::cpu1.data 1488000 # number of demand (read+write) MSHR miss cycles
2707system.l2c.demand_mshr_miss_latency::cpu2.inst 1317000 # number of demand (read+write) MSHR miss cycles
2708system.l2c.demand_mshr_miss_latency::cpu2.data 1055000 # number of demand (read+write) MSHR miss cycles
2709system.l2c.demand_mshr_miss_latency::cpu3.inst 764500 # number of demand (read+write) MSHR miss cycles
2710system.l2c.demand_mshr_miss_latency::cpu3.data 978000 # number of demand (read+write) MSHR miss cycles
2711system.l2c.demand_mshr_miss_latency::total 49252500 # number of demand (read+write) MSHR miss cycles
2712system.l2c.overall_mshr_miss_latency::cpu0.inst 25557000 # number of overall MSHR miss cycles
2713system.l2c.overall_mshr_miss_latency::cpu0.data 12246000 # number of overall MSHR miss cycles
2714system.l2c.overall_mshr_miss_latency::cpu1.inst 5847000 # number of overall MSHR miss cycles
2715system.l2c.overall_mshr_miss_latency::cpu1.data 1488000 # number of overall MSHR miss cycles
2716system.l2c.overall_mshr_miss_latency::cpu2.inst 1317000 # number of overall MSHR miss cycles
2717system.l2c.overall_mshr_miss_latency::cpu2.data 1055000 # number of overall MSHR miss cycles
2718system.l2c.overall_mshr_miss_latency::cpu3.inst 764500 # number of overall MSHR miss cycles
2719system.l2c.overall_mshr_miss_latency::cpu3.data 978000 # number of overall MSHR miss cycles
2720system.l2c.overall_mshr_miss_latency::total 49252500 # number of overall MSHR miss cycles

2753system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2754system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2755system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2756system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2757system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2721system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2722system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2723system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2724system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2725system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2758system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses
2759system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for ReadCleanReq accesses
2760system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for ReadCleanReq accesses
2761system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for ReadCleanReq accesses
2762system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173408 # mshr miss rate for ReadCleanReq accesses

2726system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.528752 # mshr miss rate for ReadCleanReq accesses
2727system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.129549 # mshr miss rate for ReadCleanReq accesses
2728system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019718 # mshr miss rate for ReadCleanReq accesses
2729system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014025 # mshr miss rate for ReadCleanReq accesses
2730system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173574 # mshr miss rate for ReadCleanReq accesses

2763system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses

2731system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses

2764system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses

2732system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.615385 # mshr miss rate for ReadSharedReq accesses

2765system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses
2766system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses

2733system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses
2734system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses

2767system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses
2768system.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses

2735system.l2c.ReadSharedReq_mshr_miss_rate::total 0.735537 # mshr miss rate for ReadSharedReq accesses
2736system.l2c.demand_mshr_miss_rate::cpu0.inst 0.528752 # mshr miss rate for demand accesses

2769system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses

2737system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses

2770system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for demand accesses
2771system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses
2772system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for demand accesses

2738system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129549 # mshr miss rate for demand accesses
2739system.l2c.demand_mshr_miss_rate::cpu1.data 0.807692 # mshr miss rate for demand accesses
2740system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019718 # mshr miss rate for demand accesses

2773system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses

2741system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses

2774system.l2c.demand_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for demand accesses

2742system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014025 # mshr miss rate for demand accesses

2775system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses

2743system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses

2776system.l2c.demand_mshr_miss_rate::total 0.230620 # mshr miss rate for demand accesses
2777system.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses

2744system.l2c.demand_mshr_miss_rate::total 0.230894 # mshr miss rate for demand accesses
2745system.l2c.overall_mshr_miss_rate::cpu0.inst 0.528752 # mshr miss rate for overall accesses

2778system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses

2746system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses

2779system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for overall accesses
2780system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses
2781system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for overall accesses

2747system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129549 # mshr miss rate for overall accesses
2748system.l2c.overall_mshr_miss_rate::cpu1.data 0.807692 # mshr miss rate for overall accesses
2749system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019718 # mshr miss rate for overall accesses

2782system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses

2750system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses

2783system.l2c.overall_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for overall accesses

2751system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014025 # mshr miss rate for overall accesses

2784system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses

2752system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses

2785system.l2c.overall_mshr_miss_rate::total 0.230620 # mshr miss rate for overall accesses
2786system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19976.190476 # average UpgradeReq mshr miss latency
2787system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20000 # average UpgradeReq mshr miss latency
2788system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20000 # average UpgradeReq mshr miss latency
2789system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19900 # average UpgradeReq mshr miss latency
2790system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19970.588235 # average UpgradeReq mshr miss latency
2791system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73255.319149 # average ReadExReq mshr miss latency

2753system.l2c.overall_mshr_miss_rate::total 0.230894 # mshr miss rate for overall accesses
2754system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73260.638298 # average ReadExReq mshr miss latency

2792system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462 # average ReadExReq mshr miss latency
2793system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333 # average ReadExReq mshr miss latency

2755system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462 # average ReadExReq mshr miss latency
2756system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333 # average ReadExReq mshr miss latency

2794system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68125 # average ReadExReq mshr miss latency

2757system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68083.333333 # average ReadExReq mshr miss latency

2795system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588 # average ReadExReq mshr miss latency

2758system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588 # average ReadExReq mshr miss latency

2796system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average ReadCleanReq mshr miss latency
2797system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average ReadCleanReq mshr miss latency
2798system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average ReadCleanReq mshr miss latency
2799system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average ReadCleanReq mshr miss latency
2800system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67495.943205 # average ReadCleanReq mshr miss latency
2801system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70703.947368 # average ReadSharedReq mshr miss latency
2802system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70888.888889 # average ReadSharedReq mshr miss latency
2803system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73833.333333 # average ReadSharedReq mshr miss latency
2804system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 87500 # average ReadSharedReq mshr miss latency
2805system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71200 # average ReadSharedReq mshr miss latency
2806system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency
2807system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency
2808system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency
2809system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency
2810system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency
2811system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency
2812system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency
2813system.l2c.demand_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency
2814system.l2c.demand_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency
2815system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency
2816system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency
2817system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency
2818system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency
2819system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency
2820system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency
2821system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency
2822system.l2c.overall_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency
2823system.l2c.overall_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency
2824system.membus.snoop_filter.tot_requests 1042 # Total number of requests made to the snoop filter.
2825system.membus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data.

2759system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average ReadCleanReq mshr miss latency
2760system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average ReadCleanReq mshr miss latency
2761system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average ReadCleanReq mshr miss latency
2762system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76450 # average ReadCleanReq mshr miss latency
2763system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68337.755102 # average ReadCleanReq mshr miss latency
2764system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70519.736842 # average ReadSharedReq mshr miss latency
2765system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72312.500000 # average ReadSharedReq mshr miss latency
2766system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 78333.333333 # average ReadSharedReq mshr miss latency
2767system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80500 # average ReadSharedReq mshr miss latency
2768system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71168.539326 # average ReadSharedReq mshr miss latency
2769system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average overall mshr miss latency
2770system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72035.294118 # average overall mshr miss latency
2771system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average overall mshr miss latency
2772system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70857.142857 # average overall mshr miss latency
2773system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average overall mshr miss latency
2774system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70333.333333 # average overall mshr miss latency
2775system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76450 # average overall mshr miss latency
2776system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69857.142857 # average overall mshr miss latency
2777system.l2c.demand_avg_mshr_miss_latency::total 69369.718310 # average overall mshr miss latency
2778system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average overall mshr miss latency
2779system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72035.294118 # average overall mshr miss latency
2780system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average overall mshr miss latency
2781system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70857.142857 # average overall mshr miss latency
2782system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average overall mshr miss latency
2783system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70333.333333 # average overall mshr miss latency
2784system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76450 # average overall mshr miss latency
2785system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69857.142857 # average overall mshr miss latency
2786system.l2c.overall_avg_mshr_miss_latency::total 69369.718310 # average overall mshr miss latency
2787system.membus.snoop_filter.tot_requests 957 # Total number of requests made to the snoop filter.
2788system.membus.snoop_filter.hit_single_requests 248 # Number of requests hitting in the snoop filter with a single holder of the requested data.

2826system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2827system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2828system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2829system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2789system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2790system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2791system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2792system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2830system.membus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
2831system.membus.trans_dist::ReadResp 582 # Transaction distribution
2832system.membus.trans_dist::UpgradeReq 274 # Transaction distribution
2833system.membus.trans_dist::ReadExReq 186 # Transaction distribution

2793system.membus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
2794system.membus.trans_dist::ReadResp 578 # Transaction distribution
2795system.membus.trans_dist::UpgradeReq 196 # Transaction distribution
2796system.membus.trans_dist::ReadExReq 183 # Transaction distribution

2834system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2797system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2835system.membus.trans_dist::ReadSharedReq 582 # Transaction distribution
2836system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1755 # Packet count per connected master and slave (bytes)
2837system.membus.pkt_count::total 1755 # Packet count per connected master and slave (bytes)
2838system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45632 # Cumulative packet size per connected master and slave (bytes)
2839system.membus.pkt_size::total 45632 # Cumulative packet size per connected master and slave (bytes)
2840system.membus.snoops 244 # Total snoops (count)

2798system.membus.trans_dist::ReadSharedReq 578 # Transaction distribution
2799system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1666 # Packet count per connected master and slave (bytes)
2800system.membus.pkt_count::total 1666 # Packet count per connected master and slave (bytes)
2801system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45376 # Cumulative packet size per connected master and slave (bytes)
2802system.membus.pkt_size::total 45376 # Cumulative packet size per connected master and slave (bytes)
2803system.membus.snoops 248 # Total snoops (count)

2841system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

2804system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

2842system.membus.snoop_fanout::samples 1042 # Request fanout histogram

2805system.membus.snoop_fanout::samples 957 # Request fanout histogram

2843system.membus.snoop_fanout::mean 0 # Request fanout histogram
2844system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2845system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2806system.membus.snoop_fanout::mean 0 # Request fanout histogram
2807system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2808system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2846system.membus.snoop_fanout::0 1042 100.00% 100.00% # Request fanout histogram

2809system.membus.snoop_fanout::0 957 100.00% 100.00% # Request fanout histogram

2847system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2848system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2849system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2850system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2810system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2811system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2812system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2813system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2851system.membus.snoop_fanout::total 1042 # Request fanout histogram
2852system.membus.reqLayer0.occupancy 989502 # Layer occupancy (ticks)
2853system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
2854system.membus.respLayer1.occupancy 3800250 # Layer occupancy (ticks)
2855system.membus.respLayer1.utilization 3.1 # Layer utilization (%)
2856system.toL2Bus.snoop_filter.tot_requests 6343 # Total number of requests made to the snoop filter.
2857system.toL2Bus.snoop_filter.hit_single_requests 1724 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2858system.toL2Bus.snoop_filter.hit_multi_requests 3317 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

2814system.membus.snoop_fanout::total 957 # Request fanout histogram
2815system.membus.reqLayer0.occupancy 877500 # Layer occupancy (ticks)
2816system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
2817system.membus.respLayer1.occupancy 3778750 # Layer occupancy (ticks)
2818system.membus.respLayer1.utilization 3.0 # Layer utilization (%)
2819system.toL2Bus.snoop_filter.tot_requests 6322 # Total number of requests made to the snoop filter.
2820system.toL2Bus.snoop_filter.hit_single_requests 1727 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2821system.toL2Bus.snoop_filter.hit_multi_requests 3289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

2859system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2860system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2861system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2822system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2823system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2824system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

2862system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
2863system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution
2864system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution

2825system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
2826system.toL2Bus.trans_dist::ReadResp 3509 # Transaction distribution
2827system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution

2865system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution

2828system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution

2866system.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution

2829system.toL2Bus.trans_dist::WritebackClean 2125 # Transaction distribution

2867system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution

2830system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution

2868system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
2869system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
2870system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution
2871system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution
2872system.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution
2873system.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution
2874system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes)
2875system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes)
2876system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes)
2877system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes)
2878system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes)
2879system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
2880system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes)
2881system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
2882system.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes)
2883system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes)

2831system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution
2832system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution
2833system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution
2834system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution
2835system.toL2Bus.trans_dist::ReadCleanReq 2823 # Transaction distribution
2836system.toL2Bus.trans_dist::ReadSharedReq 690 # Transaction distribution
2837system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1838 # Packet count per connected master and slave (bytes)
2838system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes)
2839system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1930 # Packet count per connected master and slave (bytes)
2840system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
2841system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1998 # Packet count per connected master and slave (bytes)
2842system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 378 # Packet count per connected master and slave (bytes)
2843system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2004 # Packet count per connected master and slave (bytes)
2844system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
2845system.toL2Bus.pkt_count::total 9484 # Packet count per connected master and slave (bytes)
2846system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 72000 # Cumulative packet size per connected master and slave (bytes)

2884system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes)

2847system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes)

2885system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes)
2886system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes)
2887system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes)

2848system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79552 # Cumulative packet size per connected master and slave (bytes)
2849system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
2850system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82432 # Cumulative packet size per connected master and slave (bytes)

2888system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)

2851system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)

2889system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes)

2852system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82624 # Cumulative packet size per connected master and slave (bytes)

2890system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)

2853system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)

2891system.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes)
2892system.toL2Bus.snoops 1023 # Total snoops (count)
2893system.toL2Bus.snoopTraffic 53376 # Total snoop traffic (bytes)
2894system.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram
2895system.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram
2896system.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram

2854system.toL2Bus.pkt_size::total 332800 # Cumulative packet size per connected master and slave (bytes)
2855system.toL2Bus.snoops 1032 # Total snoops (count)
2856system.toL2Bus.snoopTraffic 53504 # Total snoop traffic (bytes)
2857system.toL2Bus.snoop_fanout::samples 4195 # Request fanout histogram
2858system.toL2Bus.snoop_fanout::mean 1.291538 # Request fanout histogram
2859system.toL2Bus.snoop_fanout::stdev 1.103863 # Request fanout histogram

2897system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2860system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2898system.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram
2899system.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram
2900system.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram
2901system.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram

2861system.toL2Bus.snoop_fanout::0 1306 31.13% 31.13% # Request fanout histogram
2862system.toL2Bus.snoop_fanout::1 1176 28.03% 59.17% # Request fanout histogram
2863system.toL2Bus.snoop_fanout::2 897 21.38% 80.55% # Request fanout histogram
2864system.toL2Bus.snoop_fanout::3 816 19.45% 100.00% # Request fanout histogram

2902system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2903system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
2904system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
2905system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2906system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2907system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2908system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2909system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

2865system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2866system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
2867system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
2868system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
2869system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2870system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2871system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2872system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

2910system.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram
2911system.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks)

2873system.toL2Bus.snoop_fanout::total 4195 # Request fanout histogram
2874system.toL2Bus.reqLayer0.occupancy 5296980 # Layer occupancy (ticks)

2912system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)

2875system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)

2913system.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks)
2914system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
2915system.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks)

2876system.toL2Bus.respLayer0.occupancy 1068997 # Layer occupancy (ticks)
2877system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
2878system.toL2Bus.respLayer1.occupancy 528987 # Layer occupancy (ticks)

2916system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

2879system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

2917system.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks)
2918system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%)
2919system.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks)

2880system.toL2Bus.respLayer2.occupancy 1032995 # Layer occupancy (ticks)
2881system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%)
2882system.toL2Bus.respLayer3.occupancy 438456 # Layer occupancy (ticks)

2920system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)

2883system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)

2921system.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks)

2884system.toL2Bus.respLayer4.occupancy 1069486 # Layer occupancy (ticks)

2922system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%)

2885system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%)

2923system.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks)
2924system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
2925system.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks)
2926system.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%)
2927system.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks)

2886system.toL2Bus.respLayer5.occupancy 439965 # Layer occupancy (ticks)
2887system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
2888system.toL2Bus.respLayer6.occupancy 1070997 # Layer occupancy (ticks)
2889system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%)
2890system.toL2Bus.respLayer7.occupancy 415480 # Layer occupancy (ticks)