| stats.txt (11456:c0fb4435b80f) | stats.txt (11502:e273e86a873d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000126 # Number of seconds simulated 4sim_ticks 125889000 # Number of ticks simulated 5final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 196054 # Simulator instruction rate (inst/s) 8host_op_rate 196054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21072637 # Simulator tick rate (ticks/s) 10host_mem_usage 267156 # Number of bytes of host memory used 11host_seconds 5.97 # Real time elapsed on the host 12sim_insts 1171234 # Number of instructions simulated 13sim_ops 1171234 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 1536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 896 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 5824 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1344 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 45696 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 1536 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 5824 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 31616 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 24 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 14 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 91 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 21 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 714 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 190644139 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 86425343 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 12201225 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7117381 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 46262978 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 10676072 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 2033537 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7625766 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 362986440 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 190644139 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 12201225 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 46262978 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 2033537 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 251141879 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 190644139 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 86425343 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 12201225 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7117381 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 46262978 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 10676072 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 2033537 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7625766 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 362986440 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 714 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 714 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 45696 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 45696 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 120 # Per bank write bursts 75system.physmem.perBankRdBursts::1 45 # Per bank write bursts 76system.physmem.perBankRdBursts::2 34 # Per bank write bursts 77system.physmem.perBankRdBursts::3 62 # Per bank write bursts 78system.physmem.perBankRdBursts::4 68 # Per bank write bursts 79system.physmem.perBankRdBursts::5 28 # Per bank write bursts 80system.physmem.perBankRdBursts::6 19 # Per bank write bursts 81system.physmem.perBankRdBursts::7 28 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 31 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts 85system.physmem.perBankRdBursts::11 13 # Per bank write bursts 86system.physmem.perBankRdBursts::12 69 # Per bank write bursts 87system.physmem.perBankRdBursts::13 47 # Per bank write bursts 88system.physmem.perBankRdBursts::14 19 # Per bank write bursts 89system.physmem.perBankRdBursts::15 101 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 108system.physmem.totGap 125655000 # Total gap between requests 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 714 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 431 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 209 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 219system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 245.392265 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 162.885057 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 238.848920 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 70 38.67% 38.67% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 41 22.65% 61.33% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 29 16.02% 77.35% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 15 8.29% 85.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 9 4.97% 90.61% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 7 3.87% 94.48% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 3 1.66% 96.13% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 2 1.10% 97.24% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 2.76% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation 233system.physmem.totQLat 8022250 # Total ticks spent queuing 234system.physmem.totMemAccLat 21409750 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3570000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 11235.64 # Average queueing delay per DRAM burst 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 238system.physmem.avgMemAccLat 29985.64 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 362.99 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 362.99 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 2.84 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.84 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 249system.physmem.readRowHits 529 # Number of row buffer hits during reads 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 74.09 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 253system.physmem.avgGap 175987.39 # Average gap between requests 254system.physmem.pageHitRate 74.09 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 914760 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 499125 # Energy for precharge commands per rank (pJ) 257system.physmem_0.readEnergy 3088800 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) 260system.physmem_0.actBackEnergy 61236810 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 21187500 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 95063955 # Total energy per rank (pJ) 263system.physmem_0.averagePower 761.486343 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 34878500 # Time in different power states 265system.physmem_0.memoryStateTime::REF 4160000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 85815250 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 453600 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 247500 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 2324400 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 43234785 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 36978750 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 91375995 # Total energy per rank (pJ) 277system.physmem_1.averagePower 731.944849 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 61171750 # Time in different power states 279system.physmem_1.memoryStateTime::REF 4160000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_1.memoryStateTime::ACT 59522000 # Time in different power states 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 283system.cpu0.branchPred.lookups 99978 # Number of BP lookups 284system.cpu0.branchPred.condPredicted 95393 # Number of conditional branches predicted 285system.cpu0.branchPred.condIncorrect 1592 # Number of conditional branches incorrect 286system.cpu0.branchPred.BTBLookups 97255 # Number of BTB lookups 287system.cpu0.branchPred.BTBHits 0 # Number of BTB hits 288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 289system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 290system.cpu0.branchPred.usedRAS 1133 # Number of times the RAS was used to get a target. 291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 292system.cpu0.branchPred.indirectLookups 97255 # Number of indirect predictor lookups. 293system.cpu0.branchPred.indirectHits 89772 # Number of indirect target hits. 294system.cpu0.branchPred.indirectMisses 7483 # Number of indirect misses. 295system.cpu0.branchPredindirectMispredicted 1066 # Number of mispredicted indirect branches. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu0.workload.num_syscalls 89 # Number of system calls 298system.cpu0.numCycles 251779 # number of cpu cycles simulated 299system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu0.fetch.icacheStallCycles 22796 # Number of cycles fetch is stalled on an Icache miss 302system.cpu0.fetch.Insts 589750 # Number of instructions fetch has processed 303system.cpu0.fetch.Branches 99978 # Number of branches that fetch encountered 304system.cpu0.fetch.predictedBranches 90905 # Number of branches that fetch has predicted taken 305system.cpu0.fetch.Cycles 197463 # Number of cycles fetch has run and was not squashing or blocked 306system.cpu0.fetch.SquashCycles 3483 # Number of cycles fetch has spent squashing 307system.cpu0.fetch.TlbCycles 64 # Number of cycles fetch has spent waiting for tlb 308system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu0.fetch.PendingTrapStallCycles 2183 # Number of stall cycles due to pending traps 310system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR 311system.cpu0.fetch.CacheLines 8051 # Number of cache lines fetched 312system.cpu0.fetch.IcacheSquashes 854 # Number of outstanding Icache misses that were squashed 313system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 314system.cpu0.fetch.rateDist::samples 224259 # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::mean 2.629772 # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::stdev 2.263592 # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::0 34588 15.42% 15.42% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::1 92788 41.38% 56.80% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::2 690 0.31% 57.11% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::3 1001 0.45% 57.55% # Number of instructions fetched each cycle (Total) 322system.cpu0.fetch.rateDist::4 509 0.23% 57.78% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::5 88318 39.38% 97.16% # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::6 733 0.33% 97.49% # Number of instructions fetched each cycle (Total) 325system.cpu0.fetch.rateDist::7 501 0.22% 97.71% # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.rateDist::8 5131 2.29% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 328system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 329system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 330system.cpu0.fetch.rateDist::total 224259 # Number of instructions fetched each cycle (Total) 331system.cpu0.fetch.branchRate 0.397086 # Number of branch fetches per cycle 332system.cpu0.fetch.rate 2.342332 # Number of inst fetches per cycle 333system.cpu0.decode.IdleCycles 17767 # Number of cycles decode is idle 334system.cpu0.decode.BlockedCycles 19916 # Number of cycles decode is blocked 335system.cpu0.decode.RunCycles 184006 # Number of cycles decode is running 336system.cpu0.decode.UnblockCycles 829 # Number of cycles decode is unblocking 337system.cpu0.decode.SquashCycles 1741 # Number of cycles decode is squashing 338system.cpu0.decode.DecodedInsts 571897 # Number of instructions handled by decode 339system.cpu0.rename.SquashCycles 1741 # Number of cycles rename is squashing 340system.cpu0.rename.IdleCycles 18447 # Number of cycles rename is idle 341system.cpu0.rename.BlockCycles 2370 # Number of cycles rename is blocking 342system.cpu0.rename.serializeStallCycles 16226 # count of cycles rename stalled for serializing inst 343system.cpu0.rename.RunCycles 184143 # Number of cycles rename is running 344system.cpu0.rename.UnblockCycles 1332 # Number of cycles rename is unblocking 345system.cpu0.rename.RenamedInsts 566816 # Number of instructions processed by rename 346system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 347system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full 348system.cpu0.rename.SQFullEvents 855 # Number of times rename has blocked due to SQ full 349system.cpu0.rename.RenamedOperands 387804 # Number of destination operands rename has renamed 350system.cpu0.rename.RenameLookups 1129387 # Number of register rename lookups that rename has made 351system.cpu0.rename.int_rename_lookups 853087 # Number of integer rename lookups 352system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups 353system.cpu0.rename.CommittedMaps 368443 # Number of HB maps that are committed 354system.cpu0.rename.UndoneMaps 19361 # Number of HB maps that are undone due to squashing 355system.cpu0.rename.serializingInsts 1077 # count of serializing insts renamed 356system.cpu0.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed 357system.cpu0.rename.skidInsts 5304 # count of insts added to the skid buffer 358system.cpu0.memDep0.insertedLoads 180818 # Number of loads inserted to the mem dependence unit. 359system.cpu0.memDep0.insertedStores 91318 # Number of stores inserted to the mem dependence unit. 360system.cpu0.memDep0.conflictingLoads 88191 # Number of conflicting loads. 361system.cpu0.memDep0.conflictingStores 87908 # Number of conflicting stores. 362system.cpu0.iq.iqInstsAdded 472586 # Number of instructions added to the IQ (excludes non-spec) 363system.cpu0.iq.iqNonSpecInstsAdded 1109 # Number of non-speculative instructions added to the IQ 364system.cpu0.iq.iqInstsIssued 468485 # Number of instructions issued 365system.cpu0.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued 366system.cpu0.iq.iqSquashedInstsExamined 16710 # Number of squashed instructions iterated over during squash; mainly for profiling 367system.cpu0.iq.iqSquashedOperandsExamined 13548 # Number of squashed operands that are examined and possibly removed from graph 368system.cpu0.iq.iqSquashedNonSpecRemoved 550 # Number of squashed non-spec instructions that were removed 369system.cpu0.iq.issued_per_cycle::samples 224259 # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::mean 2.089035 # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::stdev 1.110026 # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::0 37572 16.75% 16.75% # Number of insts issued each cycle 374system.cpu0.iq.issued_per_cycle::1 4453 1.99% 18.74% # Number of insts issued each cycle 375system.cpu0.iq.issued_per_cycle::2 89499 39.91% 58.65% # Number of insts issued each cycle 376system.cpu0.iq.issued_per_cycle::3 89119 39.74% 98.39% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::4 1731 0.77% 99.16% # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::5 984 0.44% 99.60% # Number of insts issued each cycle 379system.cpu0.iq.issued_per_cycle::6 574 0.26% 99.85% # Number of insts issued each cycle 380system.cpu0.iq.issued_per_cycle::7 227 0.10% 99.96% # Number of insts issued each cycle 381system.cpu0.iq.issued_per_cycle::8 100 0.04% 100.00% # Number of insts issued each cycle 382system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 383system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 384system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 385system.cpu0.iq.issued_per_cycle::total 224259 # Number of insts issued each cycle 386system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 387system.cpu0.iq.fu_full::IntAlu 140 42.68% 42.68% # attempts to use FU when none available 388system.cpu0.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available 389system.cpu0.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available 390system.cpu0.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available 391system.cpu0.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available 392system.cpu0.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available 393system.cpu0.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available 394system.cpu0.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available 395system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available 410system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available 411system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available 412system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available 413system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available 414system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available 415system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available 416system.cpu0.iq.fu_full::MemRead 69 21.04% 63.72% # attempts to use FU when none available 417system.cpu0.iq.fu_full::MemWrite 119 36.28% 100.00% # attempts to use FU when none available 418system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 419system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 421system.cpu0.iq.FU_type_0::IntAlu 197740 42.21% 42.21% # Type of FU issued 422system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.21% # Type of FU issued 423system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.21% # Type of FU issued 424system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.21% # Type of FU issued 425system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.21% # Type of FU issued 426system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.21% # Type of FU issued 427system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.21% # Type of FU issued 428system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.21% # Type of FU issued 429system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.21% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.21% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.21% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.21% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.21% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.21% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.21% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.21% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.21% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.21% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.21% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.21% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.21% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.21% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.21% # Type of FU issued 444system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.21% # Type of FU issued 445system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.21% # Type of FU issued 446system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.21% # Type of FU issued 447system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.21% # Type of FU issued 448system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.21% # Type of FU issued 449system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.21% # Type of FU issued 450system.cpu0.iq.FU_type_0::MemRead 180204 38.47% 80.67% # Type of FU issued 451system.cpu0.iq.FU_type_0::MemWrite 90541 19.33% 100.00% # Type of FU issued 452system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 453system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 454system.cpu0.iq.FU_type_0::total 468485 # Type of FU issued 455system.cpu0.iq.rate 1.860699 # Inst issue rate 456system.cpu0.iq.fu_busy_cnt 328 # FU busy when requested 457system.cpu0.iq.fu_busy_rate 0.000700 # FU busy rate (busy events/executed inst) 458system.cpu0.iq.int_inst_queue_reads 1161676 # Number of integer instruction queue reads 459system.cpu0.iq.int_inst_queue_writes 490453 # Number of integer instruction queue writes 460system.cpu0.iq.int_inst_queue_wakeup_accesses 465867 # Number of integer instruction queue wakeup accesses 461system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 462system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 463system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 464system.cpu0.iq.int_alu_accesses 468813 # Number of integer alu accesses 465system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 466system.cpu0.iew.lsq.thread0.forwLoads 87651 # Number of loads that had data forwarded from stores 467system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 468system.cpu0.iew.lsq.thread0.squashedLoads 3007 # Number of loads squashed 469system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 470system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 471system.cpu0.iew.lsq.thread0.squashedStores 1906 # Number of stores squashed 472system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 473system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 474system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 475system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked 476system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 477system.cpu0.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing 478system.cpu0.iew.iewBlockCycles 2371 # Number of cycles IEW is blocking 479system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking 480system.cpu0.iew.iewDispatchedInsts 562514 # Number of instructions dispatched to IQ 481system.cpu0.iew.iewDispSquashedInsts 182 # Number of squashed instructions skipped by dispatch 482system.cpu0.iew.iewDispLoadInsts 180818 # Number of dispatched load instructions 483system.cpu0.iew.iewDispStoreInsts 91318 # Number of dispatched store instructions 484system.cpu0.iew.iewDispNonSpecInsts 990 # Number of dispatched non-speculative instructions 485system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall 486system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 487system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 488system.cpu0.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly 489system.cpu0.iew.predictedNotTakenIncorrect 1703 # Number of branches that were predicted not taken incorrectly 490system.cpu0.iew.branchMispredicts 1939 # Number of branch mispredicts detected at execute 491system.cpu0.iew.iewExecutedInsts 466997 # Number of executed instructions 492system.cpu0.iew.iewExecLoadInsts 179835 # Number of load instructions executed 493system.cpu0.iew.iewExecSquashedInsts 1488 # Number of squashed instructions skipped in execute 494system.cpu0.iew.exec_swp 0 # number of swp insts executed 495system.cpu0.iew.exec_nop 88819 # number of nop insts executed 496system.cpu0.iew.exec_refs 270170 # number of memory reference insts executed 497system.cpu0.iew.exec_branches 92803 # Number of branches executed 498system.cpu0.iew.exec_stores 90335 # Number of stores executed 499system.cpu0.iew.exec_rate 1.854789 # Inst execution rate 500system.cpu0.iew.wb_sent 466340 # cumulative count of insts sent to commit 501system.cpu0.iew.wb_count 465867 # cumulative count of insts written-back 502system.cpu0.iew.wb_producers 276291 # num instructions producing a value 503system.cpu0.iew.wb_consumers 279830 # num instructions consuming a value 504system.cpu0.iew.wb_rate 1.850301 # insts written-back per cycle 505system.cpu0.iew.wb_fanout 0.987353 # average fanout of values written-back 506system.cpu0.commit.commitSquashedInsts 17414 # The number of squashed insts skipped by commit 507system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 508system.cpu0.commit.branchMispredicts 1592 # The number of times a branch was mispredicted 509system.cpu0.commit.committed_per_cycle::samples 220844 # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::mean 2.467878 # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::stdev 2.142709 # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::0 37532 16.99% 16.99% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::1 91545 41.45% 58.45% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::2 2011 0.91% 59.36% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::3 623 0.28% 59.64% # Number of insts commited each cycle 517system.cpu0.commit.committed_per_cycle::4 506 0.23% 59.87% # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::5 87423 39.59% 99.45% # Number of insts commited each cycle 519system.cpu0.commit.committed_per_cycle::6 455 0.21% 99.66% # Number of insts commited each cycle 520system.cpu0.commit.committed_per_cycle::7 281 0.13% 99.79% # Number of insts commited each cycle 521system.cpu0.commit.committed_per_cycle::8 468 0.21% 100.00% # Number of insts commited each cycle 522system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 525system.cpu0.commit.committed_per_cycle::total 220844 # Number of insts commited each cycle 526system.cpu0.commit.committedInsts 545016 # Number of instructions committed 527system.cpu0.commit.committedOps 545016 # Number of ops (including micro ops) committed 528system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu0.commit.refs 267223 # Number of memory references committed 530system.cpu0.commit.loads 177811 # Number of loads committed 531system.cpu0.commit.membars 84 # Number of memory barriers committed 532system.cpu0.commit.branches 91299 # Number of branches committed 533system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 534system.cpu0.commit.int_insts 366774 # Number of committed integer instructions. 535system.cpu0.commit.function_calls 223 # Number of function calls committed. 536system.cpu0.commit.op_class_0::No_OpClass 88031 16.15% 16.15% # Class of committed instruction 537system.cpu0.commit.op_class_0::IntAlu 189678 34.80% 50.95% # Class of committed instruction 538system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.95% # Class of committed instruction 539system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.95% # Class of committed instruction 540system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.95% # Class of committed instruction 541system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.95% # Class of committed instruction 542system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.95% # Class of committed instruction 543system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.95% # Class of committed instruction 544system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.95% # Class of committed instruction 545system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.95% # Class of committed instruction 546system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.95% # Class of committed instruction 547system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.95% # Class of committed instruction 548system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.95% # Class of committed instruction 549system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.95% # Class of committed instruction 550system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.95% # Class of committed instruction 551system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.95% # Class of committed instruction 552system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.95% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.95% # Class of committed instruction 554system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.95% # Class of committed instruction 555system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.95% # Class of committed instruction 556system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.95% # Class of committed instruction 557system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.95% # Class of committed instruction 558system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.95% # Class of committed instruction 559system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.95% # Class of committed instruction 560system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.95% # Class of committed instruction 561system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.95% # Class of committed instruction 562system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.95% # Class of committed instruction 563system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.95% # Class of committed instruction 564system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.95% # Class of committed instruction 565system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.95% # Class of committed instruction 566system.cpu0.commit.op_class_0::MemRead 177895 32.64% 83.59% # Class of committed instruction 567system.cpu0.commit.op_class_0::MemWrite 89412 16.41% 100.00% # Class of committed instruction 568system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 569system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 570system.cpu0.commit.op_class_0::total 545016 # Class of committed instruction 571system.cpu0.commit.bw_lim_events 468 # number cycles where commit BW limit reached 572system.cpu0.rob.rob_reads 781645 # The number of ROB reads 573system.cpu0.rob.rob_writes 1128336 # The number of ROB writes 574system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself 575system.cpu0.idleCycles 27520 # Total number of cycles that the CPU has spent unscheduled due to idling 576system.cpu0.committedInsts 456901 # Number of Instructions Simulated 577system.cpu0.committedOps 456901 # Number of Ops (including micro ops) Simulated 578system.cpu0.cpi 0.551058 # CPI: Cycles Per Instruction 579system.cpu0.cpi_total 0.551058 # CPI: Total CPI of All Threads 580system.cpu0.ipc 1.814691 # IPC: Instructions Per Cycle 581system.cpu0.ipc_total 1.814691 # IPC: Total IPC of All Threads 582system.cpu0.int_regfile_reads 834795 # number of integer regfile reads 583system.cpu0.int_regfile_writes 376287 # number of integer regfile writes 584system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 585system.cpu0.misc_regfile_reads 272308 # number of misc regfile reads 586system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 587system.cpu0.dcache.tags.replacements 2 # number of replacements 588system.cpu0.dcache.tags.tagsinuse 143.015419 # Cycle average of tags in use 589system.cpu0.dcache.tags.total_refs 180238 # Total number of references to valid blocks. 590system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. 591system.cpu0.dcache.tags.avg_refs 1047.895349 # Average number of references to valid blocks. 592system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 593system.cpu0.dcache.tags.occ_blocks::cpu0.data 143.015419 # Average occupied blocks per requestor 594system.cpu0.dcache.tags.occ_percent::cpu0.data 0.279327 # Average percentage of cache occupancy 595system.cpu0.dcache.tags.occ_percent::total 0.279327 # Average percentage of cache occupancy 596system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id 597system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 598system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 599system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id 600system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id 601system.cpu0.dcache.tags.tag_accesses 726286 # Number of tag accesses 602system.cpu0.dcache.tags.data_accesses 726286 # Number of data accesses 603system.cpu0.dcache.ReadReq_hits::cpu0.data 91504 # number of ReadReq hits 604system.cpu0.dcache.ReadReq_hits::total 91504 # number of ReadReq hits 605system.cpu0.dcache.WriteReq_hits::cpu0.data 88818 # number of WriteReq hits 606system.cpu0.dcache.WriteReq_hits::total 88818 # number of WriteReq hits 607system.cpu0.dcache.SwapReq_hits::cpu0.data 19 # number of SwapReq hits 608system.cpu0.dcache.SwapReq_hits::total 19 # number of SwapReq hits 609system.cpu0.dcache.demand_hits::cpu0.data 180322 # number of demand (read+write) hits 610system.cpu0.dcache.demand_hits::total 180322 # number of demand (read+write) hits 611system.cpu0.dcache.overall_hits::cpu0.data 180322 # number of overall hits 612system.cpu0.dcache.overall_hits::total 180322 # number of overall hits 613system.cpu0.dcache.ReadReq_misses::cpu0.data 576 # number of ReadReq misses 614system.cpu0.dcache.ReadReq_misses::total 576 # number of ReadReq misses 615system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses 616system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses 617system.cpu0.dcache.SwapReq_misses::cpu0.data 23 # number of SwapReq misses 618system.cpu0.dcache.SwapReq_misses::total 23 # number of SwapReq misses 619system.cpu0.dcache.demand_misses::cpu0.data 1128 # number of demand (read+write) misses 620system.cpu0.dcache.demand_misses::total 1128 # number of demand (read+write) misses 621system.cpu0.dcache.overall_misses::cpu0.data 1128 # number of overall misses 622system.cpu0.dcache.overall_misses::total 1128 # number of overall misses 623system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18232000 # number of ReadReq miss cycles 624system.cpu0.dcache.ReadReq_miss_latency::total 18232000 # number of ReadReq miss cycles 625system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36205990 # number of WriteReq miss cycles 626system.cpu0.dcache.WriteReq_miss_latency::total 36205990 # number of WriteReq miss cycles 627system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 589500 # number of SwapReq miss cycles 628system.cpu0.dcache.SwapReq_miss_latency::total 589500 # number of SwapReq miss cycles 629system.cpu0.dcache.demand_miss_latency::cpu0.data 54437990 # number of demand (read+write) miss cycles 630system.cpu0.dcache.demand_miss_latency::total 54437990 # number of demand (read+write) miss cycles 631system.cpu0.dcache.overall_miss_latency::cpu0.data 54437990 # number of overall miss cycles 632system.cpu0.dcache.overall_miss_latency::total 54437990 # number of overall miss cycles 633system.cpu0.dcache.ReadReq_accesses::cpu0.data 92080 # number of ReadReq accesses(hits+misses) 634system.cpu0.dcache.ReadReq_accesses::total 92080 # number of ReadReq accesses(hits+misses) 635system.cpu0.dcache.WriteReq_accesses::cpu0.data 89370 # number of WriteReq accesses(hits+misses) 636system.cpu0.dcache.WriteReq_accesses::total 89370 # number of WriteReq accesses(hits+misses) 637system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 638system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 639system.cpu0.dcache.demand_accesses::cpu0.data 181450 # number of demand (read+write) accesses 640system.cpu0.dcache.demand_accesses::total 181450 # number of demand (read+write) accesses 641system.cpu0.dcache.overall_accesses::cpu0.data 181450 # number of overall (read+write) accesses 642system.cpu0.dcache.overall_accesses::total 181450 # number of overall (read+write) accesses 643system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006255 # miss rate for ReadReq accesses 644system.cpu0.dcache.ReadReq_miss_rate::total 0.006255 # miss rate for ReadReq accesses 645system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006177 # miss rate for WriteReq accesses 646system.cpu0.dcache.WriteReq_miss_rate::total 0.006177 # miss rate for WriteReq accesses 647system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.547619 # miss rate for SwapReq accesses 648system.cpu0.dcache.SwapReq_miss_rate::total 0.547619 # miss rate for SwapReq accesses 649system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006217 # miss rate for demand accesses 650system.cpu0.dcache.demand_miss_rate::total 0.006217 # miss rate for demand accesses 651system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006217 # miss rate for overall accesses 652system.cpu0.dcache.overall_miss_rate::total 0.006217 # miss rate for overall accesses 653system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31652.777778 # average ReadReq miss latency 654system.cpu0.dcache.ReadReq_avg_miss_latency::total 31652.777778 # average ReadReq miss latency 655system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65590.561594 # average WriteReq miss latency 656system.cpu0.dcache.WriteReq_avg_miss_latency::total 65590.561594 # average WriteReq miss latency 657system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 25630.434783 # average SwapReq miss latency 658system.cpu0.dcache.SwapReq_avg_miss_latency::total 25630.434783 # average SwapReq miss latency 659system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency 660system.cpu0.dcache.demand_avg_miss_latency::total 48260.629433 # average overall miss latency 661system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency 662system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433 # average overall miss latency 663system.cpu0.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked 664system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked 666system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked 668system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 670system.cpu0.dcache.writebacks::total 1 # number of writebacks 671system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits 672system.cpu0.dcache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits 673system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 386 # number of WriteReq MSHR hits 674system.cpu0.dcache.WriteReq_mshr_hits::total 386 # number of WriteReq MSHR hits 675system.cpu0.dcache.demand_mshr_hits::cpu0.data 766 # number of demand (read+write) MSHR hits 676system.cpu0.dcache.demand_mshr_hits::total 766 # number of demand (read+write) MSHR hits 677system.cpu0.dcache.overall_mshr_hits::cpu0.data 766 # number of overall MSHR hits 678system.cpu0.dcache.overall_mshr_hits::total 766 # number of overall MSHR hits 679system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 196 # number of ReadReq MSHR misses 680system.cpu0.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses 681system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses 682system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses 683system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 23 # number of SwapReq MSHR misses 684system.cpu0.dcache.SwapReq_mshr_misses::total 23 # number of SwapReq MSHR misses 685system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses 686system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses 687system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 688system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses 689system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7598500 # number of ReadReq MSHR miss cycles 690system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7598500 # number of ReadReq MSHR miss cycles 691system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8576000 # number of WriteReq MSHR miss cycles 692system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8576000 # number of WriteReq MSHR miss cycles 693system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 566500 # number of SwapReq MSHR miss cycles 694system.cpu0.dcache.SwapReq_mshr_miss_latency::total 566500 # number of SwapReq MSHR miss cycles 695system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 16174500 # number of demand (read+write) MSHR miss cycles 696system.cpu0.dcache.demand_mshr_miss_latency::total 16174500 # number of demand (read+write) MSHR miss cycles 697system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 16174500 # number of overall MSHR miss cycles 698system.cpu0.dcache.overall_mshr_miss_latency::total 16174500 # number of overall MSHR miss cycles 699system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002129 # mshr miss rate for ReadReq accesses 700system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002129 # mshr miss rate for ReadReq accesses 701system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001857 # mshr miss rate for WriteReq accesses 702system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001857 # mshr miss rate for WriteReq accesses 703system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.547619 # mshr miss rate for SwapReq accesses 704system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.547619 # mshr miss rate for SwapReq accesses 705system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for demand accesses 706system.cpu0.dcache.demand_mshr_miss_rate::total 0.001995 # mshr miss rate for demand accesses 707system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for overall accesses 708system.cpu0.dcache.overall_mshr_miss_rate::total 0.001995 # mshr miss rate for overall accesses 709system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38767.857143 # average ReadReq mshr miss latency 710system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38767.857143 # average ReadReq mshr miss latency 711system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602 # average WriteReq mshr miss latency 712system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602 # average WriteReq mshr miss latency 713system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783 # average SwapReq mshr miss latency 714system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783 # average SwapReq mshr miss latency 715system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 716system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency 717system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 718system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency 719system.cpu0.icache.tags.replacements 403 # number of replacements 720system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use 721system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. 722system.cpu0.icache.tags.sampled_refs 705 # Sample count of references to valid blocks. 723system.cpu0.icache.tags.avg_refs 10.113475 # Average number of references to valid blocks. 724system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 725system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.059263 # Average occupied blocks per requestor 726system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490350 # Average percentage of cache occupancy 727system.cpu0.icache.tags.occ_percent::total 0.490350 # Average percentage of cache occupancy 728system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id 729system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 730system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 731system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id 732system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id 733system.cpu0.icache.tags.tag_accesses 8756 # Number of tag accesses 734system.cpu0.icache.tags.data_accesses 8756 # Number of data accesses 735system.cpu0.icache.ReadReq_hits::cpu0.inst 7130 # number of ReadReq hits 736system.cpu0.icache.ReadReq_hits::total 7130 # number of ReadReq hits 737system.cpu0.icache.demand_hits::cpu0.inst 7130 # number of demand (read+write) hits 738system.cpu0.icache.demand_hits::total 7130 # number of demand (read+write) hits 739system.cpu0.icache.overall_hits::cpu0.inst 7130 # number of overall hits 740system.cpu0.icache.overall_hits::total 7130 # number of overall hits 741system.cpu0.icache.ReadReq_misses::cpu0.inst 921 # number of ReadReq misses 742system.cpu0.icache.ReadReq_misses::total 921 # number of ReadReq misses 743system.cpu0.icache.demand_misses::cpu0.inst 921 # number of demand (read+write) misses 744system.cpu0.icache.demand_misses::total 921 # number of demand (read+write) misses 745system.cpu0.icache.overall_misses::cpu0.inst 921 # number of overall misses 746system.cpu0.icache.overall_misses::total 921 # number of overall misses 747system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43922000 # number of ReadReq miss cycles 748system.cpu0.icache.ReadReq_miss_latency::total 43922000 # number of ReadReq miss cycles 749system.cpu0.icache.demand_miss_latency::cpu0.inst 43922000 # number of demand (read+write) miss cycles 750system.cpu0.icache.demand_miss_latency::total 43922000 # number of demand (read+write) miss cycles 751system.cpu0.icache.overall_miss_latency::cpu0.inst 43922000 # number of overall miss cycles 752system.cpu0.icache.overall_miss_latency::total 43922000 # number of overall miss cycles 753system.cpu0.icache.ReadReq_accesses::cpu0.inst 8051 # number of ReadReq accesses(hits+misses) 754system.cpu0.icache.ReadReq_accesses::total 8051 # number of ReadReq accesses(hits+misses) 755system.cpu0.icache.demand_accesses::cpu0.inst 8051 # number of demand (read+write) accesses 756system.cpu0.icache.demand_accesses::total 8051 # number of demand (read+write) accesses 757system.cpu0.icache.overall_accesses::cpu0.inst 8051 # number of overall (read+write) accesses 758system.cpu0.icache.overall_accesses::total 8051 # number of overall (read+write) accesses 759system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114396 # miss rate for ReadReq accesses 760system.cpu0.icache.ReadReq_miss_rate::total 0.114396 # miss rate for ReadReq accesses 761system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114396 # miss rate for demand accesses 762system.cpu0.icache.demand_miss_rate::total 0.114396 # miss rate for demand accesses 763system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114396 # miss rate for overall accesses 764system.cpu0.icache.overall_miss_rate::total 0.114396 # miss rate for overall accesses 765system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47689.467970 # average ReadReq miss latency 766system.cpu0.icache.ReadReq_avg_miss_latency::total 47689.467970 # average ReadReq miss latency 767system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency 768system.cpu0.icache.demand_avg_miss_latency::total 47689.467970 # average overall miss latency 769system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency 770system.cpu0.icache.overall_avg_miss_latency::total 47689.467970 # average overall miss latency 771system.cpu0.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked 772system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked 774system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 775system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked 776system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 777system.cpu0.icache.writebacks::writebacks 403 # number of writebacks 778system.cpu0.icache.writebacks::total 403 # number of writebacks 779system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits 780system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 781system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits 782system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 783system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits 784system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits 785system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 706 # number of ReadReq MSHR misses 786system.cpu0.icache.ReadReq_mshr_misses::total 706 # number of ReadReq MSHR misses 787system.cpu0.icache.demand_mshr_misses::cpu0.inst 706 # number of demand (read+write) MSHR misses 788system.cpu0.icache.demand_mshr_misses::total 706 # number of demand (read+write) MSHR misses 789system.cpu0.icache.overall_mshr_misses::cpu0.inst 706 # number of overall MSHR misses 790system.cpu0.icache.overall_mshr_misses::total 706 # number of overall MSHR misses 791system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33748500 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.ReadReq_mshr_miss_latency::total 33748500 # number of ReadReq MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33748500 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.demand_mshr_miss_latency::total 33748500 # number of demand (read+write) MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33748500 # number of overall MSHR miss cycles 796system.cpu0.icache.overall_mshr_miss_latency::total 33748500 # number of overall MSHR miss cycles 797system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for ReadReq accesses 798system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087691 # mshr miss rate for ReadReq accesses 799system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for demand accesses 800system.cpu0.icache.demand_mshr_miss_rate::total 0.087691 # mshr miss rate for demand accesses 801system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for overall accesses 802system.cpu0.icache.overall_mshr_miss_rate::total 0.087691 # mshr miss rate for overall accesses 803system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average ReadReq mshr miss latency 804system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932 # average ReadReq mshr miss latency 805system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 806system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency 807system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 808system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency 809system.cpu1.branchPred.lookups 75929 # Number of BP lookups 810system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted 811system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect 812system.cpu1.branchPred.BTBLookups 68395 # Number of BTB lookups 813system.cpu1.branchPred.BTBHits 0 # Number of BTB hits 814system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 815system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 816system.cpu1.branchPred.usedRAS 1839 # Number of times the RAS was used to get a target. 817system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 818system.cpu1.branchPred.indirectLookups 68395 # Number of indirect predictor lookups. 819system.cpu1.branchPred.indirectHits 58396 # Number of indirect target hits. 820system.cpu1.branchPred.indirectMisses 9999 # Number of indirect misses. 821system.cpu1.branchPredindirectMispredicted 1194 # Number of mispredicted indirect branches. 822system.cpu1.numCycles 196540 # number of cpu cycles simulated 823system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 824system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 825system.cpu1.fetch.icacheStallCycles 32617 # Number of cycles fetch is stalled on an Icache miss 826system.cpu1.fetch.Insts 424540 # Number of instructions fetch has processed 827system.cpu1.fetch.Branches 75929 # Number of branches that fetch encountered 828system.cpu1.fetch.predictedBranches 60235 # Number of branches that fetch has predicted taken 829system.cpu1.fetch.Cycles 157282 # Number of cycles fetch has run and was not squashing or blocked 830system.cpu1.fetch.SquashCycles 4599 # Number of cycles fetch has spent squashing 831system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 832system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 833system.cpu1.fetch.PendingTrapStallCycles 1756 # Number of stall cycles due to pending traps 834system.cpu1.fetch.CacheLines 22091 # Number of cache lines fetched 835system.cpu1.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed 836system.cpu1.fetch.rateDist::samples 193967 # Number of instructions fetched each cycle (Total) 837system.cpu1.fetch.rateDist::mean 2.188723 # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::stdev 2.372433 # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::0 56525 29.14% 29.14% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::1 66630 34.35% 63.49% # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::2 5516 2.84% 66.34% # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::3 3688 1.90% 68.24% # Number of instructions fetched each cycle (Total) 844system.cpu1.fetch.rateDist::4 688 0.35% 68.59% # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::5 50225 25.89% 94.49% # Number of instructions fetched each cycle (Total) 846system.cpu1.fetch.rateDist::6 1136 0.59% 95.07% # Number of instructions fetched each cycle (Total) 847system.cpu1.fetch.rateDist::7 1351 0.70% 95.77% # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.rateDist::8 8208 4.23% 100.00% # Number of instructions fetched each cycle (Total) 849system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 850system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 851system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 852system.cpu1.fetch.rateDist::total 193967 # Number of instructions fetched each cycle (Total) 853system.cpu1.fetch.branchRate 0.386328 # Number of branch fetches per cycle 854system.cpu1.fetch.rate 2.160069 # Number of inst fetches per cycle 855system.cpu1.decode.IdleCycles 20990 # Number of cycles decode is idle 856system.cpu1.decode.BlockedCycles 50963 # Number of cycles decode is blocked 857system.cpu1.decode.RunCycles 116406 # Number of cycles decode is running 858system.cpu1.decode.UnblockCycles 3299 # Number of cycles decode is unblocking 859system.cpu1.decode.SquashCycles 2299 # Number of cycles decode is squashing 860system.cpu1.decode.DecodedInsts 394135 # Number of instructions handled by decode 861system.cpu1.rename.SquashCycles 2299 # Number of cycles rename is squashing 862system.cpu1.rename.IdleCycles 22042 # Number of cycles rename is idle 863system.cpu1.rename.BlockCycles 22361 # Number of cycles rename is blocking 864system.cpu1.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst 865system.cpu1.rename.RunCycles 117990 # Number of cycles rename is running 866system.cpu1.rename.UnblockCycles 14649 # Number of cycles rename is unblocking 867system.cpu1.rename.RenamedInsts 387817 # Number of instructions processed by rename 868system.cpu1.rename.IQFullEvents 13215 # Number of times rename has blocked due to IQ full 869system.cpu1.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full 870system.cpu1.rename.RenamedOperands 272713 # Number of destination operands rename has renamed 871system.cpu1.rename.RenameLookups 753683 # Number of register rename lookups that rename has made 872system.cpu1.rename.int_rename_lookups 582463 # Number of integer rename lookups 873system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups 874system.cpu1.rename.CommittedMaps 245854 # Number of HB maps that are committed 875system.cpu1.rename.UndoneMaps 26859 # Number of HB maps that are undone due to squashing 876system.cpu1.rename.serializingInsts 1602 # count of serializing insts renamed 877system.cpu1.rename.tempSerializingInsts 1739 # count of temporary serializing insts renamed 878system.cpu1.rename.skidInsts 20098 # count of insts added to the skid buffer 879system.cpu1.memDep0.insertedLoads 111716 # Number of loads inserted to the mem dependence unit. 880system.cpu1.memDep0.insertedStores 54519 # Number of stores inserted to the mem dependence unit. 881system.cpu1.memDep0.conflictingLoads 52739 # Number of conflicting loads. 882system.cpu1.memDep0.conflictingStores 48254 # Number of conflicting stores. 883system.cpu1.iq.iqInstsAdded 321016 # Number of instructions added to the IQ (excludes non-spec) 884system.cpu1.iq.iqNonSpecInstsAdded 5993 # Number of non-speculative instructions added to the IQ 885system.cpu1.iq.iqInstsIssued 319557 # Number of instructions issued 886system.cpu1.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 887system.cpu1.iq.iqSquashedInstsExamined 23622 # Number of squashed instructions iterated over during squash; mainly for profiling 888system.cpu1.iq.iqSquashedOperandsExamined 18296 # Number of squashed operands that are examined and possibly removed from graph 889system.cpu1.iq.iqSquashedNonSpecRemoved 1159 # Number of squashed non-spec instructions that were removed 890system.cpu1.iq.issued_per_cycle::samples 193967 # Number of insts issued each cycle 891system.cpu1.iq.issued_per_cycle::mean 1.647481 # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::stdev 1.362491 # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::0 60994 31.45% 31.45% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::1 19742 10.18% 41.62% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::2 53241 27.45% 69.07% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::3 52847 27.25% 96.32% # Number of insts issued each cycle 898system.cpu1.iq.issued_per_cycle::4 3638 1.88% 98.19% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::5 1763 0.91% 99.10% # Number of insts issued each cycle 900system.cpu1.iq.issued_per_cycle::6 1052 0.54% 99.64% # Number of insts issued each cycle 901system.cpu1.iq.issued_per_cycle::7 407 0.21% 99.85% # Number of insts issued each cycle 902system.cpu1.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle 903system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 904system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 905system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 906system.cpu1.iq.issued_per_cycle::total 193967 # Number of insts issued each cycle 907system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 908system.cpu1.iq.fu_full::IntAlu 169 37.31% 37.31% # attempts to use FU when none available 909system.cpu1.iq.fu_full::IntMult 0 0.00% 37.31% # attempts to use FU when none available 910system.cpu1.iq.fu_full::IntDiv 0 0.00% 37.31% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatAdd 0 0.00% 37.31% # attempts to use FU when none available 912system.cpu1.iq.fu_full::FloatCmp 0 0.00% 37.31% # attempts to use FU when none available 913system.cpu1.iq.fu_full::FloatCvt 0 0.00% 37.31% # attempts to use FU when none available 914system.cpu1.iq.fu_full::FloatMult 0 0.00% 37.31% # attempts to use FU when none available 915system.cpu1.iq.fu_full::FloatDiv 0 0.00% 37.31% # attempts to use FU when none available 916system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 37.31% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdAdd 0 0.00% 37.31% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 37.31% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdAlu 0 0.00% 37.31% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdCmp 0 0.00% 37.31% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdCvt 0 0.00% 37.31% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdMisc 0 0.00% 37.31% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdMult 0 0.00% 37.31% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 37.31% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdShift 0 0.00% 37.31% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 37.31% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 37.31% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 37.31% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 37.31% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 37.31% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 37.31% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 37.31% # attempts to use FU when none available 933system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 37.31% # attempts to use FU when none available 934system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 37.31% # attempts to use FU when none available 935system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.31% # attempts to use FU when none available 936system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 37.31% # attempts to use FU when none available 937system.cpu1.iq.fu_full::MemRead 58 12.80% 50.11% # attempts to use FU when none available 938system.cpu1.iq.fu_full::MemWrite 226 49.89% 100.00% # attempts to use FU when none available 939system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 940system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 941system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 942system.cpu1.iq.FU_type_0::IntAlu 151236 47.33% 47.33% # Type of FU issued 943system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.33% # Type of FU issued 944system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued 946system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued 947system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued 948system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued 949system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued 950system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.33% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.33% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.33% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued 967system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.33% # Type of FU issued 968system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued 969system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued 970system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued 971system.cpu1.iq.FU_type_0::MemRead 114807 35.93% 83.25% # Type of FU issued 972system.cpu1.iq.FU_type_0::MemWrite 53514 16.75% 100.00% # Type of FU issued 973system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 974system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 975system.cpu1.iq.FU_type_0::total 319557 # Type of FU issued 976system.cpu1.iq.rate 1.625913 # Inst issue rate 977system.cpu1.iq.fu_busy_cnt 453 # FU busy when requested 978system.cpu1.iq.fu_busy_rate 0.001418 # FU busy rate (busy events/executed inst) 979system.cpu1.iq.int_inst_queue_reads 833588 # Number of integer instruction queue reads 980system.cpu1.iq.int_inst_queue_writes 350606 # Number of integer instruction queue writes 981system.cpu1.iq.int_inst_queue_wakeup_accesses 315974 # Number of integer instruction queue wakeup accesses 982system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 983system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes 984system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 985system.cpu1.iq.int_alu_accesses 320010 # Number of integer alu accesses 986system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 987system.cpu1.iew.lsq.thread0.forwLoads 48132 # Number of loads that had data forwarded from stores 988system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 989system.cpu1.iew.lsq.thread0.squashedLoads 4290 # Number of loads squashed 990system.cpu1.iew.lsq.thread0.ignoredResponses 32 # Number of memory responses ignored because the instruction is squashed 991system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations 992system.cpu1.iew.lsq.thread0.squashedStores 2608 # Number of stores squashed 993system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 994system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 995system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 996system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 997system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 998system.cpu1.iew.iewSquashCycles 2299 # Number of cycles IEW is squashing 999system.cpu1.iew.iewBlockCycles 7227 # Number of cycles IEW is blocking 1000system.cpu1.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking 1001system.cpu1.iew.iewDispatchedInsts 380950 # Number of instructions dispatched to IQ 1002system.cpu1.iew.iewDispSquashedInsts 338 # Number of squashed instructions skipped by dispatch 1003system.cpu1.iew.iewDispLoadInsts 111716 # Number of dispatched load instructions 1004system.cpu1.iew.iewDispStoreInsts 54519 # Number of dispatched store instructions 1005system.cpu1.iew.iewDispNonSpecInsts 1500 # Number of dispatched non-speculative instructions 1006system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 1007system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1008system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations 1009system.cpu1.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly 1010system.cpu1.iew.predictedNotTakenIncorrect 2382 # Number of branches that were predicted not taken incorrectly 1011system.cpu1.iew.branchMispredicts 2811 # Number of branch mispredicts detected at execute 1012system.cpu1.iew.iewExecutedInsts 317250 # Number of executed instructions 1013system.cpu1.iew.iewExecLoadInsts 110168 # Number of load instructions executed 1014system.cpu1.iew.iewExecSquashedInsts 2307 # Number of squashed instructions skipped in execute 1015system.cpu1.iew.exec_swp 0 # number of swp insts executed 1016system.cpu1.iew.exec_nop 53941 # number of nop insts executed 1017system.cpu1.iew.exec_refs 163396 # number of memory reference insts executed 1018system.cpu1.iew.exec_branches 64160 # Number of branches executed 1019system.cpu1.iew.exec_stores 53228 # Number of stores executed 1020system.cpu1.iew.exec_rate 1.614175 # Inst execution rate 1021system.cpu1.iew.wb_sent 316458 # cumulative count of insts sent to commit 1022system.cpu1.iew.wb_count 315974 # cumulative count of insts written-back 1023system.cpu1.iew.wb_producers 181395 # num instructions producing a value 1024system.cpu1.iew.wb_consumers 189019 # num instructions consuming a value 1025system.cpu1.iew.wb_rate 1.607683 # insts written-back per cycle 1026system.cpu1.iew.wb_fanout 0.959665 # average fanout of values written-back 1027system.cpu1.commit.commitSquashedInsts 24733 # The number of squashed insts skipped by commit 1028system.cpu1.commit.commitNonSpecStalls 4834 # The number of times commit has been forced to stall to communicate backwards 1029system.cpu1.commit.branchMispredicts 2222 # The number of times a branch was mispredicted 1030system.cpu1.commit.committed_per_cycle::samples 189334 # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::mean 1.881189 # Number of insts commited each cycle 1032system.cpu1.commit.committed_per_cycle::stdev 2.115429 # Number of insts commited each cycle 1033system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::0 65341 34.51% 34.51% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::1 60499 31.95% 66.46% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::2 5361 2.83% 69.30% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::3 5469 2.89% 72.18% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::4 1297 0.69% 72.87% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::5 48347 25.54% 98.40% # Number of insts commited each cycle 1040system.cpu1.commit.committed_per_cycle::6 750 0.40% 98.80% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::7 1038 0.55% 99.35% # Number of insts commited each cycle 1042system.cpu1.commit.committed_per_cycle::8 1232 0.65% 100.00% # Number of insts commited each cycle 1043system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1044system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1045system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1046system.cpu1.commit.committed_per_cycle::total 189334 # Number of insts commited each cycle 1047system.cpu1.commit.committedInsts 356173 # Number of instructions committed 1048system.cpu1.commit.committedOps 356173 # Number of ops (including micro ops) committed 1049system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1050system.cpu1.commit.refs 159337 # Number of memory references committed 1051system.cpu1.commit.loads 107426 # Number of loads committed 1052system.cpu1.commit.membars 4118 # Number of memory barriers committed 1053system.cpu1.commit.branches 61998 # Number of branches committed 1054system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1055system.cpu1.commit.int_insts 243452 # Number of committed integer instructions. 1056system.cpu1.commit.function_calls 322 # Number of function calls committed. 1057system.cpu1.commit.op_class_0::No_OpClass 52786 14.82% 14.82% # Class of committed instruction 1058system.cpu1.commit.op_class_0::IntAlu 139932 39.29% 54.11% # Class of committed instruction 1059system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.11% # Class of committed instruction 1060system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.11% # Class of committed instruction 1061system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.11% # Class of committed instruction 1062system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.11% # Class of committed instruction 1063system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.11% # Class of committed instruction 1064system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.11% # Class of committed instruction 1065system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.11% # Class of committed instruction 1066system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.11% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.11% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.11% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.11% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.11% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.11% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.11% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.11% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.11% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.11% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.11% # Class of committed instruction 1077system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.11% # Class of committed instruction 1078system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.11% # Class of committed instruction 1079system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.11% # Class of committed instruction 1080system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.11% # Class of committed instruction 1081system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.11% # Class of committed instruction 1082system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.11% # Class of committed instruction 1083system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.11% # Class of committed instruction 1084system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.11% # Class of committed instruction 1085system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.11% # Class of committed instruction 1086system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.11% # Class of committed instruction 1087system.cpu1.commit.op_class_0::MemRead 111544 31.32% 85.43% # Class of committed instruction 1088system.cpu1.commit.op_class_0::MemWrite 51911 14.57% 100.00% # Class of committed instruction 1089system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1090system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1091system.cpu1.commit.op_class_0::total 356173 # Class of committed instruction 1092system.cpu1.commit.bw_lim_events 1232 # number cycles where commit BW limit reached 1093system.cpu1.rob.rob_reads 568422 # The number of ROB reads 1094system.cpu1.rob.rob_writes 766486 # The number of ROB writes 1095system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself 1096system.cpu1.idleCycles 2573 # Total number of cycles that the CPU has spent unscheduled due to idling 1097system.cpu1.quiesceCycles 46533 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1098system.cpu1.committedInsts 299269 # Number of Instructions Simulated 1099system.cpu1.committedOps 299269 # Number of Ops (including micro ops) Simulated 1100system.cpu1.cpi 0.656734 # CPI: Cycles Per Instruction 1101system.cpu1.cpi_total 0.656734 # CPI: Total CPI of All Threads 1102system.cpu1.ipc 1.522687 # IPC: Instructions Per Cycle 1103system.cpu1.ipc_total 1.522687 # IPC: Total IPC of All Threads 1104system.cpu1.int_regfile_reads 554283 # number of integer regfile reads 1105system.cpu1.int_regfile_writes 257020 # number of integer regfile writes 1106system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1107system.cpu1.misc_regfile_reads 165298 # number of misc regfile reads 1108system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1109system.cpu1.dcache.tags.replacements 0 # number of replacements 1110system.cpu1.dcache.tags.tagsinuse 25.915239 # Cycle average of tags in use 1111system.cpu1.dcache.tags.total_refs 58936 # Total number of references to valid blocks. 1112system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1113system.cpu1.dcache.tags.avg_refs 2032.275862 # Average number of references to valid blocks. 1114system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1115system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.915239 # Average occupied blocks per requestor 1116system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050616 # Average percentage of cache occupancy 1117system.cpu1.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy 1118system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1119system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 1120system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 1121system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1122system.cpu1.dcache.tags.tag_accesses 455882 # Number of tag accesses 1123system.cpu1.dcache.tags.data_accesses 455882 # Number of data accesses 1124system.cpu1.dcache.ReadReq_hits::cpu1.data 61472 # number of ReadReq hits 1125system.cpu1.dcache.ReadReq_hits::total 61472 # number of ReadReq hits 1126system.cpu1.dcache.WriteReq_hits::cpu1.data 51691 # number of WriteReq hits 1127system.cpu1.dcache.WriteReq_hits::total 51691 # number of WriteReq hits 1128system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits 1129system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits 1130system.cpu1.dcache.demand_hits::cpu1.data 113163 # number of demand (read+write) hits 1131system.cpu1.dcache.demand_hits::total 113163 # number of demand (read+write) hits 1132system.cpu1.dcache.overall_hits::cpu1.data 113163 # number of overall hits 1133system.cpu1.dcache.overall_hits::total 113163 # number of overall hits 1134system.cpu1.dcache.ReadReq_misses::cpu1.data 523 # number of ReadReq misses 1135system.cpu1.dcache.ReadReq_misses::total 523 # number of ReadReq misses 1136system.cpu1.dcache.WriteReq_misses::cpu1.data 150 # number of WriteReq misses 1137system.cpu1.dcache.WriteReq_misses::total 150 # number of WriteReq misses 1138system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses 1139system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses 1140system.cpu1.dcache.demand_misses::cpu1.data 673 # number of demand (read+write) misses 1141system.cpu1.dcache.demand_misses::total 673 # number of demand (read+write) misses 1142system.cpu1.dcache.overall_misses::cpu1.data 673 # number of overall misses 1143system.cpu1.dcache.overall_misses::total 673 # number of overall misses 1144system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8464500 # number of ReadReq miss cycles 1145system.cpu1.dcache.ReadReq_miss_latency::total 8464500 # number of ReadReq miss cycles 1146system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2960500 # number of WriteReq miss cycles 1147system.cpu1.dcache.WriteReq_miss_latency::total 2960500 # number of WriteReq miss cycles 1148system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 828000 # number of SwapReq miss cycles 1149system.cpu1.dcache.SwapReq_miss_latency::total 828000 # number of SwapReq miss cycles 1150system.cpu1.dcache.demand_miss_latency::cpu1.data 11425000 # number of demand (read+write) miss cycles 1151system.cpu1.dcache.demand_miss_latency::total 11425000 # number of demand (read+write) miss cycles 1152system.cpu1.dcache.overall_miss_latency::cpu1.data 11425000 # number of overall miss cycles 1153system.cpu1.dcache.overall_miss_latency::total 11425000 # number of overall miss cycles 1154system.cpu1.dcache.ReadReq_accesses::cpu1.data 61995 # number of ReadReq accesses(hits+misses) 1155system.cpu1.dcache.ReadReq_accesses::total 61995 # number of ReadReq accesses(hits+misses) 1156system.cpu1.dcache.WriteReq_accesses::cpu1.data 51841 # number of WriteReq accesses(hits+misses) 1157system.cpu1.dcache.WriteReq_accesses::total 51841 # number of WriteReq accesses(hits+misses) 1158system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 1159system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 1160system.cpu1.dcache.demand_accesses::cpu1.data 113836 # number of demand (read+write) accesses 1161system.cpu1.dcache.demand_accesses::total 113836 # number of demand (read+write) accesses 1162system.cpu1.dcache.overall_accesses::cpu1.data 113836 # number of overall (read+write) accesses 1163system.cpu1.dcache.overall_accesses::total 113836 # number of overall (read+write) accesses 1164system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008436 # miss rate for ReadReq accesses 1165system.cpu1.dcache.ReadReq_miss_rate::total 0.008436 # miss rate for ReadReq accesses 1166system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002893 # miss rate for WriteReq accesses 1167system.cpu1.dcache.WriteReq_miss_rate::total 0.002893 # miss rate for WriteReq accesses 1168system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.857143 # miss rate for SwapReq accesses 1169system.cpu1.dcache.SwapReq_miss_rate::total 0.857143 # miss rate for SwapReq accesses 1170system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005912 # miss rate for demand accesses 1171system.cpu1.dcache.demand_miss_rate::total 0.005912 # miss rate for demand accesses 1172system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005912 # miss rate for overall accesses 1173system.cpu1.dcache.overall_miss_rate::total 0.005912 # miss rate for overall accesses 1174system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16184.512428 # average ReadReq miss latency 1175system.cpu1.dcache.ReadReq_avg_miss_latency::total 16184.512428 # average ReadReq miss latency 1176system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19736.666667 # average WriteReq miss latency 1177system.cpu1.dcache.WriteReq_avg_miss_latency::total 19736.666667 # average WriteReq miss latency 1178system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13800 # average SwapReq miss latency 1179system.cpu1.dcache.SwapReq_avg_miss_latency::total 13800 # average SwapReq miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency 1181system.cpu1.dcache.demand_avg_miss_latency::total 16976.225854 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency 1183system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854 # average overall miss latency 1184system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1187system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1189system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1190system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits 1191system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits 1192system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits 1193system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits 1194system.cpu1.dcache.demand_mshr_hits::cpu1.data 405 # number of demand (read+write) MSHR hits 1195system.cpu1.dcache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits 1196system.cpu1.dcache.overall_mshr_hits::cpu1.data 405 # number of overall MSHR hits 1197system.cpu1.dcache.overall_mshr_hits::total 405 # number of overall MSHR hits 1198system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 161 # number of ReadReq MSHR misses 1199system.cpu1.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses 1200system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1201system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1202system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses 1203system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses 1204system.cpu1.dcache.demand_mshr_misses::cpu1.data 268 # number of demand (read+write) MSHR misses 1205system.cpu1.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1206system.cpu1.dcache.overall_mshr_misses::cpu1.data 268 # number of overall MSHR misses 1207system.cpu1.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1208system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles 1209system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles 1210system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1517000 # number of WriteReq MSHR miss cycles 1211system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1517000 # number of WriteReq MSHR miss cycles 1212system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 768000 # number of SwapReq MSHR miss cycles 1213system.cpu1.dcache.SwapReq_mshr_miss_latency::total 768000 # number of SwapReq MSHR miss cycles 1214system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3047000 # number of demand (read+write) MSHR miss cycles 1215system.cpu1.dcache.demand_mshr_miss_latency::total 3047000 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3047000 # number of overall MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::total 3047000 # number of overall MSHR miss cycles 1218system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002597 # mshr miss rate for ReadReq accesses 1219system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002597 # mshr miss rate for ReadReq accesses 1220system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002064 # mshr miss rate for WriteReq accesses 1221system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002064 # mshr miss rate for WriteReq accesses 1222system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.857143 # mshr miss rate for SwapReq accesses 1223system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.857143 # mshr miss rate for SwapReq accesses 1224system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for demand accesses 1225system.cpu1.dcache.demand_mshr_miss_rate::total 0.002354 # mshr miss rate for demand accesses 1226system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for overall accesses 1227system.cpu1.dcache.overall_mshr_miss_rate::total 0.002354 # mshr miss rate for overall accesses 1228system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9503.105590 # average ReadReq mshr miss latency 1229system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9503.105590 # average ReadReq mshr miss latency 1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093 # average WriteReq mshr miss latency 1231system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093 # average WriteReq mshr miss latency 1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 12800 # average SwapReq mshr miss latency 1233system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 12800 # average SwapReq mshr miss latency 1234system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1235system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency 1236system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1237system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency 1238system.cpu1.icache.tags.replacements 548 # number of replacements 1239system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use 1240system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. 1241system.cpu1.icache.tags.sampled_refs 682 # Sample count of references to valid blocks. 1242system.cpu1.icache.tags.avg_refs 31.180352 # Average number of references to valid blocks. 1243system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1244system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.609803 # Average occupied blocks per requestor 1245system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190644 # Average percentage of cache occupancy 1246system.cpu1.icache.tags.occ_percent::total 0.190644 # Average percentage of cache occupancy 1247system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 1248system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1249system.cpu1.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id 1250system.cpu1.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 1251system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id 1252system.cpu1.icache.tags.tag_accesses 22773 # Number of tag accesses 1253system.cpu1.icache.tags.data_accesses 22773 # Number of data accesses 1254system.cpu1.icache.ReadReq_hits::cpu1.inst 21265 # number of ReadReq hits 1255system.cpu1.icache.ReadReq_hits::total 21265 # number of ReadReq hits 1256system.cpu1.icache.demand_hits::cpu1.inst 21265 # number of demand (read+write) hits 1257system.cpu1.icache.demand_hits::total 21265 # number of demand (read+write) hits 1258system.cpu1.icache.overall_hits::cpu1.inst 21265 # number of overall hits 1259system.cpu1.icache.overall_hits::total 21265 # number of overall hits 1260system.cpu1.icache.ReadReq_misses::cpu1.inst 826 # number of ReadReq misses 1261system.cpu1.icache.ReadReq_misses::total 826 # number of ReadReq misses 1262system.cpu1.icache.demand_misses::cpu1.inst 826 # number of demand (read+write) misses 1263system.cpu1.icache.demand_misses::total 826 # number of demand (read+write) misses 1264system.cpu1.icache.overall_misses::cpu1.inst 826 # number of overall misses 1265system.cpu1.icache.overall_misses::total 826 # number of overall misses 1266system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13533000 # number of ReadReq miss cycles 1267system.cpu1.icache.ReadReq_miss_latency::total 13533000 # number of ReadReq miss cycles 1268system.cpu1.icache.demand_miss_latency::cpu1.inst 13533000 # number of demand (read+write) miss cycles 1269system.cpu1.icache.demand_miss_latency::total 13533000 # number of demand (read+write) miss cycles 1270system.cpu1.icache.overall_miss_latency::cpu1.inst 13533000 # number of overall miss cycles 1271system.cpu1.icache.overall_miss_latency::total 13533000 # number of overall miss cycles 1272system.cpu1.icache.ReadReq_accesses::cpu1.inst 22091 # number of ReadReq accesses(hits+misses) 1273system.cpu1.icache.ReadReq_accesses::total 22091 # number of ReadReq accesses(hits+misses) 1274system.cpu1.icache.demand_accesses::cpu1.inst 22091 # number of demand (read+write) accesses 1275system.cpu1.icache.demand_accesses::total 22091 # number of demand (read+write) accesses 1276system.cpu1.icache.overall_accesses::cpu1.inst 22091 # number of overall (read+write) accesses 1277system.cpu1.icache.overall_accesses::total 22091 # number of overall (read+write) accesses 1278system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037391 # miss rate for ReadReq accesses 1279system.cpu1.icache.ReadReq_miss_rate::total 0.037391 # miss rate for ReadReq accesses 1280system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037391 # miss rate for demand accesses 1281system.cpu1.icache.demand_miss_rate::total 0.037391 # miss rate for demand accesses 1282system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037391 # miss rate for overall accesses 1283system.cpu1.icache.overall_miss_rate::total 0.037391 # miss rate for overall accesses 1284system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16383.777240 # average ReadReq miss latency 1285system.cpu1.icache.ReadReq_avg_miss_latency::total 16383.777240 # average ReadReq miss latency 1286system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency 1287system.cpu1.icache.demand_avg_miss_latency::total 16383.777240 # average overall miss latency 1288system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency 1289system.cpu1.icache.overall_avg_miss_latency::total 16383.777240 # average overall miss latency 1290system.cpu1.icache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked 1291system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1292system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1293system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1294system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked 1295system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1296system.cpu1.icache.writebacks::writebacks 548 # number of writebacks 1297system.cpu1.icache.writebacks::total 548 # number of writebacks 1298system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits 1299system.cpu1.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 1300system.cpu1.icache.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits 1301system.cpu1.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 1302system.cpu1.icache.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits 1303system.cpu1.icache.overall_mshr_hits::total 144 # number of overall MSHR hits 1304system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 682 # number of ReadReq MSHR misses 1305system.cpu1.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses 1306system.cpu1.icache.demand_mshr_misses::cpu1.inst 682 # number of demand (read+write) MSHR misses 1307system.cpu1.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses 1308system.cpu1.icache.overall_mshr_misses::cpu1.inst 682 # number of overall MSHR misses 1309system.cpu1.icache.overall_mshr_misses::total 682 # number of overall MSHR misses 1310system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 10822000 # number of ReadReq MSHR miss cycles 1311system.cpu1.icache.ReadReq_mshr_miss_latency::total 10822000 # number of ReadReq MSHR miss cycles 1312system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 10822000 # number of demand (read+write) MSHR miss cycles 1313system.cpu1.icache.demand_mshr_miss_latency::total 10822000 # number of demand (read+write) MSHR miss cycles 1314system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 10822000 # number of overall MSHR miss cycles 1315system.cpu1.icache.overall_mshr_miss_latency::total 10822000 # number of overall MSHR miss cycles 1316system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for ReadReq accesses 1317system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030872 # mshr miss rate for ReadReq accesses 1318system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for demand accesses 1319system.cpu1.icache.demand_mshr_miss_rate::total 0.030872 # mshr miss rate for demand accesses 1320system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for overall accesses 1321system.cpu1.icache.overall_mshr_miss_rate::total 0.030872 # mshr miss rate for overall accesses 1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average ReadReq mshr miss latency 1323system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191 # average ReadReq mshr miss latency 1324system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1325system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency 1326system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1327system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency 1328system.cpu2.branchPred.lookups 65577 # Number of BP lookups 1329system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted 1330system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect 1331system.cpu2.branchPred.BTBLookups 57712 # Number of BTB lookups 1332system.cpu2.branchPred.BTBHits 0 # Number of BTB hits 1333system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1334system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1335system.cpu2.branchPred.usedRAS 1983 # Number of times the RAS was used to get a target. 1336system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1337system.cpu2.branchPred.indirectLookups 57712 # Number of indirect predictor lookups. 1338system.cpu2.branchPred.indirectHits 46848 # Number of indirect target hits. 1339system.cpu2.branchPred.indirectMisses 10864 # Number of indirect misses. 1340system.cpu2.branchPredindirectMispredicted 1379 # Number of mispredicted indirect branches. 1341system.cpu2.numCycles 195641 # number of cpu cycles simulated 1342system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1343system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1344system.cpu2.fetch.icacheStallCycles 39175 # Number of cycles fetch is stalled on an Icache miss 1345system.cpu2.fetch.Insts 357136 # Number of instructions fetch has processed 1346system.cpu2.fetch.Branches 65577 # Number of branches that fetch encountered 1347system.cpu2.fetch.predictedBranches 48831 # Number of branches that fetch has predicted taken 1348system.cpu2.fetch.Cycles 146036 # Number of cycles fetch has run and was not squashing or blocked 1349system.cpu2.fetch.SquashCycles 5085 # Number of cycles fetch has spent squashing 1350system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1351system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1352system.cpu2.fetch.PendingTrapStallCycles 2246 # Number of stall cycles due to pending traps 1353system.cpu2.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR 1354system.cpu2.fetch.CacheLines 27545 # Number of cache lines fetched 1355system.cpu2.fetch.IcacheSquashes 945 # Number of outstanding Icache misses that were squashed 1356system.cpu2.fetch.rateDist::samples 190045 # Number of instructions fetched each cycle (Total) 1357system.cpu2.fetch.rateDist::mean 1.879218 # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::stdev 2.350973 # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.rateDist::0 72125 37.95% 37.95% # Number of instructions fetched each cycle (Total) 1361system.cpu2.fetch.rateDist::1 57864 30.45% 68.40% # Number of instructions fetched each cycle (Total) 1362system.cpu2.fetch.rateDist::2 8007 4.21% 72.61% # Number of instructions fetched each cycle (Total) 1363system.cpu2.fetch.rateDist::3 3378 1.78% 74.39% # Number of instructions fetched each cycle (Total) 1364system.cpu2.fetch.rateDist::4 697 0.37% 74.76% # Number of instructions fetched each cycle (Total) 1365system.cpu2.fetch.rateDist::5 36524 19.22% 93.98% # Number of instructions fetched each cycle (Total) 1366system.cpu2.fetch.rateDist::6 1219 0.64% 94.62% # Number of instructions fetched each cycle (Total) 1367system.cpu2.fetch.rateDist::7 1446 0.76% 95.38% # Number of instructions fetched each cycle (Total) 1368system.cpu2.fetch.rateDist::8 8785 4.62% 100.00% # Number of instructions fetched each cycle (Total) 1369system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1370system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1371system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1372system.cpu2.fetch.rateDist::total 190045 # Number of instructions fetched each cycle (Total) 1373system.cpu2.fetch.branchRate 0.335190 # Number of branch fetches per cycle 1374system.cpu2.fetch.rate 1.825466 # Number of inst fetches per cycle 1375system.cpu2.decode.IdleCycles 23115 # Number of cycles decode is idle 1376system.cpu2.decode.BlockedCycles 69586 # Number of cycles decode is blocked 1377system.cpu2.decode.RunCycles 90388 # Number of cycles decode is running 1378system.cpu2.decode.UnblockCycles 4404 # Number of cycles decode is unblocking 1379system.cpu2.decode.SquashCycles 2542 # Number of cycles decode is squashing 1380system.cpu2.decode.DecodedInsts 325134 # Number of instructions handled by decode 1381system.cpu2.rename.SquashCycles 2542 # Number of cycles rename is squashing 1382system.cpu2.rename.IdleCycles 24144 # Number of cycles rename is idle 1383system.cpu2.rename.BlockCycles 33213 # Number of cycles rename is blocking 1384system.cpu2.rename.serializeStallCycles 15151 # count of cycles rename stalled for serializing inst 1385system.cpu2.rename.RunCycles 91754 # Number of cycles rename is running 1386system.cpu2.rename.UnblockCycles 23231 # Number of cycles rename is unblocking 1387system.cpu2.rename.RenamedInsts 318523 # Number of instructions processed by rename 1388system.cpu2.rename.IQFullEvents 20453 # Number of times rename has blocked due to IQ full 1389system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full 1390system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1391system.cpu2.rename.RenamedOperands 223607 # Number of destination operands rename has renamed 1392system.cpu2.rename.RenameLookups 605589 # Number of register rename lookups that rename has made 1393system.cpu2.rename.int_rename_lookups 472031 # Number of integer rename lookups 1394system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups 1395system.cpu2.rename.CommittedMaps 193721 # Number of HB maps that are committed 1396system.cpu2.rename.UndoneMaps 29886 # Number of HB maps that are undone due to squashing 1397system.cpu2.rename.serializingInsts 1685 # count of serializing insts renamed 1398system.cpu2.rename.tempSerializingInsts 1831 # count of temporary serializing insts renamed 1399system.cpu2.rename.skidInsts 29018 # count of insts added to the skid buffer 1400system.cpu2.memDep0.insertedLoads 87037 # Number of loads inserted to the mem dependence unit. 1401system.cpu2.memDep0.insertedStores 41099 # Number of stores inserted to the mem dependence unit. 1402system.cpu2.memDep0.conflictingLoads 41296 # Number of conflicting loads. 1403system.cpu2.memDep0.conflictingStores 34595 # Number of conflicting stores. 1404system.cpu2.iq.iqInstsAdded 259686 # Number of instructions added to the IQ (excludes non-spec) 1405system.cpu2.iq.iqNonSpecInstsAdded 8253 # Number of non-speculative instructions added to the IQ 1406system.cpu2.iq.iqInstsIssued 260132 # Number of instructions issued 1407system.cpu2.iq.iqSquashedInstsIssued 104 # Number of squashed instructions issued 1408system.cpu2.iq.iqSquashedInstsExamined 25858 # Number of squashed instructions iterated over during squash; mainly for profiling 1409system.cpu2.iq.iqSquashedOperandsExamined 19408 # Number of squashed operands that are examined and possibly removed from graph 1410system.cpu2.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed 1411system.cpu2.iq.issued_per_cycle::samples 190045 # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::mean 1.368792 # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::stdev 1.393545 # Number of insts issued each cycle 1414system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1415system.cpu2.iq.issued_per_cycle::0 77002 40.52% 40.52% # Number of insts issued each cycle 1416system.cpu2.iq.issued_per_cycle::1 26562 13.98% 54.49% # Number of insts issued each cycle 1417system.cpu2.iq.issued_per_cycle::2 39729 20.91% 75.40% # Number of insts issued each cycle 1418system.cpu2.iq.issued_per_cycle::3 39504 20.79% 96.19% # Number of insts issued each cycle 1419system.cpu2.iq.issued_per_cycle::4 3584 1.89% 98.07% # Number of insts issued each cycle 1420system.cpu2.iq.issued_per_cycle::5 1794 0.94% 99.02% # Number of insts issued each cycle 1421system.cpu2.iq.issued_per_cycle::6 1114 0.59% 99.60% # Number of insts issued each cycle 1422system.cpu2.iq.issued_per_cycle::7 438 0.23% 99.83% # Number of insts issued each cycle 1423system.cpu2.iq.issued_per_cycle::8 318 0.17% 100.00% # Number of insts issued each cycle 1424system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1425system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1426system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1427system.cpu2.iq.issued_per_cycle::total 190045 # Number of insts issued each cycle 1428system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::IntAlu 198 41.51% 41.51% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::IntMult 0 0.00% 41.51% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::IntDiv 0 0.00% 41.51% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::FloatAdd 0 0.00% 41.51% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::FloatCmp 0 0.00% 41.51% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::FloatCvt 0 0.00% 41.51% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::FloatMult 0 0.00% 41.51% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::FloatDiv 0 0.00% 41.51% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 41.51% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdAdd 0 0.00% 41.51% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 41.51% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdAlu 0 0.00% 41.51% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdCmp 0 0.00% 41.51% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdCvt 0 0.00% 41.51% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdMisc 0 0.00% 41.51% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::SimdMult 0 0.00% 41.51% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 41.51% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::SimdShift 0 0.00% 41.51% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 41.51% # attempts to use FU when none available 1448system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 41.51% # attempts to use FU when none available 1449system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 41.51% # attempts to use FU when none available 1450system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 41.51% # attempts to use FU when none available 1451system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 41.51% # attempts to use FU when none available 1452system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 41.51% # attempts to use FU when none available 1453system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 41.51% # attempts to use FU when none available 1454system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 41.51% # attempts to use FU when none available 1455system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 41.51% # attempts to use FU when none available 1456system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.51% # attempts to use FU when none available 1457system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 41.51% # attempts to use FU when none available 1458system.cpu2.iq.fu_full::MemRead 44 9.22% 50.73% # attempts to use FU when none available 1459system.cpu2.iq.fu_full::MemWrite 235 49.27% 100.00% # attempts to use FU when none available 1460system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1461system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1462system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1463system.cpu2.iq.FU_type_0::IntAlu 127776 49.12% 49.12% # Type of FU issued 1464system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.12% # Type of FU issued 1465system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.12% # Type of FU issued 1466system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.12% # Type of FU issued 1467system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.12% # Type of FU issued 1468system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.12% # Type of FU issued 1469system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.12% # Type of FU issued 1470system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.12% # Type of FU issued 1471system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.12% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.12% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.12% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.12% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.12% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.12% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.12% # Type of FU issued 1478system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.12% # Type of FU issued 1479system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.12% # Type of FU issued 1480system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.12% # Type of FU issued 1481system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.12% # Type of FU issued 1482system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.12% # Type of FU issued 1483system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.12% # Type of FU issued 1484system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.12% # Type of FU issued 1485system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.12% # Type of FU issued 1486system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.12% # Type of FU issued 1487system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.12% # Type of FU issued 1488system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.12% # Type of FU issued 1489system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.12% # Type of FU issued 1490system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.12% # Type of FU issued 1491system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.12% # Type of FU issued 1492system.cpu2.iq.FU_type_0::MemRead 92295 35.48% 84.60% # Type of FU issued 1493system.cpu2.iq.FU_type_0::MemWrite 40061 15.40% 100.00% # Type of FU issued 1494system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1495system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1496system.cpu2.iq.FU_type_0::total 260132 # Type of FU issued 1497system.cpu2.iq.rate 1.329639 # Inst issue rate 1498system.cpu2.iq.fu_busy_cnt 477 # FU busy when requested 1499system.cpu2.iq.fu_busy_rate 0.001834 # FU busy rate (busy events/executed inst) 1500system.cpu2.iq.int_inst_queue_reads 710890 # Number of integer instruction queue reads 1501system.cpu2.iq.int_inst_queue_writes 293781 # Number of integer instruction queue writes 1502system.cpu2.iq.int_inst_queue_wakeup_accesses 256087 # Number of integer instruction queue wakeup accesses 1503system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1504system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes 1505system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1506system.cpu2.iq.int_alu_accesses 260609 # Number of integer alu accesses 1507system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1508system.cpu2.iew.lsq.thread0.forwLoads 34538 # Number of loads that had data forwarded from stores 1509system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1510system.cpu2.iew.lsq.thread0.squashedLoads 4572 # Number of loads squashed 1511system.cpu2.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed 1512system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations 1513system.cpu2.iew.lsq.thread0.squashedStores 2770 # Number of stores squashed 1514system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1515system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1516system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1517system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1518system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1519system.cpu2.iew.iewSquashCycles 2542 # Number of cycles IEW is squashing 1520system.cpu2.iew.iewBlockCycles 9787 # Number of cycles IEW is blocking 1521system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking 1522system.cpu2.iew.iewDispatchedInsts 310555 # Number of instructions dispatched to IQ 1523system.cpu2.iew.iewDispSquashedInsts 374 # Number of squashed instructions skipped by dispatch 1524system.cpu2.iew.iewDispLoadInsts 87037 # Number of dispatched load instructions 1525system.cpu2.iew.iewDispStoreInsts 41099 # Number of dispatched store instructions 1526system.cpu2.iew.iewDispNonSpecInsts 1544 # Number of dispatched non-speculative instructions 1527system.cpu2.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall 1528system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1529system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations 1530system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly 1531system.cpu2.iew.predictedNotTakenIncorrect 2649 # Number of branches that were predicted not taken incorrectly 1532system.cpu2.iew.branchMispredicts 3110 # Number of branch mispredicts detected at execute 1533system.cpu2.iew.iewExecutedInsts 257554 # Number of executed instructions 1534system.cpu2.iew.iewExecLoadInsts 85462 # Number of load instructions executed 1535system.cpu2.iew.iewExecSquashedInsts 2578 # Number of squashed instructions skipped in execute 1536system.cpu2.iew.exec_swp 0 # number of swp insts executed 1537system.cpu2.iew.exec_nop 42616 # number of nop insts executed 1538system.cpu2.iew.exec_refs 125205 # number of memory reference insts executed 1539system.cpu2.iew.exec_branches 53054 # Number of branches executed 1540system.cpu2.iew.exec_stores 39743 # Number of stores executed 1541system.cpu2.iew.exec_rate 1.316462 # Inst execution rate 1542system.cpu2.iew.wb_sent 256619 # cumulative count of insts sent to commit 1543system.cpu2.iew.wb_count 256087 # cumulative count of insts written-back 1544system.cpu2.iew.wb_producers 143359 # num instructions producing a value 1545system.cpu2.iew.wb_consumers 151246 # num instructions consuming a value 1546system.cpu2.iew.wb_rate 1.308964 # insts written-back per cycle 1547system.cpu2.iew.wb_fanout 0.947853 # average fanout of values written-back 1548system.cpu2.commit.commitSquashedInsts 27054 # The number of squashed insts skipped by commit 1549system.cpu2.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards 1550system.cpu2.commit.branchMispredicts 2464 # The number of times a branch was mispredicted 1551system.cpu2.commit.committed_per_cycle::samples 184962 # Number of insts commited each cycle 1552system.cpu2.commit.committed_per_cycle::mean 1.532661 # Number of insts commited each cycle 1553system.cpu2.commit.committed_per_cycle::stdev 2.012592 # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::0 83513 45.15% 45.15% # Number of insts commited each cycle 1556system.cpu2.commit.committed_per_cycle::1 49247 26.63% 71.78% # Number of insts commited each cycle 1557system.cpu2.commit.committed_per_cycle::2 5539 2.99% 74.77% # Number of insts commited each cycle 1558system.cpu2.commit.committed_per_cycle::3 7621 4.12% 78.89% # Number of insts commited each cycle 1559system.cpu2.commit.committed_per_cycle::4 1289 0.70% 79.59% # Number of insts commited each cycle 1560system.cpu2.commit.committed_per_cycle::5 34776 18.80% 98.39% # Number of insts commited each cycle 1561system.cpu2.commit.committed_per_cycle::6 735 0.40% 98.79% # Number of insts commited each cycle 1562system.cpu2.commit.committed_per_cycle::7 1086 0.59% 99.38% # Number of insts commited each cycle 1563system.cpu2.commit.committed_per_cycle::8 1156 0.62% 100.00% # Number of insts commited each cycle 1564system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1565system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1566system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1567system.cpu2.commit.committed_per_cycle::total 184962 # Number of insts commited each cycle 1568system.cpu2.commit.committedInsts 283484 # Number of instructions committed 1569system.cpu2.commit.committedOps 283484 # Number of ops (including micro ops) committed 1570system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1571system.cpu2.commit.refs 120794 # Number of memory references committed 1572system.cpu2.commit.loads 82465 # Number of loads committed 1573system.cpu2.commit.membars 6325 # Number of memory barriers committed 1574system.cpu2.commit.branches 50613 # Number of branches committed 1575system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1576system.cpu2.commit.int_insts 193531 # Number of committed integer instructions. 1577system.cpu2.commit.function_calls 322 # Number of function calls committed. 1578system.cpu2.commit.op_class_0::No_OpClass 41403 14.61% 14.61% # Class of committed instruction 1579system.cpu2.commit.op_class_0::IntAlu 114962 40.55% 55.16% # Class of committed instruction 1580system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.16% # Class of committed instruction 1581system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.16% # Class of committed instruction 1582system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.16% # Class of committed instruction 1583system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.16% # Class of committed instruction 1584system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.16% # Class of committed instruction 1585system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.16% # Class of committed instruction 1586system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.16% # Class of committed instruction 1587system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.16% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.16% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.16% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.16% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.16% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.16% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.16% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.16% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.16% # Class of committed instruction 1596system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.16% # Class of committed instruction 1597system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.16% # Class of committed instruction 1598system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.16% # Class of committed instruction 1599system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.16% # Class of committed instruction 1600system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.16% # Class of committed instruction 1601system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.16% # Class of committed instruction 1602system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.16% # Class of committed instruction 1603system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.16% # Class of committed instruction 1604system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.16% # Class of committed instruction 1605system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.16% # Class of committed instruction 1606system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.16% # Class of committed instruction 1607system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.16% # Class of committed instruction 1608system.cpu2.commit.op_class_0::MemRead 88790 31.32% 86.48% # Class of committed instruction 1609system.cpu2.commit.op_class_0::MemWrite 38329 13.52% 100.00% # Class of committed instruction 1610system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1611system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1612system.cpu2.commit.op_class_0::total 283484 # Class of committed instruction 1613system.cpu2.commit.bw_lim_events 1156 # number cycles where commit BW limit reached 1614system.cpu2.rob.rob_reads 493758 # The number of ROB reads 1615system.cpu2.rob.rob_writes 626207 # The number of ROB writes 1616system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself 1617system.cpu2.idleCycles 5596 # Total number of cycles that the CPU has spent unscheduled due to idling 1618system.cpu2.quiesceCycles 47431 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1619system.cpu2.committedInsts 235756 # Number of Instructions Simulated 1620system.cpu2.committedOps 235756 # Number of Ops (including micro ops) Simulated 1621system.cpu2.cpi 0.829845 # CPI: Cycles Per Instruction 1622system.cpu2.cpi_total 0.829845 # CPI: Total CPI of All Threads 1623system.cpu2.ipc 1.205044 # IPC: Instructions Per Cycle 1624system.cpu2.ipc_total 1.205044 # IPC: Total IPC of All Threads 1625system.cpu2.int_regfile_reads 440950 # number of integer regfile reads 1626system.cpu2.int_regfile_writes 206257 # number of integer regfile writes 1627system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1628system.cpu2.misc_regfile_reads 127194 # number of misc regfile reads 1629system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1630system.cpu2.dcache.tags.replacements 0 # number of replacements 1631system.cpu2.dcache.tags.tagsinuse 26.976674 # Cycle average of tags in use 1632system.cpu2.dcache.tags.total_refs 45756 # Total number of references to valid blocks. 1633system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 1634system.cpu2.dcache.tags.avg_refs 1525.200000 # Average number of references to valid blocks. 1635system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1636system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.976674 # Average occupied blocks per requestor 1637system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052689 # Average percentage of cache occupancy 1638system.cpu2.dcache.tags.occ_percent::total 0.052689 # Average percentage of cache occupancy 1639system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 1640system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1641system.cpu2.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 1642system.cpu2.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 1643system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 1644system.cpu2.dcache.tags.tag_accesses 357076 # Number of tag accesses 1645system.cpu2.dcache.tags.data_accesses 357076 # Number of data accesses 1646system.cpu2.dcache.ReadReq_hits::cpu2.data 50413 # number of ReadReq hits 1647system.cpu2.dcache.ReadReq_hits::total 50413 # number of ReadReq hits 1648system.cpu2.dcache.WriteReq_hits::cpu2.data 38109 # number of WriteReq hits 1649system.cpu2.dcache.WriteReq_hits::total 38109 # number of WriteReq hits 1650system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits 1651system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits 1652system.cpu2.dcache.demand_hits::cpu2.data 88522 # number of demand (read+write) hits 1653system.cpu2.dcache.demand_hits::total 88522 # number of demand (read+write) hits 1654system.cpu2.dcache.overall_hits::cpu2.data 88522 # number of overall hits 1655system.cpu2.dcache.overall_hits::total 88522 # number of overall hits 1656system.cpu2.dcache.ReadReq_misses::cpu2.data 463 # number of ReadReq misses 1657system.cpu2.dcache.ReadReq_misses::total 463 # number of ReadReq misses 1658system.cpu2.dcache.WriteReq_misses::cpu2.data 152 # number of WriteReq misses 1659system.cpu2.dcache.WriteReq_misses::total 152 # number of WriteReq misses 1660system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses 1661system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses 1662system.cpu2.dcache.demand_misses::cpu2.data 615 # number of demand (read+write) misses 1663system.cpu2.dcache.demand_misses::total 615 # number of demand (read+write) misses 1664system.cpu2.dcache.overall_misses::cpu2.data 615 # number of overall misses 1665system.cpu2.dcache.overall_misses::total 615 # number of overall misses 1666system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8046000 # number of ReadReq miss cycles 1667system.cpu2.dcache.ReadReq_miss_latency::total 8046000 # number of ReadReq miss cycles 1668system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3843000 # number of WriteReq miss cycles 1669system.cpu2.dcache.WriteReq_miss_latency::total 3843000 # number of WriteReq miss cycles 1670system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 809500 # number of SwapReq miss cycles 1671system.cpu2.dcache.SwapReq_miss_latency::total 809500 # number of SwapReq miss cycles 1672system.cpu2.dcache.demand_miss_latency::cpu2.data 11889000 # number of demand (read+write) miss cycles 1673system.cpu2.dcache.demand_miss_latency::total 11889000 # number of demand (read+write) miss cycles 1674system.cpu2.dcache.overall_miss_latency::cpu2.data 11889000 # number of overall miss cycles 1675system.cpu2.dcache.overall_miss_latency::total 11889000 # number of overall miss cycles 1676system.cpu2.dcache.ReadReq_accesses::cpu2.data 50876 # number of ReadReq accesses(hits+misses) 1677system.cpu2.dcache.ReadReq_accesses::total 50876 # number of ReadReq accesses(hits+misses) 1678system.cpu2.dcache.WriteReq_accesses::cpu2.data 38261 # number of WriteReq accesses(hits+misses) 1679system.cpu2.dcache.WriteReq_accesses::total 38261 # number of WriteReq accesses(hits+misses) 1680system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 1681system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 1682system.cpu2.dcache.demand_accesses::cpu2.data 89137 # number of demand (read+write) accesses 1683system.cpu2.dcache.demand_accesses::total 89137 # number of demand (read+write) accesses 1684system.cpu2.dcache.overall_accesses::cpu2.data 89137 # number of overall (read+write) accesses 1685system.cpu2.dcache.overall_accesses::total 89137 # number of overall (read+write) accesses 1686system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009101 # miss rate for ReadReq accesses 1687system.cpu2.dcache.ReadReq_miss_rate::total 0.009101 # miss rate for ReadReq accesses 1688system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003973 # miss rate for WriteReq accesses 1689system.cpu2.dcache.WriteReq_miss_rate::total 0.003973 # miss rate for WriteReq accesses 1690system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses 1691system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses 1692system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006899 # miss rate for demand accesses 1693system.cpu2.dcache.demand_miss_rate::total 0.006899 # miss rate for demand accesses 1694system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006899 # miss rate for overall accesses 1695system.cpu2.dcache.overall_miss_rate::total 0.006899 # miss rate for overall accesses 1696system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17377.969762 # average ReadReq miss latency 1697system.cpu2.dcache.ReadReq_avg_miss_latency::total 17377.969762 # average ReadReq miss latency 1698system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25282.894737 # average WriteReq miss latency 1699system.cpu2.dcache.WriteReq_avg_miss_latency::total 25282.894737 # average WriteReq miss latency 1700system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15273.584906 # average SwapReq miss latency 1701system.cpu2.dcache.SwapReq_avg_miss_latency::total 15273.584906 # average SwapReq miss latency 1702system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency 1703system.cpu2.dcache.demand_avg_miss_latency::total 19331.707317 # average overall miss latency 1704system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency 1705system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317 # average overall miss latency 1706system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1707system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1708system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1709system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1710system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1711system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1712system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits 1713system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits 1714system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits 1715system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits 1716system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 5 # number of SwapReq MSHR hits 1717system.cpu2.dcache.SwapReq_mshr_hits::total 5 # number of SwapReq MSHR hits 1718system.cpu2.dcache.demand_mshr_hits::cpu2.data 345 # number of demand (read+write) MSHR hits 1719system.cpu2.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits 1720system.cpu2.dcache.overall_mshr_hits::cpu2.data 345 # number of overall MSHR hits 1721system.cpu2.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits 1722system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses 1723system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses 1724system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses 1725system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1726system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 48 # number of SwapReq MSHR misses 1727system.cpu2.dcache.SwapReq_mshr_misses::total 48 # number of SwapReq MSHR misses 1728system.cpu2.dcache.demand_mshr_misses::cpu2.data 270 # number of demand (read+write) MSHR misses 1729system.cpu2.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 1730system.cpu2.dcache.overall_mshr_misses::cpu2.data 270 # number of overall MSHR misses 1731system.cpu2.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 1732system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1997000 # number of ReadReq MSHR miss cycles 1733system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1997000 # number of ReadReq MSHR miss cycles 1734system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1762500 # number of WriteReq MSHR miss cycles 1735system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1762500 # number of WriteReq MSHR miss cycles 1736system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 756500 # number of SwapReq MSHR miss cycles 1737system.cpu2.dcache.SwapReq_mshr_miss_latency::total 756500 # number of SwapReq MSHR miss cycles 1738system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3759500 # number of demand (read+write) MSHR miss cycles 1739system.cpu2.dcache.demand_mshr_miss_latency::total 3759500 # number of demand (read+write) MSHR miss cycles 1740system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3759500 # number of overall MSHR miss cycles 1741system.cpu2.dcache.overall_mshr_miss_latency::total 3759500 # number of overall MSHR miss cycles 1742system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003243 # mshr miss rate for ReadReq accesses 1743system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003243 # mshr miss rate for ReadReq accesses 1744system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002744 # mshr miss rate for WriteReq accesses 1745system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002744 # mshr miss rate for WriteReq accesses 1746system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.705882 # mshr miss rate for SwapReq accesses 1747system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.705882 # mshr miss rate for SwapReq accesses 1748system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for demand accesses 1749system.cpu2.dcache.demand_mshr_miss_rate::total 0.003029 # mshr miss rate for demand accesses 1750system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for overall accesses 1751system.cpu2.dcache.overall_mshr_miss_rate::total 0.003029 # mshr miss rate for overall accesses 1752system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12103.030303 # average ReadReq mshr miss latency 1753system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12103.030303 # average ReadReq mshr miss latency 1754system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286 # average WriteReq mshr miss latency 1755system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286 # average WriteReq mshr miss latency 1756system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667 # average SwapReq mshr miss latency 1757system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667 # average SwapReq mshr miss latency 1758system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1759system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency 1760system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1761system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency 1762system.cpu2.icache.tags.replacements 555 # number of replacements 1763system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use 1764system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. 1765system.cpu2.icache.tags.sampled_refs 694 # Sample count of references to valid blocks. 1766system.cpu2.icache.tags.avg_refs 38.475504 # Average number of references to valid blocks. 1767system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1768system.cpu2.icache.tags.occ_blocks::cpu2.inst 101.261159 # Average occupied blocks per requestor 1769system.cpu2.icache.tags.occ_percent::cpu2.inst 0.197776 # Average percentage of cache occupancy 1770system.cpu2.icache.tags.occ_percent::total 0.197776 # Average percentage of cache occupancy 1771system.cpu2.icache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 1772system.cpu2.icache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 1773system.cpu2.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 1774system.cpu2.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 1775system.cpu2.icache.tags.occ_task_id_percent::1024 0.271484 # Percentage of cache occupancy per task id 1776system.cpu2.icache.tags.tag_accesses 28239 # Number of tag accesses 1777system.cpu2.icache.tags.data_accesses 28239 # Number of data accesses 1778system.cpu2.icache.ReadReq_hits::cpu2.inst 26702 # number of ReadReq hits 1779system.cpu2.icache.ReadReq_hits::total 26702 # number of ReadReq hits 1780system.cpu2.icache.demand_hits::cpu2.inst 26702 # number of demand (read+write) hits 1781system.cpu2.icache.demand_hits::total 26702 # number of demand (read+write) hits 1782system.cpu2.icache.overall_hits::cpu2.inst 26702 # number of overall hits 1783system.cpu2.icache.overall_hits::total 26702 # number of overall hits 1784system.cpu2.icache.ReadReq_misses::cpu2.inst 843 # number of ReadReq misses 1785system.cpu2.icache.ReadReq_misses::total 843 # number of ReadReq misses 1786system.cpu2.icache.demand_misses::cpu2.inst 843 # number of demand (read+write) misses 1787system.cpu2.icache.demand_misses::total 843 # number of demand (read+write) misses 1788system.cpu2.icache.overall_misses::cpu2.inst 843 # number of overall misses 1789system.cpu2.icache.overall_misses::total 843 # number of overall misses 1790system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 19527000 # number of ReadReq miss cycles 1791system.cpu2.icache.ReadReq_miss_latency::total 19527000 # number of ReadReq miss cycles 1792system.cpu2.icache.demand_miss_latency::cpu2.inst 19527000 # number of demand (read+write) miss cycles 1793system.cpu2.icache.demand_miss_latency::total 19527000 # number of demand (read+write) miss cycles 1794system.cpu2.icache.overall_miss_latency::cpu2.inst 19527000 # number of overall miss cycles 1795system.cpu2.icache.overall_miss_latency::total 19527000 # number of overall miss cycles 1796system.cpu2.icache.ReadReq_accesses::cpu2.inst 27545 # number of ReadReq accesses(hits+misses) 1797system.cpu2.icache.ReadReq_accesses::total 27545 # number of ReadReq accesses(hits+misses) 1798system.cpu2.icache.demand_accesses::cpu2.inst 27545 # number of demand (read+write) accesses 1799system.cpu2.icache.demand_accesses::total 27545 # number of demand (read+write) accesses 1800system.cpu2.icache.overall_accesses::cpu2.inst 27545 # number of overall (read+write) accesses 1801system.cpu2.icache.overall_accesses::total 27545 # number of overall (read+write) accesses 1802system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.030604 # miss rate for ReadReq accesses 1803system.cpu2.icache.ReadReq_miss_rate::total 0.030604 # miss rate for ReadReq accesses 1804system.cpu2.icache.demand_miss_rate::cpu2.inst 0.030604 # miss rate for demand accesses 1805system.cpu2.icache.demand_miss_rate::total 0.030604 # miss rate for demand accesses 1806system.cpu2.icache.overall_miss_rate::cpu2.inst 0.030604 # miss rate for overall accesses 1807system.cpu2.icache.overall_miss_rate::total 0.030604 # miss rate for overall accesses 1808system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23163.701068 # average ReadReq miss latency 1809system.cpu2.icache.ReadReq_avg_miss_latency::total 23163.701068 # average ReadReq miss latency 1810system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency 1811system.cpu2.icache.demand_avg_miss_latency::total 23163.701068 # average overall miss latency 1812system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency 1813system.cpu2.icache.overall_avg_miss_latency::total 23163.701068 # average overall miss latency 1814system.cpu2.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked 1815system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1816system.cpu2.icache.blocked::no_mshrs 7 # number of cycles access was blocked 1817system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1818system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked 1819system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1820system.cpu2.icache.writebacks::writebacks 555 # number of writebacks 1821system.cpu2.icache.writebacks::total 555 # number of writebacks 1822system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits 1823system.cpu2.icache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits 1824system.cpu2.icache.demand_mshr_hits::cpu2.inst 149 # number of demand (read+write) MSHR hits 1825system.cpu2.icache.demand_mshr_hits::total 149 # number of demand (read+write) MSHR hits 1826system.cpu2.icache.overall_mshr_hits::cpu2.inst 149 # number of overall MSHR hits 1827system.cpu2.icache.overall_mshr_hits::total 149 # number of overall MSHR hits 1828system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 694 # number of ReadReq MSHR misses 1829system.cpu2.icache.ReadReq_mshr_misses::total 694 # number of ReadReq MSHR misses 1830system.cpu2.icache.demand_mshr_misses::cpu2.inst 694 # number of demand (read+write) MSHR misses 1831system.cpu2.icache.demand_mshr_misses::total 694 # number of demand (read+write) MSHR misses 1832system.cpu2.icache.overall_mshr_misses::cpu2.inst 694 # number of overall MSHR misses 1833system.cpu2.icache.overall_mshr_misses::total 694 # number of overall MSHR misses 1834system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 15501500 # number of ReadReq MSHR miss cycles 1835system.cpu2.icache.ReadReq_mshr_miss_latency::total 15501500 # number of ReadReq MSHR miss cycles 1836system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 15501500 # number of demand (read+write) MSHR miss cycles 1837system.cpu2.icache.demand_mshr_miss_latency::total 15501500 # number of demand (read+write) MSHR miss cycles 1838system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 15501500 # number of overall MSHR miss cycles 1839system.cpu2.icache.overall_mshr_miss_latency::total 15501500 # number of overall MSHR miss cycles 1840system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for ReadReq accesses 1841system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025195 # mshr miss rate for ReadReq accesses 1842system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for demand accesses 1843system.cpu2.icache.demand_mshr_miss_rate::total 0.025195 # mshr miss rate for demand accesses 1844system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for overall accesses 1845system.cpu2.icache.overall_mshr_miss_rate::total 0.025195 # mshr miss rate for overall accesses 1846system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average ReadReq mshr miss latency 1847system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331 # average ReadReq mshr miss latency 1848system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1849system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency 1850system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1851system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency 1852system.cpu3.branchPred.lookups 57182 # Number of BP lookups 1853system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted 1854system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect 1855system.cpu3.branchPred.BTBLookups 48362 # Number of BTB lookups 1856system.cpu3.branchPred.BTBHits 0 # Number of BTB hits 1857system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1858system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1859system.cpu3.branchPred.usedRAS 2121 # Number of times the RAS was used to get a target. 1860system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1861system.cpu3.branchPred.indirectLookups 48362 # Number of indirect predictor lookups. 1862system.cpu3.branchPred.indirectHits 37349 # Number of indirect target hits. 1863system.cpu3.branchPred.indirectMisses 11013 # Number of indirect misses. 1864system.cpu3.branchPredindirectMispredicted 1473 # Number of mispredicted indirect branches. 1865system.cpu3.numCycles 195288 # number of cpu cycles simulated 1866system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1867system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1868system.cpu3.fetch.icacheStallCycles 45700 # Number of cycles fetch is stalled on an Icache miss 1869system.cpu3.fetch.Insts 298023 # Number of instructions fetch has processed 1870system.cpu3.fetch.Branches 57182 # Number of branches that fetch encountered 1871system.cpu3.fetch.predictedBranches 39470 # Number of branches that fetch has predicted taken 1872system.cpu3.fetch.Cycles 143366 # Number of cycles fetch has run and was not squashing or blocked 1873system.cpu3.fetch.SquashCycles 5327 # Number of cycles fetch has spent squashing 1874system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1875system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1876system.cpu3.fetch.PendingTrapStallCycles 1948 # Number of stall cycles due to pending traps 1877system.cpu3.fetch.CacheLines 34377 # Number of cache lines fetched 1878system.cpu3.fetch.IcacheSquashes 1007 # Number of outstanding Icache misses that were squashed 1879system.cpu3.fetch.rateDist::samples 193690 # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::mean 1.538660 # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.rateDist::stdev 2.252819 # Number of instructions fetched each cycle (Total) 1882system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1883system.cpu3.fetch.rateDist::0 90820 46.89% 46.89% # Number of instructions fetched each cycle (Total) 1884system.cpu3.fetch.rateDist::1 51773 26.73% 73.62% # Number of instructions fetched each cycle (Total) 1885system.cpu3.fetch.rateDist::2 11180 5.77% 79.39% # Number of instructions fetched each cycle (Total) 1886system.cpu3.fetch.rateDist::3 3385 1.75% 81.14% # Number of instructions fetched each cycle (Total) 1887system.cpu3.fetch.rateDist::4 629 0.32% 81.46% # Number of instructions fetched each cycle (Total) 1888system.cpu3.fetch.rateDist::5 24090 12.44% 93.90% # Number of instructions fetched each cycle (Total) 1889system.cpu3.fetch.rateDist::6 1143 0.59% 94.49% # Number of instructions fetched each cycle (Total) 1890system.cpu3.fetch.rateDist::7 1449 0.75% 95.24% # Number of instructions fetched each cycle (Total) 1891system.cpu3.fetch.rateDist::8 9221 4.76% 100.00% # Number of instructions fetched each cycle (Total) 1892system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1893system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1894system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1895system.cpu3.fetch.rateDist::total 193690 # Number of instructions fetched each cycle (Total) 1896system.cpu3.fetch.branchRate 0.292809 # Number of branch fetches per cycle 1897system.cpu3.fetch.rate 1.526069 # Number of inst fetches per cycle 1898system.cpu3.decode.IdleCycles 23670 # Number of cycles decode is idle 1899system.cpu3.decode.BlockedCycles 95373 # Number of cycles decode is blocked 1900system.cpu3.decode.RunCycles 66026 # Number of cycles decode is running 1901system.cpu3.decode.UnblockCycles 5948 # Number of cycles decode is unblocking 1902system.cpu3.decode.SquashCycles 2663 # Number of cycles decode is squashing 1903system.cpu3.decode.DecodedInsts 265184 # Number of instructions handled by decode 1904system.cpu3.rename.SquashCycles 2663 # Number of cycles rename is squashing 1905system.cpu3.rename.IdleCycles 24704 # Number of cycles rename is idle 1906system.cpu3.rename.BlockCycles 48500 # Number of cycles rename is blocking 1907system.cpu3.rename.serializeStallCycles 15195 # count of cycles rename stalled for serializing inst 1908system.cpu3.rename.RunCycles 67410 # Number of cycles rename is running 1909system.cpu3.rename.UnblockCycles 35208 # Number of cycles rename is unblocking 1910system.cpu3.rename.RenamedInsts 258083 # Number of instructions processed by rename 1911system.cpu3.rename.IQFullEvents 30956 # Number of times rename has blocked due to IQ full 1912system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full 1913system.cpu3.rename.RenamedOperands 178302 # Number of destination operands rename has renamed 1914system.cpu3.rename.RenameLookups 471983 # Number of register rename lookups that rename has made 1915system.cpu3.rename.int_rename_lookups 372133 # Number of integer rename lookups 1916system.cpu3.rename.fp_rename_lookups 28 # Number of floating rename lookups 1917system.cpu3.rename.CommittedMaps 146703 # Number of HB maps that are committed 1918system.cpu3.rename.UndoneMaps 31599 # Number of HB maps that are undone due to squashing 1919system.cpu3.rename.serializingInsts 1744 # count of serializing insts renamed 1920system.cpu3.rename.tempSerializingInsts 1884 # count of temporary serializing insts renamed 1921system.cpu3.rename.skidInsts 41025 # count of insts added to the skid buffer 1922system.cpu3.memDep0.insertedLoads 65361 # Number of loads inserted to the mem dependence unit. 1923system.cpu3.memDep0.insertedStores 28681 # Number of stores inserted to the mem dependence unit. 1924system.cpu3.memDep0.conflictingLoads 31955 # Number of conflicting loads. 1925system.cpu3.memDep0.conflictingStores 22074 # Number of conflicting stores. 1926system.cpu3.iq.iqInstsAdded 204469 # Number of instructions added to the IQ (excludes non-spec) 1927system.cpu3.iq.iqNonSpecInstsAdded 11525 # Number of non-speculative instructions added to the IQ 1928system.cpu3.iq.iqInstsIssued 207359 # Number of instructions issued 1929system.cpu3.iq.iqSquashedInstsIssued 114 # Number of squashed instructions issued 1930system.cpu3.iq.iqSquashedInstsExamined 27267 # Number of squashed instructions iterated over during squash; mainly for profiling 1931system.cpu3.iq.iqSquashedOperandsExamined 21384 # Number of squashed operands that are examined and possibly removed from graph 1932system.cpu3.iq.iqSquashedNonSpecRemoved 1390 # Number of squashed non-spec instructions that were removed 1933system.cpu3.iq.issued_per_cycle::samples 193690 # Number of insts issued each cycle 1934system.cpu3.iq.issued_per_cycle::mean 1.070572 # Number of insts issued each cycle 1935system.cpu3.iq.issued_per_cycle::stdev 1.351583 # Number of insts issued each cycle 1936system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1937system.cpu3.iq.issued_per_cycle::0 96267 49.70% 49.70% # Number of insts issued each cycle 1938system.cpu3.iq.issued_per_cycle::1 35951 18.56% 68.26% # Number of insts issued each cycle 1939system.cpu3.iq.issued_per_cycle::2 27208 14.05% 82.31% # Number of insts issued each cycle 1940system.cpu3.iq.issued_per_cycle::3 26919 13.90% 96.21% # Number of insts issued each cycle 1941system.cpu3.iq.issued_per_cycle::4 3677 1.90% 98.11% # Number of insts issued each cycle 1942system.cpu3.iq.issued_per_cycle::5 1713 0.88% 98.99% # Number of insts issued each cycle 1943system.cpu3.iq.issued_per_cycle::6 1079 0.56% 99.55% # Number of insts issued each cycle 1944system.cpu3.iq.issued_per_cycle::7 520 0.27% 99.82% # Number of insts issued each cycle 1945system.cpu3.iq.issued_per_cycle::8 356 0.18% 100.00% # Number of insts issued each cycle 1946system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1947system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1948system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1949system.cpu3.iq.issued_per_cycle::total 193690 # Number of insts issued each cycle 1950system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::IntAlu 253 45.42% 45.42% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::IntMult 0 0.00% 45.42% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::IntDiv 0 0.00% 45.42% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::FloatAdd 0 0.00% 45.42% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::FloatCmp 0 0.00% 45.42% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::FloatCvt 0 0.00% 45.42% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::FloatMult 0 0.00% 45.42% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::FloatDiv 0 0.00% 45.42% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 45.42% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdAdd 0 0.00% 45.42% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 45.42% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdAlu 0 0.00% 45.42% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdCmp 0 0.00% 45.42% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::SimdCvt 0 0.00% 45.42% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::SimdMisc 0 0.00% 45.42% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::SimdMult 0 0.00% 45.42% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 45.42% # attempts to use FU when none available 1968system.cpu3.iq.fu_full::SimdShift 0 0.00% 45.42% # attempts to use FU when none available 1969system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 45.42% # attempts to use FU when none available 1970system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 45.42% # attempts to use FU when none available 1971system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 45.42% # attempts to use FU when none available 1972system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 45.42% # attempts to use FU when none available 1973system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 45.42% # attempts to use FU when none available 1974system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 45.42% # attempts to use FU when none available 1975system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 45.42% # attempts to use FU when none available 1976system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 45.42% # attempts to use FU when none available 1977system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 45.42% # attempts to use FU when none available 1978system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.42% # attempts to use FU when none available 1979system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 45.42% # attempts to use FU when none available 1980system.cpu3.iq.fu_full::MemRead 65 11.67% 57.09% # attempts to use FU when none available 1981system.cpu3.iq.fu_full::MemWrite 239 42.91% 100.00% # attempts to use FU when none available 1982system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1983system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1984system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1985system.cpu3.iq.FU_type_0::IntAlu 106203 51.22% 51.22% # Type of FU issued 1986system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.22% # Type of FU issued 1987system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.22% # Type of FU issued 1988system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.22% # Type of FU issued 1989system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.22% # Type of FU issued 1990system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.22% # Type of FU issued 1991system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.22% # Type of FU issued 1992system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.22% # Type of FU issued 1993system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.22% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.22% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.22% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.22% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.22% # Type of FU issued 1998system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.22% # Type of FU issued 1999system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.22% # Type of FU issued 2000system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.22% # Type of FU issued 2001system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.22% # Type of FU issued 2002system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.22% # Type of FU issued 2003system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.22% # Type of FU issued 2004system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.22% # Type of FU issued 2005system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.22% # Type of FU issued 2006system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.22% # Type of FU issued 2007system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.22% # Type of FU issued 2008system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.22% # Type of FU issued 2009system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.22% # Type of FU issued 2010system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.22% # Type of FU issued 2011system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.22% # Type of FU issued 2012system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.22% # Type of FU issued 2013system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.22% # Type of FU issued 2014system.cpu3.iq.FU_type_0::MemRead 73580 35.48% 86.70% # Type of FU issued 2015system.cpu3.iq.FU_type_0::MemWrite 27576 13.30% 100.00% # Type of FU issued 2016system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2017system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2018system.cpu3.iq.FU_type_0::total 207359 # Type of FU issued 2019system.cpu3.iq.rate 1.061811 # Inst issue rate 2020system.cpu3.iq.fu_busy_cnt 557 # FU busy when requested 2021system.cpu3.iq.fu_busy_rate 0.002686 # FU busy rate (busy events/executed inst) 2022system.cpu3.iq.int_inst_queue_reads 609079 # Number of integer instruction queue reads 2023system.cpu3.iq.int_inst_queue_writes 243241 # Number of integer instruction queue writes 2024system.cpu3.iq.int_inst_queue_wakeup_accesses 202956 # Number of integer instruction queue wakeup accesses 2025system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2026system.cpu3.iq.fp_inst_queue_writes 56 # Number of floating instruction queue writes 2027system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 2028system.cpu3.iq.int_alu_accesses 207916 # Number of integer alu accesses 2029system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2030system.cpu3.iew.lsq.thread0.forwLoads 22032 # Number of loads that had data forwarded from stores 2031system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2032system.cpu3.iew.lsq.thread0.squashedLoads 4860 # Number of loads squashed 2033system.cpu3.iew.lsq.thread0.ignoredResponses 37 # Number of memory responses ignored because the instruction is squashed 2034system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations 2035system.cpu3.iew.lsq.thread0.squashedStores 2877 # Number of stores squashed 2036system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2037system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2038system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2039system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2040system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2041system.cpu3.iew.iewSquashCycles 2663 # Number of cycles IEW is squashing 2042system.cpu3.iew.iewBlockCycles 13076 # Number of cycles IEW is blocking 2043system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking 2044system.cpu3.iew.iewDispatchedInsts 249222 # Number of instructions dispatched to IQ 2045system.cpu3.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch 2046system.cpu3.iew.iewDispLoadInsts 65361 # Number of dispatched load instructions 2047system.cpu3.iew.iewDispStoreInsts 28681 # Number of dispatched store instructions 2048system.cpu3.iew.iewDispNonSpecInsts 1596 # Number of dispatched non-speculative instructions 2049system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall 2050system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2051system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations 2052system.cpu3.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly 2053system.cpu3.iew.predictedNotTakenIncorrect 2781 # Number of branches that were predicted not taken incorrectly 2054system.cpu3.iew.branchMispredicts 3236 # Number of branch mispredicts detected at execute 2055system.cpu3.iew.iewExecutedInsts 204483 # Number of executed instructions 2056system.cpu3.iew.iewExecLoadInsts 63509 # Number of load instructions executed 2057system.cpu3.iew.iewExecSquashedInsts 2876 # Number of squashed instructions skipped in execute 2058system.cpu3.iew.exec_swp 0 # number of swp insts executed 2059system.cpu3.iew.exec_nop 33228 # number of nop insts executed 2060system.cpu3.iew.exec_refs 90738 # number of memory reference insts executed 2061system.cpu3.iew.exec_branches 43690 # Number of branches executed 2062system.cpu3.iew.exec_stores 27229 # Number of stores executed 2063system.cpu3.iew.exec_rate 1.047084 # Inst execution rate 2064system.cpu3.iew.wb_sent 203493 # cumulative count of insts sent to commit 2065system.cpu3.iew.wb_count 202956 # cumulative count of insts written-back 2066system.cpu3.iew.wb_producers 108735 # num instructions producing a value 2067system.cpu3.iew.wb_consumers 116603 # num instructions consuming a value 2068system.cpu3.iew.wb_rate 1.039265 # insts written-back per cycle 2069system.cpu3.iew.wb_fanout 0.932523 # average fanout of values written-back 2070system.cpu3.commit.commitSquashedInsts 28499 # The number of squashed insts skipped by commit 2071system.cpu3.commit.commitNonSpecStalls 10135 # The number of times commit has been forced to stall to communicate backwards 2072system.cpu3.commit.branchMispredicts 2586 # The number of times a branch was mispredicted 2073system.cpu3.commit.committed_per_cycle::samples 188297 # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::mean 1.172069 # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::stdev 1.830514 # Number of insts commited each cycle 2076system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2077system.cpu3.commit.committed_per_cycle::0 105729 56.15% 56.15% # Number of insts commited each cycle 2078system.cpu3.commit.committed_per_cycle::1 39844 21.16% 77.31% # Number of insts commited each cycle 2079system.cpu3.commit.committed_per_cycle::2 5499 2.92% 80.23% # Number of insts commited each cycle 2080system.cpu3.commit.committed_per_cycle::3 10725 5.70% 85.93% # Number of insts commited each cycle 2081system.cpu3.commit.committed_per_cycle::4 1244 0.66% 86.59% # Number of insts commited each cycle 2082system.cpu3.commit.committed_per_cycle::5 22268 11.83% 98.41% # Number of insts commited each cycle 2083system.cpu3.commit.committed_per_cycle::6 755 0.40% 98.81% # Number of insts commited each cycle 2084system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.36% # Number of insts commited each cycle 2085system.cpu3.commit.committed_per_cycle::8 1203 0.64% 100.00% # Number of insts commited each cycle 2086system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2087system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2088system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2089system.cpu3.commit.committed_per_cycle::total 188297 # Number of insts commited each cycle 2090system.cpu3.commit.committedInsts 220697 # Number of instructions committed 2091system.cpu3.commit.committedOps 220697 # Number of ops (including micro ops) committed 2092system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 2093system.cpu3.commit.refs 86305 # Number of memory references committed 2094system.cpu3.commit.loads 60501 # Number of loads committed 2095system.cpu3.commit.membars 9419 # Number of memory barriers committed 2096system.cpu3.commit.branches 41182 # Number of branches committed 2097system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 2098system.cpu3.commit.int_insts 149608 # Number of committed integer instructions. 2099system.cpu3.commit.function_calls 322 # Number of function calls committed. 2100system.cpu3.commit.op_class_0::No_OpClass 31970 14.49% 14.49% # Class of committed instruction 2101system.cpu3.commit.op_class_0::IntAlu 93003 42.14% 56.63% # Class of committed instruction 2102system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.63% # Class of committed instruction 2103system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.63% # Class of committed instruction 2104system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.63% # Class of committed instruction 2105system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.63% # Class of committed instruction 2106system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.63% # Class of committed instruction 2107system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.63% # Class of committed instruction 2108system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.63% # Class of committed instruction 2109system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.63% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.63% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.63% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.63% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.63% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.63% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.63% # Class of committed instruction 2116system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.63% # Class of committed instruction 2117system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.63% # Class of committed instruction 2118system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.63% # Class of committed instruction 2119system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.63% # Class of committed instruction 2120system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.63% # Class of committed instruction 2121system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.63% # Class of committed instruction 2122system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.63% # Class of committed instruction 2123system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.63% # Class of committed instruction 2124system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.63% # Class of committed instruction 2125system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.63% # Class of committed instruction 2126system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.63% # Class of committed instruction 2127system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.63% # Class of committed instruction 2128system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.63% # Class of committed instruction 2129system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.63% # Class of committed instruction 2130system.cpu3.commit.op_class_0::MemRead 69920 31.68% 88.31% # Class of committed instruction 2131system.cpu3.commit.op_class_0::MemWrite 25804 11.69% 100.00% # Class of committed instruction 2132system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2133system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2134system.cpu3.commit.op_class_0::total 220697 # Class of committed instruction 2135system.cpu3.commit.bw_lim_events 1203 # number cycles where commit BW limit reached 2136system.cpu3.rob.rob_reads 435704 # The number of ROB reads 2137system.cpu3.rob.rob_writes 503857 # The number of ROB writes 2138system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 2139system.cpu3.idleCycles 1598 # Total number of cycles that the CPU has spent unscheduled due to idling 2140system.cpu3.quiesceCycles 47785 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2141system.cpu3.committedInsts 179308 # Number of Instructions Simulated 2142system.cpu3.committedOps 179308 # Number of Ops (including micro ops) Simulated 2143system.cpu3.cpi 1.089120 # CPI: Cycles Per Instruction 2144system.cpu3.cpi_total 1.089120 # CPI: Total CPI of All Threads 2145system.cpu3.ipc 0.918172 # IPC: Instructions Per Cycle 2146system.cpu3.ipc_total 0.918172 # IPC: Total IPC of All Threads 2147system.cpu3.int_regfile_reads 337868 # number of integer regfile reads 2148system.cpu3.int_regfile_writes 159407 # number of integer regfile writes 2149system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2150system.cpu3.misc_regfile_reads 92688 # number of misc regfile reads 2151system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2152system.cpu3.dcache.tags.replacements 0 # number of replacements 2153system.cpu3.dcache.tags.tagsinuse 25.364861 # Cycle average of tags in use 2154system.cpu3.dcache.tags.total_refs 33092 # Total number of references to valid blocks. 2155system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 2156system.cpu3.dcache.tags.avg_refs 1103.066667 # Average number of references to valid blocks. 2157system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2158system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.364861 # Average occupied blocks per requestor 2159system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049541 # Average percentage of cache occupancy 2160system.cpu3.dcache.tags.occ_percent::total 0.049541 # Average percentage of cache occupancy 2161system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 2162system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 2163system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 2164system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 2165system.cpu3.dcache.tags.tag_accesses 269290 # Number of tag accesses 2166system.cpu3.dcache.tags.data_accesses 269290 # Number of data accesses 2167system.cpu3.dcache.ReadReq_hits::cpu3.data 40990 # number of ReadReq hits 2168system.cpu3.dcache.ReadReq_hits::total 40990 # number of ReadReq hits 2169system.cpu3.dcache.WriteReq_hits::cpu3.data 25593 # number of WriteReq hits 2170system.cpu3.dcache.WriteReq_hits::total 25593 # number of WriteReq hits 2171system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 2172system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 2173system.cpu3.dcache.demand_hits::cpu3.data 66583 # number of demand (read+write) hits 2174system.cpu3.dcache.demand_hits::total 66583 # number of demand (read+write) hits 2175system.cpu3.dcache.overall_hits::cpu3.data 66583 # number of overall hits 2176system.cpu3.dcache.overall_hits::total 66583 # number of overall hits 2177system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses 2178system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses 2179system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses 2180system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses 2181system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 2182system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 2183system.cpu3.dcache.demand_misses::cpu3.data 604 # number of demand (read+write) misses 2184system.cpu3.dcache.demand_misses::total 604 # number of demand (read+write) misses 2185system.cpu3.dcache.overall_misses::cpu3.data 604 # number of overall misses 2186system.cpu3.dcache.overall_misses::total 604 # number of overall misses 2187system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7157000 # number of ReadReq miss cycles 2188system.cpu3.dcache.ReadReq_miss_latency::total 7157000 # number of ReadReq miss cycles 2189system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3001000 # number of WriteReq miss cycles 2190system.cpu3.dcache.WriteReq_miss_latency::total 3001000 # number of WriteReq miss cycles 2191system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 868000 # number of SwapReq miss cycles 2192system.cpu3.dcache.SwapReq_miss_latency::total 868000 # number of SwapReq miss cycles 2193system.cpu3.dcache.demand_miss_latency::cpu3.data 10158000 # number of demand (read+write) miss cycles 2194system.cpu3.dcache.demand_miss_latency::total 10158000 # number of demand (read+write) miss cycles 2195system.cpu3.dcache.overall_miss_latency::cpu3.data 10158000 # number of overall miss cycles 2196system.cpu3.dcache.overall_miss_latency::total 10158000 # number of overall miss cycles 2197system.cpu3.dcache.ReadReq_accesses::cpu3.data 41453 # number of ReadReq accesses(hits+misses) 2198system.cpu3.dcache.ReadReq_accesses::total 41453 # number of ReadReq accesses(hits+misses) 2199system.cpu3.dcache.WriteReq_accesses::cpu3.data 25734 # number of WriteReq accesses(hits+misses) 2200system.cpu3.dcache.WriteReq_accesses::total 25734 # number of WriteReq accesses(hits+misses) 2201system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 2202system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2203system.cpu3.dcache.demand_accesses::cpu3.data 67187 # number of demand (read+write) accesses 2204system.cpu3.dcache.demand_accesses::total 67187 # number of demand (read+write) accesses 2205system.cpu3.dcache.overall_accesses::cpu3.data 67187 # number of overall (read+write) accesses 2206system.cpu3.dcache.overall_accesses::total 67187 # number of overall (read+write) accesses 2207system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011169 # miss rate for ReadReq accesses 2208system.cpu3.dcache.ReadReq_miss_rate::total 0.011169 # miss rate for ReadReq accesses 2209system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.005479 # miss rate for WriteReq accesses 2210system.cpu3.dcache.WriteReq_miss_rate::total 0.005479 # miss rate for WriteReq accesses 2211system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 2212system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 2213system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008990 # miss rate for demand accesses 2214system.cpu3.dcache.demand_miss_rate::total 0.008990 # miss rate for demand accesses 2215system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008990 # miss rate for overall accesses 2216system.cpu3.dcache.overall_miss_rate::total 0.008990 # miss rate for overall accesses 2217system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15457.883369 # average ReadReq miss latency 2218system.cpu3.dcache.ReadReq_avg_miss_latency::total 15457.883369 # average ReadReq miss latency 2219system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21283.687943 # average WriteReq miss latency 2220system.cpu3.dcache.WriteReq_avg_miss_latency::total 21283.687943 # average WriteReq miss latency 2221system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15781.818182 # average SwapReq miss latency 2222system.cpu3.dcache.SwapReq_avg_miss_latency::total 15781.818182 # average SwapReq miss latency 2223system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency 2224system.cpu3.dcache.demand_avg_miss_latency::total 16817.880795 # average overall miss latency 2225system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency 2226system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795 # average overall miss latency 2227system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2228system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2229system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2230system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2231system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2232system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2233system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits 2234system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits 2235system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits 2236system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 2237system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 4 # number of SwapReq MSHR hits 2238system.cpu3.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits 2239system.cpu3.dcache.demand_mshr_hits::cpu3.data 326 # number of demand (read+write) MSHR hits 2240system.cpu3.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits 2241system.cpu3.dcache.overall_mshr_hits::cpu3.data 326 # number of overall MSHR hits 2242system.cpu3.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits 2243system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses 2244system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses 2245system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2246system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2247system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses 2248system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 2249system.cpu3.dcache.demand_mshr_misses::cpu3.data 278 # number of demand (read+write) MSHR misses 2250system.cpu3.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 2251system.cpu3.dcache.overall_mshr_misses::cpu3.data 278 # number of overall MSHR misses 2252system.cpu3.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses 2253system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1798500 # number of ReadReq MSHR miss cycles 2254system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles 2255system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1645500 # number of WriteReq MSHR miss cycles 2256system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1645500 # number of WriteReq MSHR miss cycles 2257system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 813000 # number of SwapReq MSHR miss cycles 2258system.cpu3.dcache.SwapReq_mshr_miss_latency::total 813000 # number of SwapReq MSHR miss cycles 2259system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3444000 # number of demand (read+write) MSHR miss cycles 2260system.cpu3.dcache.demand_mshr_miss_latency::total 3444000 # number of demand (read+write) MSHR miss cycles 2261system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3444000 # number of overall MSHR miss cycles 2262system.cpu3.dcache.overall_mshr_miss_latency::total 3444000 # number of overall MSHR miss cycles 2263system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004149 # mshr miss rate for ReadReq accesses 2264system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004149 # mshr miss rate for ReadReq accesses 2265system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004119 # mshr miss rate for WriteReq accesses 2266system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004119 # mshr miss rate for WriteReq accesses 2267system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.728571 # mshr miss rate for SwapReq accesses 2268system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.728571 # mshr miss rate for SwapReq accesses 2269system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for demand accesses 2270system.cpu3.dcache.demand_mshr_miss_rate::total 0.004138 # mshr miss rate for demand accesses 2271system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for overall accesses 2272system.cpu3.dcache.overall_mshr_miss_rate::total 0.004138 # mshr miss rate for overall accesses 2273system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10456.395349 # average ReadReq mshr miss latency 2274system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10456.395349 # average ReadReq mshr miss latency 2275system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906 # average WriteReq mshr miss latency 2276system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906 # average WriteReq mshr miss latency 2277system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471 # average SwapReq mshr miss latency 2278system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471 # average SwapReq mshr miss latency 2279system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2280system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency 2281system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2282system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency 2283system.cpu3.icache.tags.replacements 608 # number of replacements 2284system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use 2285system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. 2286system.cpu3.icache.tags.sampled_refs 743 # Sample count of references to valid blocks. 2287system.cpu3.icache.tags.avg_refs 45.095559 # Average number of references to valid blocks. 2288system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2289system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.738869 # Average occupied blocks per requestor 2290system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183084 # Average percentage of cache occupancy 2291system.cpu3.icache.tags.occ_percent::total 0.183084 # Average percentage of cache occupancy 2292system.cpu3.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 2293system.cpu3.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 2294system.cpu3.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 2295system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 2296system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id 2297system.cpu3.icache.tags.tag_accesses 35120 # Number of tag accesses 2298system.cpu3.icache.tags.data_accesses 35120 # Number of data accesses 2299system.cpu3.icache.ReadReq_hits::cpu3.inst 33506 # number of ReadReq hits 2300system.cpu3.icache.ReadReq_hits::total 33506 # number of ReadReq hits 2301system.cpu3.icache.demand_hits::cpu3.inst 33506 # number of demand (read+write) hits 2302system.cpu3.icache.demand_hits::total 33506 # number of demand (read+write) hits 2303system.cpu3.icache.overall_hits::cpu3.inst 33506 # number of overall hits 2304system.cpu3.icache.overall_hits::total 33506 # number of overall hits 2305system.cpu3.icache.ReadReq_misses::cpu3.inst 871 # number of ReadReq misses 2306system.cpu3.icache.ReadReq_misses::total 871 # number of ReadReq misses 2307system.cpu3.icache.demand_misses::cpu3.inst 871 # number of demand (read+write) misses 2308system.cpu3.icache.demand_misses::total 871 # number of demand (read+write) misses 2309system.cpu3.icache.overall_misses::cpu3.inst 871 # number of overall misses 2310system.cpu3.icache.overall_misses::total 871 # number of overall misses 2311system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11659000 # number of ReadReq miss cycles 2312system.cpu3.icache.ReadReq_miss_latency::total 11659000 # number of ReadReq miss cycles 2313system.cpu3.icache.demand_miss_latency::cpu3.inst 11659000 # number of demand (read+write) miss cycles 2314system.cpu3.icache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles 2315system.cpu3.icache.overall_miss_latency::cpu3.inst 11659000 # number of overall miss cycles 2316system.cpu3.icache.overall_miss_latency::total 11659000 # number of overall miss cycles 2317system.cpu3.icache.ReadReq_accesses::cpu3.inst 34377 # number of ReadReq accesses(hits+misses) 2318system.cpu3.icache.ReadReq_accesses::total 34377 # number of ReadReq accesses(hits+misses) 2319system.cpu3.icache.demand_accesses::cpu3.inst 34377 # number of demand (read+write) accesses 2320system.cpu3.icache.demand_accesses::total 34377 # number of demand (read+write) accesses 2321system.cpu3.icache.overall_accesses::cpu3.inst 34377 # number of overall (read+write) accesses 2322system.cpu3.icache.overall_accesses::total 34377 # number of overall (read+write) accesses 2323system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.025337 # miss rate for ReadReq accesses 2324system.cpu3.icache.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses 2325system.cpu3.icache.demand_miss_rate::cpu3.inst 0.025337 # miss rate for demand accesses 2326system.cpu3.icache.demand_miss_rate::total 0.025337 # miss rate for demand accesses 2327system.cpu3.icache.overall_miss_rate::cpu3.inst 0.025337 # miss rate for overall accesses 2328system.cpu3.icache.overall_miss_rate::total 0.025337 # miss rate for overall accesses 2329system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13385.763490 # average ReadReq miss latency 2330system.cpu3.icache.ReadReq_avg_miss_latency::total 13385.763490 # average ReadReq miss latency 2331system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency 2332system.cpu3.icache.demand_avg_miss_latency::total 13385.763490 # average overall miss latency 2333system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency 2334system.cpu3.icache.overall_avg_miss_latency::total 13385.763490 # average overall miss latency 2335system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2336system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2337system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2338system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2339system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2340system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2341system.cpu3.icache.writebacks::writebacks 608 # number of writebacks 2342system.cpu3.icache.writebacks::total 608 # number of writebacks 2343system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits 2344system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits 2345system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits 2346system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits 2347system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits 2348system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits 2349system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 743 # number of ReadReq MSHR misses 2350system.cpu3.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses 2351system.cpu3.icache.demand_mshr_misses::cpu3.inst 743 # number of demand (read+write) MSHR misses 2352system.cpu3.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses 2353system.cpu3.icache.overall_mshr_misses::cpu3.inst 743 # number of overall MSHR misses 2354system.cpu3.icache.overall_mshr_misses::total 743 # number of overall MSHR misses 2355system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10055000 # number of ReadReq MSHR miss cycles 2356system.cpu3.icache.ReadReq_mshr_miss_latency::total 10055000 # number of ReadReq MSHR miss cycles 2357system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10055000 # number of demand (read+write) MSHR miss cycles 2358system.cpu3.icache.demand_mshr_miss_latency::total 10055000 # number of demand (read+write) MSHR miss cycles 2359system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10055000 # number of overall MSHR miss cycles 2360system.cpu3.icache.overall_mshr_miss_latency::total 10055000 # number of overall MSHR miss cycles 2361system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for ReadReq accesses 2362system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021613 # mshr miss rate for ReadReq accesses 2363system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for demand accesses 2364system.cpu3.icache.demand_mshr_miss_rate::total 0.021613 # mshr miss rate for demand accesses 2365system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for overall accesses 2366system.cpu3.icache.overall_mshr_miss_rate::total 0.021613 # mshr miss rate for overall accesses 2367system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average ReadReq mshr miss latency 2368system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428 # average ReadReq mshr miss latency 2369system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2370system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency 2371system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2372system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency 2373system.l2c.tags.replacements 0 # number of replacements 2374system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use 2375system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. 2376system.l2c.tags.sampled_refs 581 # Sample count of references to valid blocks. 2377system.l2c.tags.avg_refs 5.330465 # Average number of references to valid blocks. 2378system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2379system.l2c.tags.occ_blocks::writebacks 0.811695 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu0.inst 303.236105 # Average occupied blocks per requestor 2381system.l2c.tags.occ_blocks::cpu0.data 58.939439 # Average occupied blocks per requestor 2382system.l2c.tags.occ_blocks::cpu1.inst 17.006196 # Average occupied blocks per requestor 2383system.l2c.tags.occ_blocks::cpu1.data 1.379366 # Average occupied blocks per requestor 2384system.l2c.tags.occ_blocks::cpu2.inst 67.599671 # Average occupied blocks per requestor 2385system.l2c.tags.occ_blocks::cpu2.data 5.915132 # Average occupied blocks per requestor 2386system.l2c.tags.occ_blocks::cpu3.inst 1.812120 # Average occupied blocks per requestor 2387system.l2c.tags.occ_blocks::cpu3.data 1.862482 # Average occupied blocks per requestor 2388system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2389system.l2c.tags.occ_percent::cpu0.inst 0.004627 # Average percentage of cache occupancy 2390system.l2c.tags.occ_percent::cpu0.data 0.000899 # Average percentage of cache occupancy 2391system.l2c.tags.occ_percent::cpu1.inst 0.000259 # Average percentage of cache occupancy 2392system.l2c.tags.occ_percent::cpu1.data 0.000021 # Average percentage of cache occupancy 2393system.l2c.tags.occ_percent::cpu2.inst 0.001031 # Average percentage of cache occupancy 2394system.l2c.tags.occ_percent::cpu2.data 0.000090 # Average percentage of cache occupancy 2395system.l2c.tags.occ_percent::cpu3.inst 0.000028 # Average percentage of cache occupancy 2396system.l2c.tags.occ_percent::cpu3.data 0.000028 # Average percentage of cache occupancy 2397system.l2c.tags.occ_percent::total 0.006997 # Average percentage of cache occupancy 2398system.l2c.tags.occ_task_id_blocks::1024 581 # Occupied blocks per task id 2399system.l2c.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 2400system.l2c.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 2401system.l2c.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id 2402system.l2c.tags.occ_task_id_percent::1024 0.008865 # Percentage of cache occupancy per task id 2403system.l2c.tags.tag_accesses 32091 # Number of tag accesses 2404system.l2c.tags.data_accesses 32091 # Number of data accesses 2405system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 2406system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 2407system.l2c.WritebackClean_hits::writebacks 751 # number of WritebackClean hits 2408system.l2c.WritebackClean_hits::total 751 # number of WritebackClean hits 2409system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2410system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2411system.l2c.ReadCleanReq_hits::cpu0.inst 329 # number of ReadCleanReq hits 2412system.l2c.ReadCleanReq_hits::cpu1.inst 654 # number of ReadCleanReq hits 2413system.l2c.ReadCleanReq_hits::cpu2.inst 595 # number of ReadCleanReq hits 2414system.l2c.ReadCleanReq_hits::cpu3.inst 735 # number of ReadCleanReq hits 2415system.l2c.ReadCleanReq_hits::total 2313 # number of ReadCleanReq hits 2416system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 2417system.l2c.ReadSharedReq_hits::cpu1.data 11 # number of ReadSharedReq hits 2418system.l2c.ReadSharedReq_hits::cpu2.data 5 # number of ReadSharedReq hits 2419system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 2420system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 2421system.l2c.demand_hits::cpu0.inst 329 # number of demand (read+write) hits 2422system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2423system.l2c.demand_hits::cpu1.inst 654 # number of demand (read+write) hits 2424system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 2425system.l2c.demand_hits::cpu2.inst 595 # number of demand (read+write) hits 2426system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 2427system.l2c.demand_hits::cpu3.inst 735 # number of demand (read+write) hits 2428system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2429system.l2c.demand_hits::total 2345 # number of demand (read+write) hits 2430system.l2c.overall_hits::cpu0.inst 329 # number of overall hits 2431system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2432system.l2c.overall_hits::cpu1.inst 654 # number of overall hits 2433system.l2c.overall_hits::cpu1.data 11 # number of overall hits 2434system.l2c.overall_hits::cpu2.inst 595 # number of overall hits 2435system.l2c.overall_hits::cpu2.data 5 # number of overall hits 2436system.l2c.overall_hits::cpu3.inst 735 # number of overall hits 2437system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2438system.l2c.overall_hits::total 2345 # number of overall hits 2439system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses 2440system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 2441system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses 2442system.l2c.UpgradeReq_misses::cpu3.data 24 # number of UpgradeReq misses 2443system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses 2444system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2445system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 2446system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 2447system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2448system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2449system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses 2450system.l2c.ReadCleanReq_misses::cpu1.inst 28 # number of ReadCleanReq misses 2451system.l2c.ReadCleanReq_misses::cpu2.inst 99 # number of ReadCleanReq misses 2452system.l2c.ReadCleanReq_misses::cpu3.inst 8 # number of ReadCleanReq misses 2453system.l2c.ReadCleanReq_misses::total 512 # number of ReadCleanReq misses 2454system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses 2455system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses 2456system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses 2457system.l2c.ReadSharedReq_misses::cpu3.data 3 # number of ReadSharedReq misses 2458system.l2c.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses 2459system.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu1.inst 28 # number of demand (read+write) misses 2462system.l2c.demand_misses::cpu1.data 14 # number of demand (read+write) misses 2463system.l2c.demand_misses::cpu2.inst 99 # number of demand (read+write) misses 2464system.l2c.demand_misses::cpu2.data 21 # number of demand (read+write) misses 2465system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses 2466system.l2c.demand_misses::cpu3.data 15 # number of demand (read+write) misses 2467system.l2c.demand_misses::total 732 # number of demand (read+write) misses 2468system.l2c.overall_misses::cpu0.inst 377 # number of overall misses 2469system.l2c.overall_misses::cpu0.data 170 # number of overall misses 2470system.l2c.overall_misses::cpu1.inst 28 # number of overall misses 2471system.l2c.overall_misses::cpu1.data 14 # number of overall misses 2472system.l2c.overall_misses::cpu2.inst 99 # number of overall misses 2473system.l2c.overall_misses::cpu2.data 21 # number of overall misses 2474system.l2c.overall_misses::cpu3.inst 8 # number of overall misses 2475system.l2c.overall_misses::cpu3.data 15 # number of overall misses 2476system.l2c.overall_misses::total 732 # number of overall misses 2477system.l2c.ReadExReq_miss_latency::cpu0.data 7972500 # number of ReadExReq miss cycles 2478system.l2c.ReadExReq_miss_latency::cpu1.data 902000 # number of ReadExReq miss cycles 2479system.l2c.ReadExReq_miss_latency::cpu2.data 1048000 # number of ReadExReq miss cycles 2480system.l2c.ReadExReq_miss_latency::cpu3.data 927000 # number of ReadExReq miss cycles 2481system.l2c.ReadExReq_miss_latency::total 10849500 # number of ReadExReq miss cycles 2482system.l2c.ReadCleanReq_miss_latency::cpu0.inst 29037500 # number of ReadCleanReq miss cycles 2483system.l2c.ReadCleanReq_miss_latency::cpu1.inst 2384000 # number of ReadCleanReq miss cycles 2484system.l2c.ReadCleanReq_miss_latency::cpu2.inst 7728000 # number of ReadCleanReq miss cycles 2485system.l2c.ReadCleanReq_miss_latency::cpu3.inst 627500 # number of ReadCleanReq miss cycles 2486system.l2c.ReadCleanReq_miss_latency::total 39777000 # number of ReadCleanReq miss cycles 2487system.l2c.ReadSharedReq_miss_latency::cpu0.data 6533500 # number of ReadSharedReq miss cycles 2488system.l2c.ReadSharedReq_miss_latency::cpu1.data 165500 # number of ReadSharedReq miss cycles 2489system.l2c.ReadSharedReq_miss_latency::cpu2.data 634500 # number of ReadSharedReq miss cycles 2490system.l2c.ReadSharedReq_miss_latency::cpu3.data 262000 # number of ReadSharedReq miss cycles 2491system.l2c.ReadSharedReq_miss_latency::total 7595500 # number of ReadSharedReq miss cycles 2492system.l2c.demand_miss_latency::cpu0.inst 29037500 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::cpu0.data 14506000 # number of demand (read+write) miss cycles 2494system.l2c.demand_miss_latency::cpu1.inst 2384000 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu1.data 1067500 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu2.inst 7728000 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu2.data 1682500 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu3.inst 627500 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu3.data 1189000 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::total 58222000 # number of demand (read+write) miss cycles 2501system.l2c.overall_miss_latency::cpu0.inst 29037500 # number of overall miss cycles 2502system.l2c.overall_miss_latency::cpu0.data 14506000 # number of overall miss cycles 2503system.l2c.overall_miss_latency::cpu1.inst 2384000 # number of overall miss cycles 2504system.l2c.overall_miss_latency::cpu1.data 1067500 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu2.inst 7728000 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu2.data 1682500 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu3.inst 627500 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu3.data 1189000 # number of overall miss cycles 2509system.l2c.overall_miss_latency::total 58222000 # number of overall miss cycles 2510system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 2511system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 2512system.l2c.WritebackClean_accesses::writebacks 751 # number of WritebackClean accesses(hits+misses) 2513system.l2c.WritebackClean_accesses::total 751 # number of WritebackClean accesses(hits+misses) 2514system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) 2515system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 2516system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses) 2517system.l2c.UpgradeReq_accesses::cpu3.data 24 # number of UpgradeReq accesses(hits+misses) 2518system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) 2519system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2520system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 2521system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 2522system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2523system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2524system.l2c.ReadCleanReq_accesses::cpu0.inst 706 # number of ReadCleanReq accesses(hits+misses) 2525system.l2c.ReadCleanReq_accesses::cpu1.inst 682 # number of ReadCleanReq accesses(hits+misses) 2526system.l2c.ReadCleanReq_accesses::cpu2.inst 694 # number of ReadCleanReq accesses(hits+misses) 2527system.l2c.ReadCleanReq_accesses::cpu3.inst 743 # number of ReadCleanReq accesses(hits+misses) 2528system.l2c.ReadCleanReq_accesses::total 2825 # number of ReadCleanReq accesses(hits+misses) 2529system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses) 2530system.l2c.ReadSharedReq_accesses::cpu1.data 13 # number of ReadSharedReq accesses(hits+misses) 2531system.l2c.ReadSharedReq_accesses::cpu2.data 13 # number of ReadSharedReq accesses(hits+misses) 2532system.l2c.ReadSharedReq_accesses::cpu3.data 14 # number of ReadSharedReq accesses(hits+misses) 2533system.l2c.ReadSharedReq_accesses::total 121 # number of ReadSharedReq accesses(hits+misses) 2534system.l2c.demand_accesses::cpu0.inst 706 # number of demand (read+write) accesses 2535system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses 2536system.l2c.demand_accesses::cpu1.inst 682 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu2.inst 694 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu3.inst 743 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::total 3077 # number of demand (read+write) accesses 2543system.l2c.overall_accesses::cpu0.inst 706 # number of overall (read+write) accesses 2544system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses 2545system.l2c.overall_accesses::cpu1.inst 682 # number of overall (read+write) accesses 2546system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 2547system.l2c.overall_accesses::cpu2.inst 694 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu3.inst 743 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::total 3077 # number of overall (read+write) accesses 2552system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses 2553system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2554system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2555system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2556system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses 2557system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2558system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2559system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2560system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2561system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2562system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.533994 # miss rate for ReadCleanReq accesses 2563system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.041056 # miss rate for ReadCleanReq accesses 2564system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.142651 # miss rate for ReadCleanReq accesses 2565system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010767 # miss rate for ReadCleanReq accesses 2566system.l2c.ReadCleanReq_miss_rate::total 0.181239 # miss rate for ReadCleanReq accesses 2567system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses 2568system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.153846 # miss rate for ReadSharedReq accesses 2569system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.615385 # miss rate for ReadSharedReq accesses 2570system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.214286 # miss rate for ReadSharedReq accesses 2571system.l2c.ReadSharedReq_miss_rate::total 0.735537 # miss rate for ReadSharedReq accesses 2572system.l2c.demand_miss_rate::cpu0.inst 0.533994 # miss rate for demand accesses 2573system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses 2574system.l2c.demand_miss_rate::cpu1.inst 0.041056 # miss rate for demand accesses 2575system.l2c.demand_miss_rate::cpu1.data 0.560000 # miss rate for demand accesses 2576system.l2c.demand_miss_rate::cpu2.inst 0.142651 # miss rate for demand accesses 2577system.l2c.demand_miss_rate::cpu2.data 0.807692 # miss rate for demand accesses 2578system.l2c.demand_miss_rate::cpu3.inst 0.010767 # miss rate for demand accesses 2579system.l2c.demand_miss_rate::cpu3.data 0.576923 # miss rate for demand accesses 2580system.l2c.demand_miss_rate::total 0.237894 # miss rate for demand accesses 2581system.l2c.overall_miss_rate::cpu0.inst 0.533994 # miss rate for overall accesses 2582system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses 2583system.l2c.overall_miss_rate::cpu1.inst 0.041056 # miss rate for overall accesses 2584system.l2c.overall_miss_rate::cpu1.data 0.560000 # miss rate for overall accesses 2585system.l2c.overall_miss_rate::cpu2.inst 0.142651 # miss rate for overall accesses 2586system.l2c.overall_miss_rate::cpu2.data 0.807692 # miss rate for overall accesses 2587system.l2c.overall_miss_rate::cpu3.inst 0.010767 # miss rate for overall accesses 2588system.l2c.overall_miss_rate::cpu3.data 0.576923 # miss rate for overall accesses 2589system.l2c.overall_miss_rate::total 0.237894 # miss rate for overall accesses 2590system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84813.829787 # average ReadExReq miss latency 2591system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75166.666667 # average ReadExReq miss latency 2592system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80615.384615 # average ReadExReq miss latency 2593system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77250 # average ReadExReq miss latency 2594system.l2c.ReadExReq_avg_miss_latency::total 82820.610687 # average ReadExReq miss latency 2595system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77022.546419 # average ReadCleanReq miss latency 2596system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85142.857143 # average ReadCleanReq miss latency 2597system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 78060.606061 # average ReadCleanReq miss latency 2598system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 78437.500000 # average ReadCleanReq miss latency 2599system.l2c.ReadCleanReq_avg_miss_latency::total 77689.453125 # average ReadCleanReq miss latency 2600system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 85967.105263 # average ReadSharedReq miss latency 2601system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82750 # average ReadSharedReq miss latency 2602system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 79312.500000 # average ReadSharedReq miss latency 2603system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 87333.333333 # average ReadSharedReq miss latency 2604system.l2c.ReadSharedReq_avg_miss_latency::total 85342.696629 # average ReadSharedReq miss latency 2605system.l2c.demand_avg_miss_latency::cpu0.inst 77022.546419 # average overall miss latency 2606system.l2c.demand_avg_miss_latency::cpu0.data 85329.411765 # average overall miss latency 2607system.l2c.demand_avg_miss_latency::cpu1.inst 85142.857143 # average overall miss latency 2608system.l2c.demand_avg_miss_latency::cpu1.data 76250 # average overall miss latency 2609system.l2c.demand_avg_miss_latency::cpu2.inst 78060.606061 # average overall miss latency 2610system.l2c.demand_avg_miss_latency::cpu2.data 80119.047619 # average overall miss latency 2611system.l2c.demand_avg_miss_latency::cpu3.inst 78437.500000 # average overall miss latency 2612system.l2c.demand_avg_miss_latency::cpu3.data 79266.666667 # average overall miss latency 2613system.l2c.demand_avg_miss_latency::total 79538.251366 # average overall miss latency 2614system.l2c.overall_avg_miss_latency::cpu0.inst 77022.546419 # average overall miss latency 2615system.l2c.overall_avg_miss_latency::cpu0.data 85329.411765 # average overall miss latency 2616system.l2c.overall_avg_miss_latency::cpu1.inst 85142.857143 # average overall miss latency 2617system.l2c.overall_avg_miss_latency::cpu1.data 76250 # average overall miss latency 2618system.l2c.overall_avg_miss_latency::cpu2.inst 78060.606061 # average overall miss latency 2619system.l2c.overall_avg_miss_latency::cpu2.data 80119.047619 # average overall miss latency 2620system.l2c.overall_avg_miss_latency::cpu3.inst 78437.500000 # average overall miss latency 2621system.l2c.overall_avg_miss_latency::cpu3.data 79266.666667 # average overall miss latency 2622system.l2c.overall_avg_miss_latency::total 79538.251366 # average overall miss latency 2623system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2624system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2625system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2626system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2627system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2628system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2629system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2630system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2631system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits 2632system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits 2633system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits 2634system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2635system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2636system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits 2637system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits 2638system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 2639system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2640system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2641system.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits 2642system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits 2643system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits 2644system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses 2645system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses 2646system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses 2647system.l2c.UpgradeReq_mshr_misses::cpu3.data 24 # number of UpgradeReq MSHR misses 2648system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses 2649system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2650system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 2651system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 2652system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2653system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2654system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses 2655system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 24 # number of ReadCleanReq MSHR misses 2656system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 91 # number of ReadCleanReq MSHR misses 2657system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 4 # number of ReadCleanReq MSHR misses 2658system.l2c.ReadCleanReq_mshr_misses::total 495 # number of ReadCleanReq MSHR misses 2659system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses 2660system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2 # number of ReadSharedReq MSHR misses 2661system.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses 2662system.l2c.ReadSharedReq_mshr_misses::cpu3.data 3 # number of ReadSharedReq MSHR misses 2663system.l2c.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses 2664system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses 2666system.l2c.demand_mshr_misses::cpu1.inst 24 # number of demand (read+write) MSHR misses 2667system.l2c.demand_mshr_misses::cpu1.data 14 # number of demand (read+write) MSHR misses 2668system.l2c.demand_mshr_misses::cpu2.inst 91 # number of demand (read+write) MSHR misses 2669system.l2c.demand_mshr_misses::cpu2.data 21 # number of demand (read+write) MSHR misses 2670system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 2671system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses 2672system.l2c.demand_mshr_misses::total 715 # number of demand (read+write) MSHR misses 2673system.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses 2675system.l2c.overall_mshr_misses::cpu1.inst 24 # number of overall MSHR misses 2676system.l2c.overall_mshr_misses::cpu1.data 14 # number of overall MSHR misses 2677system.l2c.overall_mshr_misses::cpu2.inst 91 # number of overall MSHR misses 2678system.l2c.overall_mshr_misses::cpu2.data 21 # number of overall MSHR misses 2679system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses 2680system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses 2681system.l2c.overall_mshr_misses::total 715 # number of overall MSHR misses 2682system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437500 # number of UpgradeReq MSHR miss cycles 2683system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 380000 # number of UpgradeReq MSHR miss cycles 2684system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 419000 # number of UpgradeReq MSHR miss cycles 2685system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457000 # number of UpgradeReq MSHR miss cycles 2686system.l2c.UpgradeReq_mshr_miss_latency::total 1693500 # number of UpgradeReq MSHR miss cycles 2687system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7032500 # number of ReadExReq MSHR miss cycles 2688system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 782000 # number of ReadExReq MSHR miss cycles 2689system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 918000 # number of ReadExReq MSHR miss cycles 2690system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807000 # number of ReadExReq MSHR miss cycles 2691system.l2c.ReadExReq_mshr_miss_latency::total 9539500 # number of ReadExReq MSHR miss cycles 2692system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25253500 # number of ReadCleanReq MSHR miss cycles 2693system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1934500 # number of ReadCleanReq MSHR miss cycles 2694system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 6358500 # number of ReadCleanReq MSHR miss cycles 2695system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 309500 # number of ReadCleanReq MSHR miss cycles 2696system.l2c.ReadCleanReq_mshr_miss_latency::total 33856000 # number of ReadCleanReq MSHR miss cycles 2697system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5773500 # number of ReadSharedReq MSHR miss cycles 2698system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 145500 # number of ReadSharedReq MSHR miss cycles 2699system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 554500 # number of ReadSharedReq MSHR miss cycles 2700system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 232000 # number of ReadSharedReq MSHR miss cycles 2701system.l2c.ReadSharedReq_mshr_miss_latency::total 6705500 # number of ReadSharedReq MSHR miss cycles 2702system.l2c.demand_mshr_miss_latency::cpu0.inst 25253500 # number of demand (read+write) MSHR miss cycles 2703system.l2c.demand_mshr_miss_latency::cpu0.data 12806000 # number of demand (read+write) MSHR miss cycles 2704system.l2c.demand_mshr_miss_latency::cpu1.inst 1934500 # number of demand (read+write) MSHR miss cycles 2705system.l2c.demand_mshr_miss_latency::cpu1.data 927500 # number of demand (read+write) MSHR miss cycles 2706system.l2c.demand_mshr_miss_latency::cpu2.inst 6358500 # number of demand (read+write) MSHR miss cycles 2707system.l2c.demand_mshr_miss_latency::cpu2.data 1472500 # number of demand (read+write) MSHR miss cycles 2708system.l2c.demand_mshr_miss_latency::cpu3.inst 309500 # number of demand (read+write) MSHR miss cycles 2709system.l2c.demand_mshr_miss_latency::cpu3.data 1039000 # number of demand (read+write) MSHR miss cycles 2710system.l2c.demand_mshr_miss_latency::total 50101000 # number of demand (read+write) MSHR miss cycles 2711system.l2c.overall_mshr_miss_latency::cpu0.inst 25253500 # number of overall MSHR miss cycles 2712system.l2c.overall_mshr_miss_latency::cpu0.data 12806000 # number of overall MSHR miss cycles 2713system.l2c.overall_mshr_miss_latency::cpu1.inst 1934500 # number of overall MSHR miss cycles 2714system.l2c.overall_mshr_miss_latency::cpu1.data 927500 # number of overall MSHR miss cycles 2715system.l2c.overall_mshr_miss_latency::cpu2.inst 6358500 # number of overall MSHR miss cycles 2716system.l2c.overall_mshr_miss_latency::cpu2.data 1472500 # number of overall MSHR miss cycles 2717system.l2c.overall_mshr_miss_latency::cpu3.inst 309500 # number of overall MSHR miss cycles 2718system.l2c.overall_mshr_miss_latency::cpu3.data 1039000 # number of overall MSHR miss cycles 2719system.l2c.overall_mshr_miss_latency::total 50101000 # number of overall MSHR miss cycles 2720system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses 2721system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2722system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2723system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2724system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses 2725system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2726system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2727system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2728system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2729system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2730system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for ReadCleanReq accesses 2731system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for ReadCleanReq accesses 2732system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for ReadCleanReq accesses 2733system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for ReadCleanReq accesses 2734system.l2c.ReadCleanReq_mshr_miss_rate::total 0.175221 # mshr miss rate for ReadCleanReq accesses 2735system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses 2736system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153846 # mshr miss rate for ReadSharedReq accesses 2737system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.615385 # mshr miss rate for ReadSharedReq accesses 2738system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286 # mshr miss rate for ReadSharedReq accesses 2739system.l2c.ReadSharedReq_mshr_miss_rate::total 0.735537 # mshr miss rate for ReadSharedReq accesses 2740system.l2c.demand_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for demand accesses 2741system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses 2742system.l2c.demand_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for demand accesses 2743system.l2c.demand_mshr_miss_rate::cpu1.data 0.560000 # mshr miss rate for demand accesses 2744system.l2c.demand_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for demand accesses 2745system.l2c.demand_mshr_miss_rate::cpu2.data 0.807692 # mshr miss rate for demand accesses 2746system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for demand accesses 2747system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for demand accesses 2748system.l2c.demand_mshr_miss_rate::total 0.232369 # mshr miss rate for demand accesses 2749system.l2c.overall_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for overall accesses 2750system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses 2751system.l2c.overall_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for overall accesses 2752system.l2c.overall_mshr_miss_rate::cpu1.data 0.560000 # mshr miss rate for overall accesses 2753system.l2c.overall_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for overall accesses 2754system.l2c.overall_mshr_miss_rate::cpu2.data 0.807692 # mshr miss rate for overall accesses 2755system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for overall accesses 2756system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for overall accesses 2757system.l2c.overall_mshr_miss_rate::total 0.232369 # mshr miss rate for overall accesses 2758system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19021.739130 # average UpgradeReq mshr miss latency 2759system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19000 # average UpgradeReq mshr miss latency 2760system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19045.454545 # average UpgradeReq mshr miss latency 2761system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19041.666667 # average UpgradeReq mshr miss latency 2762system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19028.089888 # average UpgradeReq mshr miss latency 2763system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74813.829787 # average ReadExReq mshr miss latency 2764system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65166.666667 # average ReadExReq mshr miss latency 2765system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70615.384615 # average ReadExReq mshr miss latency 2766system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67250 # average ReadExReq mshr miss latency 2767system.l2c.ReadExReq_avg_mshr_miss_latency::total 72820.610687 # average ReadExReq mshr miss latency 2768system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average ReadCleanReq mshr miss latency 2769system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average ReadCleanReq mshr miss latency 2770system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average ReadCleanReq mshr miss latency 2771system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 77375 # average ReadCleanReq mshr miss latency 2772system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68395.959596 # average ReadCleanReq mshr miss latency 2773system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 75967.105263 # average ReadSharedReq mshr miss latency 2774system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72750 # average ReadSharedReq mshr miss latency 2775system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 69312.500000 # average ReadSharedReq mshr miss latency 2776system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 77333.333333 # average ReadSharedReq mshr miss latency 2777system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75342.696629 # average ReadSharedReq mshr miss latency 2778system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency 2779system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency 2780system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency 2781system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency 2782system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency 2783system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency 2784system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency 2785system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency 2786system.l2c.demand_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency 2787system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency 2788system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency 2789system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency 2790system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency 2791system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency 2792system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency 2793system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency 2794system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency 2795system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency 2796system.membus.trans_dist::ReadResp 583 # Transaction distribution 2797system.membus.trans_dist::UpgradeReq 286 # Transaction distribution 2798system.membus.trans_dist::ReadExReq 182 # Transaction distribution 2799system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2800system.membus.trans_dist::ReadSharedReq 583 # Transaction distribution 2801system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1765 # Packet count per connected master and slave (bytes) 2802system.membus.pkt_count::total 1765 # Packet count per connected master and slave (bytes) 2803system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45696 # Cumulative packet size per connected master and slave (bytes) 2804system.membus.pkt_size::total 45696 # Cumulative packet size per connected master and slave (bytes) 2805system.membus.snoops 248 # Total snoops (count) 2806system.membus.snoop_fanout::samples 1051 # Request fanout histogram 2807system.membus.snoop_fanout::mean 0 # Request fanout histogram 2808system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2809system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2810system.membus.snoop_fanout::0 1051 100.00% 100.00% # Request fanout histogram 2811system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2812system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2813system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2814system.membus.snoop_fanout::max_value 0 # Request fanout histogram 2815system.membus.snoop_fanout::total 1051 # Request fanout histogram 2816system.membus.reqLayer0.occupancy 998006 # Layer occupancy (ticks) 2817system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 2818system.membus.respLayer1.occupancy 3803500 # Layer occupancy (ticks) 2819system.membus.respLayer1.utilization 3.0 # Layer utilization (%) 2820system.toL2Bus.snoop_filter.tot_requests 6324 # Total number of requests made to the snoop filter. 2821system.toL2Bus.snoop_filter.hit_single_requests 1712 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2822system.toL2Bus.snoop_filter.hit_multi_requests 3265 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2823system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2824system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2825system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2826system.toL2Bus.trans_dist::ReadResp 3513 # Transaction distribution 2827system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution 2828system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 2829system.toL2Bus.trans_dist::WritebackClean 2114 # Transaction distribution 2830system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 2831system.toL2Bus.trans_dist::UpgradeReq 289 # Transaction distribution 2832system.toL2Bus.trans_dist::UpgradeResp 289 # Transaction distribution 2833system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution 2834system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution 2835system.toL2Bus.trans_dist::ReadCleanReq 2825 # Transaction distribution 2836system.toL2Bus.trans_dist::ReadSharedReq 695 # Transaction distribution 2837system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1814 # Packet count per connected master and slave (bytes) 2838system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) 2839system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1912 # Packet count per connected master and slave (bytes) 2840system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) 2841system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1943 # Packet count per connected master and slave (bytes) 2842system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) 2843system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2094 # Packet count per connected master and slave (bytes) 2844system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) 2845system.toL2Bus.pkt_count::total 9492 # Packet count per connected master and slave (bytes) 2846system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 70912 # Cumulative packet size per connected master and slave (bytes) 2847system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) 2848system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 78720 # Cumulative packet size per connected master and slave (bytes) 2849system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2850system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79936 # Cumulative packet size per connected master and slave (bytes) 2851system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 2852system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) 2853system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 2854system.toL2Bus.pkt_size::total 332224 # Cumulative packet size per connected master and slave (bytes) 2855system.toL2Bus.snoops 1039 # Total snoops (count) 2856system.toL2Bus.snoop_fanout::samples 4208 # Request fanout histogram 2857system.toL2Bus.snoop_fanout::mean 1.288736 # Request fanout histogram 2858system.toL2Bus.snoop_fanout::stdev 1.116485 # Request fanout histogram 2859system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2860system.toL2Bus.snoop_fanout::0 1347 32.01% 32.01% # Request fanout histogram 2861system.toL2Bus.snoop_fanout::1 1142 27.14% 59.15% # Request fanout histogram 2862system.toL2Bus.snoop_fanout::2 876 20.82% 79.97% # Request fanout histogram 2863system.toL2Bus.snoop_fanout::3 843 20.03% 100.00% # Request fanout histogram 2864system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2865system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 2866system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 2867system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 2868system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2869system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2870system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2871system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2872system.toL2Bus.snoop_fanout::total 4208 # Request fanout histogram 2873system.toL2Bus.reqLayer0.occupancy 5296461 # Layer occupancy (ticks) 2874system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) 2875system.toL2Bus.respLayer0.occupancy 1058997 # Layer occupancy (ticks) 2876system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 2877system.toL2Bus.respLayer1.occupancy 523496 # Layer occupancy (ticks) 2878system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 2879system.toL2Bus.respLayer2.occupancy 1025493 # Layer occupancy (ticks) 2880system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) 2881system.toL2Bus.respLayer3.occupancy 437958 # Layer occupancy (ticks) 2882system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) 2883system.toL2Bus.respLayer4.occupancy 1044987 # Layer occupancy (ticks) 2884system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) 2885system.toL2Bus.respLayer5.occupancy 431472 # Layer occupancy (ticks) 2886system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) 2887system.toL2Bus.respLayer6.occupancy 1116994 # Layer occupancy (ticks) 2888system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) 2889system.toL2Bus.respLayer7.occupancy 444965 # Layer occupancy (ticks) 2890system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) 2891 2892---------- End Simulation Statistics ---------- | |