| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000126 # Number of seconds simulated 4sim_ticks 125889000 # Number of ticks simulated 5final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000126 # Number of seconds simulated 4sim_ticks 125889000 # Number of ticks simulated 5final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 271253 # Simulator instruction rate (inst/s) 8host_op_rate 271253 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29155299 # Simulator tick rate (ticks/s) 10host_mem_usage 267160 # Number of bytes of host memory used 11host_seconds 4.32 # Real time elapsed on the host | 7host_inst_rate 196054 # Simulator instruction rate (inst/s) 8host_op_rate 196054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21072637 # Simulator tick rate (ticks/s) 10host_mem_usage 267156 # Number of bytes of host memory used 11host_seconds 5.97 # Real time elapsed on the host |
| 12sim_insts 1171234 # Number of instructions simulated 13sim_ops 1171234 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 1536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 896 # Number of bytes read from this memory --- 641 unchanged lines hidden (view full) --- 661system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency 662system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433 # average overall miss latency 663system.cpu0.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked 664system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked 666system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked 668system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 1171234 # Number of instructions simulated 13sim_ops 1171234 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 1536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 896 # Number of bytes read from this memory --- 641 unchanged lines hidden (view full) --- 661system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency 662system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433 # average overall miss latency 663system.cpu0.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked 664system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked 666system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked 668system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 669system.cpu0.dcache.fast_writes 0 # number of fast writes performed 670system.cpu0.dcache.cache_copies 0 # number of cache copies performed | |
| 671system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 672system.cpu0.dcache.writebacks::total 1 # number of writebacks 673system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits 674system.cpu0.dcache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits 675system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 386 # number of WriteReq MSHR hits 676system.cpu0.dcache.WriteReq_mshr_hits::total 386 # number of WriteReq MSHR hits 677system.cpu0.dcache.demand_mshr_hits::cpu0.data 766 # number of demand (read+write) MSHR hits 678system.cpu0.dcache.demand_mshr_hits::total 766 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 713system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602 # average WriteReq mshr miss latency 714system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602 # average WriteReq mshr miss latency 715system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783 # average SwapReq mshr miss latency 716system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783 # average SwapReq mshr miss latency 717system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 718system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency 719system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 720system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency | 669system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 670system.cpu0.dcache.writebacks::total 1 # number of writebacks 671system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits 672system.cpu0.dcache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits 673system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 386 # number of WriteReq MSHR hits 674system.cpu0.dcache.WriteReq_mshr_hits::total 386 # number of WriteReq MSHR hits 675system.cpu0.dcache.demand_mshr_hits::cpu0.data 766 # number of demand (read+write) MSHR hits 676system.cpu0.dcache.demand_mshr_hits::total 766 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 711system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602 # average WriteReq mshr miss latency 712system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602 # average WriteReq mshr miss latency 713system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783 # average SwapReq mshr miss latency 714system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783 # average SwapReq mshr miss latency 715system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 716system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency 717system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency 718system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency |
| 721system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 722system.cpu0.icache.tags.replacements 403 # number of replacements 723system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use 724system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. 725system.cpu0.icache.tags.sampled_refs 705 # Sample count of references to valid blocks. 726system.cpu0.icache.tags.avg_refs 10.113475 # Average number of references to valid blocks. 727system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 728system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.059263 # Average occupied blocks per requestor 729system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490350 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 772system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency 773system.cpu0.icache.overall_avg_miss_latency::total 47689.467970 # average overall miss latency 774system.cpu0.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked 775system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 776system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked 777system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 778system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked 779system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 719system.cpu0.icache.tags.replacements 403 # number of replacements 720system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use 721system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. 722system.cpu0.icache.tags.sampled_refs 705 # Sample count of references to valid blocks. 723system.cpu0.icache.tags.avg_refs 10.113475 # Average number of references to valid blocks. 724system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 725system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.059263 # Average occupied blocks per requestor 726system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490350 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 769system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency 770system.cpu0.icache.overall_avg_miss_latency::total 47689.467970 # average overall miss latency 771system.cpu0.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked 772system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked 774system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 775system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked 776system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 780system.cpu0.icache.fast_writes 0 # number of fast writes performed 781system.cpu0.icache.cache_copies 0 # number of cache copies performed | |
| 782system.cpu0.icache.writebacks::writebacks 403 # number of writebacks 783system.cpu0.icache.writebacks::total 403 # number of writebacks 784system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits 785system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 786system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits 787system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 788system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits 789system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 806system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for overall accesses 807system.cpu0.icache.overall_mshr_miss_rate::total 0.087691 # mshr miss rate for overall accesses 808system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average ReadReq mshr miss latency 809system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932 # average ReadReq mshr miss latency 810system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 811system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency 812system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 813system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency | 777system.cpu0.icache.writebacks::writebacks 403 # number of writebacks 778system.cpu0.icache.writebacks::total 403 # number of writebacks 779system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits 780system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 781system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits 782system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 783system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits 784system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 801system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for overall accesses 802system.cpu0.icache.overall_mshr_miss_rate::total 0.087691 # mshr miss rate for overall accesses 803system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average ReadReq mshr miss latency 804system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932 # average ReadReq mshr miss latency 805system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 806system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency 807system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency 808system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency |
| 814system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 815system.cpu1.branchPred.lookups 75929 # Number of BP lookups 816system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted 817system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect 818system.cpu1.branchPred.BTBLookups 68395 # Number of BTB lookups 819system.cpu1.branchPred.BTBHits 0 # Number of BTB hits 820system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 821system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 822system.cpu1.branchPred.usedRAS 1839 # Number of times the RAS was used to get a target. --- 365 unchanged lines hidden (view full) --- 1188system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency 1189system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854 # average overall miss latency 1190system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1191system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1192system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1193system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1194system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1195system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 809system.cpu1.branchPred.lookups 75929 # Number of BP lookups 810system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted 811system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect 812system.cpu1.branchPred.BTBLookups 68395 # Number of BTB lookups 813system.cpu1.branchPred.BTBHits 0 # Number of BTB hits 814system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 815system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 816system.cpu1.branchPred.usedRAS 1839 # Number of times the RAS was used to get a target. --- 365 unchanged lines hidden (view full) --- 1182system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency 1183system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854 # average overall miss latency 1184system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1187system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1189system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1196system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1197system.cpu1.dcache.cache_copies 0 # number of cache copies performed | |
| 1198system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits 1199system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits 1200system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits 1201system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits 1202system.cpu1.dcache.demand_mshr_hits::cpu1.data 405 # number of demand (read+write) MSHR hits 1203system.cpu1.dcache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits 1204system.cpu1.dcache.overall_mshr_hits::cpu1.data 405 # number of overall MSHR hits 1205system.cpu1.dcache.overall_mshr_hits::total 405 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 1238system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093 # average WriteReq mshr miss latency 1239system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093 # average WriteReq mshr miss latency 1240system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 12800 # average SwapReq mshr miss latency 1241system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 12800 # average SwapReq mshr miss latency 1242system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1243system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency 1244system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1245system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency | 1190system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits 1191system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits 1192system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits 1193system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits 1194system.cpu1.dcache.demand_mshr_hits::cpu1.data 405 # number of demand (read+write) MSHR hits 1195system.cpu1.dcache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits 1196system.cpu1.dcache.overall_mshr_hits::cpu1.data 405 # number of overall MSHR hits 1197system.cpu1.dcache.overall_mshr_hits::total 405 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093 # average WriteReq mshr miss latency 1231system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093 # average WriteReq mshr miss latency 1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 12800 # average SwapReq mshr miss latency 1233system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 12800 # average SwapReq mshr miss latency 1234system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1235system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency 1236system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency 1237system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency |
| 1246system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1247system.cpu1.icache.tags.replacements 548 # number of replacements 1248system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use 1249system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. 1250system.cpu1.icache.tags.sampled_refs 682 # Sample count of references to valid blocks. 1251system.cpu1.icache.tags.avg_refs 31.180352 # Average number of references to valid blocks. 1252system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1253system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.609803 # Average occupied blocks per requestor 1254system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190644 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1297system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency 1298system.cpu1.icache.overall_avg_miss_latency::total 16383.777240 # average overall miss latency 1299system.cpu1.icache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked 1300system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1301system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1302system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1303system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked 1304system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1238system.cpu1.icache.tags.replacements 548 # number of replacements 1239system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use 1240system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. 1241system.cpu1.icache.tags.sampled_refs 682 # Sample count of references to valid blocks. 1242system.cpu1.icache.tags.avg_refs 31.180352 # Average number of references to valid blocks. 1243system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1244system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.609803 # Average occupied blocks per requestor 1245system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190644 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1288system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency 1289system.cpu1.icache.overall_avg_miss_latency::total 16383.777240 # average overall miss latency 1290system.cpu1.icache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked 1291system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1292system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1293system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1294system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked 1295system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1305system.cpu1.icache.fast_writes 0 # number of fast writes performed 1306system.cpu1.icache.cache_copies 0 # number of cache copies performed | |
| 1307system.cpu1.icache.writebacks::writebacks 548 # number of writebacks 1308system.cpu1.icache.writebacks::total 548 # number of writebacks 1309system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits 1310system.cpu1.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 1311system.cpu1.icache.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits 1312system.cpu1.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 1313system.cpu1.icache.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits 1314system.cpu1.icache.overall_mshr_hits::total 144 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1331system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for overall accesses 1332system.cpu1.icache.overall_mshr_miss_rate::total 0.030872 # mshr miss rate for overall accesses 1333system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average ReadReq mshr miss latency 1334system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191 # average ReadReq mshr miss latency 1335system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1336system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency 1337system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1338system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency | 1296system.cpu1.icache.writebacks::writebacks 548 # number of writebacks 1297system.cpu1.icache.writebacks::total 548 # number of writebacks 1298system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits 1299system.cpu1.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 1300system.cpu1.icache.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits 1301system.cpu1.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 1302system.cpu1.icache.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits 1303system.cpu1.icache.overall_mshr_hits::total 144 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1320system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for overall accesses 1321system.cpu1.icache.overall_mshr_miss_rate::total 0.030872 # mshr miss rate for overall accesses 1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average ReadReq mshr miss latency 1323system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191 # average ReadReq mshr miss latency 1324system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1325system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency 1326system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency 1327system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency |
| 1339system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1340system.cpu2.branchPred.lookups 65577 # Number of BP lookups 1341system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted 1342system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect 1343system.cpu2.branchPred.BTBLookups 57712 # Number of BTB lookups 1344system.cpu2.branchPred.BTBHits 0 # Number of BTB hits 1345system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1346system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1347system.cpu2.branchPred.usedRAS 1983 # Number of times the RAS was used to get a target. --- 368 unchanged lines hidden (view full) --- 1716system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency 1717system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317 # average overall miss latency 1718system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1719system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1720system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1721system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1722system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1723system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1328system.cpu2.branchPred.lookups 65577 # Number of BP lookups 1329system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted 1330system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect 1331system.cpu2.branchPred.BTBLookups 57712 # Number of BTB lookups 1332system.cpu2.branchPred.BTBHits 0 # Number of BTB hits 1333system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1334system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1335system.cpu2.branchPred.usedRAS 1983 # Number of times the RAS was used to get a target. --- 368 unchanged lines hidden (view full) --- 1704system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency 1705system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317 # average overall miss latency 1706system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1707system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1708system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1709system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1710system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1711system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1724system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1725system.cpu2.dcache.cache_copies 0 # number of cache copies performed | |
| 1726system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits 1727system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits 1728system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits 1729system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits 1730system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 5 # number of SwapReq MSHR hits 1731system.cpu2.dcache.SwapReq_mshr_hits::total 5 # number of SwapReq MSHR hits 1732system.cpu2.dcache.demand_mshr_hits::cpu2.data 345 # number of demand (read+write) MSHR hits 1733system.cpu2.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 1768system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286 # average WriteReq mshr miss latency 1769system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286 # average WriteReq mshr miss latency 1770system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667 # average SwapReq mshr miss latency 1771system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667 # average SwapReq mshr miss latency 1772system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1773system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency 1774system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1775system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency | 1712system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits 1713system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits 1714system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits 1715system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits 1716system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 5 # number of SwapReq MSHR hits 1717system.cpu2.dcache.SwapReq_mshr_hits::total 5 # number of SwapReq MSHR hits 1718system.cpu2.dcache.demand_mshr_hits::cpu2.data 345 # number of demand (read+write) MSHR hits 1719system.cpu2.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 1754system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286 # average WriteReq mshr miss latency 1755system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286 # average WriteReq mshr miss latency 1756system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667 # average SwapReq mshr miss latency 1757system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667 # average SwapReq mshr miss latency 1758system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1759system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency 1760system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency 1761system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency |
| 1776system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1777system.cpu2.icache.tags.replacements 555 # number of replacements 1778system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use 1779system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. 1780system.cpu2.icache.tags.sampled_refs 694 # Sample count of references to valid blocks. 1781system.cpu2.icache.tags.avg_refs 38.475504 # Average number of references to valid blocks. 1782system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1783system.cpu2.icache.tags.occ_blocks::cpu2.inst 101.261159 # Average occupied blocks per requestor 1784system.cpu2.icache.tags.occ_percent::cpu2.inst 0.197776 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1827system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency 1828system.cpu2.icache.overall_avg_miss_latency::total 23163.701068 # average overall miss latency 1829system.cpu2.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked 1830system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1831system.cpu2.icache.blocked::no_mshrs 7 # number of cycles access was blocked 1832system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1833system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked 1834system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1762system.cpu2.icache.tags.replacements 555 # number of replacements 1763system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use 1764system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. 1765system.cpu2.icache.tags.sampled_refs 694 # Sample count of references to valid blocks. 1766system.cpu2.icache.tags.avg_refs 38.475504 # Average number of references to valid blocks. 1767system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1768system.cpu2.icache.tags.occ_blocks::cpu2.inst 101.261159 # Average occupied blocks per requestor 1769system.cpu2.icache.tags.occ_percent::cpu2.inst 0.197776 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1812system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency 1813system.cpu2.icache.overall_avg_miss_latency::total 23163.701068 # average overall miss latency 1814system.cpu2.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked 1815system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1816system.cpu2.icache.blocked::no_mshrs 7 # number of cycles access was blocked 1817system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1818system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked 1819system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1835system.cpu2.icache.fast_writes 0 # number of fast writes performed 1836system.cpu2.icache.cache_copies 0 # number of cache copies performed | |
| 1837system.cpu2.icache.writebacks::writebacks 555 # number of writebacks 1838system.cpu2.icache.writebacks::total 555 # number of writebacks 1839system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits 1840system.cpu2.icache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits 1841system.cpu2.icache.demand_mshr_hits::cpu2.inst 149 # number of demand (read+write) MSHR hits 1842system.cpu2.icache.demand_mshr_hits::total 149 # number of demand (read+write) MSHR hits 1843system.cpu2.icache.overall_mshr_hits::cpu2.inst 149 # number of overall MSHR hits 1844system.cpu2.icache.overall_mshr_hits::total 149 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1861system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for overall accesses 1862system.cpu2.icache.overall_mshr_miss_rate::total 0.025195 # mshr miss rate for overall accesses 1863system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average ReadReq mshr miss latency 1864system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331 # average ReadReq mshr miss latency 1865system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1866system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency 1867system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1868system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency | 1820system.cpu2.icache.writebacks::writebacks 555 # number of writebacks 1821system.cpu2.icache.writebacks::total 555 # number of writebacks 1822system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits 1823system.cpu2.icache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits 1824system.cpu2.icache.demand_mshr_hits::cpu2.inst 149 # number of demand (read+write) MSHR hits 1825system.cpu2.icache.demand_mshr_hits::total 149 # number of demand (read+write) MSHR hits 1826system.cpu2.icache.overall_mshr_hits::cpu2.inst 149 # number of overall MSHR hits 1827system.cpu2.icache.overall_mshr_hits::total 149 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1844system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for overall accesses 1845system.cpu2.icache.overall_mshr_miss_rate::total 0.025195 # mshr miss rate for overall accesses 1846system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average ReadReq mshr miss latency 1847system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331 # average ReadReq mshr miss latency 1848system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1849system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency 1850system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency 1851system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency |
| 1869system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1870system.cpu3.branchPred.lookups 57182 # Number of BP lookups 1871system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted 1872system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect 1873system.cpu3.branchPred.BTBLookups 48362 # Number of BTB lookups 1874system.cpu3.branchPred.BTBHits 0 # Number of BTB hits 1875system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1876system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1877system.cpu3.branchPred.usedRAS 2121 # Number of times the RAS was used to get a target. --- 365 unchanged lines hidden (view full) --- 2243system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency 2244system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795 # average overall miss latency 2245system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2246system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2247system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2248system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2249system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2250system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1852system.cpu3.branchPred.lookups 57182 # Number of BP lookups 1853system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted 1854system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect 1855system.cpu3.branchPred.BTBLookups 48362 # Number of BTB lookups 1856system.cpu3.branchPred.BTBHits 0 # Number of BTB hits 1857system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1858system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 1859system.cpu3.branchPred.usedRAS 2121 # Number of times the RAS was used to get a target. --- 365 unchanged lines hidden (view full) --- 2225system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency 2226system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795 # average overall miss latency 2227system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2228system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2229system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2230system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2231system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2232system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2251system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2252system.cpu3.dcache.cache_copies 0 # number of cache copies performed | |
| 2253system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits 2254system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits 2255system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits 2256system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 2257system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 4 # number of SwapReq MSHR hits 2258system.cpu3.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits 2259system.cpu3.dcache.demand_mshr_hits::cpu3.data 326 # number of demand (read+write) MSHR hits 2260system.cpu3.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 2295system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906 # average WriteReq mshr miss latency 2296system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906 # average WriteReq mshr miss latency 2297system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471 # average SwapReq mshr miss latency 2298system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471 # average SwapReq mshr miss latency 2299system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2300system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency 2301system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2302system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency | 2233system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits 2234system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits 2235system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits 2236system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 2237system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 4 # number of SwapReq MSHR hits 2238system.cpu3.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits 2239system.cpu3.dcache.demand_mshr_hits::cpu3.data 326 # number of demand (read+write) MSHR hits 2240system.cpu3.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 2275system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906 # average WriteReq mshr miss latency 2276system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906 # average WriteReq mshr miss latency 2277system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471 # average SwapReq mshr miss latency 2278system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471 # average SwapReq mshr miss latency 2279system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2280system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency 2281system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency 2282system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency |
| 2303system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2304system.cpu3.icache.tags.replacements 608 # number of replacements 2305system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use 2306system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. 2307system.cpu3.icache.tags.sampled_refs 743 # Sample count of references to valid blocks. 2308system.cpu3.icache.tags.avg_refs 45.095559 # Average number of references to valid blocks. 2309system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2310system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.738869 # Average occupied blocks per requestor 2311system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183084 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 2354system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency 2355system.cpu3.icache.overall_avg_miss_latency::total 13385.763490 # average overall miss latency 2356system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2357system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2358system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2359system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2360system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2361system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2283system.cpu3.icache.tags.replacements 608 # number of replacements 2284system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use 2285system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. 2286system.cpu3.icache.tags.sampled_refs 743 # Sample count of references to valid blocks. 2287system.cpu3.icache.tags.avg_refs 45.095559 # Average number of references to valid blocks. 2288system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2289system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.738869 # Average occupied blocks per requestor 2290system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183084 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 2333system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency 2334system.cpu3.icache.overall_avg_miss_latency::total 13385.763490 # average overall miss latency 2335system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2336system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2337system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2338system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2339system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2340system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2362system.cpu3.icache.fast_writes 0 # number of fast writes performed 2363system.cpu3.icache.cache_copies 0 # number of cache copies performed | |
| 2364system.cpu3.icache.writebacks::writebacks 608 # number of writebacks 2365system.cpu3.icache.writebacks::total 608 # number of writebacks 2366system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits 2367system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits 2368system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits 2369system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits 2370system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits 2371system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 2388system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for overall accesses 2389system.cpu3.icache.overall_mshr_miss_rate::total 0.021613 # mshr miss rate for overall accesses 2390system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average ReadReq mshr miss latency 2391system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428 # average ReadReq mshr miss latency 2392system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2393system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency 2394system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2395system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency | 2341system.cpu3.icache.writebacks::writebacks 608 # number of writebacks 2342system.cpu3.icache.writebacks::total 608 # number of writebacks 2343system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits 2344system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits 2345system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits 2346system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits 2347system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits 2348system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 2365system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for overall accesses 2366system.cpu3.icache.overall_mshr_miss_rate::total 0.021613 # mshr miss rate for overall accesses 2367system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average ReadReq mshr miss latency 2368system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428 # average ReadReq mshr miss latency 2369system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2370system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency 2371system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency 2372system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency |
| 2396system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2397system.l2c.tags.replacements 0 # number of replacements 2398system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use 2399system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. 2400system.l2c.tags.sampled_refs 581 # Sample count of references to valid blocks. 2401system.l2c.tags.avg_refs 5.330465 # Average number of references to valid blocks. 2402system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2403system.l2c.tags.occ_blocks::writebacks 0.811695 # Average occupied blocks per requestor 2404system.l2c.tags.occ_blocks::cpu0.inst 303.236105 # Average occupied blocks per requestor --- 240 unchanged lines hidden (view full) --- 2645system.l2c.overall_avg_miss_latency::cpu3.data 79266.666667 # average overall miss latency 2646system.l2c.overall_avg_miss_latency::total 79538.251366 # average overall miss latency 2647system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2648system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2649system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2650system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2651system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2652system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2373system.l2c.tags.replacements 0 # number of replacements 2374system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use 2375system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. 2376system.l2c.tags.sampled_refs 581 # Sample count of references to valid blocks. 2377system.l2c.tags.avg_refs 5.330465 # Average number of references to valid blocks. 2378system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2379system.l2c.tags.occ_blocks::writebacks 0.811695 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu0.inst 303.236105 # Average occupied blocks per requestor --- 240 unchanged lines hidden (view full) --- 2621system.l2c.overall_avg_miss_latency::cpu3.data 79266.666667 # average overall miss latency 2622system.l2c.overall_avg_miss_latency::total 79538.251366 # average overall miss latency 2623system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2624system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2625system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2626system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2627system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2628system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2653system.l2c.fast_writes 0 # number of fast writes performed 2654system.l2c.cache_copies 0 # number of cache copies performed | |
| 2655system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2656system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2657system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits 2658system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits 2659system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits 2660system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2661system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2662system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits --- 151 unchanged lines hidden (view full) --- 2814system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency 2815system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency 2816system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency 2817system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency 2818system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency 2819system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency 2820system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency 2821system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency | 2629system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2630system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2631system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits 2632system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits 2633system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits 2634system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2635system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2636system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits --- 151 unchanged lines hidden (view full) --- 2788system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency 2789system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency 2790system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency 2791system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency 2792system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency 2793system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency 2794system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency 2795system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency |
| 2822system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2823system.membus.trans_dist::ReadResp 583 # Transaction distribution 2824system.membus.trans_dist::UpgradeReq 286 # Transaction distribution 2825system.membus.trans_dist::ReadExReq 182 # Transaction distribution 2826system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2827system.membus.trans_dist::ReadSharedReq 583 # Transaction distribution 2828system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1765 # Packet count per connected master and slave (bytes) 2829system.membus.pkt_count::total 1765 # Packet count per connected master and slave (bytes) 2830system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45696 # Cumulative packet size per connected master and slave (bytes) --- 89 unchanged lines hidden --- | 2796system.membus.trans_dist::ReadResp 583 # Transaction distribution 2797system.membus.trans_dist::UpgradeReq 286 # Transaction distribution 2798system.membus.trans_dist::ReadExReq 182 # Transaction distribution 2799system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2800system.membus.trans_dist::ReadSharedReq 583 # Transaction distribution 2801system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1765 # Packet count per connected master and slave (bytes) 2802system.membus.pkt_count::total 1765 # Packet count per connected master and slave (bytes) 2803system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45696 # Cumulative packet size per connected master and slave (bytes) --- 89 unchanged lines hidden --- |