| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000107 # Number of seconds simulated 4sim_ticks 107049000 # Number of ticks simulated 5final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000108 # Number of seconds simulated 4sim_ticks 107711000 # Number of ticks simulated 5final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93620 # Simulator instruction rate (inst/s) 8host_op_rate 93620 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10161795 # Simulator tick rate (ticks/s) 10host_mem_usage 304708 # Number of bytes of host memory used 11host_seconds 10.53 # Real time elapsed on the host 12sim_insts 986230 # Number of instructions simulated 13sim_ops 986230 # Number of ops (including micro ops) simulated | 7host_inst_rate 152784 # Simulator instruction rate (inst/s) 8host_op_rate 152784 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16568657 # Simulator tick rate (ticks/s) 10host_mem_usage 311444 # Number of bytes of host memory used 11host_seconds 6.50 # Real time elapsed on the host 12sim_insts 993230 # Number of instructions simulated 13sim_ops 993230 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory | 22system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 42560 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory | 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 42560 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory |
| 26system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory | 26system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory |
| 29system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory | 29system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 665 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 665 # Number of read requests responded to by this memory |
| 39system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s) |
| 62system.physmem.readReqs 666 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 62system.physmem.readReqs 666 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 73system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write | 73system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write |
| 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts 76system.physmem.perBankRdBursts::2 30 # Per bank write bursts 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 66 # Per bank write bursts 79system.physmem.perBankRdBursts::5 27 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts --- 18 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts 76system.physmem.perBankRdBursts::2 30 # Per bank write bursts 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 66 # Per bank write bursts 79system.physmem.perBankRdBursts::5 27 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts --- 18 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 108system.physmem.totGap 107021000 # Total gap between requests | 108system.physmem.totGap 107683000 # Total gap between requests |
| 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 666 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) | 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 666 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 123system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see |
| 126system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 126system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 219system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation 233system.physmem.totQLat 6009250 # Total ticks spent queuing 234system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM | 219system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation 233system.physmem.totQLat 6590000 # Total ticks spent queuing 234system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM |
| 235system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers | 235system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers |
| 236system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst | 236system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst |
| 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 238system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s |
| 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 241system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s | 241system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s |
| 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 244system.physmem.busUtil 3.11 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads | 244system.physmem.busUtil 3.09 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads |
| 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 247system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing | 247system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing |
| 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 249system.physmem.readRowHits 511 # Number of row buffer hits during reads | 249system.physmem.readRowHits 510 # Number of row buffer hits during reads |
| 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 251system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads | 251system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads |
| 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 253system.physmem.avgGap 160692.19 # Average gap between requests 254system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) | 253system.physmem.avgGap 161686.19 # Average gap between requests 254system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) |
| 257system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) | 257system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) |
| 260system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ) 263system.physmem_0.averagePower 748.690472 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states | 260system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ) 263system.physmem_0.averagePower 749.440907 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states |
| 265system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 265system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 267system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states | 267system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states |
| 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) | 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) |
| 274system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ) 277system.physmem_1.averagePower 730.471639 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states | 274system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ) 277system.physmem_1.averagePower 729.430757 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states |
| 279system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 279system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 281system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states | 281system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states |
| 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 283system.cpu0.branchPred.lookups 81022 # Number of BP lookups 284system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted | 283system.cpu0.branchPred.lookups 81565 # Number of BP lookups 284system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted |
| 285system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect | 285system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect |
| 286system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups 287system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits | 286system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups 287system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits |
| 288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 289system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage | 289system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage |
| 290system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 292system.cpu_clk_domain.clock 500 # Clock period in ticks 293system.cpu0.workload.num_syscalls 89 # Number of system calls | 290system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 292system.cpu_clk_domain.clock 500 # Clock period in ticks 293system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 294system.cpu0.numCycles 214099 # number of cpu cycles simulated | 294system.cpu0.numCycles 215423 # number of cpu cycles simulated |
| 295system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 296system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 295system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 296system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 297system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss 298system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed 299system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered 300system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken 301system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked | 297system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss 298system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed 299system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered 300system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken 301system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked |
| 302system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing 303system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb 304system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 302system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing 303system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb 304system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 305system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps | 305system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps |
| 306system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched | 306system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched |
| 307system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed | 307system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed |
| 308system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed | 308system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed |
| 309system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total) 310system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total) 311system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total) | 309system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total) 310system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total) 311system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total) |
| 312system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 312system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 313system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total) | 313system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total) |
| 322system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 322system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 325system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle 327system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle 328system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle 329system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked 330system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running 331system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking | 325system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle 327system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle 328system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle 329system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked 330system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running 331system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking |
| 332system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing | 332system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing |
| 333system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode | 333system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode |
| 334system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing | 334system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing |
| 335system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle 336system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking 337system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst 338system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running 339system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking 340system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename 341system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 342system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full 343system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full 344system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed 345system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made 346system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups 347system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed 348system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing 349system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed 350system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed 351system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer 352system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit. 353system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit. 354system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads. 355system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores. 356system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec) | 335system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle 336system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking 337system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst 338system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running 339system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking 340system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename 341system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full 342system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full 343system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full 344system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed 345system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made 346system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups 347system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed 348system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing 349system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed 350system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed 351system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer 352system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit. 353system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit. 354system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads. 355system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores. 356system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec) |
| 357system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ | 357system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ |
| 358system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued | 358system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued |
| 359system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued | 359system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued |
| 360system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling 361system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph | 360system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling 361system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph |
| 362system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed | 362system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed |
| 363system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle 364system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle | 363system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle 364system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle |
| 366system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 366system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 367system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle | 367system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle |
| 374system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle | 374system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle |
| 375system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle | 375system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle |
| 376system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 376system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 379system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle | 379system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle |
| 380system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 380system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 381system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available 382system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available 383system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available 384system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available 388system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available 389system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available 410system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available | 381system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available 382system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available 383system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available 384system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available 388system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available 389system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available 410system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available |
| 411system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available 412system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 413system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 411system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available 412system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 413system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 415system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued 416system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued 417system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued 418system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued 422system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued 423system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued 444system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued 445system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued | 415system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued 416system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued 417system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued 418system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued 422system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued 423system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued 444system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued 445system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued |
| 446system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 447system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 446system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 447system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 448system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued 449system.cpu0.iq.rate 1.801713 # Inst issue rate | 448system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued 449system.cpu0.iq.rate 1.803452 # Inst issue rate |
| 450system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested | 450system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested |
| 451system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst) 452system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads 453system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes 454system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses | 451system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) 452system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads 453system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes 454system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses |
| 455system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 456system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 457system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 455system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 456system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 457system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 458system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses | 458system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses |
| 459system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 459system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 460system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores | 460system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores |
| 461system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 461system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 462system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed | 462system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed |
| 463system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 464system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations | 463system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 464system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations |
| 465system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed | 465system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed |
| 466system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 467system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 468system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 469system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 470system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 471system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing | 466system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 467system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 468system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 469system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 470system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 471system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing |
| 472system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking 473system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking 474system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ | 472system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking 473system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking 474system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ |
| 475system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch | 475system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch |
| 476system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions 477system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions | 476system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions 477system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions |
| 478system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions | 478system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions |
| 479system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall | 479system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall |
| 480system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 481system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations 482system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly | 480system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 481system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations 482system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly |
| 483system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly 484system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute 485system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions 486system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed | 483system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly 484system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute 485system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions 486system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed |
| 487system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute 488system.cpu0.iew.exec_swp 0 # number of swp insts executed | 487system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute 488system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 489system.cpu0.iew.exec_nop 73033 # number of nop insts executed 490system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed 491system.cpu0.iew.exec_branches 76355 # Number of branches executed 492system.cpu0.iew.exec_stores 74340 # Number of stores executed 493system.cpu0.iew.exec_rate 1.796991 # Inst execution rate 494system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit 495system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back 496system.cpu0.iew.wb_producers 227714 # num instructions producing a value 497system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value | 489system.cpu0.iew.exec_nop 73578 # number of nop insts executed 490system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed 491system.cpu0.iew.exec_branches 76909 # Number of branches executed 492system.cpu0.iew.exec_stores 74891 # Number of stores executed 493system.cpu0.iew.exec_rate 1.798759 # Inst execution rate 494system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit 495system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back 496system.cpu0.iew.wb_producers 229361 # num instructions producing a value 497system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value |
| 498system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 498system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 499system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle 500system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back | 499system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle 500system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back |
| 501system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 501system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 502system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit | 502system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit |
| 503system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 504system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted | 503system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 504system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted |
| 505system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle 506system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle | 505system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle 506system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle |
| 508system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 508system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 509system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle | 509system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle |
| 517system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 519system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 520system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 517system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 519system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 520system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 521system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle 522system.cpu0.commit.committedInsts 449946 # Number of instructions committed 523system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed | 521system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle 522system.cpu0.commit.committedInsts 453252 # Number of instructions committed 523system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed |
| 524system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 524system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 525system.cpu0.commit.refs 219688 # Number of memory references committed 526system.cpu0.commit.loads 146121 # Number of loads committed | 525system.cpu0.commit.refs 221341 # Number of memory references committed 526system.cpu0.commit.loads 147223 # Number of loads committed |
| 527system.cpu0.commit.membars 84 # Number of memory barriers committed | 527system.cpu0.commit.membars 84 # Number of memory barriers committed |
| 528system.cpu0.commit.branches 75454 # Number of branches committed | 528system.cpu0.commit.branches 76005 # Number of branches committed |
| 529system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 529system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
| 530system.cpu0.commit.int_insts 303394 # Number of committed integer instructions. | 530system.cpu0.commit.int_insts 305598 # Number of committed integer instructions. |
| 531system.cpu0.commit.function_calls 223 # Number of function calls committed. | 531system.cpu0.commit.function_calls 223 # Number of function calls committed. |
| 532system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction 533system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction 534system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction 535system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction 536system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction 537system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction 538system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction 539system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction 540system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction 541system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction 542system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction 543system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction 544system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction 545system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction 546system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction 547system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction 548system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction 549system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction 550system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction 551system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction 552system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction 554system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction 555system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction 556system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction 557system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction 558system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction 559system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction 560system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction 561system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction 562system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction 563system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction | 532system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction 533system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction 534system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction 535system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction 536system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction 537system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction 538system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction 539system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction 540system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction 541system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction 542system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction 543system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction 544system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction 545system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction 546system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction 547system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction 548system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction 549system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction 550system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction 551system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction 552system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction 554system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction 555system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction 556system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction 557system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction 558system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction 559system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction 560system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction 561system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction 562system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction 563system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction |
| 564system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 565system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 564system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 565system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 566system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction | 566system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction |
| 567system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached | 567system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached |
| 568system.cpu0.rob.rob_reads 646481 # The number of ROB reads 569system.cpu0.rob.rob_writes 928572 # The number of ROB writes | 568system.cpu0.rob.rob_reads 651013 # The number of ROB reads 569system.cpu0.rob.rob_writes 935136 # The number of ROB writes |
| 570system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself | 570system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 571system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling 572system.cpu0.committedInsts 377676 # Number of Instructions Simulated 573system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated 574system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction 575system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads 576system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle 577system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads 578system.cpu0.int_regfile_reads 688304 # number of integer regfile reads 579system.cpu0.int_regfile_writes 310378 # number of integer regfile writes | 571system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling 572system.cpu0.committedInsts 380431 # Number of Instructions Simulated 573system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated 574system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction 575system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads 576system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle 577system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads 578system.cpu0.int_regfile_reads 693268 # number of integer regfile reads 579system.cpu0.int_regfile_writes 312587 # number of integer regfile writes |
| 580system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 580system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
| 581system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads | 581system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads |
| 582system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 583system.cpu0.dcache.tags.replacements 2 # number of replacements | 582system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 583system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 584system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use 585system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks. | 584system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use 585system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks. |
| 586system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. | 586system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. |
| 587system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks. | 587system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks. |
| 588system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 588system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 589system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor 590system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy 591system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy | 589system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor 590system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy 591system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy |
| 592system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 593system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id | 592system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 593system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id |
| 594system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id | 594system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id |
| 596system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id | 596system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id |
| 597system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses 598system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses 599system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits 600system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits 601system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits 602system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits | 597system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses 598system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses 599system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits 600system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits 601system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits 602system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits |
| 603system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 604system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits | 603system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 604system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits |
| 605system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits 606system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits 607system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits 608system.cpu0.dcache.overall_hits::total 148294 # number of overall hits 609system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses 610system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses 611system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses 612system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses | 605system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits 606system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits 607system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits 608system.cpu0.dcache.overall_hits::total 149410 # number of overall hits 609system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses 610system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses 611system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses 612system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses |
| 613system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 614system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses | 613system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 614system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses |
| 615system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses 616system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses 617system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses 618system.cpu0.dcache.overall_misses::total 1118 # number of overall misses 619system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles 620system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles 621system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles 622system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles | 615system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses 616system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses 617system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses 618system.cpu0.dcache.overall_misses::total 1102 # number of overall misses 619system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles 620system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles 621system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles 622system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles |
| 623system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles 624system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles | 623system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles 624system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles |
| 625system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles 626system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles 627system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles 628system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles 629system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses) 630system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses) 631system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses) 632system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses) | 625system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles 626system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles 627system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles 628system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles 629system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses) 630system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses) 631system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses) 632system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses) |
| 633system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 634system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 633system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 634system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 635system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses 636system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses 637system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses 638system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses 639system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses 640system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses 641system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses 642system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses | 635system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses 636system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses 637system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses 638system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses 639system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses 640system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses 641system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses 642system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses |
| 643system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 644system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses | 643system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 644system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses |
| 645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses 646system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses 647system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses 648system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses 649system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency 650system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency 651system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency 652system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency | 645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses 646system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses 647system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses 648system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses 649system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency 650system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency 651system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency 652system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency |
| 653system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency 654system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency | 653system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency 654system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency |
| 655system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency 656system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency 657system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency 658system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency | 655system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency 656system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency 657system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency 658system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency |
| 659system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked 660system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 662system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked 664system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.cpu0.dcache.fast_writes 0 # number of fast writes performed 666system.cpu0.dcache.cache_copies 0 # number of cache copies performed 667system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 668system.cpu0.dcache.writebacks::total 1 # number of writebacks | 659system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked 660system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 662system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked 664system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.cpu0.dcache.fast_writes 0 # number of fast writes performed 666system.cpu0.dcache.cache_copies 0 # number of cache copies performed 667system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 668system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 669system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits 670system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits 671system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits 672system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits 673system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits 674system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits 675system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits 676system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits 677system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses 678system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses 679system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses 680system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses | 669system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits 670system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits 671system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits 672system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits 673system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits 674system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits 675system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits 676system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits 677system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses 678system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses 679system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses 680system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses |
| 681system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 682system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 683system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 685system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 686system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses | 681system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 682system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 683system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 685system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 686system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses |
| 687system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles 688system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles 689system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles 690system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles | 687system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles 688system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles 689system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles 690system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles |
| 691system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles 692system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles | 691system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles 692system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles |
| 693system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles 694system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles 695system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles 696system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles 697system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses 698system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses 699system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses 700system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses | 693system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles 694system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles 695system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles 696system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles 697system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses 698system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses 699system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses 700system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses |
| 701system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 702system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses | 701system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 702system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses |
| 703system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses 704system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses 705system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses 706system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses 707system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency 708system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency 709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency 710system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency | 703system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses 704system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses 705system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses 706system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses 707system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency 708system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency 709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency 710system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency |
| 711system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency 712system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency | 711system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency 712system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency |
| 713system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency 714system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency 715system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency 716system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency | 713system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency 714system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency 715system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency 716system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency |
| 717system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 718system.cpu0.icache.tags.replacements 315 # number of replacements | 717system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 718system.cpu0.icache.tags.replacements 315 # number of replacements |
| 719system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use | 719system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use |
| 720system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. 721system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. 722system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. 723system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 720system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. 721system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. 722system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. 723system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 724system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor 725system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy 726system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy | 724system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor 725system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy 726system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy |
| 727system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 728system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id | 727system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 728system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id |
| 729system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 730system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id | 729system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 730system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id |
| 731system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id 732system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses 733system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses 734system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits 735system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits 736system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits 737system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits 738system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits 739system.cpu0.icache.overall_hits::total 5949 # number of overall hits 740system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses 741system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses 742system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses 743system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses 744system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses 745system.cpu0.icache.overall_misses::total 784 # number of overall misses | 731system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id 732system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses 733system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses 734system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits 735system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits 736system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits 737system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits 738system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits 739system.cpu0.icache.overall_hits::total 5949 # number of overall hits 740system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses 741system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses 742system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses 743system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses 744system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses 745system.cpu0.icache.overall_misses::total 784 # number of overall misses |
| 746system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles 747system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles 748system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles 749system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles 750system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles 751system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles | 746system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles 747system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles 748system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles 749system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles 750system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles 751system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles |
| 752system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) 753system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) 754system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses 755system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses 756system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses 757system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses 758system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses 759system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses 760system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses 761system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses 762system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses 763system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses | 752system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) 753system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) 754system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses 755system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses 756system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses 757system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses 758system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses 759system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses 760system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses 761system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses 762system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses 763system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses |
| 764system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency 765system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency 766system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency 767system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency 768system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency 769system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency | 764system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency 765system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency 766system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency 767system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency 768system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency 769system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency |
| 770system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked 771system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 773system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 775system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu0.icache.fast_writes 0 # number of fast writes performed 777system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 782system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits 783system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits 784system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses 785system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses 786system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses 787system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses 788system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses 789system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses | 770system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked 771system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 773system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 775system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu0.icache.fast_writes 0 # number of fast writes performed 777system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 782system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits 783system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits 784system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses 785system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses 786system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses 787system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses 788system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses 789system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses |
| 790system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles | 790system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles |
| 796system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses 797system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses 798system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses 799system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses 800system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses 801system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses | 796system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses 797system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses 798system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses 799system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses 800system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses 801system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses |
| 802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency 803system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency 804system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency 805system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency 806system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency 807system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency | 802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency 803system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency 804system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency 805system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency 806system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency 807system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency |
| 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu1.branchPred.lookups 50039 # Number of BP lookups 810system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted 811system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect 812system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups 813system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits | 809system.cpu1.branchPred.lookups 53924 # Number of BP lookups 810system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted 811system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect 812system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups 813system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits |
| 814system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 814system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 815system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage 816system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target. | 815system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage 816system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target. |
| 817system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 817system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 818system.cpu1.numCycles 161348 # number of cpu cycles simulated | 818system.cpu1.numCycles 162664 # number of cpu cycles simulated |
| 819system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 820system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 819system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 820system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 821system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss 822system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed 823system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered 824system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken 825system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked 826system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing | 821system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss 822system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed 823system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered 824system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken 825system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked 826system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing |
| 827system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 828system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 829system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps 830system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR | 827system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 828system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 829system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps 830system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR |
| 831system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched 832system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed 833system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total) 834system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total) 835system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total) | 831system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched 832system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed 833system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total) 834system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total) 835system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total) |
| 836system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 836system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 837system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total) 844system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total) | 837system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total) 844system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total) |
| 846system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 847system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 846system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 847system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 849system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total) 850system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle 851system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle 852system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle 853system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked 854system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running 855system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking 856system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing 857system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode 858system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing 859system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle 860system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking 861system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst 862system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running 863system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking 864system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename 865system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full 866system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full | 849system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total) 850system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle 851system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle 852system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle 853system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked 854system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running 855system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking 856system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing 857system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode 858system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing 859system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle 860system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking 861system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst 862system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running 863system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking 864system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename 865system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full 866system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full |
| 867system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers | 867system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers |
| 868system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed 869system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made 870system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups 871system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed 872system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing 873system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed 874system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed 875system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer 876system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit. 877system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit. 878system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads. 879system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores. 880system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec) 881system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ 882system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued 883system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 884system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling 885system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph 886system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed 887system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle 888system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle 889system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle | 868system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed 869system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made 870system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups 871system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed 872system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing 873system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed 874system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed 875system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer 876system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit. 877system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit. 878system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads. 879system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores. 880system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec) 881system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ 882system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued 883system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued 884system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling 885system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph 886system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed 887system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle 888system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle 889system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle |
| 890system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 890system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 891system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle 898system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle | 891system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle 898system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle |
| 900system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 901system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 902system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 900system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 901system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 902system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 903system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle | 903system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle |
| 904system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 904system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 905system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available 906system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available 907system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available 908system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available 909system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available 910system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available 912system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available 913system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available 933system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available 934system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available 935system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available | 905system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available 906system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available 907system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available 908system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available 909system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available 910system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available 912system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available 913system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available 933system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available 934system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available 935system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available |
| 936system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 937system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 938system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 936system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 937system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 938system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 939system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued 940system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued 941system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued 942system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued 943system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued 944system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued 946system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued 947system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued 967system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued 968system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued 969system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued | 939system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued 940system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued 941system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued 942system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued 943system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued 944system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued 946system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued 947system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued 967system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued 968system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued 969system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued |
| 970system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 971system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 970system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 971system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 972system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued 973system.cpu1.iq.rate 1.332331 # Inst issue rate 974system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested 975system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst) 976system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads 977system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes 978system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses | 972system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued 973system.cpu1.iq.rate 1.453419 # Inst issue rate 974system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested 975system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst) 976system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads 977system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes 978system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses |
| 979system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 980system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 981system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 979system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 980system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 981system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 982system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses | 982system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses |
| 983system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 983system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 984system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores | 984system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores |
| 985system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 985system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 986system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed | 986system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed |
| 987system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 987system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 988system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations 989system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed | 988system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 989system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed |
| 990system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 991system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 992system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 993system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 994system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 990system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 991system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 992system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 993system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 994system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 995system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing 996system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking 997system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking 998system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ 999system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch 1000system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions 1001system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions 1002system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions 1003system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall | 995system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing 996system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking 997system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking 998system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ 999system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch 1000system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions 1001system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions 1002system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions 1003system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall |
| 1004system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1004system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 1005system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations 1006system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly 1007system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly 1008system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute 1009system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions 1010system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed 1011system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute | 1005system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations 1006system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly 1007system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly 1008system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute 1009system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions 1010system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed 1011system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute |
| 1012system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1012system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1013system.cpu1.iew.exec_nop 34741 # number of nop insts executed 1014system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed 1015system.cpu1.iew.exec_branches 44094 # Number of branches executed 1016system.cpu1.iew.exec_stores 32748 # Number of stores executed 1017system.cpu1.iew.exec_rate 1.326090 # Inst execution rate 1018system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit 1019system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back 1020system.cpu1.iew.wb_producers 120431 # num instructions producing a value 1021system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value | 1013system.cpu1.iew.exec_nop 38619 # number of nop insts executed 1014system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed 1015system.cpu1.iew.exec_branches 48027 # Number of branches executed 1016system.cpu1.iew.exec_stores 37584 # Number of stores executed 1017system.cpu1.iew.exec_rate 1.447253 # Inst execution rate 1018system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit 1019system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back 1020system.cpu1.iew.wb_producers 134020 # num instructions producing a value 1021system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value |
| 1022system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1022system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1023system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle 1024system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back | 1023system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle 1024system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back |
| 1025system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1025system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1026system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit 1027system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards 1028system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted 1029system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle 1030system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle | 1026system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit 1027system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards 1028system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted 1029system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle 1030system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle |
| 1032system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1032system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1033system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle 1040system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle | 1033system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle 1040system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle |
| 1042system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1043system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1044system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1042system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1043system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1044system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1045system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle 1046system.cpu1.commit.committedInsts 240471 # Number of instructions committed 1047system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed | 1045system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle 1046system.cpu1.commit.committedInsts 265858 # Number of instructions committed 1047system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed |
| 1048system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1048system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1049system.cpu1.commit.refs 100469 # Number of memory references committed 1050system.cpu1.commit.loads 68518 # Number of loads committed 1051system.cpu1.commit.membars 5139 # Number of memory barriers committed 1052system.cpu1.commit.branches 43053 # Number of branches committed | 1049system.cpu1.commit.refs 114070 # Number of memory references committed 1050system.cpu1.commit.loads 77284 # Number of loads committed 1051system.cpu1.commit.membars 4232 # Number of memory barriers committed 1052system.cpu1.commit.branches 46981 # Number of branches committed |
| 1053system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 1053system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1054system.cpu1.commit.int_insts 165641 # Number of committed integer instructions. | 1054system.cpu1.commit.int_insts 183171 # Number of committed integer instructions. |
| 1055system.cpu1.commit.function_calls 322 # Number of function calls committed. | 1055system.cpu1.commit.function_calls 322 # Number of function calls committed. |
| 1056system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction 1057system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction 1058system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction 1059system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction 1060system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction 1061system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction 1062system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction 1063system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction 1064system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction 1065system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction 1066system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction 1077system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction 1078system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction 1079system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction 1080system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction 1081system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction 1082system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction 1083system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction 1084system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction 1085system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction 1086system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction 1087system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction | 1056system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction 1057system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction 1058system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction 1059system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction 1060system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction 1061system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction 1062system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction 1063system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction 1064system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction 1065system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction 1066system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction 1077system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction 1078system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction 1079system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction 1080system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction 1081system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction 1082system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction 1083system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction 1084system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction 1085system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction 1086system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction 1087system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction |
| 1088system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1089system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1088system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1089system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1090system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction 1091system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached 1092system.cpu1.rob.rob_reads 405414 # The number of ROB reads 1093system.cpu1.rob.rob_writes 511356 # The number of ROB writes 1094system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 1095system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling | 1090system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction 1091system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached 1092system.cpu1.rob.rob_reads 431808 # The number of ROB reads 1093system.cpu1.rob.rob_writes 561746 # The number of ROB writes 1094system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself 1095system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 1096system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt | 1096system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| 1097system.cpu1.committedInsts 201492 # Number of Instructions Simulated 1098system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated 1099system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction 1100system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads 1101system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle 1102system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads 1103system.cpu1.int_regfile_reads 368266 # number of integer regfile reads 1104system.cpu1.int_regfile_writes 172947 # number of integer regfile writes | 1097system.cpu1.committedInsts 223857 # Number of Instructions Simulated 1098system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated 1099system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction 1100system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads 1101system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle 1102system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads 1103system.cpu1.int_regfile_reads 409049 # number of integer regfile reads 1104system.cpu1.int_regfile_writes 191377 # number of integer regfile writes |
| 1105system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 1105system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
| 1106system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads | 1106system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads |
| 1107system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1108system.cpu1.dcache.tags.replacements 0 # number of replacements | 1107system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1108system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 1109system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use 1110system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks. | 1109system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use 1110system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks. |
| 1111system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. | 1111system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. |
| 1112system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks. | 1112system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks. |
| 1113system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1113system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1114system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor 1115system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy 1116system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy | 1114system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor 1115system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy 1116system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy |
| 1117system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1118system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1119system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1120system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id | 1117system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1118system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1119system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1120system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id |
| 1121system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses 1122system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses 1123system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits 1124system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits 1125system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits 1126system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits | 1121system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses 1122system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses 1123system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits 1124system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits 1125system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits 1126system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits |
| 1127system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits 1128system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits | 1127system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits 1128system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits |
| 1129system.cpu1.dcache.demand_hits::cpu1.data 73089 # number of demand (read+write) hits 1130system.cpu1.dcache.demand_hits::total 73089 # number of demand (read+write) hits 1131system.cpu1.dcache.overall_hits::cpu1.data 73089 # number of overall hits 1132system.cpu1.dcache.overall_hits::total 73089 # number of overall hits 1133system.cpu1.dcache.ReadReq_misses::cpu1.data 504 # number of ReadReq misses 1134system.cpu1.dcache.ReadReq_misses::total 504 # number of ReadReq misses 1135system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses 1136system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses 1137system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 1138system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1139system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses 1140system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses 1141system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses 1142system.cpu1.dcache.overall_misses::total 664 # number of overall misses 1143system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9769000 # number of ReadReq miss cycles 1144system.cpu1.dcache.ReadReq_miss_latency::total 9769000 # number of ReadReq miss cycles 1145system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3369500 # number of WriteReq miss cycles 1146system.cpu1.dcache.WriteReq_miss_latency::total 3369500 # number of WriteReq miss cycles 1147system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 693500 # number of SwapReq miss cycles 1148system.cpu1.dcache.SwapReq_miss_latency::total 693500 # number of SwapReq miss cycles 1149system.cpu1.dcache.demand_miss_latency::cpu1.data 13138500 # number of demand (read+write) miss cycles 1150system.cpu1.dcache.demand_miss_latency::total 13138500 # number of demand (read+write) miss cycles 1151system.cpu1.dcache.overall_miss_latency::cpu1.data 13138500 # number of overall miss cycles 1152system.cpu1.dcache.overall_miss_latency::total 13138500 # number of overall miss cycles 1153system.cpu1.dcache.ReadReq_accesses::cpu1.data 41873 # number of ReadReq accesses(hits+misses) 1154system.cpu1.dcache.ReadReq_accesses::total 41873 # number of ReadReq accesses(hits+misses) 1155system.cpu1.dcache.WriteReq_accesses::cpu1.data 31880 # number of WriteReq accesses(hits+misses) 1156system.cpu1.dcache.WriteReq_accesses::total 31880 # number of WriteReq accesses(hits+misses) 1157system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1158system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 1159system.cpu1.dcache.demand_accesses::cpu1.data 73753 # number of demand (read+write) accesses 1160system.cpu1.dcache.demand_accesses::total 73753 # number of demand (read+write) accesses 1161system.cpu1.dcache.overall_accesses::cpu1.data 73753 # number of overall (read+write) accesses 1162system.cpu1.dcache.overall_accesses::total 73753 # number of overall (read+write) accesses 1163system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012036 # miss rate for ReadReq accesses 1164system.cpu1.dcache.ReadReq_miss_rate::total 0.012036 # miss rate for ReadReq accesses 1165system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005019 # miss rate for WriteReq accesses 1166system.cpu1.dcache.WriteReq_miss_rate::total 0.005019 # miss rate for WriteReq accesses 1167system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.788732 # miss rate for SwapReq accesses 1168system.cpu1.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses 1169system.cpu1.dcache.demand_miss_rate::cpu1.data 0.009003 # miss rate for demand accesses 1170system.cpu1.dcache.demand_miss_rate::total 0.009003 # miss rate for demand accesses 1171system.cpu1.dcache.overall_miss_rate::cpu1.data 0.009003 # miss rate for overall accesses 1172system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses 1173system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency 1174system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency 1175system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency 1176system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency 1177system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency 1178system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency 1179system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency 1181system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency | 1129system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits 1130system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits 1131system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits 1132system.cpu1.dcache.overall_hits::total 81866 # number of overall hits 1133system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses 1134system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses 1135system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses 1136system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses 1137system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses 1138system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses 1139system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses 1140system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses 1141system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses 1142system.cpu1.dcache.overall_misses::total 648 # number of overall misses 1143system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles 1144system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles 1145system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles 1146system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles 1147system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles 1148system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles 1149system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles 1150system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles 1151system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles 1152system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles 1153system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses) 1154system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses) 1155system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses) 1156system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses) 1157system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 1158system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 1159system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses 1160system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses 1161system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses 1162system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses 1163system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses 1164system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses 1165system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses 1166system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses 1167system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses 1168system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses 1169system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses 1170system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses 1171system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses 1172system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses 1173system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency 1174system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency 1175system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency 1176system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency 1177system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency 1178system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency 1179system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency 1181system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency |
| 1183system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1190system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1183system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1190system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1191system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332 # number of ReadReq MSHR hits 1192system.cpu1.dcache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits | 1191system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits 1192system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits |
| 1193system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits 1194system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits | 1193system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits 1194system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits |
| 1195system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits 1196system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits 1197system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits 1198system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits 1199system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses 1200system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses 1201system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1202system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1203system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 1204system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1205system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses 1206system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 1207system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses 1208system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses 1209system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles 1210system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles 1211system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles 1212system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles 1213system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles 1214system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles 1215system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles 1218system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles 1219system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses 1220system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses 1221system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses 1222system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses 1223system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses 1224system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses 1225system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses 1226system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses 1227system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses 1228system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses 1229system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency 1230system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency 1231system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency 1232system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency 1233system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency 1234system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency 1235system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency 1236system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency 1237system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency 1238system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency | 1195system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits 1196system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits 1197system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits 1198system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits 1199system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses 1200system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses 1201system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 1202system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 1203system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses 1204system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 1205system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses 1206system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses 1207system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses 1208system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses 1209system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles 1210system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles 1211system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles 1212system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles 1213system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles 1214system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles 1215system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles 1218system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles 1219system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses 1220system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses 1221system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses 1222system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses 1223system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses 1224system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses 1225system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses 1226system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses 1227system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses 1228system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses 1229system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency 1230system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency 1231system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency 1232system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency 1233system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency 1234system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency 1235system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency 1236system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency 1237system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency 1238system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency |
| 1239system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1240system.cpu1.icache.tags.replacements 383 # number of replacements | 1239system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1240system.cpu1.icache.tags.replacements 383 # number of replacements |
| 1241system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use 1242system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks. | 1241system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use 1242system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks. |
| 1243system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. | 1243system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. |
| 1244system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks. | 1244system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks. |
| 1245system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1245system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1246system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor 1247system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy 1248system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy | 1246system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor 1247system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy 1248system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy |
| 1249system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id 1250system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1251system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 1252system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id | 1249system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id 1250system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1251system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 1252system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id |
| 1253system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses 1254system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses 1255system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits 1256system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits 1257system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits 1258system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits 1259system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits 1260system.cpu1.icache.overall_hits::total 21349 # number of overall hits 1261system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses 1262system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses 1263system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses 1264system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses 1265system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses 1266system.cpu1.icache.overall_misses::total 579 # number of overall misses 1267system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles 1268system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles 1269system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles 1270system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles 1271system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles 1272system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles 1273system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses) 1274system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses) 1275system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses 1276system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses 1277system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses 1278system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses 1279system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses 1280system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses 1281system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses 1282system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses 1283system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses 1284system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses 1285system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency 1286system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency 1287system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency 1288system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency 1289system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency 1290system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency | 1253system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses 1254system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses 1255system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits 1256system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits 1257system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits 1258system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits 1259system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits 1260system.cpu1.icache.overall_hits::total 19439 # number of overall hits 1261system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses 1262system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses 1263system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses 1264system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses 1265system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses 1266system.cpu1.icache.overall_misses::total 581 # number of overall misses 1267system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles 1268system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles 1269system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles 1270system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles 1271system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles 1272system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles 1273system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses) 1274system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses) 1275system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses 1276system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses 1277system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses 1278system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses 1279system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses 1280system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses 1281system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses 1282system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses 1283system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses 1284system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses 1285system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency 1286system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency 1287system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency 1288system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency 1289system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency 1290system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency |
| 1291system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked 1292system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1293system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1294system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1295system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 1296system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1297system.cpu1.icache.fast_writes 0 # number of fast writes performed 1298system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1291system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked 1292system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1293system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1294system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1295system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 1296system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1297system.cpu1.icache.fast_writes 0 # number of fast writes performed 1298system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1299system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits 1300system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 1301system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits 1302system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits 1303system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits 1304system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits | 1299system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits 1300system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 1301system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits 1302system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits 1303system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits 1304system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits |
| 1305system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses 1306system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses 1307system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses 1308system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses 1309system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses 1310system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses | 1305system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses 1306system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses 1307system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses 1308system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses 1309system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses 1310system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses |
| 1311system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles 1312system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles 1313system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles 1314system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles 1315system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles 1316system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles 1317system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses 1318system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses 1319system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses 1320system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses 1321system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses 1322system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses 1323system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency 1324system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency 1325system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency 1326system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency 1327system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency 1328system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency | 1311system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles 1312system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles 1313system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles 1314system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles 1315system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles 1316system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles 1317system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses 1318system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses 1319system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses 1320system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses 1321system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses 1322system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses 1323system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency 1324system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency 1325system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency 1326system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency 1327system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency 1328system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency |
| 1329system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1329system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1330system.cpu2.branchPred.lookups 42880 # Number of BP lookups 1331system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted 1332system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect 1333system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups 1334system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits | 1330system.cpu2.branchPred.lookups 55489 # Number of BP lookups 1331system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted 1332system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect 1333system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups 1334system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits |
| 1335system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1335system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1336system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage 1337system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. | 1336system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage 1337system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target. |
| 1338system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 1338system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 1339system.cpu2.numCycles 160976 # number of cpu cycles simulated | 1339system.cpu2.numCycles 162291 # number of cpu cycles simulated |
| 1340system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1341system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1340system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1341system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1342system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss 1343system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed 1344system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered 1345system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken 1346system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked 1347system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing | 1342system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss 1343system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed 1344system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered 1345system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken 1346system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked 1347system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing |
| 1348system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1349system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from | 1348system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1349system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from |
| 1350system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps 1351system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched 1352system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed 1353system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total) 1354system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total) 1355system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total) | 1350system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps 1351system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched 1352system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed 1353system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total) 1354system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total) 1355system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total) |
| 1356system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1356system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1357system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total) 1361system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total) 1362system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total) 1363system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total) 1364system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total) 1365system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total) | 1357system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total) 1361system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total) 1362system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total) 1363system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total) 1364system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total) 1365system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total) |
| 1366system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1367system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1368system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1366system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1367system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1368system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1369system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total) 1370system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle 1371system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle 1372system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle 1373system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked 1374system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running 1375system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking 1376system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing 1377system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode 1378system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing 1379system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle 1380system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking 1381system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst 1382system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running 1383system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking 1384system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename 1385system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full 1386system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full 1387system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers 1388system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed 1389system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made 1390system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups 1391system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed 1392system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing 1393system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed 1394system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed 1395system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer 1396system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit. 1397system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit. 1398system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads. 1399system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores. 1400system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec) 1401system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ 1402system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued 1403system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued 1404system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling 1405system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph 1406system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed 1407system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle 1408system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle 1409system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle | 1369system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total) 1370system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle 1371system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle 1372system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle 1373system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked 1374system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running 1375system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking 1376system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing 1377system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode 1378system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing 1379system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle 1380system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking 1381system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst 1382system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running 1383system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking 1384system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename 1385system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full 1386system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 1387system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1388system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed 1389system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made 1390system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups 1391system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed 1392system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing 1393system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed 1394system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed 1395system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer 1396system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit. 1397system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit. 1398system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads. 1399system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores. 1400system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec) 1401system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ 1402system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued 1403system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued 1404system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling 1405system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph 1406system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed 1407system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle 1408system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle 1409system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle |
| 1410system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1410system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1411system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle 1414system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle 1415system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle 1416system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle 1417system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle 1418system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle 1419system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle | 1411system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle 1414system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle 1415system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle 1416system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle 1417system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle 1418system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle 1419system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle |
| 1420system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1421system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1422system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1420system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1421system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1422system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1423system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle | 1423system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle |
| 1424system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1424system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1425system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available 1426system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available 1427system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available 1428system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available 1448system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available 1449system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available 1450system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available 1451system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available 1452system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available 1453system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available 1454system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available 1455system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available | 1425system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available 1426system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available 1427system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available 1428system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available 1448system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available 1449system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available 1450system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available 1451system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available 1452system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available 1453system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available 1454system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available 1455system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available |
| 1456system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1457system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1458system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1456system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1457system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1458system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1459system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued 1460system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued 1461system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued 1462system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued 1463system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued 1464system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued 1465system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued 1466system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued 1467system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued 1468system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued 1469system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued 1470system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued 1471system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued 1478system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued 1479system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued 1480system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued 1481system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued 1482system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued 1483system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued 1484system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued 1485system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued 1486system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued 1487system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued 1488system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued 1489system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued | 1459system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued 1460system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued 1461system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued 1462system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued 1463system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued 1464system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued 1465system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued 1466system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued 1467system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued 1468system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued 1469system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued 1470system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued 1471system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued 1478system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued 1479system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued 1480system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued 1481system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued 1482system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued 1483system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued 1484system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued 1485system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued 1486system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued 1487system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued 1488system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued 1489system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued |
| 1490system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1491system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1490system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1491system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1492system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued 1493system.cpu2.iq.rate 1.076160 # Inst issue rate 1494system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested 1495system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst) 1496system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads 1497system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes 1498system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses | 1492system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued 1493system.cpu2.iq.rate 1.508309 # Inst issue rate 1494system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested 1495system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) 1496system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads 1497system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes 1498system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses |
| 1499system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1500system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1501system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1499system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1500system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1501system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1502system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses | 1502system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses |
| 1503system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1503system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1504system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores | 1504system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores |
| 1505system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1505system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1506system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed | 1506system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed |
| 1507system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1508system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations | 1507system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1508system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations |
| 1509system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed | 1509system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed |
| 1510system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1511system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1512system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1513system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1514system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1510system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1511system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1512system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1513system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1514system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1515system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing 1516system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking 1517system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking 1518system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ 1519system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch 1520system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions 1521system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions 1522system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions 1523system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall | 1515system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing 1516system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking 1517system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking 1518system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ 1519system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch 1520system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions 1521system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions 1522system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions 1523system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall |
| 1524system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1525system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations | 1524system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1525system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations |
| 1526system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly 1527system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly 1528system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute 1529system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions 1530system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed 1531system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute | 1526system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly 1527system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly 1528system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute 1529system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions 1530system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed 1531system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute |
| 1532system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1532system.cpu2.iew.exec_swp 0 # number of swp insts executed |
| 1533system.cpu2.iew.exec_nop 27525 # number of nop insts executed 1534system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed 1535system.cpu2.iew.exec_branches 36863 # Number of branches executed 1536system.cpu2.iew.exec_stores 22775 # Number of stores executed 1537system.cpu2.iew.exec_rate 1.069917 # Inst execution rate 1538system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit 1539system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back 1540system.cpu2.iew.wb_producers 93200 # num instructions producing a value 1541system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value | 1533system.cpu2.iew.exec_nop 40321 # number of nop insts executed 1534system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed 1535system.cpu2.iew.exec_branches 49723 # Number of branches executed 1536system.cpu2.iew.exec_stores 39200 # Number of stores executed 1537system.cpu2.iew.exec_rate 1.501993 # Inst execution rate 1538system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit 1539system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back 1540system.cpu2.iew.wb_producers 138958 # num instructions producing a value 1541system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value |
| 1542system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1542system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1543system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle 1544system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back | 1543system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle 1544system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back |
| 1545system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1545system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1546system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit 1547system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards 1548system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted 1549system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle 1550system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle 1551system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle | 1546system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit 1547system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards 1548system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted 1549system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle 1550system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle 1551system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle |
| 1552system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1552system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1553system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle 1556system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle 1557system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle 1558system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle 1559system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle 1560system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle 1561system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle | 1553system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle 1556system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle 1557system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle 1558system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle 1559system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle 1560system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle 1561system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle |
| 1562system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1563system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1564system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1562system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1563system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1564system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1565system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle 1566system.cpu2.commit.committedInsts 191691 # Number of instructions committed 1567system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed | 1565system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle 1566system.cpu2.commit.committedInsts 275802 # Number of instructions committed 1567system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed |
| 1568system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 1568system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
| 1569system.cpu2.commit.refs 73311 # Number of memory references committed 1570system.cpu2.commit.loads 51335 # Number of loads committed 1571system.cpu2.commit.membars 7910 # Number of memory barriers committed 1572system.cpu2.commit.branches 35845 # Number of branches committed | 1569system.cpu2.commit.refs 118948 # Number of memory references committed 1570system.cpu2.commit.loads 80570 # Number of loads committed 1571system.cpu2.commit.membars 4324 # Number of memory barriers committed 1572system.cpu2.commit.branches 48669 # Number of branches committed |
| 1573system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 1573system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1574system.cpu2.commit.int_insts 131277 # Number of committed integer instructions. | 1574system.cpu2.commit.int_insts 189737 # Number of committed integer instructions. |
| 1575system.cpu2.commit.function_calls 322 # Number of function calls committed. | 1575system.cpu2.commit.function_calls 322 # Number of function calls committed. |
| 1576system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction 1577system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction 1578system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction 1579system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction 1580system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction 1581system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction 1582system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction 1583system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction 1584system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction 1585system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction 1586system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction 1587system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction 1596system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction 1597system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction 1598system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction 1599system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction 1600system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction 1601system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction 1602system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction 1603system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction 1604system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction 1605system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction 1606system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction 1607system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction | 1576system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction 1577system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction 1578system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction 1579system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction 1580system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction 1581system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction 1582system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction 1583system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction 1584system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction 1585system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction 1586system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction 1587system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction 1596system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction 1597system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction 1598system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction 1599system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction 1600system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction 1601system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction 1602system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction 1603system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction 1604system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction 1605system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction 1606system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction 1607system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction |
| 1608system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1609system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1608system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1609system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1610system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction 1611system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached 1612system.cpu2.rob.rob_reads 360642 # The number of ROB reads 1613system.cpu2.rob.rob_writes 413593 # The number of ROB writes 1614system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself 1615system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling | 1610system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction 1611system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached 1612system.cpu2.rob.rob_reads 445356 # The number of ROB reads 1613system.cpu2.rob.rob_writes 582010 # The number of ROB writes 1614system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself 1615system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 1616system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt | 1616system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| 1617system.cpu2.committedInsts 157149 # Number of Instructions Simulated 1618system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated 1619system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction 1620system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads 1621system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle 1622system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads 1623system.cpu2.int_regfile_reads 286558 # number of integer regfile reads 1624system.cpu2.int_regfile_writes 135654 # number of integer regfile writes | 1617system.cpu2.committedInsts 232019 # Number of Instructions Simulated 1618system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated 1619system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction 1620system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads 1621system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle 1622system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads 1623system.cpu2.int_regfile_reads 423842 # number of integer regfile reads 1624system.cpu2.int_regfile_writes 197927 # number of integer regfile writes |
| 1625system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 1625system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
| 1626system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads | 1626system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads |
| 1627system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1628system.cpu2.dcache.tags.replacements 0 # number of replacements | 1627system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1628system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 1629system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use 1630system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks. | 1629system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use 1630system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks. |
| 1631system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 1631system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
| 1632system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks. | 1632system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks. |
| 1633system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1633system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1634system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor 1635system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy 1636system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy | 1634system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor 1635system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy 1636system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy |
| 1637system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1638system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1639system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 1637system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1638system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1639system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
| 1640system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses 1641system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses 1642system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits 1643system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits 1644system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits 1645system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits 1646system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits 1647system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits 1648system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits 1649system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits 1650system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits 1651system.cpu2.dcache.overall_hits::total 55890 # number of overall hits 1652system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses 1653system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses 1654system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses 1655system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses 1656system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses 1657system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses 1658system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses 1659system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses 1660system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses 1661system.cpu2.dcache.overall_misses::total 639 # number of overall misses 1662system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles 1663system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles 1664system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles 1665system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles 1666system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles 1667system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles 1668system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles 1669system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles 1670system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles 1671system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles 1672system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses) 1673system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses) 1674system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses) 1675system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses) 1676system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) 1677system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 1678system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses 1679system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses 1680system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses 1681system.cpu2.dcache.overall_accesses::total 56529 # number of overall (read+write) accesses 1682system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013950 # miss rate for ReadReq accesses 1683system.cpu2.dcache.ReadReq_miss_rate::total 0.013950 # miss rate for ReadReq accesses 1684system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007122 # miss rate for WriteReq accesses 1685system.cpu2.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses 1686system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.732394 # miss rate for SwapReq accesses 1687system.cpu2.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses 1688system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011304 # miss rate for demand accesses 1689system.cpu2.dcache.demand_miss_rate::total 0.011304 # miss rate for demand accesses 1690system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011304 # miss rate for overall accesses 1691system.cpu2.dcache.overall_miss_rate::total 0.011304 # miss rate for overall accesses 1692system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832 # average ReadReq miss latency 1693system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832 # average ReadReq miss latency 1694system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179 # average WriteReq miss latency 1695system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179 # average WriteReq miss latency 1696system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538 # average SwapReq miss latency 1697system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538 # average SwapReq miss latency 1698system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency 1699system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612 # average overall miss latency 1700system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency 1701system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency | 1640system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses 1641system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses 1642system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits 1643system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits 1644system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits 1645system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits 1646system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 1647system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1648system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits 1649system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits 1650system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits 1651system.cpu2.dcache.overall_hits::total 85153 # number of overall hits 1652system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses 1653system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses 1654system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses 1655system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses 1656system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses 1657system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1658system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses 1659system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses 1660system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses 1661system.cpu2.dcache.overall_misses::total 686 # number of overall misses 1662system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles 1663system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles 1664system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles 1665system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles 1666system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles 1667system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles 1668system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles 1669system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles 1670system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles 1671system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles 1672system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses) 1673system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses) 1674system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses) 1675system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses) 1676system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 1677system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 1678system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses 1679system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses 1680system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses 1681system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses 1682system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses 1683system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses 1684system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses 1685system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses 1686system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses 1687system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses 1688system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses 1689system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses 1690system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses 1691system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses 1692system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency 1693system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency 1694system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency 1695system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency 1696system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency 1697system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency 1698system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency 1699system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency 1700system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency 1701system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency |
| 1702system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1703system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1704system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1705system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1706system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1707system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1708system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1709system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 1702system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1703system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1704system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1705system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1706system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1707system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1708system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1709system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 1710system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits 1711system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 1712system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits 1713system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits 1714system.cpu2.dcache.demand_mshr_hits::cpu2.data 364 # number of demand (read+write) MSHR hits 1715system.cpu2.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 1716system.cpu2.dcache.overall_mshr_hits::cpu2.data 364 # number of overall MSHR hits 1717system.cpu2.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 1718system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 172 # number of ReadReq MSHR misses 1719system.cpu2.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses 1720system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses 1721system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses 1722system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses 1723system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 1724system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses 1725system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses 1726system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses 1727system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses 1728system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles 1729system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles 1730system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles 1731system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles 1732system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles 1733system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles 1734system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3514000 # number of demand (read+write) MSHR miss cycles 1735system.cpu2.dcache.demand_mshr_miss_latency::total 3514000 # number of demand (read+write) MSHR miss cycles 1736system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3514000 # number of overall MSHR miss cycles 1737system.cpu2.dcache.overall_mshr_miss_latency::total 3514000 # number of overall MSHR miss cycles 1738system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004968 # mshr miss rate for ReadReq accesses 1739system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004968 # mshr miss rate for ReadReq accesses 1740system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004702 # mshr miss rate for WriteReq accesses 1741system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004702 # mshr miss rate for WriteReq accesses 1742system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.732394 # mshr miss rate for SwapReq accesses 1743system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses 1744system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses 1745system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses 1746system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses 1747system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses 1748system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency 1749system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency 1750system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency 1751system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency 1752system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency 1753system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency 1754system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency 1755system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency 1756system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency 1757system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency | 1710system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits 1711system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits 1712system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits 1713system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits 1714system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits 1715system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits 1716system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits 1717system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits 1718system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses 1719system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses 1720system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 1721system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 1722system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses 1723system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1724system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses 1725system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 1726system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses 1727system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 1728system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles 1729system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles 1730system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles 1731system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles 1732system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles 1733system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles 1734system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles 1735system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles 1736system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles 1737system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles 1738system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses 1739system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses 1740system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses 1741system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses 1742system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses 1743system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses 1744system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses 1745system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses 1746system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses 1747system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses 1748system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency 1749system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency 1750system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency 1751system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency 1752system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency 1753system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency 1754system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency 1755system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency 1756system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency 1757system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency |
| 1758system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1759system.cpu2.icache.tags.replacements 386 # number of replacements | 1758system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1759system.cpu2.icache.tags.replacements 386 # number of replacements |
| 1760system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use 1761system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks. | 1760system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use 1761system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks. |
| 1762system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. | 1762system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. |
| 1763system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks. | 1763system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks. |
| 1764system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1764system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1765system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor 1766system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy 1767system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy | 1765system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor 1766system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy 1767system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy |
| 1768system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 1769system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1770system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 1771system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id | 1768system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 1769system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1770system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 1771system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id |
| 1772system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses 1773system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses 1774system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits 1775system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits 1776system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits 1777system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits 1778system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits 1779system.cpu2.icache.overall_hits::total 27109 # number of overall hits 1780system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses 1781system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses 1782system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses 1783system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses 1784system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses 1785system.cpu2.icache.overall_misses::total 571 # number of overall misses 1786system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles 1787system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles 1788system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles 1789system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles 1790system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles 1791system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles 1792system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses) 1793system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses) 1794system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses 1795system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses 1796system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses 1797system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses 1798system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses 1799system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses 1800system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses 1801system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses 1802system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses 1803system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses 1804system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency 1805system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency 1806system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency 1807system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency 1808system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency 1809system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency 1810system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked | 1772system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses 1773system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses 1774system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits 1775system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits 1776system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits 1777system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits 1778system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits 1779system.cpu2.icache.overall_hits::total 19454 # number of overall hits 1780system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses 1781system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses 1782system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses 1783system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses 1784system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses 1785system.cpu2.icache.overall_misses::total 573 # number of overall misses 1786system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles 1787system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles 1788system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles 1789system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles 1790system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles 1791system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles 1792system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses) 1793system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses) 1794system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses 1795system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses 1796system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses 1797system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses 1798system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses 1799system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses 1800system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses 1801system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses 1802system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses 1803system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses 1804system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency 1805system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency 1806system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency 1807system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency 1808system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency 1809system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency 1810system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked |
| 1811system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1812system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1813system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked | 1811system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1812system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1813system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1814system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked | 1814system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked |
| 1815system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1816system.cpu2.icache.fast_writes 0 # number of fast writes performed 1817system.cpu2.icache.cache_copies 0 # number of cache copies performed | 1815system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1816system.cpu2.icache.fast_writes 0 # number of fast writes performed 1817system.cpu2.icache.cache_copies 0 # number of cache copies performed |
| 1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits 1819system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits 1821system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits 1823system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits | 1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits 1819system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits 1821system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits 1823system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits |
| 1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses 1825system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses 1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses 1827system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses 1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses 1829system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses | 1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses 1825system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses 1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses 1827system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses 1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses 1829system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses |
| 1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles 1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles 1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles 1833system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles 1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles 1835system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles 1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses 1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses 1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses 1839system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses 1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses 1841system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses 1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency 1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency 1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency 1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency 1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency 1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency | 1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles 1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles 1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles 1833system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles 1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles 1835system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles 1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses 1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses 1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses 1839system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses 1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses 1841system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses 1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency 1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency 1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency 1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency 1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency 1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency |
| 1848system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1848system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1849system.cpu3.branchPred.lookups 58611 # Number of BP lookups 1850system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted 1851system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect 1852system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups 1853system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits | 1849system.cpu3.branchPred.lookups 42820 # Number of BP lookups 1850system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted 1851system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect 1852system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups 1853system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits |
| 1854system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1854system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1855system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage 1856system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. | 1855system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage 1856system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target. |
| 1857system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 1857system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 1858system.cpu3.numCycles 160611 # number of cpu cycles simulated | 1858system.cpu3.numCycles 161928 # number of cpu cycles simulated |
| 1859system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1860system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 1859system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1860system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1861system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss 1862system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed 1863system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered 1864system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken 1865system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked 1866system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing | 1861system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss 1862system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed 1863system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered 1864system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken 1865system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked 1866system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing |
| 1867system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1868system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from | 1867system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1868system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from |
| 1869system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps 1870system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched 1871system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed 1872system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total) 1873system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total) 1874system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total) | 1869system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps 1870system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched 1871system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed 1872system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total) 1873system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total) 1874system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total) |
| 1875system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1875system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1876system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total) 1877system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total) 1878system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total) 1879system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total) 1882system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total) 1883system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total) 1884system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total) | 1876system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total) 1877system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total) 1878system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total) 1879system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total) 1882system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total) 1883system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total) 1884system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total) |
| 1885system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1885system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1888system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total) 1889system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle 1890system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle 1891system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle 1892system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked 1893system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running 1894system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking 1895system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing 1896system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode 1897system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing 1898system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle 1899system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking 1900system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst 1901system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running 1902system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking 1903system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename 1904system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full 1905system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 1906system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers 1907system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed 1908system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made 1909system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups 1910system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed 1911system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing 1912system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed 1913system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed 1914system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer 1915system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit. 1916system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit. 1917system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads. 1918system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores. 1919system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec) 1920system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ 1921system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued 1922system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued 1923system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling 1924system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph 1925system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed 1926system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle 1927system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle 1928system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle | 1888system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total) 1889system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle 1890system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle 1891system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle 1892system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked 1893system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running 1894system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking 1895system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing 1896system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode 1897system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing 1898system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle 1899system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking 1900system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst 1901system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running 1902system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking 1903system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename 1904system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full 1905system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full 1906system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1907system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed 1908system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made 1909system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups 1910system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed 1911system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing 1912system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed 1913system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed 1914system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer 1915system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit. 1916system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit. 1917system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads. 1918system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores. 1919system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec) 1920system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ 1921system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued 1922system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued 1923system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling 1924system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph 1925system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed 1926system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle 1927system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle 1928system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle |
| 1929system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1929system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1930system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle 1931system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle 1932system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle 1933system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle 1934system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle 1935system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle 1936system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle 1937system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle 1938system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle | 1930system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle 1931system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle 1932system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle 1933system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle 1934system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle 1935system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle 1936system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle 1937system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle 1938system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle |
| 1939system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1940system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1941system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1939system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1940system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1941system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1942system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle | 1942system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle |
| 1943system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1943system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1944system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available 1945system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available 1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available 1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available 1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available 1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available 1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available 1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available 1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available 1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available 1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available 1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available 1973system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available 1974system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available | 1944system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available 1945system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available 1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available 1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available 1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available 1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available 1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available 1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available 1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available 1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available 1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available 1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available 1973system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available 1974system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available |
| 1975system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1976system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1977system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1975system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1976system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1977system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1978system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued 1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued 1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued 1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued 1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued 1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued 1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued 1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued 1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued 1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued 1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued 1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued 1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued 1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued 1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued 1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued 1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued 1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued 2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued 2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued 2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued 2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued 2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued 2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued 2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued 2007system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued 2008system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued | 1978system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued 1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued 1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued 1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued 1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued 1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued 1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued 1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued 1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued 1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued 1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued 1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued 1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued 1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued 1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued 1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued 1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued 1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued 2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued 2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued 2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued 2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued 2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued 2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued 2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued 2007system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued 2008system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued |
| 2009system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2010system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2009system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2010system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2011system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued 2012system.cpu3.iq.rate 1.629365 # Inst issue rate 2013system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested 2014system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) 2015system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads 2016system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes 2017system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses | 2011system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued 2012system.cpu3.iq.rate 1.068166 # Inst issue rate 2013system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested 2014system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst) 2015system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads 2016system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes 2017system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses |
| 2018system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2019system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2020system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 2018system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2019system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2020system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 2021system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses | 2021system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses |
| 2022system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 2022system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 2023system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores | 2023system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores |
| 2024system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2024system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2025system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed | 2025system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed |
| 2026system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 2026system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 2027system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations 2028system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed | 2027system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations 2028system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed |
| 2029system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2030system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2031system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2032system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2033system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2029system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2030system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2031system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2032system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2033system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2034system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing 2035system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking 2036system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking 2037system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ 2038system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch 2039system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions 2040system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions 2041system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions 2042system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall | 2034system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing 2035system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking 2036system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking 2037system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ 2038system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch 2039system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions 2040system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions 2041system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions 2042system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall |
| 2043system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 2043system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 2044system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations 2045system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly 2046system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly 2047system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute 2048system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions 2049system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed 2050system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute | 2044system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations 2045system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly 2046system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly 2047system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute 2048system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions 2049system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed 2050system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute |
| 2051system.cpu3.iew.exec_swp 0 # number of swp insts executed | 2051system.cpu3.iew.exec_swp 0 # number of swp insts executed |
| 2052system.cpu3.iew.exec_nop 43196 # number of nop insts executed 2053system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed 2054system.cpu3.iew.exec_branches 52784 # Number of branches executed 2055system.cpu3.iew.exec_stores 43135 # Number of stores executed 2056system.cpu3.iew.exec_rate 1.623027 # Inst execution rate 2057system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit 2058system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back 2059system.cpu3.iew.wb_producers 149829 # num instructions producing a value 2060system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value | 2052system.cpu3.iew.exec_nop 27464 # number of nop insts executed 2053system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed 2054system.cpu3.iew.exec_branches 36861 # Number of branches executed 2055system.cpu3.iew.exec_stores 22696 # Number of stores executed 2056system.cpu3.iew.exec_rate 1.062126 # Inst execution rate 2057system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit 2058system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back 2059system.cpu3.iew.wb_producers 92998 # num instructions producing a value 2060system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value |
| 2061system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2061system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2062system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle 2063system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back | 2062system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle 2063system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back |
| 2064system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2064system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2065system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit 2066system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards 2067system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted 2068system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle 2069system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle 2070system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle | 2065system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit 2066system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards 2067system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted 2068system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle 2069system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle 2070system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle |
| 2071system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2071system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2072system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle 2073system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle 2076system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle 2077system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle 2078system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle 2079system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle 2080system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle | 2072system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle 2073system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle 2076system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle 2077system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle 2078system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle 2079system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle 2080system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle |
| 2081system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2082system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2083system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2081system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2082system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2083system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2084system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle 2085system.cpu3.commit.committedInsts 295833 # Number of instructions committed 2086system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed | 2084system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle 2085system.cpu3.commit.committedInsts 191557 # Number of instructions committed 2086system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed |
| 2087system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 2087system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
| 2088system.cpu3.commit.refs 129866 # Number of memory references committed 2089system.cpu3.commit.loads 87548 # Number of loads committed 2090system.cpu3.commit.membars 3423 # Number of memory barriers committed 2091system.cpu3.commit.branches 51706 # Number of branches committed | 2088system.cpu3.commit.refs 73159 # Number of memory references committed 2089system.cpu3.commit.loads 51261 # Number of loads committed 2090system.cpu3.commit.membars 7996 # Number of memory barriers committed 2091system.cpu3.commit.branches 35851 # Number of branches committed |
| 2092system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 2092system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
| 2093system.cpu3.commit.int_insts 203693 # Number of committed integer instructions. | 2093system.cpu3.commit.int_insts 131131 # Number of committed integer instructions. |
| 2094system.cpu3.commit.function_calls 322 # Number of function calls committed. | 2094system.cpu3.commit.function_calls 322 # Number of function calls committed. |
| 2095system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction 2096system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction 2097system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction 2098system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction 2099system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction 2100system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction 2101system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction 2102system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction 2103system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction 2104system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction 2105system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction 2106system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction 2107system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction 2108system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction 2109system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction 2116system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction 2117system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction 2118system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction 2119system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction 2120system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction 2121system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction 2122system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction 2123system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction 2124system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction 2125system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction 2126system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction | 2095system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction 2096system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction 2097system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction 2098system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction 2099system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction 2100system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction 2101system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction 2102system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction 2103system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction 2104system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction 2105system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction 2106system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction 2107system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction 2108system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction 2109system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction 2116system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction 2117system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction 2118system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction 2119system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction 2120system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction 2121system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction 2122system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction 2123system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction 2124system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction 2125system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction 2126system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction |
| 2127system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2128system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2127system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2128system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2129system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction 2130system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached 2131system.cpu3.rob.rob_reads 464044 # The number of ROB reads 2132system.cpu3.rob.rob_writes 620441 # The number of ROB writes 2133system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself 2134system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling | 2129system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction 2130system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached 2131system.cpu3.rob.rob_reads 361140 # The number of ROB reads 2132system.cpu3.rob.rob_writes 412450 # The number of ROB writes 2133system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself 2134system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 2135system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt | 2135system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| 2136system.cpu3.committedInsts 249913 # Number of Instructions Simulated 2137system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated 2138system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction 2139system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads 2140system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle 2141system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads 2142system.cpu3.int_regfile_reads 456401 # number of integer regfile reads 2143system.cpu3.int_regfile_writes 212686 # number of integer regfile writes | 2136system.cpu3.committedInsts 156923 # Number of Instructions Simulated 2137system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated 2138system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction 2139system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads 2140system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle 2141system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads 2142system.cpu3.int_regfile_reads 285937 # number of integer regfile reads 2143system.cpu3.int_regfile_writes 135307 # number of integer regfile writes |
| 2144system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 2144system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
| 2145system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads | 2145system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads |
| 2146system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2147system.cpu3.dcache.tags.replacements 0 # number of replacements | 2146system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2147system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 2148system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use 2149system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks. | 2148system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use 2149system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks. |
| 2150system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 2150system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
| 2151system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks. | 2151system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks. |
| 2152system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2152system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2153system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor 2154system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy 2155system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy | 2153system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor 2154system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy 2155system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy |
| 2156system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2157system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2158system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 2156system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2157system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2158system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
| 2159system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses 2160system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses 2161system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits 2162system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits 2163system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits 2164system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits 2165system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits 2166system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits 2167system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits 2168system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits 2169system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits 2170system.cpu3.dcache.overall_hits::total 92057 # number of overall hits 2171system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses 2172system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses 2173system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses 2174system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses 2175system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 2176system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 2177system.cpu3.dcache.demand_misses::cpu3.data 674 # number of demand (read+write) misses 2178system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses 2179system.cpu3.dcache.overall_misses::cpu3.data 674 # number of overall misses 2180system.cpu3.dcache.overall_misses::total 674 # number of overall misses 2181system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles 2182system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles 2183system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles 2184system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles 2185system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles 2186system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles 2187system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles 2188system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles 2189system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles 2190system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles 2191system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses) 2192system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses) 2193system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses) 2194system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses) 2195system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) 2196system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 2197system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses 2198system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses 2199system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses 2200system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses 2201system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses 2202system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses 2203system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses 2204system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses 2205system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses 2206system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses 2207system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses 2208system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses 2209system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses 2210system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses 2211system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency 2212system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency 2213system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency 2214system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency 2215system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency 2216system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency 2217system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency 2218system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency 2219system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency 2220system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency | 2159system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses 2160system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses 2161system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits 2162system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits 2163system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits 2164system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits 2165system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits 2166system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits 2167system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits 2168system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits 2169system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits 2170system.cpu3.dcache.overall_hits::total 55817 # number of overall hits 2171system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses 2172system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses 2173system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses 2174system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses 2175system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 2176system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 2177system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses 2178system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses 2179system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses 2180system.cpu3.dcache.overall_misses::total 617 # number of overall misses 2181system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles 2182system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles 2183system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles 2184system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles 2185system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles 2186system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles 2187system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles 2188system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles 2189system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles 2190system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles 2191system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses) 2192system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses) 2193system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses) 2194system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses) 2195system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 2196system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 2197system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses 2198system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses 2199system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses 2200system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses 2201system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses 2202system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses 2203system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses 2204system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses 2205system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses 2206system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses 2207system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses 2208system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses 2209system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses 2210system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses 2211system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency 2212system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency 2213system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency 2214system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency 2215system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency 2216system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency 2217system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency 2218system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency 2219system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency 2220system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency |
| 2221system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2222system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2223system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2224system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2225system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2226system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2227system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2228system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 2221system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2222system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2223system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2224system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2225system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2226system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2227system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2228system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 2229system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 369 # number of ReadReq MSHR hits 2230system.cpu3.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits 2231system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 48 # number of WriteReq MSHR hits 2232system.cpu3.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits 2233system.cpu3.dcache.demand_mshr_hits::cpu3.data 417 # number of demand (read+write) MSHR hits 2234system.cpu3.dcache.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits 2235system.cpu3.dcache.overall_mshr_hits::cpu3.data 417 # number of overall MSHR hits 2236system.cpu3.dcache.overall_mshr_hits::total 417 # number of overall MSHR hits 2237system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses 2238system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 2239system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses 2240system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 2241system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 2242system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 2243system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses 2244system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 2245system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses 2246system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses 2247system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles 2248system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles 2249system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles 2250system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles 2251system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles 2252system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles 2253system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles 2254system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles 2255system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles 2256system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles 2257system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses 2258system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses 2259system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses 2260system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses 2261system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses 2262system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses 2263system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses 2264system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses 2265system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses 2266system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses 2267system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency 2268system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency 2269system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency 2270system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency 2271system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency 2272system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency 2273system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency 2274system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency 2275system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency 2276system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency | 2229system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits 2230system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits 2231system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits 2232system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 2233system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits 2234system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 2235system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits 2236system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 2237system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses 2238system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses 2239system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses 2240system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 2241system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 2242system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 2243system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses 2244system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses 2245system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses 2246system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses 2247system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles 2248system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles 2249system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles 2250system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles 2251system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles 2252system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles 2253system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles 2254system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles 2255system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles 2256system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles 2257system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses 2258system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses 2259system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses 2260system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses 2261system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses 2262system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses 2263system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses 2264system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses 2265system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses 2266system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses 2267system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency 2268system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency 2269system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency 2270system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency 2271system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency 2272system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency 2273system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency 2274system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency 2275system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency 2276system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency |
| 2277system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2278system.cpu3.icache.tags.replacements 384 # number of replacements | 2277system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2278system.cpu3.icache.tags.replacements 384 # number of replacements |
| 2279system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use 2280system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks. | 2279system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use 2280system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks. |
| 2281system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. | 2281system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. |
| 2282system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks. | 2282system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks. |
| 2283system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2283system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2284system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor 2285system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy 2286system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy | 2284system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor 2285system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy 2286system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy |
| 2287system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 2288system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2289system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 2290system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id | 2287system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 2288system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2289system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 2290system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id |
| 2291system.cpu3.icache.tags.tag_accesses 18767 # Number of tag accesses 2292system.cpu3.icache.tags.data_accesses 18767 # Number of data accesses 2293system.cpu3.icache.ReadReq_hits::cpu3.inst 17696 # number of ReadReq hits 2294system.cpu3.icache.ReadReq_hits::total 17696 # number of ReadReq hits 2295system.cpu3.icache.demand_hits::cpu3.inst 17696 # number of demand (read+write) hits 2296system.cpu3.icache.demand_hits::total 17696 # number of demand (read+write) hits 2297system.cpu3.icache.overall_hits::cpu3.inst 17696 # number of overall hits 2298system.cpu3.icache.overall_hits::total 17696 # number of overall hits 2299system.cpu3.icache.ReadReq_misses::cpu3.inst 573 # number of ReadReq misses 2300system.cpu3.icache.ReadReq_misses::total 573 # number of ReadReq misses 2301system.cpu3.icache.demand_misses::cpu3.inst 573 # number of demand (read+write) misses 2302system.cpu3.icache.demand_misses::total 573 # number of demand (read+write) misses 2303system.cpu3.icache.overall_misses::cpu3.inst 573 # number of overall misses 2304system.cpu3.icache.overall_misses::total 573 # number of overall misses 2305system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles 2306system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles 2307system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles 2308system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles 2309system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles 2310system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles 2311system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses) 2312system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses) 2313system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses 2314system.cpu3.icache.demand_accesses::total 18269 # number of demand (read+write) accesses 2315system.cpu3.icache.overall_accesses::cpu3.inst 18269 # number of overall (read+write) accesses 2316system.cpu3.icache.overall_accesses::total 18269 # number of overall (read+write) accesses 2317system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031365 # miss rate for ReadReq accesses 2318system.cpu3.icache.ReadReq_miss_rate::total 0.031365 # miss rate for ReadReq accesses 2319system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031365 # miss rate for demand accesses 2320system.cpu3.icache.demand_miss_rate::total 0.031365 # miss rate for demand accesses 2321system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031365 # miss rate for overall accesses 2322system.cpu3.icache.overall_miss_rate::total 0.031365 # miss rate for overall accesses 2323system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187 # average ReadReq miss latency 2324system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187 # average ReadReq miss latency 2325system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency 2326system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency 2327system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency 2328system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency | 2291system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses 2292system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses 2293system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits 2294system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits 2295system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits 2296system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits 2297system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits 2298system.cpu3.icache.overall_hits::total 27370 # number of overall hits 2299system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses 2300system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses 2301system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses 2302system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses 2303system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses 2304system.cpu3.icache.overall_misses::total 571 # number of overall misses 2305system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles 2306system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles 2307system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles 2308system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles 2309system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles 2310system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles 2311system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses) 2312system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses) 2313system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses 2314system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses 2315system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses 2316system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses 2317system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses 2318system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses 2319system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses 2320system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses 2321system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses 2322system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses 2323system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency 2324system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency 2325system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency 2326system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency 2327system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency 2328system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency |
| 2329system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2330system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2331system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2332system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2333system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2334system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2335system.cpu3.icache.fast_writes 0 # number of fast writes performed 2336system.cpu3.icache.cache_copies 0 # number of cache copies performed | 2329system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2330system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2331system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2332system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2333system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2334system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2335system.cpu3.icache.fast_writes 0 # number of fast writes performed 2336system.cpu3.icache.cache_copies 0 # number of cache copies performed |
| 2337system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits 2338system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 2339system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits 2340system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 2341system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits 2342system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits | 2337system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits 2338system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 2339system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits 2340system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 2341system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits 2342system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits |
| 2343system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses 2344system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 2345system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses 2346system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses 2347system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses 2348system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses | 2343system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses 2344system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 2345system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses 2346system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses 2347system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses 2348system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses |
| 2349system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles 2350system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles 2351system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles 2352system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles 2353system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # number of overall MSHR miss cycles 2354system.cpu3.icache.overall_mshr_miss_latency::total 6421000 # number of overall MSHR miss cycles 2355system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for ReadReq accesses 2356system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027259 # mshr miss rate for ReadReq accesses 2357system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for demand accesses 2358system.cpu3.icache.demand_mshr_miss_rate::total 0.027259 # mshr miss rate for demand accesses 2359system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for overall accesses 2360system.cpu3.icache.overall_mshr_miss_rate::total 0.027259 # mshr miss rate for overall accesses 2361system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average ReadReq mshr miss latency 2362system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12893.574297 # average ReadReq mshr miss latency 2363system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency 2364system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency 2365system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency 2366system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency | 2349system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles 2350system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles 2351system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles 2352system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles 2353system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles 2354system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles 2355system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses 2356system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses 2357system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses 2358system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses 2359system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses 2360system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses 2361system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency 2362system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency 2363system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency 2364system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency 2365system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency 2366system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency |
| 2367system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2368system.l2c.tags.replacements 0 # number of replacements | 2367system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2368system.l2c.tags.replacements 0 # number of replacements |
| 2369system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use 2370system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. | 2369system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use 2370system.l2c.tags.total_refs 2348 # Total number of references to valid blocks. |
| 2371system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. | 2371system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. |
| 2372system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. | 2372system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks. |
| 2373system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2373system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2374system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor 2375system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor 2376system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor 2377system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor 2378system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor 2379system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor 2381system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor 2382system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor | 2374system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor 2375system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor 2376system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor 2377system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor 2378system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor 2379system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor 2381system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor 2382system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor |
| 2383system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy | 2383system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy |
| 2384system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy | 2384system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy |
| 2385system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy | 2385system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy |
| 2386system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy | 2386system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy |
| 2387system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy | 2387system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy |
| 2388system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy 2389system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy 2390system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy 2391system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2392system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy | 2388system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy 2389system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy 2390system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy 2391system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy 2392system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy |
| 2393system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 2394system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id | 2393system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 2394system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id |
| 2395system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 2396system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id | 2395system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id 2396system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id |
| 2397system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id | 2397system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id |
| 2398system.l2c.tags.tag_accesses 25618 # Number of tag accesses 2399system.l2c.tags.data_accesses 25618 # Number of data accesses | 2398system.l2c.tags.tag_accesses 25610 # Number of tag accesses 2399system.l2c.tags.data_accesses 25610 # Number of data accesses |
| 2400system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2401system.l2c.Writeback_hits::total 1 # number of Writeback hits 2402system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2403system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2404system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits | 2400system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2401system.l2c.Writeback_hits::total 1 # number of Writeback hits 2402system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2403system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2404system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits |
| 2405system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits 2406system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits 2407system.l2c.ReadCleanReq_hits::cpu3.inst 491 # number of ReadCleanReq hits | 2405system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits 2406system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits 2407system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits |
| 2408system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits 2409system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 2410system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits 2411system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits 2412system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 2413system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 2414system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits | 2408system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits 2409system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 2410system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits 2411system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits 2412system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 2413system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 2414system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits |
| 2416system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits | 2416system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits |
| 2417system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits | 2417system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits |
| 2418system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits | 2418system.l2c.demand_hits::cpu2.inst 490 # number of demand (read+write) hits |
| 2419system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits | 2419system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits |
| 2420system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits | 2420system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits |
| 2421system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2422system.l2c.demand_hits::total 1670 # number of demand (read+write) hits 2423system.l2c.overall_hits::cpu0.inst 246 # number of overall hits 2424system.l2c.overall_hits::cpu0.data 5 # number of overall hits | 2421system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2422system.l2c.demand_hits::total 1670 # number of demand (read+write) hits 2423system.l2c.overall_hits::cpu0.inst 246 # number of overall hits 2424system.l2c.overall_hits::cpu0.data 5 # number of overall hits |
| 2425system.l2c.overall_hits::cpu1.inst 410 # number of overall hits | 2425system.l2c.overall_hits::cpu1.inst 409 # number of overall hits |
| 2426system.l2c.overall_hits::cpu1.data 5 # number of overall hits | 2426system.l2c.overall_hits::cpu1.data 5 # number of overall hits |
| 2427system.l2c.overall_hits::cpu2.inst 491 # number of overall hits | 2427system.l2c.overall_hits::cpu2.inst 490 # number of overall hits |
| 2428system.l2c.overall_hits::cpu2.data 11 # number of overall hits | 2428system.l2c.overall_hits::cpu2.data 11 # number of overall hits |
| 2429system.l2c.overall_hits::cpu3.inst 491 # number of overall hits | 2429system.l2c.overall_hits::cpu3.inst 493 # number of overall hits |
| 2430system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2431system.l2c.overall_hits::total 1670 # number of overall hits 2432system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses 2433system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses | 2430system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2431system.l2c.overall_hits::total 1670 # number of overall hits 2432system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses 2433system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses |
| 2434system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses 2436system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses | 2434system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses 2436system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses |
| 2437system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2438system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2439system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2442system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses | 2437system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2438system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2439system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2442system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses |
| 2443system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses 2444system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses 2445system.l2c.ReadCleanReq_misses::cpu3.inst 7 # number of ReadCleanReq misses | 2443system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses 2444system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses 2445system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses |
| 2446system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses 2447system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses 2448system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 2449system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 2452system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses 2453system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses | 2446system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses 2447system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses 2448system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 2449system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 2452system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses 2453system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses |
| 2454system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses | 2454system.l2c.demand_misses::cpu1.inst 87 # number of demand (read+write) misses |
| 2455system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses | 2455system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses |
| 2456system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses | 2456system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses |
| 2457system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses | 2457system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses |
| 2458system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses | 2458system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses |
| 2459system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2460system.l2c.demand_misses::total 679 # number of demand (read+write) misses 2461system.l2c.overall_misses::cpu0.inst 362 # number of overall misses 2462system.l2c.overall_misses::cpu0.data 169 # number of overall misses | 2459system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2460system.l2c.demand_misses::total 679 # number of demand (read+write) misses 2461system.l2c.overall_misses::cpu0.inst 362 # number of overall misses 2462system.l2c.overall_misses::cpu0.data 169 # number of overall misses |
| 2463system.l2c.overall_misses::cpu1.inst 86 # number of overall misses | 2463system.l2c.overall_misses::cpu1.inst 87 # number of overall misses |
| 2464system.l2c.overall_misses::cpu1.data 20 # number of overall misses | 2464system.l2c.overall_misses::cpu1.data 20 # number of overall misses |
| 2465system.l2c.overall_misses::cpu2.inst 9 # number of overall misses | 2465system.l2c.overall_misses::cpu2.inst 10 # number of overall misses |
| 2466system.l2c.overall_misses::cpu2.data 13 # number of overall misses | 2466system.l2c.overall_misses::cpu2.data 13 # number of overall misses |
| 2467system.l2c.overall_misses::cpu3.inst 7 # number of overall misses | 2467system.l2c.overall_misses::cpu3.inst 5 # number of overall misses |
| 2468system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2469system.l2c.overall_misses::total 679 # number of overall misses | 2468system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2469system.l2c.overall_misses::total 679 # number of overall misses |
| 2470system.l2c.ReadExReq_miss_latency::cpu0.data 7390000 # number of ReadExReq miss cycles | 2470system.l2c.ReadExReq_miss_latency::cpu0.data 7619000 # number of ReadExReq miss cycles |
| 2471system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles | 2471system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles |
| 2472system.l2c.ReadExReq_miss_latency::cpu2.data 956500 # number of ReadExReq miss cycles 2473system.l2c.ReadExReq_miss_latency::cpu3.data 1308500 # number of ReadExReq miss cycles 2474system.l2c.ReadExReq_miss_latency::total 10714000 # number of ReadExReq miss cycles 2475system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27682000 # number of ReadCleanReq miss cycles 2476system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6449000 # number of ReadCleanReq miss cycles 2477system.l2c.ReadCleanReq_miss_latency::cpu2.inst 632000 # number of ReadCleanReq miss cycles 2478system.l2c.ReadCleanReq_miss_latency::cpu3.inst 514000 # number of ReadCleanReq miss cycles 2479system.l2c.ReadCleanReq_miss_latency::total 35277000 # number of ReadCleanReq miss cycles | 2472system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles 2473system.l2c.ReadExReq_miss_latency::cpu3.data 1133500 # number of ReadExReq miss cycles 2474system.l2c.ReadExReq_miss_latency::total 11297000 # number of ReadExReq miss cycles 2475system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679000 # number of ReadCleanReq miss cycles 2476system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6525500 # number of ReadCleanReq miss cycles 2477system.l2c.ReadCleanReq_miss_latency::cpu2.inst 707500 # number of ReadCleanReq miss cycles 2478system.l2c.ReadCleanReq_miss_latency::cpu3.inst 342000 # number of ReadCleanReq miss cycles 2479system.l2c.ReadCleanReq_miss_latency::total 35254000 # number of ReadCleanReq miss cycles |
| 2480system.l2c.ReadSharedReq_miss_latency::cpu0.data 5980500 # number of ReadSharedReq miss cycles 2481system.l2c.ReadSharedReq_miss_latency::cpu1.data 540500 # number of ReadSharedReq miss cycles | 2480system.l2c.ReadSharedReq_miss_latency::cpu0.data 5980500 # number of ReadSharedReq miss cycles 2481system.l2c.ReadSharedReq_miss_latency::cpu1.data 540500 # number of ReadSharedReq miss cycles |
| 2482system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles 2483system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles | 2482system.l2c.ReadSharedReq_miss_latency::cpu2.data 96500 # number of ReadSharedReq miss cycles 2483system.l2c.ReadSharedReq_miss_latency::cpu3.data 82500 # number of ReadSharedReq miss cycles |
| 2484system.l2c.ReadSharedReq_miss_latency::total 6700000 # number of ReadSharedReq miss cycles | 2484system.l2c.ReadSharedReq_miss_latency::total 6700000 # number of ReadSharedReq miss cycles |
| 2485system.l2c.demand_miss_latency::cpu0.inst 27682000 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu0.data 13370500 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::cpu1.inst 6449000 # number of demand (read+write) miss cycles | 2485system.l2c.demand_miss_latency::cpu0.inst 27679000 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu0.data 13599500 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::cpu1.inst 6525500 # number of demand (read+write) miss cycles |
| 2488system.l2c.demand_miss_latency::cpu1.data 1599500 # number of demand (read+write) miss cycles | 2488system.l2c.demand_miss_latency::cpu1.data 1599500 # number of demand (read+write) miss cycles |
| 2489system.l2c.demand_miss_latency::cpu2.inst 632000 # number of demand (read+write) miss cycles 2490system.l2c.demand_miss_latency::cpu2.data 1039000 # number of demand (read+write) miss cycles 2491system.l2c.demand_miss_latency::cpu3.inst 514000 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::cpu3.data 1405000 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::total 52691000 # number of demand (read+write) miss cycles 2494system.l2c.overall_miss_latency::cpu0.inst 27682000 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu0.data 13370500 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.inst 6449000 # number of overall miss cycles | 2489system.l2c.demand_miss_latency::cpu2.inst 707500 # number of demand (read+write) miss cycles 2490system.l2c.demand_miss_latency::cpu2.data 1582000 # number of demand (read+write) miss cycles 2491system.l2c.demand_miss_latency::cpu3.inst 342000 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::cpu3.data 1216000 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::total 53251000 # number of demand (read+write) miss cycles 2494system.l2c.overall_miss_latency::cpu0.inst 27679000 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu0.data 13599500 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.inst 6525500 # number of overall miss cycles |
| 2497system.l2c.overall_miss_latency::cpu1.data 1599500 # number of overall miss cycles | 2497system.l2c.overall_miss_latency::cpu1.data 1599500 # number of overall miss cycles |
| 2498system.l2c.overall_miss_latency::cpu2.inst 632000 # number of overall miss cycles 2499system.l2c.overall_miss_latency::cpu2.data 1039000 # number of overall miss cycles 2500system.l2c.overall_miss_latency::cpu3.inst 514000 # number of overall miss cycles 2501system.l2c.overall_miss_latency::cpu3.data 1405000 # number of overall miss cycles 2502system.l2c.overall_miss_latency::total 52691000 # number of overall miss cycles | 2498system.l2c.overall_miss_latency::cpu2.inst 707500 # number of overall miss cycles 2499system.l2c.overall_miss_latency::cpu2.data 1582000 # number of overall miss cycles 2500system.l2c.overall_miss_latency::cpu3.inst 342000 # number of overall miss cycles 2501system.l2c.overall_miss_latency::cpu3.data 1216000 # number of overall miss cycles 2502system.l2c.overall_miss_latency::total 53251000 # number of overall miss cycles |
| 2503system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2504system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2505system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 2506system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) | 2503system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2504system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2505system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 2506system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) |
| 2507system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) 2508system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) 2509system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) | 2507system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) 2508system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) 2509system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) |
| 2510system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2511system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2512system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2513system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2514system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2515system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses) 2516system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses) 2517system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 2539system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses 2541system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2542system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses 2543system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses 2544system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2545system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2546system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses | 2510system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2511system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2512system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2513system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2514system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2515system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses) 2516system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses) 2517system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 2539system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses 2541system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2542system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses 2543system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses 2544system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2545system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2546system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses |
| 2547system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses | 2547system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses |
| 2548system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2549system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2550system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2551system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2552system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2553system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses | 2548system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2549system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2550system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2551system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2552system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2553system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses |
| 2554system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses 2555system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses 2556system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadCleanReq accesses | 2554system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.175403 # miss rate for ReadCleanReq accesses 2555system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020000 # miss rate for ReadCleanReq accesses 2556system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses |
| 2557system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses 2558system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses 2559system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses 2560system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses 2561system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses 2562system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses 2563system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses | 2557system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses 2558system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses 2559system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses 2560system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses 2561system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses 2562system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses 2563system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses |
| 2565system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses | 2565system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses |
| 2566system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses | 2566system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses |
| 2567system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses | 2567system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses |
| 2568system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses | 2568system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses |
| 2569system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses | 2569system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses |
| 2570system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2571system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses 2572system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses | 2570system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2571system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses 2572system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses |
| 2574system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses | 2574system.l2c.overall_miss_rate::cpu1.inst 0.175403 # miss rate for overall accesses |
| 2575system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses | 2575system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses |
| 2576system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses | 2576system.l2c.overall_miss_rate::cpu2.inst 0.020000 # miss rate for overall accesses |
| 2577system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses | 2577system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses |
| 2578system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses | 2578system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses |
| 2579system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2580system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses | 2579system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2580system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses |
| 2581system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78617.021277 # average ReadExReq miss latency | 2581system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81053.191489 # average ReadExReq miss latency |
| 2582system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency | 2582system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency |
| 2583system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79708.333333 # average ReadExReq miss latency 2584system.l2c.ReadExReq_avg_miss_latency::cpu3.data 109041.666667 # average ReadExReq miss latency 2585system.l2c.ReadExReq_avg_miss_latency::total 81786.259542 # average ReadExReq miss latency 2586system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76469.613260 # average ReadCleanReq miss latency 2587system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74988.372093 # average ReadCleanReq miss latency 2588system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70222.222222 # average ReadCleanReq miss latency 2589system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73428.571429 # average ReadCleanReq miss latency 2590system.l2c.ReadCleanReq_avg_miss_latency::total 76028.017241 # average ReadCleanReq miss latency | 2583system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency 2584system.l2c.ReadExReq_avg_miss_latency::cpu3.data 94458.333333 # average ReadExReq miss latency 2585system.l2c.ReadExReq_avg_miss_latency::total 86236.641221 # average ReadExReq miss latency 2586system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76461.325967 # average ReadCleanReq miss latency 2587system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 75005.747126 # average ReadCleanReq miss latency 2588system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70750 # average ReadCleanReq miss latency 2589system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68400 # average ReadCleanReq miss latency 2590system.l2c.ReadCleanReq_avg_miss_latency::total 75978.448276 # average ReadCleanReq miss latency |
| 2591system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79740 # average ReadSharedReq miss latency 2592system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714 # average ReadSharedReq miss latency | 2591system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79740 # average ReadSharedReq miss latency 2592system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714 # average ReadSharedReq miss latency |
| 2593system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency 2594system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency | 2593system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96500 # average ReadSharedReq miss latency 2594system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 82500 # average ReadSharedReq miss latency |
| 2595system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762 # average ReadSharedReq miss latency | 2595system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762 # average ReadSharedReq miss latency |
| 2596system.l2c.demand_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency 2597system.l2c.demand_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency 2598system.l2c.demand_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency | 2596system.l2c.demand_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency 2597system.l2c.demand_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency 2598system.l2c.demand_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency |
| 2599system.l2c.demand_avg_miss_latency::cpu1.data 79975 # average overall miss latency | 2599system.l2c.demand_avg_miss_latency::cpu1.data 79975 # average overall miss latency |
| 2600system.l2c.demand_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency 2601system.l2c.demand_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::total 77600.883652 # average overall miss latency 2605system.l2c.overall_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency 2606system.l2c.overall_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency 2607system.l2c.overall_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency | 2600system.l2c.demand_avg_miss_latency::cpu2.inst 70750 # average overall miss latency 2601system.l2c.demand_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu3.inst 68400 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::total 78425.625920 # average overall miss latency 2605system.l2c.overall_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency 2606system.l2c.overall_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency 2607system.l2c.overall_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency |
| 2608system.l2c.overall_avg_miss_latency::cpu1.data 79975 # average overall miss latency | 2608system.l2c.overall_avg_miss_latency::cpu1.data 79975 # average overall miss latency |
| 2609system.l2c.overall_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency 2610system.l2c.overall_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::total 77600.883652 # average overall miss latency | 2609system.l2c.overall_avg_miss_latency::cpu2.inst 70750 # average overall miss latency 2610system.l2c.overall_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu3.inst 68400 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::total 78425.625920 # average overall miss latency |
| 2614system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2615system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2616system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2617system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2618system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2619system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2620system.l2c.fast_writes 0 # number of fast writes performed 2621system.l2c.cache_copies 0 # number of cache copies performed 2622system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2623system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits | 2614system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2615system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2616system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2617system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2618system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2619system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2620system.l2c.fast_writes 0 # number of fast writes performed 2621system.l2c.cache_copies 0 # number of cache copies performed 2622system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2623system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits |
| 2624system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits 2625system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits | 2624system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits 2625system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits |
| 2626system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 2627system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2628system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits | 2626system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 2627system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2628system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits |
| 2629system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits 2630system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits | 2629system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits 2630system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits |
| 2631system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 2632system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2633system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits | 2631system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 2632system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2633system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits |
| 2634system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits 2635system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits | 2634system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits 2635system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits |
| 2636system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits 2637system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses 2638system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses | 2636system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits 2637system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses 2638system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses |
| 2639system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses 2640system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses 2641system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses | 2639system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses 2640system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses 2641system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses |
| 2642system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2643system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2644system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2645system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2646system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2647system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses | 2642system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2643system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2644system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2645system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2646system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2647system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses |
| 2648system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses 2649system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses 2650system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5 # number of ReadCleanReq MSHR misses | 2648system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 83 # number of ReadCleanReq MSHR misses 2649system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5 # number of ReadCleanReq MSHR misses 2650system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses |
| 2651system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses 2652system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses 2653system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses 2654system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses 2655system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses 2656system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses 2657system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses 2658system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses | 2651system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses 2652system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses 2653system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses 2654system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses 2655system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses 2656system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses 2657system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses 2658system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses |
| 2659system.l2c.demand_mshr_misses::cpu1.inst 82 # number of demand (read+write) MSHR misses | 2659system.l2c.demand_mshr_misses::cpu1.inst 83 # number of demand (read+write) MSHR misses |
| 2660system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses | 2660system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses |
| 2661system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses | 2661system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses |
| 2662system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses | 2662system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses |
| 2663system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses | 2663system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses |
| 2664system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses 2666system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses 2667system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses | 2664system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses 2666system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses 2667system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses |
| 2668system.l2c.overall_mshr_misses::cpu1.inst 82 # number of overall MSHR misses | 2668system.l2c.overall_mshr_misses::cpu1.inst 83 # number of overall MSHR misses |
| 2669system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses | 2669system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses |
| 2670system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses | 2670system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses |
| 2671system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses | 2671system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses |
| 2672system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses | 2672system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses |
| 2673system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses | 2673system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses |
| 2675system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 560500 # number of UpgradeReq MSHR miss cycles 2676system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 396000 # number of UpgradeReq MSHR miss cycles 2677system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 438496 # number of UpgradeReq MSHR miss cycles 2678system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 459499 # number of UpgradeReq MSHR miss cycles 2679system.l2c.UpgradeReq_mshr_miss_latency::total 1854495 # number of UpgradeReq MSHR miss cycles 2680system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6450000 # number of ReadExReq MSHR miss cycles | 2675system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 586500 # number of UpgradeReq MSHR miss cycles 2676system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 413500 # number of UpgradeReq MSHR miss cycles 2677system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 436000 # number of UpgradeReq MSHR miss cycles 2678system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457997 # number of UpgradeReq MSHR miss cycles 2679system.l2c.UpgradeReq_mshr_miss_latency::total 1893997 # number of UpgradeReq MSHR miss cycles 2680system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6679000 # number of ReadExReq MSHR miss cycles |
| 2681system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles | 2681system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles |
| 2682system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 836500 # number of ReadExReq MSHR miss cycles 2683system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1188500 # number of ReadExReq MSHR miss cycles 2684system.l2c.ReadExReq_mshr_miss_latency::total 9404000 # number of ReadExReq MSHR miss cycles 2685system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23878500 # number of ReadCleanReq MSHR miss cycles 2686system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5430000 # number of ReadCleanReq MSHR miss cycles 2687system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 217000 # number of ReadCleanReq MSHR miss cycles 2688system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 364000 # number of ReadCleanReq MSHR miss cycles 2689system.l2c.ReadCleanReq_mshr_miss_latency::total 29889500 # number of ReadCleanReq MSHR miss cycles | 2682system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1365500 # number of ReadExReq MSHR miss cycles 2683system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1013500 # number of ReadExReq MSHR miss cycles 2684system.l2c.ReadExReq_mshr_miss_latency::total 9987000 # number of ReadExReq MSHR miss cycles 2685system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23885500 # number of ReadCleanReq MSHR miss cycles 2686system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5496500 # number of ReadCleanReq MSHR miss cycles 2687system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 363500 # number of ReadCleanReq MSHR miss cycles 2688system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 146000 # number of ReadCleanReq MSHR miss cycles 2689system.l2c.ReadCleanReq_mshr_miss_latency::total 29891500 # number of ReadCleanReq MSHR miss cycles |
| 2690system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5230500 # number of ReadSharedReq MSHR miss cycles 2691system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470500 # number of ReadSharedReq MSHR miss cycles | 2690system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5230500 # number of ReadSharedReq MSHR miss cycles 2691system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470500 # number of ReadSharedReq MSHR miss cycles |
| 2692system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles 2693system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles | 2692system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 86500 # number of ReadSharedReq MSHR miss cycles 2693system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 72500 # number of ReadSharedReq MSHR miss cycles |
| 2694system.l2c.ReadSharedReq_mshr_miss_latency::total 5860000 # number of ReadSharedReq MSHR miss cycles | 2694system.l2c.ReadSharedReq_mshr_miss_latency::total 5860000 # number of ReadSharedReq MSHR miss cycles |
| 2695system.l2c.demand_mshr_miss_latency::cpu0.inst 23878500 # number of demand (read+write) MSHR miss cycles 2696system.l2c.demand_mshr_miss_latency::cpu0.data 11680500 # number of demand (read+write) MSHR miss cycles 2697system.l2c.demand_mshr_miss_latency::cpu1.inst 5430000 # number of demand (read+write) MSHR miss cycles | 2695system.l2c.demand_mshr_miss_latency::cpu0.inst 23885500 # number of demand (read+write) MSHR miss cycles 2696system.l2c.demand_mshr_miss_latency::cpu0.data 11909500 # number of demand (read+write) MSHR miss cycles 2697system.l2c.demand_mshr_miss_latency::cpu1.inst 5496500 # number of demand (read+write) MSHR miss cycles |
| 2698system.l2c.demand_mshr_miss_latency::cpu1.data 1399500 # number of demand (read+write) MSHR miss cycles | 2698system.l2c.demand_mshr_miss_latency::cpu1.data 1399500 # number of demand (read+write) MSHR miss cycles |
| 2699system.l2c.demand_mshr_miss_latency::cpu2.inst 217000 # number of demand (read+write) MSHR miss cycles 2700system.l2c.demand_mshr_miss_latency::cpu2.data 909000 # number of demand (read+write) MSHR miss cycles 2701system.l2c.demand_mshr_miss_latency::cpu3.inst 364000 # number of demand (read+write) MSHR miss cycles 2702system.l2c.demand_mshr_miss_latency::cpu3.data 1275000 # number of demand (read+write) MSHR miss cycles 2703system.l2c.demand_mshr_miss_latency::total 45153500 # number of demand (read+write) MSHR miss cycles 2704system.l2c.overall_mshr_miss_latency::cpu0.inst 23878500 # number of overall MSHR miss cycles 2705system.l2c.overall_mshr_miss_latency::cpu0.data 11680500 # number of overall MSHR miss cycles 2706system.l2c.overall_mshr_miss_latency::cpu1.inst 5430000 # number of overall MSHR miss cycles | 2699system.l2c.demand_mshr_miss_latency::cpu2.inst 363500 # number of demand (read+write) MSHR miss cycles 2700system.l2c.demand_mshr_miss_latency::cpu2.data 1452000 # number of demand (read+write) MSHR miss cycles 2701system.l2c.demand_mshr_miss_latency::cpu3.inst 146000 # number of demand (read+write) MSHR miss cycles 2702system.l2c.demand_mshr_miss_latency::cpu3.data 1086000 # number of demand (read+write) MSHR miss cycles 2703system.l2c.demand_mshr_miss_latency::total 45738500 # number of demand (read+write) MSHR miss cycles 2704system.l2c.overall_mshr_miss_latency::cpu0.inst 23885500 # number of overall MSHR miss cycles 2705system.l2c.overall_mshr_miss_latency::cpu0.data 11909500 # number of overall MSHR miss cycles 2706system.l2c.overall_mshr_miss_latency::cpu1.inst 5496500 # number of overall MSHR miss cycles |
| 2707system.l2c.overall_mshr_miss_latency::cpu1.data 1399500 # number of overall MSHR miss cycles | 2707system.l2c.overall_mshr_miss_latency::cpu1.data 1399500 # number of overall MSHR miss cycles |
| 2708system.l2c.overall_mshr_miss_latency::cpu2.inst 217000 # number of overall MSHR miss cycles 2709system.l2c.overall_mshr_miss_latency::cpu2.data 909000 # number of overall MSHR miss cycles 2710system.l2c.overall_mshr_miss_latency::cpu3.inst 364000 # number of overall MSHR miss cycles 2711system.l2c.overall_mshr_miss_latency::cpu3.data 1275000 # number of overall MSHR miss cycles 2712system.l2c.overall_mshr_miss_latency::total 45153500 # number of overall MSHR miss cycles | 2708system.l2c.overall_mshr_miss_latency::cpu2.inst 363500 # number of overall MSHR miss cycles 2709system.l2c.overall_mshr_miss_latency::cpu2.data 1452000 # number of overall MSHR miss cycles 2710system.l2c.overall_mshr_miss_latency::cpu3.inst 146000 # number of overall MSHR miss cycles 2711system.l2c.overall_mshr_miss_latency::cpu3.data 1086000 # number of overall MSHR miss cycles 2712system.l2c.overall_mshr_miss_latency::total 45738500 # number of overall MSHR miss cycles |
| 2713system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses 2714system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2715system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2716system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses | 2713system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses 2714system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2715system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2716system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses |
| 2717system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses | 2717system.l2c.UpgradeReq_mshr_miss_rate::total 0.966667 # mshr miss rate for UpgradeReq accesses |
| 2718system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2719system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2720system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2721system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2722system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2723system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses | 2718system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2719system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2720system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2721system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2722system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2723system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses |
| 2724system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses 2725system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses 2726system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadCleanReq accesses | 2724system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses 2725system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses 2726system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses |
| 2727system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses 2728system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses 2729system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses 2730system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2731system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2732system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses 2733system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses 2734system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses | 2727system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses 2728system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses 2729system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses 2730system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2731system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2732system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses 2733system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses 2734system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses |
| 2735system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses | 2735system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses |
| 2736system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses | 2736system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses |
| 2737system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses | 2737system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses |
| 2738system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses | 2738system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses |
| 2739system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses | 2739system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses |
| 2740system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2741system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses 2742system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses 2743system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses | 2740system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2741system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses 2742system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses 2743system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses |
| 2744system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses | 2744system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses |
| 2745system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses | 2745system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses |
| 2746system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses | 2746system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses |
| 2747system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses | 2747system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses |
| 2748system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses | 2748system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses |
| 2749system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2750system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses | 2749system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2750system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses |
| 2751system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency 2752system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency 2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency 2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency 2756system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency | 2751system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency 2752system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency 2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency 2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency 2756system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency |
| 2757system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency | 2757system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency |
| 2758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency 2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency 2760system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency 2761system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency 2762system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency 2763system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency 2764system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency 2765system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency | 2758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency 2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency 2760system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency 2761system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency 2762system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency 2763system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency 2764system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency 2765system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency |
| 2766system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency 2767system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency | 2766system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency 2767system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency |
| 2768system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency 2769system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency | 2768system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency 2769system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency |
| 2770system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency | 2770system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency |
| 2771system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency 2772system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency 2773system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency | 2771system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency 2772system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency 2773system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency |
| 2774system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency | 2774system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency |
| 2775system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency 2776system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency 2777system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency 2778system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency 2779system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency 2780system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency 2781system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency 2782system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency | 2775system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency 2776system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency 2777system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency 2778system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency 2779system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency 2780system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency 2781system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency 2782system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency |
| 2783system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency | 2783system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency |
| 2784system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency 2785system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency 2786system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency 2787system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency 2788system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency | 2784system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency 2785system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency 2786system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency 2787system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency 2788system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency |
| 2789system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2790system.membus.trans_dist::ReadResp 534 # Transaction distribution | 2789system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2790system.membus.trans_dist::ReadResp 534 # Transaction distribution |
| 2791system.membus.trans_dist::UpgradeReq 292 # Transaction distribution 2792system.membus.trans_dist::UpgradeResp 89 # Transaction distribution 2793system.membus.trans_dist::ReadExReq 161 # Transaction distribution | 2791system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 2792system.membus.trans_dist::UpgradeResp 87 # Transaction distribution 2793system.membus.trans_dist::ReadExReq 162 # Transaction distribution |
| 2794system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2795system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution | 2794system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2795system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution |
| 2796system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes) 2797system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes) | 2796system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) 2797system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) |
| 2798system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) 2799system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) | 2798system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) 2799system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) |
| 2800system.membus.snoops 233 # Total snoops (count) 2801system.membus.snoop_fanout::samples 988 # Request fanout histogram | 2800system.membus.snoops 231 # Total snoops (count) 2801system.membus.snoop_fanout::samples 984 # Request fanout histogram |
| 2802system.membus.snoop_fanout::mean 0 # Request fanout histogram 2803system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2804system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2802system.membus.snoop_fanout::mean 0 # Request fanout histogram 2803system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2804system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2805system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram | 2805system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram |
| 2806system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2807system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2808system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2809system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 2806system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2807system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2808system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2809system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 2810system.membus.snoop_fanout::total 988 # Request fanout histogram 2811system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks) | 2810system.membus.snoop_fanout::total 984 # Request fanout histogram 2811system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks) |
| 2812system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) | 2812system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 2813system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) 2814system.membus.respLayer1.utilization 3.5 # Layer utilization (%) 2815system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution | 2813system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks) 2814system.membus.respLayer1.utilization 3.4 # Layer utilization (%) 2815system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter. 2816system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2817system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2818system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2819system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2820system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2821system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution |
| 2816system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution | 2822system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution |
| 2817system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution 2818system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution 2819system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution 2820system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution 2821system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution | 2823system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution 2824system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 2825system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 2826system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution 2827system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution |
| 2822system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution | 2828system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution |
| 2823system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution | 2829system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution |
| 2824system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) | 2830system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) |
| 2825system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) | 2831system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) |
| 2826system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) | 2832system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) |
| 2827system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) 2828system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 2829system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) 2830system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) 2831system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes) 2832system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes) | 2833system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes) 2834system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes) 2835system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) 2836system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes) 2837system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) 2838system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes) |
| 2833system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) 2834system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 2835system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) 2836system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2837system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) 2838system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2839system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) 2840system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2841system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) | 2839system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) 2840system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 2841system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) 2842system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2843system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) 2844system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2845system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) 2846system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2847system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) |
| 2842system.toL2Bus.snoops 1026 # Total snoops (count) 2843system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram 2844system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 2845system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 2848system.toL2Bus.snoops 1019 # Total snoops (count) 2849system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram 2850system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram 2851system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram |
| 2846system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2852system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2847system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2848system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2849system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2850system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2851system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2852system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 2853system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 2854system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram | 2853system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram 2854system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram 2855system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram 2856system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram 2857system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2858system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 2859system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 2860system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram |
| 2855system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2856system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2861system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2862system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2857system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 2858system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 2859system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram 2860system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks) | 2863system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2864system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2865system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram 2866system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks) |
| 2861system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 2862system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) | 2867system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 2868system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) |
| 2863system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 2864system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks) | 2869system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 2870system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks) |
| 2865system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 2866system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) 2867system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) | 2871system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 2872system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) 2873system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) |
| 2868system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks) | 2874system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks) |
| 2869system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) | 2875system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) |
| 2870system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks) | 2876system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks) |
| 2871system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) | 2877system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) |
| 2872system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks) | 2878system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks) |
| 2873system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) | 2879system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) |
| 2874system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) | 2880system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) |
| 2875system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) | 2881system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) |
| 2876system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks) | 2882system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks) |
| 2877system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) 2878 2879---------- End Simulation Statistics ---------- | 2883system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) 2884 2885---------- End Simulation Statistics ---------- |