Cross Reference: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000106 # Number of seconds simulated
4sim_ticks 105542000 # Number of ticks simulated
5final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000108 # Number of seconds simulated
4sim_ticks 107944000 # Number of ticks simulated
5final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 163449 # Simulator instruction rate (inst/s)
8host_op_rate 163449 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17392605 # Simulator tick rate (ticks/s)
10host_mem_usage 309188 # Number of bytes of host memory used
11host_seconds 6.07 # Real time elapsed on the host
12sim_insts 991839 # Number of instructions simulated
13sim_ops 991839 # Number of ops (including micro ops) simulated

7host_inst_rate 162812 # Simulator instruction rate (inst/s)
8host_op_rate 162812 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17679745 # Simulator tick rate (ticks/s)
10host_mem_usage 308116 # Number of bytes of host memory used
11host_seconds 6.11 # Real time elapsed on the host
12sim_insts 994048 # Number of instructions simulated
13sim_ops 994048 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory

16system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory

23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory

24system.physmem.bytes_read::total 42496 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory

24system.physmem.bytes_read::total 42816 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory
30system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory

37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory

38system.physmem.num_reads::total 664 # Number of read requests responded to by this memory
39system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.readReqs 665 # Number of read requests accepted

38system.physmem.num_reads::total 669 # Number of read requests responded to by this memory
39system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s)
49system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s)
50system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s)
51system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s)
56system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s)
57system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.readReqs 670 # Number of read requests accepted

63system.physmem.writeReqs 0 # Number of write requests accepted

64system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue

64system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue

65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue

66system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM

66system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM

67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM

69system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side

69system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side

70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one

73system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write
74system.physmem.perBankRdBursts::0 114 # Per bank write bursts

73system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write
74system.physmem.perBankRdBursts::0 115 # Per bank write bursts

75system.physmem.perBankRdBursts::1 42 # Per bank write bursts
76system.physmem.perBankRdBursts::2 27 # Per bank write bursts
77system.physmem.perBankRdBursts::3 60 # Per bank write bursts

78system.physmem.perBankRdBursts::4 65 # Per bank write bursts

78system.physmem.perBankRdBursts::4 66 # Per bank write bursts

79system.physmem.perBankRdBursts::5 28 # Per bank write bursts
80system.physmem.perBankRdBursts::6 18 # Per bank write bursts
81system.physmem.perBankRdBursts::7 24 # Per bank write bursts
82system.physmem.perBankRdBursts::8 7 # Per bank write bursts

83system.physmem.perBankRdBursts::9 28 # Per bank write bursts
84system.physmem.perBankRdBursts::10 22 # Per bank write bursts
85system.physmem.perBankRdBursts::11 13 # Per bank write bursts

83system.physmem.perBankRdBursts::9 29 # Per bank write bursts
84system.physmem.perBankRdBursts::10 23 # Per bank write bursts
85system.physmem.perBankRdBursts::11 14 # Per bank write bursts

86system.physmem.perBankRdBursts::12 65 # Per bank write bursts
87system.physmem.perBankRdBursts::13 38 # Per bank write bursts
88system.physmem.perBankRdBursts::14 17 # Per bank write bursts
89system.physmem.perBankRdBursts::15 97 # Per bank write bursts
90system.physmem.perBankWrBursts::0 0 # Per bank write bursts
91system.physmem.perBankWrBursts::1 0 # Per bank write bursts
92system.physmem.perBankWrBursts::2 0 # Per bank write bursts
93system.physmem.perBankWrBursts::3 0 # Per bank write bursts

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100system.physmem.perBankWrBursts::10 0 # Per bank write bursts
101system.physmem.perBankWrBursts::11 0 # Per bank write bursts
102system.physmem.perBankWrBursts::12 0 # Per bank write bursts
103system.physmem.perBankWrBursts::13 0 # Per bank write bursts
104system.physmem.perBankWrBursts::14 0 # Per bank write bursts
105system.physmem.perBankWrBursts::15 0 # Per bank write bursts
106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

108system.physmem.totGap 105514000 # Total gap between requests

108system.physmem.totGap 107916000 # Total gap between requests

109system.physmem.readPktSize::0 0 # Read request sizes (log2)
110system.physmem.readPktSize::1 0 # Read request sizes (log2)
111system.physmem.readPktSize::2 0 # Read request sizes (log2)
112system.physmem.readPktSize::3 0 # Read request sizes (log2)
113system.physmem.readPktSize::4 0 # Read request sizes (log2)
114system.physmem.readPktSize::5 0 # Read request sizes (log2)

115system.physmem.readPktSize::6 665 # Read request sizes (log2)

115system.physmem.readPktSize::6 670 # Read request sizes (log2)

116system.physmem.writePktSize::0 0 # Write request sizes (log2)
117system.physmem.writePktSize::1 0 # Write request sizes (log2)
118system.physmem.writePktSize::2 0 # Write request sizes (log2)
119system.physmem.writePktSize::3 0 # Write request sizes (log2)
120system.physmem.writePktSize::4 0 # Write request sizes (log2)
121system.physmem.writePktSize::5 0 # Write request sizes (log2)
122system.physmem.writePktSize::6 0 # Write request sizes (log2)

123system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see

123system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see

127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 76 unchanged lines hidden (view full) ---

211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see

219system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation
220system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation
221system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation
233system.physmem.totQLat 6421750 # Total ticks spent queuing
234system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM
235system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers
236system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst

219system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
220system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation
221system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation
222system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation
223system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
233system.physmem.totQLat 6539750 # Total ticks spent queuing
234system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM
235system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers
236system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst

237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

238system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst
239system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s

238system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst
239system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s

240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

241system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s

241system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s

242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s

244system.physmem.busUtil 3.15 # Data bus utilization in percentage
245system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads

244system.physmem.busUtil 3.10 # Data bus utilization in percentage
245system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads

246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes

247system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing

247system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing

248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

249system.physmem.readRowHits 512 # Number of row buffer hits during reads

249system.physmem.readRowHits 511 # Number of row buffer hits during reads

250system.physmem.writeRowHits 0 # Number of row buffer hits during writes

251system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads

251system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads

252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

253system.physmem.avgGap 158667.67 # Average gap between requests
254system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined
255system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ)
256system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ)
257system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ)

253system.physmem.avgGap 161068.66 # Average gap between requests
254system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined
255system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
256system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
257system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ)

258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
259system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)

260system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ)
261system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ)
262system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ)
263system.physmem_0.averagePower 738.913691 # Core power per rank (mW)
264system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states

260system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ)
261system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ)
262system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ)
263system.physmem_0.averagePower 750.559832 # Core power per rank (mW)
264system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states

265system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

267system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states

267system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states

268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

269system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
270system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
271system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ)

269system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
270system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
271system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ)

272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
273system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)

274system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ)
275system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ)
276system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ)
277system.physmem_1.averagePower 723.948851 # Core power per rank (mW)
278system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states

274system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ)
275system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ)
276system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ)
277system.physmem_1.averagePower 728.745214 # Core power per rank (mW)
278system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states

279system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

281system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states

281system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states

282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

283system.cpu0.branchPred.lookups 81296 # Number of BP lookups
284system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted
285system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect
286system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups
287system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits

283system.cpu0.branchPred.lookups 81450 # Number of BP lookups
284system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted
285system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect
286system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups
287system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits

288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

289system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage
290system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target.

289system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage
290system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target.

291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
292system.cpu_clk_domain.clock 500 # Clock period in ticks
293system.cpu0.workload.num_syscalls 89 # Number of system calls

294system.cpu0.numCycles 211085 # number of cpu cycles simulated

294system.cpu0.numCycles 215889 # number of cpu cycles simulated

295system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
296system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

297system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss
298system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed
299system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered
300system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken
301system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked
302system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing

297system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss
298system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed
299system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered
300system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken
301system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked
302system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing

303system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

304system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps
305system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched
306system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed
307system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total)
308system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total)
309system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total)

304system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps
305system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched
306system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed
307system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total)
308system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total)
309system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total)

310system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

311system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total)
312system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total)
313system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total)
314system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total)
315system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total)
316system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total)
317system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total)
318system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total)
319system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total)

311system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total)
312system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total)
313system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total)
314system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total)
315system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total)
316system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total)
317system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total)
318system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total)
319system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total)

320system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
321system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
322system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

323system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total)
324system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle
325system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle

323system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total)
324system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle
325system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle

326system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle

327system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked
328system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running
329system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking
330system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing
331system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode
332system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing
333system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle
334system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking
335system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst
336system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running
337system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking
338system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename
339system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
340system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full
341system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full
342system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed
343system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made
344system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups
345system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed
346system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing

327system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked
328system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running
329system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking
330system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing
331system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode
332system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing
333system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle
334system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking
335system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst
336system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running
337system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking
338system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename
339system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
340system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
341system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full
342system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed
343system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made
344system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups
345system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed
346system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing

347system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed

348system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed
349system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer
350system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit.
351system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit.
352system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads.
353system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores.
354system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec)
355system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ
356system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued
357system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
358system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling
359system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph
360system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed
361system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle
362system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle
363system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle

348system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed
349system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer
350system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit.
351system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit.
352system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads.
353system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores.
354system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec)
355system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ
356system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued
357system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued
358system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling
359system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph
360system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed
361system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle
362system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle
363system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle

364system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

365system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle
366system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle
367system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle
368system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle
369system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle
370system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle
371system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle
372system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle
373system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle

365system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle
366system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle
367system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle
368system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle
369system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle
370system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle
371system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle
372system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle
373system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle

374system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
375system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
376system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

377system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle

377system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle

378system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

379system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available
380system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available
381system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available
382system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available
383system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available
384system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available
385system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available
386system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available
387system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available
388system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available
389system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available
390system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available
391system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available
392system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available
393system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available
394system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available
395system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available
396system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available
397system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available
398system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available
399system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available
400system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available
401system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available
402system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available
403system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available
404system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available
405system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available
406system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available
407system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available
408system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available
409system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available

379system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available
380system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available
381system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
382system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
383system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
384system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
385system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
386system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
387system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
388system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
389system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
390system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
391system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
392system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
393system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
394system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
395system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
396system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
397system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
398system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
399system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
400system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
401system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
402system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
403system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
404system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
405system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
406system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
407system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
408system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available
409system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available

410system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
411system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
412system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

413system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued
414system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued
415system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued
416system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued
417system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued
418system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued
419system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued
420system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued
421system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued
422system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued
423system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued
424system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued
425system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued
426system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued
427system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued
428system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued
429system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued
430system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued
431system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued
432system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued
433system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued
434system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued
435system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued
436system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued
437system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued
438system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued
439system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued
440system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued
441system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued
442system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued
443system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued

413system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued
414system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued
415system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued
416system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued
417system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued
418system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued
419system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued
420system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued
421system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued
422system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued
423system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued
424system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued
425system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued
426system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued
427system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued
428system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued
429system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued
430system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued
431system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued
432system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued
433system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued
434system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued
435system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued
436system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued
437system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued
438system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued
439system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued
440system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued
441system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued
442system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued
443system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued

444system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
445system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

446system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued
447system.cpu0.iq.rate 1.826459 # Inst issue rate
448system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
449system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst)
450system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads
451system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes
452system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses

446system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued
447system.cpu0.iq.rate 1.792574 # Inst issue rate
448system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested
449system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst)
450system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads
451system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes
452system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses

453system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
454system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
455system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

456system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses

456system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses

457system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses

458system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores

458system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores

459system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

460system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed

460system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed

461system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed

462system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
463system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed

462system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
463system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed

464system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
465system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
466system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled

467system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked

467system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked

468system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

469system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
470system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking
471system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
472system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ
473system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
474system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions
475system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions
476system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions
477system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
478system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
479system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
480system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly
481system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly

469system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing
470system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking
471system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
472system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ
473system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch
474system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions
475system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions
476system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions
477system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
478system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
479system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
480system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly
481system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly

482system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute

483system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions
484system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed
485system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute

483system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions
484system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed
485system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute

486system.cpu0.iew.exec_swp 0 # number of swp insts executed

487system.cpu0.iew.exec_nop 72677 # number of nop insts executed
488system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed
489system.cpu0.iew.exec_branches 76264 # Number of branches executed
490system.cpu0.iew.exec_stores 74195 # Number of stores executed
491system.cpu0.iew.exec_rate 1.821660 # Inst execution rate
492system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit
493system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back
494system.cpu0.iew.wb_producers 227520 # num instructions producing a value
495system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value

487system.cpu0.iew.exec_nop 72936 # number of nop insts executed
488system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed
489system.cpu0.iew.exec_branches 76534 # Number of branches executed
490system.cpu0.iew.exec_stores 74459 # Number of stores executed
491system.cpu0.iew.exec_rate 1.787706 # Inst execution rate
492system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit
493system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back
494system.cpu0.iew.wb_producers 228400 # num instructions producing a value
495system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value

496system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

497system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle
498system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back

497system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle
498system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back

499system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

500system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit

500system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit

501system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards

502system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted
503system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle
504system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle
505system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle

502system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted
503system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle
504system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle
505system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle

506system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

507system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle
508system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle
509system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle
510system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle
511system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle
512system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle
513system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle
514system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle
515system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle

507system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle
508system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle
509system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle
510system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle
511system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle
512system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle
513system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle
514system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
515system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle

516system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
517system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
518system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

519system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle
520system.cpu0.commit.committedInsts 448740 # Number of instructions committed
521system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed

519system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle
520system.cpu0.commit.committedInsts 450384 # Number of instructions committed
521system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed

522system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

523system.cpu0.commit.refs 219085 # Number of memory references committed
524system.cpu0.commit.loads 145719 # Number of loads committed

523system.cpu0.commit.refs 219907 # Number of memory references committed
524system.cpu0.commit.loads 146267 # Number of loads committed

525system.cpu0.commit.membars 84 # Number of memory barriers committed

526system.cpu0.commit.branches 75253 # Number of branches committed

526system.cpu0.commit.branches 75527 # Number of branches committed

527system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.

528system.cpu0.commit.int_insts 302590 # Number of committed integer instructions.

528system.cpu0.commit.int_insts 303686 # Number of committed integer instructions.

529system.cpu0.commit.function_calls 223 # Number of function calls committed.

530system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction
531system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction
532system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
533system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
534system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
535system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
536system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
537system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
538system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
539system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
540system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
541system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
542system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
543system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
544system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
545system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
546system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
547system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
548system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
549system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
550system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
551system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
552system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
553system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction
554system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction
555system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction
556system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction
557system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
558system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
559system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
560system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction
561system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction

530system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction
531system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction
532system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
533system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
534system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
535system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
536system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
537system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
538system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
539system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
540system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
541system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
542system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
543system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
544system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
545system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
546system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
547system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
548system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
549system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
550system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
551system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
552system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
553system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
554system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
555system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
556system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
557system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
558system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
559system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
560system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction
561system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction

562system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
563system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

564system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction
565system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached

564system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction
565system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached

566system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits

567system.cpu0.rob.rob_reads 645314 # The number of ROB reads
568system.cpu0.rob.rob_writes 927635 # The number of ROB writes
569system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
570system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling
571system.cpu0.committedInsts 376671 # Number of Instructions Simulated
572system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated
573system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction
574system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads
575system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle
576system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads
577system.cpu0.int_regfile_reads 687652 # number of integer regfile reads
578system.cpu0.int_regfile_writes 310240 # number of integer regfile writes

567system.cpu0.rob.rob_reads 649458 # The number of ROB reads
568system.cpu0.rob.rob_writes 931043 # The number of ROB writes
569system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself
570system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling
571system.cpu0.committedInsts 378041 # Number of Instructions Simulated
572system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated
573system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction
574system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads
575system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle
576system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads
577system.cpu0.int_regfile_reads 690199 # number of integer regfile reads
578system.cpu0.int_regfile_writes 311415 # number of integer regfile writes

579system.cpu0.fp_regfile_reads 192 # number of floating regfile reads

580system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads

580system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads

581system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
582system.cpu0.dcache.tags.replacements 2 # number of replacements

583system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use
584system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks.
585system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
586system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks.

583system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use
584system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks.
585system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
586system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks.

587system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

588system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor
589system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy
590system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy
591system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
592system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
593system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
594system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
595system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id
596system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses
597system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses
598system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits
599system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits
600system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits
601system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits
602system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits
603system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits
604system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits
605system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits
606system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits
607system.cpu0.dcache.overall_hits::total 147973 # number of overall hits
608system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses
609system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses
610system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses
611system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses
612system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses
613system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses
614system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses
615system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses
616system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses
617system.cpu0.dcache.overall_misses::total 1026 # number of overall misses
618system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles
619system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles
620system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles
621system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles
622system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles
623system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles
624system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles
625system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles
626system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles
627system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles
628system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses)
629system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses)
630system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses)
631system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses)

588system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor
589system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy
590system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy
591system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
592system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
593system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
594system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
595system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
596system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses
597system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses
598system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits
599system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits
600system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits
601system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits
602system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
603system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
604system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits
605system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits
606system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits
607system.cpu0.dcache.overall_hits::total 148458 # number of overall hits
608system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses
609system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses
610system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses
611system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses
612system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
613system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
614system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses
615system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses
616system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses
617system.cpu0.dcache.overall_misses::total 1053 # number of overall misses
618system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles
619system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles
620system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles
621system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles
622system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles
623system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles
624system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles
625system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles
626system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles
627system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles
628system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses)
629system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses)
630system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses)
631system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses)

632system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
633system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)

634system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses
635system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses
636system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses
637system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses
638system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses
639system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses
640system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses
641system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses
642system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses
643system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses
644system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses
645system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses
646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses
647system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses
648system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency
649system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency
650system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency
651system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency
652system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency
653system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency
654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency
655system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency
656system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency
657system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency
658system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked

634system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses
635system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses
636system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses
637system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses
638system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses
639system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses
640system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses
641system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses
642system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
643system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
644system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses
645system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses
646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses
647system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses
648system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency
649system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency
650system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency
651system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency
652system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency
653system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency
654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
655system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency
656system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency
657system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency
658system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked

659system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

660system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked

660system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked

661system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked

662system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked

662system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked

663system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
664system.cpu0.dcache.fast_writes 0 # number of fast writes performed
665system.cpu0.dcache.cache_copies 0 # number of cache copies performed
666system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
667system.cpu0.dcache.writebacks::total 1 # number of writebacks

668system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits
669system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
670system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits
671system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits
672system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits
673system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits
674system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits
675system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits
676system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
677system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
678system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses
679system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses
680system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses
681system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses
682system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
683system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
684system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
685system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
686system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles
687system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles
688system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles
689system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles
690system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles
691system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles
692system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles
693system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles
694system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles
695system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles
696system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses
697system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses
698system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses
699system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses
700system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses
701system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses
702system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses
703system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses
704system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses
705system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses
706system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency
707system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency
708system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency
709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency
710system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency
711system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency
712system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency
713system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency
714system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency
715system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency

668system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits
669system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits
670system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits
671system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits
672system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits
673system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits
674system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits
675system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits
676system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses
677system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses
678system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
679system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
680system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
681system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
682system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
683system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
684system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
685system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
686system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles
687system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles
688system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles
689system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles
690system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles
691system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles
692system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles
693system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles
694system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles
695system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles
696system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses
697system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses
698system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses
699system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses
700system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
701system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
702system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses
703system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses
704system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses
705system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses
706system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency
707system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency
708system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency
709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency
710system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency
711system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency
712system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
713system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency
714system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency
715system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency

716system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

717system.cpu0.icache.tags.replacements 319 # number of replacements
718system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use
719system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks.
720system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks.
721system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks.

717system.cpu0.icache.tags.replacements 323 # number of replacements
718system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use
719system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks.
720system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks.
721system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks.

722system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

723system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor
724system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy
725system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy
726system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id

723system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor
724system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy
725system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy
726system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id

727system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id

728system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
729system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
730system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id
731system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses
732system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses
733system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits
734system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits
735system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits
736system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits
737system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits
738system.cpu0.icache.overall_hits::total 6347 # number of overall hits
739system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses
740system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses
741system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses
742system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses
743system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses
744system.cpu0.icache.overall_misses::total 792 # number of overall misses
745system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles
746system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles
747system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles
748system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles
749system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles
750system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles
751system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses)
752system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses)
753system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses
754system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses
755system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses
756system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses
757system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses
758system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses
759system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses
760system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses
761system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses
762system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses
763system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency
764system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency
765system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency
766system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency
767system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency
768system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency

728system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
729system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
730system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id
731system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses
732system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses
733system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits
734system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits
735system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits
736system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits
737system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits
738system.cpu0.icache.overall_hits::total 6428 # number of overall hits
739system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses
740system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses
741system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses
742system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses
743system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses
744system.cpu0.icache.overall_misses::total 797 # number of overall misses
745system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles
746system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles
747system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles
748system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles
749system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles
750system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles
751system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses)
752system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses)
753system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses
754system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses
755system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses
756system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses
757system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses
758system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses
759system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses
760system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses
761system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses
762system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses
763system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency
764system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency
765system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
766system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency
767system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency
768system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency

769system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
770system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
772system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
773system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
774system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775system.cpu0.icache.fast_writes 0 # number of fast writes performed
776system.cpu0.icache.cache_copies 0 # number of cache copies performed

777system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits
778system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits
779system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits
780system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits
781system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits
782system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits
783system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses
784system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses
785system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses
786system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses
787system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses
788system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses
789system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles
790system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles
791system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles
792system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles
793system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles
794system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles
795system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses
796system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses
797system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses
798system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses
799system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses
800system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses
801system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency
802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency
803system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency
804system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency
805system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency
806system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency

777system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits
778system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
779system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits
780system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
781system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits
782system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
783system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses
784system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses
785system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses
786system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses
787system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses
788system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses
789system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles
790system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles
791system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles
792system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles
793system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles
794system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles
795system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses
796system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses
797system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses
798system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses
799system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses
800system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses
801system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency
802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency
803system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
804system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency
805system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency
806system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency

807system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

808system.cpu1.branchPred.lookups 48230 # Number of BP lookups
809system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted
810system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect
811system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups
812system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits

808system.cpu1.branchPred.lookups 52261 # Number of BP lookups
809system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted
810system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect
811system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups
812system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits

813system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

814system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage
815system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target.

814system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage
815system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.

816system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

817system.cpu1.numCycles 160735 # number of cpu cycles simulated

817system.cpu1.numCycles 162232 # number of cpu cycles simulated

818system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
819system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

820system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss
821system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed
822system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered
823system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken
824system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked
825system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing

820system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss
821system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed
822system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered
823system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken
824system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked
825system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing

826system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
827system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

828system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps
829system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched
830system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed
831system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total)
832system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total)
833system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total)

828system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps
829system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched
830system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
831system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total)
832system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total)
833system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total)

834system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

835system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total)
836system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total)
837system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total)
838system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total)
839system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total)
840system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total)
841system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total)
842system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total)
843system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total)

835system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total)
836system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total)
837system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total)
838system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total)
839system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total)
840system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total)
841system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total)
842system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total)
843system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total)

844system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
845system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
846system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

847system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total)
848system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle
849system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle
850system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle
851system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked
852system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running
853system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking
854system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing
855system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode
856system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing
857system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle
858system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking
859system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst
860system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running
861system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking
862system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename
863system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full
864system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full
865system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers
866system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed
867system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made
868system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups
869system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed
870system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing
871system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
872system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
873system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer
874system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit.
875system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit.
876system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads.
877system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores.
878system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec)
879system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ
880system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued
881system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
882system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling
883system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph
884system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed
885system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle
886system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle
887system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle

847system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total)
848system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle
849system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle
850system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle
851system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked
852system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running
853system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking
854system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing
855system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode
856system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing
857system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle
858system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking
859system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst
860system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running
861system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking
862system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename
863system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full
864system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full
865system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
866system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed
867system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made
868system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups
869system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed
870system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing
871system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed
872system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
873system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer
874system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit.
875system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit.
876system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads.
877system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores.
878system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec)
879system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ
880system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued
881system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
882system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling
883system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph
884system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed
885system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle
886system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle
887system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle

888system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

889system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle
890system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle
891system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle
892system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle
893system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle
894system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle
895system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle
896system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle
897system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle

889system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle
890system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle
891system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle
892system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle
893system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle
894system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle
895system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle
896system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle
897system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle

898system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
899system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
900system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

901system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle

901system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle

902system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

903system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available
904system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available
905system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available
906system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available
907system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available
908system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available
909system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available
910system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available
911system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available
912system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available
913system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available
914system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available
915system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available
916system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available
917system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available
918system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available
919system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available
920system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available
921system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available
922system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available
923system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available
924system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available
925system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available
926system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available
927system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available
928system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available
929system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available
930system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available
931system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available
932system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available
933system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available

903system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available
904system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available
905system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available
906system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available
907system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available
908system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available
909system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available
910system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available
911system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
912system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available
913system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available
914system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available
915system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available
916system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available
917system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available
918system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available
919system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available
920system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available
921system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available
922system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available
923system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available
924system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available
925system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available
926system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available
927system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available
928system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available
929system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available
930system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available
931system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available
932system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available
933system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available

934system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
935system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
936system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

937system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued
938system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued
939system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued
940system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued
941system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued
942system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued
943system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued
944system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued
945system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued
946system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued
947system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued
948system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued
949system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued
950system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued
951system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued
952system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued
953system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued
954system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued
955system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued
956system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued
957system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued
958system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued
959system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued
960system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued
961system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued
962system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued
963system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued
964system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued
965system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued
966system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued
967system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued

937system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued
938system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued
939system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued
940system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued
941system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued
942system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued
943system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued
944system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued
945system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued
946system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued
947system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued
948system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued
949system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued
950system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued
951system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued
952system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued
953system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued
954system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued
955system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued
956system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued
957system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued
958system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued
959system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued
960system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued
961system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued
962system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued
963system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued
964system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued
965system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued
966system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued
967system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued

968system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
969system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

970system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued
971system.cpu1.iq.rate 1.263247 # Inst issue rate
972system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested
973system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst)
974system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads
975system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes
976system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses

970system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued
971system.cpu1.iq.rate 1.386958 # Inst issue rate
972system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested
973system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst)
974system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads
975system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes
976system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses

977system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
978system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
979system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

980system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses

980system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses

981system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses

982system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores

982system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores

983system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

984system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed

984system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed

985system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed

986system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
987system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed

986system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
987system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed

988system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
989system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
990system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
991system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
992system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

993system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing
994system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking
995system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
996system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ
997system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch
998system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions
999system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions
1000system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions
1001system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall

993system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing
994system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking
995system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
996system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ
997system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch
998system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions
999system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions
1000system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions
1001system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall

1002system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1003system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations
1004system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
1005system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly
1006system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute
1007system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions
1008system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed
1009system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute

1003system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations
1004system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
1005system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly
1006system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute
1007system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions
1008system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed
1009system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute

1010system.cpu1.iew.exec_swp 0 # number of swp insts executed

1011system.cpu1.iew.exec_nop 32947 # number of nop insts executed
1012system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed
1013system.cpu1.iew.exec_branches 42219 # Number of branches executed
1014system.cpu1.iew.exec_stores 29534 # Number of stores executed
1015system.cpu1.iew.exec_rate 1.256422 # Inst execution rate
1016system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit
1017system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back
1018system.cpu1.iew.wb_producers 112178 # num instructions producing a value
1019system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value

1011system.cpu1.iew.exec_nop 36391 # number of nop insts executed
1012system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed
1013system.cpu1.iew.exec_branches 45914 # Number of branches executed
1014system.cpu1.iew.exec_stores 34905 # Number of stores executed
1015system.cpu1.iew.exec_rate 1.380418 # Inst execution rate
1016system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit
1017system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back
1018system.cpu1.iew.wb_producers 126652 # num instructions producing a value
1019system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value

1020system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

1021system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle
1022system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back

1021system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle
1022system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back

1023system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

1024system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit
1025system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards
1026system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted
1027system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle
1028system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle
1029system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle

1024system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit
1025system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards
1026system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted
1027system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle
1028system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle
1029system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle

1030system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1031system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle
1032system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle
1033system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle
1034system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle
1035system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle
1036system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle
1037system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle
1038system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle
1039system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle

1031system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle
1032system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle
1033system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle
1034system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle
1035system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle
1036system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle
1037system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle
1038system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle
1039system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle

1040system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1041system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1042system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1043system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle
1044system.cpu1.commit.committedInsts 226660 # Number of instructions committed
1045system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed

1043system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle
1044system.cpu1.commit.committedInsts 251602 # Number of instructions committed
1045system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed

1046system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

1047system.cpu1.commit.refs 92171 # Number of memory references committed
1048system.cpu1.commit.loads 63450 # Number of loads committed
1049system.cpu1.commit.membars 6533 # Number of memory barriers committed
1050system.cpu1.commit.branches 41215 # Number of branches committed

1047system.cpu1.commit.refs 106422 # Number of memory references committed
1048system.cpu1.commit.loads 72360 # Number of loads committed
1049system.cpu1.commit.membars 4751 # Number of memory barriers committed
1050system.cpu1.commit.branches 44778 # Number of branches committed

1051system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.

1052system.cpu1.commit.int_insts 155506 # Number of committed integer instructions.

1052system.cpu1.commit.int_insts 173320 # Number of committed integer instructions.

1053system.cpu1.commit.function_calls 322 # Number of function calls committed.

1054system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction
1055system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction
1056system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction
1057system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction
1058system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction
1059system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction
1060system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction
1061system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction
1062system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction
1063system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction
1064system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction
1065system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction
1066system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction
1067system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction
1068system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction
1069system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction
1070system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction
1071system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction
1072system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction
1073system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction
1074system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction
1075system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction
1076system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction
1077system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction
1078system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction
1079system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction
1080system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction
1081system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction
1082system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction
1083system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction
1084system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction
1085system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction

1054system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction
1055system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction
1056system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction
1057system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction
1058system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction
1059system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction
1060system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction
1061system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction
1062system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction
1063system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction
1064system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction
1065system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction
1066system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction
1067system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction
1068system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction
1069system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction
1070system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction
1071system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction
1072system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction
1073system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction
1074system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction
1075system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction
1076system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction
1077system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction
1078system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction
1079system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction
1080system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction
1081system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction
1082system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction
1083system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction
1084system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction
1085system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction

1086system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1087system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1088system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction
1089system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached

1088system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction
1089system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached

1090system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits

1091system.cpu1.rob.rob_reads 395483 # The number of ROB reads
1092system.cpu1.rob.rob_writes 484550 # The number of ROB writes
1093system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
1094system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling
1095system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1096system.cpu1.committedInsts 188125 # Number of Instructions Simulated
1097system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated
1098system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction
1099system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads
1100system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle
1101system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads
1102system.cpu1.int_regfile_reads 343348 # number of integer regfile reads
1103system.cpu1.int_regfile_writes 161358 # number of integer regfile writes

1091system.cpu1.rob.rob_reads 417798 # The number of ROB reads
1092system.cpu1.rob.rob_writes 534614 # The number of ROB writes
1093system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
1094system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
1095system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1096system.cpu1.committedInsts 211284 # Number of Instructions Simulated
1097system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated
1098system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction
1099system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads
1100system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle
1101system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads
1102system.cpu1.int_regfile_reads 386957 # number of integer regfile reads
1103system.cpu1.int_regfile_writes 181537 # number of integer regfile writes

1104system.cpu1.fp_regfile_writes 64 # number of floating regfile writes

1105system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads

1105system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads

1106system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
1107system.cpu1.dcache.tags.replacements 0 # number of replacements

1108system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use
1109system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks.

1108system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use
1109system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks.

1110system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.

1111system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks.

1111system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks.

1112system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1113system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor
1114system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy
1115system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy

1113system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor
1114system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy
1115system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy

1116system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
1117system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
1118system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id

1119system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses
1120system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses
1121system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits
1122system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits
1123system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits
1124system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits
1125system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
1126system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1127system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits
1128system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits
1129system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits
1130system.cpu1.dcache.overall_hits::total 68186 # number of overall hits
1131system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses
1132system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses
1133system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses
1134system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses

1119system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses
1120system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses
1121system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits
1122system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits
1123system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits
1124system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits
1125system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
1126system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1127system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits
1128system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits
1129system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits
1130system.cpu1.dcache.overall_hits::total 77097 # number of overall hits
1131system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses
1132system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses
1133system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses
1134system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses

1135system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
1136system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses

1137system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses
1138system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses
1139system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses
1140system.cpu1.dcache.overall_misses::total 559 # number of overall misses
1141system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles
1142system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles
1143system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles
1144system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles
1145system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles
1146system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles
1147system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles
1148system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles
1149system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles
1150system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles
1151system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses)
1152system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses)
1153system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses)
1154system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses)
1155system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
1156system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1157system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses
1158system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses
1159system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses
1160system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses
1161system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses
1162system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses
1163system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses
1164system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses
1165system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
1166system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses
1168system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses
1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses
1170system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses
1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency
1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency
1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency
1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency
1175system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency
1176system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency
1177system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency
1178system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency
1179system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency
1180system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency

1137system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses
1138system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses
1139system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses
1140system.cpu1.dcache.overall_misses::total 619 # number of overall misses
1141system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles
1142system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles
1143system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles
1144system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles
1145system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles
1146system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles
1147system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles
1148system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles
1149system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles
1150system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles
1151system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses)
1152system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses)
1153system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses)
1154system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses)
1155system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
1156system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
1157system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses
1158system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses
1159system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses
1160system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses
1161system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses
1162system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses
1163system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses
1164system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses
1165system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses
1166system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses
1168system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses
1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses
1170system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses
1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency
1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency
1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency
1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency
1175system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency
1176system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency
1177system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
1178system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency
1179system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency
1180system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency

1181system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1182system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1183system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1184system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1185system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1186system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1187system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1188system.cpu1.dcache.cache_copies 0 # number of cache copies performed

1189system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits
1190system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits
1191system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
1192system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
1193system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits
1194system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits
1195system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits
1196system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits
1197system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
1198system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
1199system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses
1200system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses

1189system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits
1190system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
1191system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits
1192system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits
1193system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits
1194system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits
1195system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits
1196system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits
1197system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses
1198system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses
1199system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
1200system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses

1201system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
1202system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses

1203system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
1204system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
1205system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
1206system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
1207system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles
1208system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles
1209system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles
1210system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles
1211system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles
1212system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles
1213system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles
1214system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles
1215system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles
1216system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles
1217system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses
1218system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses
1219system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses
1220system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses
1221system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses
1222system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
1223system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses
1224system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses
1225system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses
1226system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses
1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency
1228system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency
1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency
1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency
1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency
1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency
1233system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency
1234system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency
1235system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency
1236system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency

1203system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses
1204system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
1205system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses
1206system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
1207system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles
1208system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles
1209system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles
1210system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles
1211system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles
1212system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles
1213system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles
1214system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles
1215system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles
1216system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles
1217system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses
1218system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses
1219system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses
1220system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses
1221system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses
1222system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
1223system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses
1224system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses
1225system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses
1226system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses
1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency
1228system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency
1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency
1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency
1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency
1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency
1233system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
1234system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency
1235system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency
1236system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency

1237system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1238system.cpu1.icache.tags.replacements 388 # number of replacements
1239system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use
1240system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks.
1241system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
1242system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks.

1238system.cpu1.icache.tags.replacements 385 # number of replacements
1239system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use
1240system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks.
1241system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks.
1242system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks.

1243system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1244system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor
1245system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy
1246system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy
1247system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id

1244system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor
1245system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy
1246system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy
1247system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id

1248system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

1249system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
1250system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
1251system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses
1252system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses
1253system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits
1254system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits
1255system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits
1256system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits
1257system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits
1258system.cpu1.icache.overall_hits::total 24292 # number of overall hits
1259system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses
1260system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses
1261system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses
1262system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses
1263system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses
1264system.cpu1.icache.overall_misses::total 562 # number of overall misses
1265system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles
1266system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles
1267system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles
1268system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles
1269system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles
1270system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles
1271system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses)
1272system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses)
1273system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses
1274system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses
1275system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses
1276system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses
1277system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses
1278system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses
1279system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses
1280system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses
1281system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses
1282system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses
1283system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency
1284system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency
1285system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency
1286system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency
1287system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency
1288system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency
1289system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked

1249system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
1250system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
1251system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses
1252system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses
1253system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits
1254system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits
1255system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits
1256system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits
1257system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits
1258system.cpu1.icache.overall_hits::total 21045 # number of overall hits
1259system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses
1260system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses
1261system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses
1262system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses
1263system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses
1264system.cpu1.icache.overall_misses::total 578 # number of overall misses
1265system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles
1266system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles
1267system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles
1268system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles
1269system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles
1270system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles
1271system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses)
1272system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses)
1273system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses
1274system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses
1275system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses
1276system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses
1277system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses
1278system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses
1279system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses
1280system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses
1281system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses
1282system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses
1283system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency
1284system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency
1285system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
1286system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency
1287system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency
1288system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency
1289system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked

1290system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1291system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked

1291system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked

1292system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked

1293system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked

1293system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked

1294system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1295system.cpu1.icache.fast_writes 0 # number of fast writes performed
1296system.cpu1.icache.cache_copies 0 # number of cache copies performed

1297system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits
1298system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
1299system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits
1300system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits
1301system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits
1302system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits
1303system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses
1304system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
1305system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses
1306system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
1307system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses
1308system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
1309system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles
1310system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles
1311system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles
1312system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles
1313system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles
1314system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles
1315system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses
1316system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses
1317system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses
1318system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses
1319system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses
1320system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses
1321system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency
1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency
1323system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency
1324system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency
1325system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency
1326system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency

1297system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
1298system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
1299system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
1300system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
1301system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
1302system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
1303system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses
1304system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses
1305system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses
1306system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses
1307system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses
1308system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses
1309system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles
1310system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles
1311system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles
1312system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles
1313system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles
1314system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles
1315system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses
1316system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses
1317system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses
1318system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses
1319system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses
1320system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses
1321system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency
1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency
1323system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
1324system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency
1325system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency
1326system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency

1327system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1328system.cpu2.branchPred.lookups 55295 # Number of BP lookups
1329system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted
1330system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect
1331system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups
1332system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits

1328system.cpu2.branchPred.lookups 51309 # Number of BP lookups
1329system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted
1330system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect
1331system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups
1332system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits

1333system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

1334system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage
1335system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target.

1334system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage
1335system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.

1336system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1337system.cpu2.numCycles 160375 # number of cpu cycles simulated

1337system.cpu2.numCycles 161860 # number of cpu cycles simulated

1338system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1339system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed

1340system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss
1341system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed
1342system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered
1343system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken
1344system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked
1345system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing
1346system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

1340system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss
1341system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed
1342system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered
1343system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken
1344system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked
1345system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing
1346system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

1347system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1348system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps
1349system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR
1350system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched
1351system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed
1352system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total)
1353system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total)
1354system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total)

1348system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps
1349system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched
1350system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed
1351system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total)
1352system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total)
1353system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total)

1355system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1354system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1356system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total)
1357system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total)
1358system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total)
1359system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total)
1360system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total)
1361system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total)
1362system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total)
1363system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total)
1364system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total)

1355system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total)
1356system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total)
1357system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total)
1358system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total)
1359system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total)
1360system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total)
1361system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total)
1362system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total)
1363system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total)

1365system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1366system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1367system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1364system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1365system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1366system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1368system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total)
1369system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle
1370system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle
1371system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle
1372system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked
1373system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running
1374system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking
1375system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing
1376system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode
1377system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing
1378system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle
1379system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking
1380system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst
1381system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running
1382system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking
1383system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename
1384system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full
1385system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full
1386system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers
1387system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed
1388system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made
1389system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups
1390system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed
1391system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing
1392system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed
1393system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed
1394system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer
1395system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit.
1396system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit.
1397system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads.
1398system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores.
1399system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec)
1400system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ
1401system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued
1402system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued
1403system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling
1404system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph
1405system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed
1406system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle
1407system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle
1408system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle

1367system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total)
1368system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle
1369system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle
1370system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle
1371system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked
1372system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running
1373system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking
1374system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing
1375system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode
1376system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing
1377system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle
1378system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking
1379system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst
1380system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running
1381system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking
1382system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename
1383system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full
1384system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
1385system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
1386system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed
1387system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made
1388system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups
1389system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed
1390system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing
1391system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed
1392system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
1393system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer
1394system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit.
1395system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit.
1396system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads.
1397system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores.
1398system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec)
1399system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ
1400system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued
1401system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
1402system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling
1403system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph
1404system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed
1405system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle
1406system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle
1407system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle

1409system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1408system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1410system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle
1411system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle
1412system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle
1413system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle
1414system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle
1415system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle
1416system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle
1417system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle
1418system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle

1409system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle
1410system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle
1411system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle
1412system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle
1413system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle
1414system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle
1415system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle
1416system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle
1417system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle

1419system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1420system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1421system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1418system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1419system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1420system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1422system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle

1421system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle

1423system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1422system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1424system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available
1425system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available
1426system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available
1427system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available
1428system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available
1429system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available
1430system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available
1431system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available
1432system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available
1433system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available
1434system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available
1435system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available
1436system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available
1437system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available
1438system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available
1439system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available
1440system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available
1441system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available
1442system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available
1443system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available
1444system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available
1445system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available
1446system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available
1447system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available
1448system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available
1449system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available
1450system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available
1451system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available
1452system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available
1453system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available
1454system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available

1423system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available
1424system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available
1425system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available
1426system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available
1427system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available
1428system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available
1429system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available
1430system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available
1431system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
1432system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available
1433system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available
1434system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available
1435system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available
1436system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available
1437system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available
1438system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available
1439system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available
1440system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available
1441system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available
1442system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available
1443system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available
1444system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available
1445system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available
1446system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available
1447system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available
1448system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available
1449system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available
1450system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available
1451system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available
1452system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available
1453system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available

1455system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1456system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1457system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1454system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1455system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1456system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1458system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued
1459system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued
1460system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued
1461system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued
1462system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued
1463system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued
1464system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued
1465system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued
1466system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued
1467system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued
1468system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued
1469system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued
1470system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued
1471system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued
1472system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued
1473system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued
1474system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued
1475system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued
1476system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued
1477system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued
1478system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued
1479system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued
1480system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued
1481system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued
1482system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued
1483system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued
1484system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued
1485system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued
1486system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued
1487system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued
1488system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued

1457system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued
1458system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
1459system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
1460system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
1461system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
1462system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
1463system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
1464system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
1465system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
1466system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
1467system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
1468system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
1469system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
1470system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
1471system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
1472system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
1473system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
1474system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
1475system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
1476system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
1477system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
1478system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
1479system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
1480system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
1481system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
1482system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
1483system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
1484system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
1485system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
1486system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued
1487system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued

1489system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1490system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1488system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1489system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1491system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued
1492system.cpu2.iq.rate 1.514600 # Inst issue rate
1493system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested
1494system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst)
1495system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads
1496system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes
1497system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses

1490system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued
1491system.cpu2.iq.rate 1.362270 # Inst issue rate
1492system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested
1493system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst)
1494system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads
1495system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes
1496system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses

1498system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1499system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1500system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1497system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1498system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
1499system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

1501system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses

1500system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses

1502system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1501system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses

1503system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores

1502system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores

1504system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1503system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1505system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed

1504system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed

1506system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed

1505system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed

1507system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations
1508system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed

1506system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
1507system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed

1509system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1510system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1511system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1512system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1513system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1508system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1509system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1510system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
1511system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
1512system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1514system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing
1515system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking
1516system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
1517system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ
1518system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch
1519system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions
1520system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions
1521system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions
1522system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall

1513system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing
1514system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking
1515system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
1516system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ
1517system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch
1518system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions
1519system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions
1520system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
1521system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall

1523system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1522system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

1524system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations
1525system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
1526system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly
1527system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute
1528system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions
1529system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed
1530system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute

1523system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations
1524system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly
1525system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly
1526system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute
1527system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions
1528system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed
1529system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute

1531system.cpu2.iew.exec_swp 0 # number of swp insts executed

1530system.cpu2.iew.exec_swp 0 # number of swp insts executed

1532system.cpu2.iew.exec_nop 39706 # number of nop insts executed
1533system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed
1534system.cpu2.iew.exec_branches 49059 # Number of branches executed
1535system.cpu2.iew.exec_stores 39036 # Number of stores executed
1536system.cpu2.iew.exec_rate 1.507585 # Inst execution rate
1537system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit
1538system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back
1539system.cpu2.iew.wb_producers 138145 # num instructions producing a value
1540system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value

1531system.cpu2.iew.exec_nop 36005 # number of nop insts executed
1532system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed
1533system.cpu2.iew.exec_branches 45327 # Number of branches executed
1534system.cpu2.iew.exec_stores 33515 # Number of stores executed
1535system.cpu2.iew.exec_rate 1.355350 # Inst execution rate
1536system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit
1537system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back
1538system.cpu2.iew.wb_producers 123331 # num instructions producing a value
1539system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value

1541system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

1540system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

1542system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle
1543system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back

1541system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle
1542system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back

1544system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

1543system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

1545system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit
1546system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards
1547system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted
1548system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle
1549system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle
1550system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle

1544system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit
1545system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards
1546system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted
1547system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle
1548system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle
1549system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle

1551system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1550system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

1552system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle
1553system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle
1554system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle
1555system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle
1556system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle
1557system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle
1558system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle
1559system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle
1560system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle

1551system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle
1552system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle
1553system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle
1554system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle
1555system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle
1556system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle
1557system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle
1558system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle
1559system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle

1561system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1562system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1563system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1560system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1561system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1562system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

1564system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle
1565system.cpu2.commit.committedInsts 272860 # Number of instructions committed
1566system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed

1563system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle
1564system.cpu2.commit.committedInsts 246921 # Number of instructions committed
1565system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed

1567system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1566system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed

1568system.cpu2.commit.refs 117938 # Number of memory references committed
1569system.cpu2.commit.loads 79744 # Number of loads committed
1570system.cpu2.commit.membars 3865 # Number of memory barriers committed
1571system.cpu2.commit.branches 48024 # Number of branches committed

1567system.cpu2.commit.refs 103190 # Number of memory references committed
1568system.cpu2.commit.loads 70499 # Number of loads committed
1569system.cpu2.commit.membars 5644 # Number of memory barriers committed
1570system.cpu2.commit.branches 44296 # Number of branches committed

1572system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1571system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.

1573system.cpu2.commit.int_insts 188084 # Number of committed integer instructions.

1572system.cpu2.commit.int_insts 169605 # Number of committed integer instructions.

1574system.cpu2.commit.function_calls 322 # Number of function calls committed.

1573system.cpu2.commit.function_calls 322 # Number of function calls committed.

1575system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction
1576system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction
1577system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction
1578system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction
1579system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction
1580system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction
1581system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction
1582system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction
1583system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction
1584system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction
1585system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction
1586system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction
1587system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction
1588system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction
1589system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction
1590system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction
1591system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction
1592system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction
1593system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction
1594system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction
1595system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction
1596system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction
1597system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction
1598system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction
1599system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction
1600system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction
1601system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction
1602system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction
1603system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction
1604system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction
1605system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction
1606system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction

1574system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction
1575system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction
1576system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction
1577system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction
1578system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction
1579system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction
1580system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction
1581system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction
1582system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction
1583system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction
1584system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction
1585system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction
1586system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction
1587system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction
1588system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction
1589system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction
1590system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction
1591system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction
1592system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction
1593system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction
1594system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction
1595system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction
1596system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction
1597system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction
1598system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction
1599system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction
1600system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction
1601system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction
1602system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction
1603system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction
1604system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction
1605system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction

1607system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1608system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1606system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1607system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

1609system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction
1610system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached

1608system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction
1609system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached

1611system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits

1610system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits

1612system.cpu2.rob.rob_reads 438358 # The number of ROB reads
1613system.cpu2.rob.rob_writes 577962 # The number of ROB writes
1614system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
1615system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling
1616system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1617system.cpu2.committedInsts 230180 # Number of Instructions Simulated
1618system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated
1619system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction
1620system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads
1621system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle
1622system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads
1623system.cpu2.int_regfile_reads 421380 # number of integer regfile reads
1624system.cpu2.int_regfile_writes 197053 # number of integer regfile writes

1611system.cpu2.rob.rob_reads 416888 # The number of ROB reads
1612system.cpu2.rob.rob_writes 525783 # The number of ROB writes
1613system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
1614system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling
1615system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1616system.cpu2.committedInsts 206194 # Number of Instructions Simulated
1617system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated
1618system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction
1619system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads
1620system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle
1621system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads
1622system.cpu2.int_regfile_reads 376797 # number of integer regfile reads
1623system.cpu2.int_regfile_writes 176595 # number of integer regfile writes

1625system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1624system.cpu2.fp_regfile_writes 64 # number of floating regfile writes

1626system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads

1625system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads

1627system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
1628system.cpu2.dcache.tags.replacements 0 # number of replacements

1626system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
1627system.cpu2.dcache.tags.replacements 0 # number of replacements

1629system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use
1630system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks.
1631system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
1632system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks.

1628system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use
1629system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks.
1630system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
1631system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks.

1633system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1632system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1634system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor
1635system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy
1636system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy
1637system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id

1633system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor
1634system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy
1635system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy
1636system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
1637system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id

1638system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id

1639system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
1640system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses
1641system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses
1642system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits
1643system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits
1644system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits
1645system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits
1646system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
1647system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
1648system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits
1649system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits
1650system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits
1651system.cpu2.dcache.overall_hits::total 84526 # number of overall hits
1652system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses
1653system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses
1654system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses
1655system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses
1656system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
1657system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
1658system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses
1659system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses
1660system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses
1661system.cpu2.dcache.overall_misses::total 597 # number of overall misses
1662system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles
1663system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles
1664system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles
1665system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles
1666system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles
1667system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles
1668system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles
1669system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles
1670system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles
1671system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles
1672system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses)
1673system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses)
1674system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses)
1675system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses)
1676system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses)
1677system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
1678system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses
1679system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses
1680system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses
1681system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses
1682system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses
1683system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses
1684system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses
1685system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses
1686system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses
1687system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses
1688system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses
1689system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses
1690system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses
1691system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses
1692system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency
1693system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency
1694system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency
1695system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency
1696system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency
1697system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency
1698system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency
1699system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency
1700system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency
1701system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency

1639system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
1640system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses
1641system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses
1642system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits
1643system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits
1644system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits
1645system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits
1646system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
1647system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
1648system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits
1649system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits
1650system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits
1651system.cpu2.dcache.overall_hits::total 75268 # number of overall hits
1652system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses
1653system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses
1654system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses
1655system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses
1656system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
1657system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
1658system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses
1659system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses
1660system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses
1661system.cpu2.dcache.overall_misses::total 573 # number of overall misses
1662system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles
1663system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles
1664system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles
1665system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles
1666system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles
1667system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles
1668system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles
1669system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles
1670system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles
1671system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles
1672system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses)
1673system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses)
1674system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses)
1675system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses)
1676system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
1677system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
1678system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses
1679system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses
1680system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses
1681system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses
1682system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses
1683system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses
1684system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses
1685system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses
1686system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses
1687system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
1688system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses
1689system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses
1690system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses
1691system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses
1692system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency
1693system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency
1694system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency
1695system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency
1696system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency
1697system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency
1698system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
1699system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency
1700system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency
1701system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency

1702system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1703system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1704system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1705system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
1706system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1707system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1708system.cpu2.dcache.fast_writes 0 # number of fast writes performed
1709system.cpu2.dcache.cache_copies 0 # number of cache copies performed

1710system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits
1711system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits
1712system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits
1713system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits
1714system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits
1715system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits
1716system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits
1717system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits
1718system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses
1719system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses
1720system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
1721system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
1722system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses
1723system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
1724system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
1725system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
1726system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
1727system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
1728system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles
1729system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles
1730system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles
1731system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles
1732system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles
1733system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles
1734system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles
1735system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles
1736system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles
1737system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles
1738system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses
1739system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses
1740system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses
1741system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses
1742system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses
1743system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses
1744system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses
1745system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses
1746system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses
1747system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses
1748system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency
1749system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency
1750system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency
1751system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency
1752system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency
1753system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency
1754system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency
1755system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency
1756system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency
1757system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency

1710system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits
1711system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits
1712system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits
1713system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
1714system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits
1715system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits
1716system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits
1717system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits
1718system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses
1719system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
1720system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses
1721system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
1722system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
1723system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
1724system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses
1725system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
1726system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses
1727system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
1728system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles
1729system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles
1730system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles
1731system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles
1732system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles
1733system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles
1734system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles
1735system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles
1736system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles
1737system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles
1738system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses
1739system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses
1740system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses
1741system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses
1742system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses
1743system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
1744system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses
1745system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses
1746system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses
1747system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses
1748system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency
1749system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency
1750system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency
1751system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency
1752system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency
1753system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency
1754system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
1755system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency
1756system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency
1757system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency

1758system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1759system.cpu2.icache.tags.replacements 378 # number of replacements
1760system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use
1761system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks.
1762system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks.
1763system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks.

1759system.cpu2.icache.tags.replacements 384 # number of replacements
1760system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use
1761system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks.
1762system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks.
1763system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks.

1764system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

1765system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor
1766system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy
1767system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy
1768system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id

1765system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor
1766system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy
1767system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy
1768system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id

1769system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

1770system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
1771system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id
1772system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses
1773system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses
1774system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits
1775system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits
1776system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits
1777system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits
1778system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits
1779system.cpu2.icache.overall_hits::total 18881 # number of overall hits
1780system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses
1781system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses
1782system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses
1783system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses
1784system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses
1785system.cpu2.icache.overall_misses::total 570 # number of overall misses
1786system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles
1787system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles
1788system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles
1789system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles
1790system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles
1791system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles
1792system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses)
1793system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses)
1794system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses
1795system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses
1796system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses
1797system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses
1798system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses
1799system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses
1800system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses
1801system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses
1802system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses
1803system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses
1804system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency
1805system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency
1806system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency
1807system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency
1808system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency
1809system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency
1810system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked

1770system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
1771system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
1772system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses
1773system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses
1774system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits
1775system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits
1776system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits
1777system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits
1778system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits
1779system.cpu2.icache.overall_hits::total 22324 # number of overall hits
1780system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses
1781system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses
1782system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses
1783system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses
1784system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses
1785system.cpu2.icache.overall_misses::total 560 # number of overall misses
1786system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles
1787system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles
1788system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles
1789system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles
1790system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles
1791system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles
1792system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses)
1793system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses)
1794system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses
1795system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses
1796system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses
1797system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses
1798system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses
1799system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses
1800system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses
1801system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses
1802system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses
1803system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses
1804system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency
1805system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency
1806system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
1807system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency
1808system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency
1809system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency
1810system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

1811system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1812system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked

1812system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked

1813system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked

1814system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked

1814system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

1815system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1816system.cpu2.icache.fast_writes 0 # number of fast writes performed
1817system.cpu2.icache.cache_copies 0 # number of cache copies performed

1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits
1819system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits
1821system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits
1823system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits
1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses
1825system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses
1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses
1827system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses
1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses
1829system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses
1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles
1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles
1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles
1833system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles
1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles
1835system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles
1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses
1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses
1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses
1839system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses
1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses
1841system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses
1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency
1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency
1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency
1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency
1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency
1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency

1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits
1819system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits
1821system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits
1823system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses
1825system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses
1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses
1827system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses
1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses
1829system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses
1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles
1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles
1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles
1833system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles
1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles
1835system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles
1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses
1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses
1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses
1839system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses
1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses
1841system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses
1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency
1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency
1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency
1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency
1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency

1848system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1849system.cpu3.branchPred.lookups 49708 # Number of BP lookups
1850system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted
1851system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
1852system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups
1853system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits

1849system.cpu3.branchPred.lookups 49957 # Number of BP lookups
1850system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted
1851system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect
1852system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups
1853system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits

1854system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

1855system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage
1856system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target.

1855system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage
1856system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.

1857system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.

1858system.cpu3.numCycles 160031 # number of cpu cycles simulated

1858system.cpu3.numCycles 161075 # number of cpu cycles simulated

1859system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1860system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed

1861system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss
1862system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed
1863system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered
1864system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken
1865system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked
1866system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing

1861system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss
1862system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed
1863system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered
1864system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken
1865system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked
1866system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing

1867system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1868system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from

1869system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps
1870system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched
1871system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed
1872system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total)
1873system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total)
1874system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total)

1869system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps
1870system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched
1871system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed
1872system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total)
1873system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total)
1874system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total)

1875system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1876system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total)
1877system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total)
1878system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total)
1879system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total)
1880system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total)
1881system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total)
1882system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total)
1883system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total)
1884system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total)

1876system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total)
1877system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total)
1878system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total)
1879system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total)
1880system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total)
1881system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total)
1882system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total)
1883system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total)
1884system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total)

1885system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1886system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1887system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

1888system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total)
1889system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle
1890system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle
1891system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle
1892system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked
1893system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running
1894system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking
1895system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing
1896system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode
1897system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing
1898system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle
1899system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking
1900system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst
1901system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running
1902system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking
1903system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename
1904system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full
1905system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full
1906system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
1907system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed
1908system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made
1909system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups
1910system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed
1911system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing
1912system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed
1913system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed
1914system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer
1915system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit.
1916system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit.
1917system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads.
1918system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores.
1919system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec)
1920system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ
1921system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued
1922system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued
1923system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling
1924system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph
1925system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed
1926system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle
1927system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle
1928system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle

1888system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total)
1889system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle
1890system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle
1891system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle
1892system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked
1893system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running
1894system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking
1895system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing
1896system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode
1897system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing
1898system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle
1899system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking
1900system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst
1901system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running
1902system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking
1903system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename
1904system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
1905system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full
1906system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
1907system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed
1908system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made
1909system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups
1910system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed
1911system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing
1912system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed
1913system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed
1914system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer
1915system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit.
1916system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit.
1917system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads.
1918system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores.
1919system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec)
1920system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ
1921system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued
1922system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
1923system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling
1924system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph
1925system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed
1926system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle
1927system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle
1928system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle

1929system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1930system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle
1931system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle
1932system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle
1933system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle
1934system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle
1935system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle
1936system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle
1937system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle
1938system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle

1930system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle
1931system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle
1932system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle
1933system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle
1934system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle
1935system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle
1936system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle
1937system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle
1938system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle

1939system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1940system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1941system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

1942system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle

1942system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle

1943system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1944system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available
1945system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available
1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available
1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available
1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available
1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available
1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available
1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available
1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available
1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available
1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available
1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available
1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available
1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available
1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available
1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available
1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available
1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available
1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available
1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available
1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available
1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available
1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available
1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available
1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available
1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available
1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available
1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available
1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available
1973system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available
1974system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available

1944system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available
1945system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available
1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available
1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available
1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available
1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available
1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available
1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available
1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available
1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available
1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available
1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available
1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available
1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available
1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available
1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available
1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available
1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available
1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available
1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available
1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available
1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available
1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available
1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available
1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available
1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available
1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available
1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available
1973system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available
1974system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available

1975system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1976system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1977system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

1978system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued
1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued
1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued
1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued
1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued
1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued
1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued
1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued
1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued
1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued
1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued
1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued
1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued
1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued
1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued
1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued
1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued
1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued
1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued
1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued
1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued
1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued
2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued
2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued
2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued
2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued
2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued
2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued
2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued
2007system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued
2008system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued

1978system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued
1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
2007system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued
2008system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued

2009system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2010system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

2011system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued
2012system.cpu3.iq.rate 1.322737 # Inst issue rate
2013system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested
2014system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst)
2015system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads
2016system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes
2017system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses

2011system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued
2012system.cpu3.iq.rate 1.322999 # Inst issue rate
2013system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested
2014system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst)
2015system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads
2016system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes
2017system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses

2018system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
2019system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
2020system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

2021system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses

2021system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses

2022system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses

2023system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores

2023system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores

2024system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

2025system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed

2025system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed

2026system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed

2027system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations
2028system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed

2027system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
2028system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed

2029system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2030system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2031system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2032system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
2033system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle

2034system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing
2035system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking
2036system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking
2037system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ
2038system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch
2039system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions
2040system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions
2041system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions

2034system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing
2035system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking
2036system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
2037system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ
2038system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch
2039system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions
2040system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions
2041system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions

2042system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
2043system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

2044system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations
2045system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly
2046system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly
2047system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
2048system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions
2049system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed
2050system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute

2044system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
2045system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
2046system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly
2047system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute
2048system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions
2049system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed
2050system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute

2051system.cpu3.iew.exec_swp 0 # number of swp insts executed

2052system.cpu3.iew.exec_nop 34395 # number of nop insts executed
2053system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed
2054system.cpu3.iew.exec_branches 43728 # Number of branches executed
2055system.cpu3.iew.exec_stores 31474 # Number of stores executed
2056system.cpu3.iew.exec_rate 1.315601 # Inst execution rate
2057system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit
2058system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back
2059system.cpu3.iew.wb_producers 117676 # num instructions producing a value
2060system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value

2052system.cpu3.iew.exec_nop 34658 # number of nop insts executed
2053system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed
2054system.cpu3.iew.exec_branches 44015 # Number of branches executed
2055system.cpu3.iew.exec_stores 31810 # Number of stores executed
2056system.cpu3.iew.exec_rate 1.315989 # Inst execution rate
2057system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit
2058system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back
2059system.cpu3.iew.wb_producers 118601 # num instructions producing a value
2060system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value

2061system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

2062system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle
2063system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back

2062system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle
2063system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back

2064system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

2065system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit
2066system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards
2067system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
2068system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle
2069system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle
2070system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle

2065system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit
2066system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards
2067system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted
2068system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle
2069system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle
2070system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle

2071system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2072system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle
2073system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle
2074system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle
2075system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle
2076system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle
2077system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle
2078system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle
2079system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle
2080system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle

2072system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle
2073system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle
2074system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle
2075system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle
2076system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle
2077system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle
2078system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle
2079system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle
2080system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle

2081system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2082system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2083system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2084system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle
2085system.cpu3.commit.committedInsts 236439 # Number of instructions committed
2086system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed

2084system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle
2085system.cpu3.commit.committedInsts 238347 # Number of instructions committed
2086system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed

2087system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed

2088system.cpu3.commit.refs 97502 # Number of memory references committed
2089system.cpu3.commit.loads 66856 # Number of loads committed
2090system.cpu3.commit.membars 6091 # Number of memory barriers committed
2091system.cpu3.commit.branches 42698 # Number of branches committed

2088system.cpu3.commit.refs 98515 # Number of memory references committed
2089system.cpu3.commit.loads 67516 # Number of loads committed
2090system.cpu3.commit.membars 6034 # Number of memory barriers committed
2091system.cpu3.commit.branches 42994 # Number of branches committed

2092system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.

2093system.cpu3.commit.int_insts 162319 # Number of committed integer instructions.

2093system.cpu3.commit.int_insts 163632 # Number of committed integer instructions.

2094system.cpu3.commit.function_calls 322 # Number of function calls committed.

2095system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction
2096system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction
2097system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction
2098system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction
2099system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction
2100system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction
2101system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction
2102system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction
2103system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction
2104system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction
2105system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction
2106system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction
2107system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction
2108system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction
2109system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction
2110system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction
2111system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction
2112system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction
2113system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction
2114system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction
2115system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction
2116system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction
2117system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction
2118system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction
2119system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction
2120system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction
2121system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction
2122system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction
2123system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction
2124system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction
2125system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction
2126system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction

2095system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction
2096system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction
2097system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction
2098system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction
2099system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction
2100system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction
2101system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction
2102system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction
2103system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction
2104system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction
2105system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction
2106system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction
2107system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction
2108system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction
2109system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction
2110system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction
2111system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction
2112system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction
2113system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction
2114system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction
2115system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction
2116system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction
2117system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction
2118system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction
2119system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction
2120system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction
2121system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction
2122system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction
2123system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction
2124system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction
2125system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction
2126system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction

2127system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2128system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2129system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction
2130system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached

2129system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction
2130system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached

2131system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits

2132system.cpu3.rob.rob_reads 405464 # The number of ROB reads
2133system.cpu3.rob.rob_writes 504751 # The number of ROB writes
2134system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
2135system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling
2136system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2137system.cpu3.committedInsts 196863 # Number of Instructions Simulated
2138system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated
2139system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction
2140system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads
2141system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle
2142system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads
2143system.cpu3.int_regfile_reads 359772 # number of integer regfile reads
2144system.cpu3.int_regfile_writes 168916 # number of integer regfile writes

2132system.cpu3.rob.rob_reads 408052 # The number of ROB reads
2133system.cpu3.rob.rob_writes 507784 # The number of ROB writes
2134system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
2135system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling
2136system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2137system.cpu3.committedInsts 198529 # Number of Instructions Simulated
2138system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated
2139system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction
2140system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads
2141system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle
2142system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads
2143system.cpu3.int_regfile_reads 362535 # number of integer regfile reads
2144system.cpu3.int_regfile_writes 170128 # number of integer regfile writes

2145system.cpu3.fp_regfile_writes 64 # number of floating regfile writes

2146system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads

2146system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads

2147system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
2148system.cpu3.dcache.tags.replacements 0 # number of replacements

2149system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use
2150system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks.
2151system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
2152system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks.

2149system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use
2150system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks.
2151system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
2152system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks.

2153system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2154system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor
2155system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy
2156system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy
2157system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
2158system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id

2154system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor
2155system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy
2156system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy
2157system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id

2159system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id

2158system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id

2160system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
2161system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses
2162system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses
2163system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits
2164system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits
2165system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits
2166system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits

2159system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
2160system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses
2161system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses
2162system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits
2163system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits
2164system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits
2165system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits

2167system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
2168system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits

2166system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
2167system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits

2169system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits
2170system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits
2171system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits
2172system.cpu3.dcache.overall_hits::total 71643 # number of overall hits
2173system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses
2174system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses
2175system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses
2176system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses
2177system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses
2178system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses
2179system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses
2180system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses
2181system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses
2182system.cpu3.dcache.overall_misses::total 560 # number of overall misses
2183system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles
2184system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles
2185system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles
2186system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles
2187system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles
2188system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles
2189system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles
2190system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles
2191system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles
2192system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles
2193system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses)
2194system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses)
2195system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses)
2196system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses)
2197system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
2198system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
2199system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses
2200system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses
2201system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses
2202system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses
2203system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses
2204system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses
2205system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses
2206system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses
2207system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses
2208system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
2209system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses
2210system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses
2211system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses
2212system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses
2213system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency
2214system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency
2215system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency
2216system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency
2217system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency
2218system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency
2219system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency
2220system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency
2221system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency
2222system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency

2168system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits
2169system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits
2170system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits
2171system.cpu3.dcache.overall_hits::total 72250 # number of overall hits
2172system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses
2173system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses
2174system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses
2175system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses
2176system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
2177system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
2178system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses
2179system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses
2180system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses
2181system.cpu3.dcache.overall_misses::total 577 # number of overall misses
2182system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles
2183system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles
2184system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles
2185system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles
2186system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles
2187system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles
2188system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles
2189system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles
2190system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles
2191system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles
2192system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses)
2193system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses)
2194system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses)
2195system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses)
2196system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses)
2197system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
2198system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses
2199system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses
2200system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses
2201system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses
2202system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses
2203system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses
2204system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses
2205system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses
2206system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses
2207system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses
2208system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses
2209system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses
2210system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses
2211system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses
2212system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency
2213system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency
2214system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency
2215system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency
2216system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency
2217system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency
2218system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
2219system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency
2220system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency
2221system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency

2223system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2224system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2225system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2226system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2227system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2228system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2229system.cpu3.dcache.fast_writes 0 # number of fast writes performed
2230system.cpu3.dcache.cache_copies 0 # number of cache copies performed

2222system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2223system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2224system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2225system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
2226system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2227system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2228system.cpu3.dcache.fast_writes 0 # number of fast writes performed
2229system.cpu3.dcache.cache_copies 0 # number of cache copies performed

2231system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits
2232system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits

2230system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits
2231system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits

2233system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits
2234system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits

2232system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits
2233system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits

2235system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits
2236system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits
2237system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits
2238system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits
2239system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses
2240system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
2241system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
2242system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
2243system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses
2244system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
2245system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses
2246system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
2247system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses
2248system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
2249system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles
2250system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles
2251system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles
2252system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles
2253system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles
2254system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles
2255system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles
2256system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles
2257system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles
2258system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles
2259system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses
2260system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses
2261system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses
2262system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses
2263system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses
2264system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
2265system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses
2266system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses
2267system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses
2268system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses
2269system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency
2270system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency
2271system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency
2272system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency
2273system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency
2274system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency
2275system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency
2276system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency
2277system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency
2278system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency

2234system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits
2235system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits
2236system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits
2237system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits
2238system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
2239system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
2240system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses
2241system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
2242system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
2243system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
2244system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses
2245system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2246system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses
2247system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses
2248system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles
2249system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles
2250system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles
2251system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles
2252system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles
2253system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles
2254system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles
2255system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles
2256system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles
2257system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles
2258system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses
2259system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses
2260system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses
2261system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses
2262system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses
2263system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses
2264system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses
2265system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses
2266system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses
2267system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses
2268system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency
2269system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency
2270system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency
2271system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency
2272system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency
2273system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency
2274system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
2275system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency
2276system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency
2277system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency

2279system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

2278system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

2280system.cpu3.icache.tags.replacements 386 # number of replacements
2281system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use
2282system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks.
2283system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks.
2284system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks.

2279system.cpu3.icache.tags.replacements 387 # number of replacements
2280system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use
2281system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks.
2282system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
2283system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks.

2285system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2284system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2286system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor
2287system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy
2288system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy
2289system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id

2285system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor
2286system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy
2287system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy
2288system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id

2290system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

2289system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id

2291system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
2292system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id
2293system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses
2294system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses
2295system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits
2296system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits
2297system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits
2298system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits
2299system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits
2300system.cpu3.icache.overall_hits::total 23274 # number of overall hits
2301system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses
2302system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses
2303system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses
2304system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses
2305system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses
2306system.cpu3.icache.overall_misses::total 556 # number of overall misses
2307system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles
2308system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles
2309system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles
2310system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles
2311system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles
2312system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles
2313system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses)
2314system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses)
2315system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses
2316system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses
2317system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses
2318system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses
2319system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses
2320system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses
2321system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses
2322system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses
2323system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses
2324system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses
2325system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency
2326system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency
2327system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency
2328system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency
2329system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency
2330system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency

2290system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
2291system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id
2292system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses
2293system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses
2294system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits
2295system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits
2296system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits
2297system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits
2298system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits
2299system.cpu3.icache.overall_hits::total 23109 # number of overall hits
2300system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses
2301system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses
2302system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses
2303system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses
2304system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses
2305system.cpu3.icache.overall_misses::total 560 # number of overall misses
2306system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles
2307system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles
2308system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles
2309system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles
2310system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles
2311system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles
2312system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses)
2313system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses)
2314system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses
2315system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses
2316system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses
2317system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses
2318system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses
2319system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses
2320system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses
2321system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses
2322system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses
2323system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses
2324system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency
2325system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency
2326system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
2327system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency
2328system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency
2329system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency

2331system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2332system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2333system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2334system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2335system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2336system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2337system.cpu3.icache.fast_writes 0 # number of fast writes performed
2338system.cpu3.icache.cache_copies 0 # number of cache copies performed

2330system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2331system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2332system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2333system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
2334system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2335system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2336system.cpu3.icache.fast_writes 0 # number of fast writes performed
2337system.cpu3.icache.cache_copies 0 # number of cache copies performed

2339system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits
2340system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
2341system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits
2342system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
2343system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits
2344system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
2345system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses
2346system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses
2347system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses
2348system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses
2349system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses
2350system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses
2351system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles
2352system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles
2353system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles
2354system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles
2355system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles
2356system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles
2357system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses
2358system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses
2359system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses
2360system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses
2361system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses
2362system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses
2363system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency
2364system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency
2365system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency
2366system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency
2367system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency
2368system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency

2338system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits
2339system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
2340system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits
2341system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
2342system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits
2343system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
2344system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
2345system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
2346system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
2347system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
2348system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
2349system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
2350system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles
2351system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles
2352system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles
2353system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles
2354system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles
2355system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles
2356system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses
2357system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses
2358system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses
2359system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses
2360system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses
2361system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses
2362system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency
2363system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency
2364system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
2365system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency
2366system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency
2367system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency

2369system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2370system.l2c.tags.replacements 0 # number of replacements

2368system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2369system.l2c.tags.replacements 0 # number of replacements

2371system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use
2372system.l2c.tags.total_refs 1661 # Total number of references to valid blocks.
2373system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks.
2374system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks.

2370system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use
2371system.l2c.tags.total_refs 1669 # Total number of references to valid blocks.
2372system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks.
2373system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks.

2375system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2374system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2376system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor
2377system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor
2378system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor
2379system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor
2380system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor
2381system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor
2382system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor
2383system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor
2384system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor

2375system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor
2376system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor
2377system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor
2378system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor
2379system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor
2380system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor
2381system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor
2382system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor
2383system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor

2385system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy

2384system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy

2386system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy
2387system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy
2388system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy
2389system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy
2390system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy
2391system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy
2392system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy
2393system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy

2385system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy
2386system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy
2387system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy
2388system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
2389system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy
2390system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
2391system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy
2392system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy

2394system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy

2393system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy

2395system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id
2396system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
2397system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
2398system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id
2399system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id
2400system.l2c.tags.tag_accesses 20025 # Number of tag accesses
2401system.l2c.tags.data_accesses 20025 # Number of data accesses
2402system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits

2394system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id
2395system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
2396system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
2397system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
2398system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id
2399system.l2c.tags.tag_accesses 20118 # Number of tag accesses
2400system.l2c.tags.data_accesses 20118 # Number of data accesses
2401system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits

2403system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits

2402system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits

2404system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits
2405system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
2406system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits
2407system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
2408system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits

2403system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits
2404system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
2405system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits
2406system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
2407system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits

2409system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits

2408system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits

2410system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits

2409system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits

2411system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
2412system.l2c.Writeback_hits::total 1 # number of Writeback hits
2413system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2414system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits

2410system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
2411system.l2c.Writeback_hits::total 1 # number of Writeback hits
2412system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
2413system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits

2415system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits

2414system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits

2416system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2415system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits

2417system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits
2418system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
2419system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits
2420system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
2421system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits

2416system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits
2417system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
2418system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits
2419system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
2420system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits

2422system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2421system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits

2423system.l2c.demand_hits::total 1661 # number of demand (read+write) hits
2424system.l2c.overall_hits::cpu0.inst 248 # number of overall hits

2422system.l2c.demand_hits::total 1669 # number of demand (read+write) hits
2423system.l2c.overall_hits::cpu0.inst 251 # number of overall hits

2425system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2424system.l2c.overall_hits::cpu0.data 5 # number of overall hits

2426system.l2c.overall_hits::cpu1.inst 483 # number of overall hits
2427system.l2c.overall_hits::cpu1.data 11 # number of overall hits
2428system.l2c.overall_hits::cpu2.inst 409 # number of overall hits
2429system.l2c.overall_hits::cpu2.data 5 # number of overall hits
2430system.l2c.overall_hits::cpu3.inst 489 # number of overall hits

2425system.l2c.overall_hits::cpu1.inst 414 # number of overall hits
2426system.l2c.overall_hits::cpu1.data 5 # number of overall hits
2427system.l2c.overall_hits::cpu2.inst 481 # number of overall hits
2428system.l2c.overall_hits::cpu2.data 11 # number of overall hits
2429system.l2c.overall_hits::cpu3.inst 491 # number of overall hits

2431system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2430system.l2c.overall_hits::cpu3.data 11 # number of overall hits

2432system.l2c.overall_hits::total 1661 # number of overall hits
2433system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses
2434system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
2435system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
2436system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
2437system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses
2438system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
2439system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses

2431system.l2c.overall_hits::total 1669 # number of overall hits
2432system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses
2433system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses
2434system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses
2435system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
2436system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses
2437system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
2438system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses

2440system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses

2439system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses

2441system.l2c.ReadReq_misses::total 546 # number of ReadReq misses
2442system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses

2440system.l2c.ReadReq_misses::total 551 # number of ReadReq misses
2441system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses

2443system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses

2442system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses

2444system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
2445system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses
2446system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses

2443system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
2444system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
2445system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses

2447system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses

2446system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses

2448system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
2449system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses

2447system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
2448system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses

2450system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2451system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2449system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
2450system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses

2452system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses
2453system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
2454system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
2455system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
2456system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses
2457system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
2458system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses

2451system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses
2452system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
2453system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses
2454system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
2455system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses
2456system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
2457system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses

2459system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses

2458system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses

2460system.l2c.demand_misses::total 677 # number of demand (read+write) misses
2461system.l2c.overall_misses::cpu0.inst 361 # number of overall misses
2462system.l2c.overall_misses::cpu0.data 168 # number of overall misses
2463system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
2464system.l2c.overall_misses::cpu1.data 13 # number of overall misses
2465system.l2c.overall_misses::cpu2.inst 81 # number of overall misses
2466system.l2c.overall_misses::cpu2.data 20 # number of overall misses
2467system.l2c.overall_misses::cpu3.inst 6 # number of overall misses

2459system.l2c.demand_misses::total 682 # number of demand (read+write) misses
2460system.l2c.overall_misses::cpu0.inst 364 # number of overall misses
2461system.l2c.overall_misses::cpu0.data 169 # number of overall misses
2462system.l2c.overall_misses::cpu1.inst 83 # number of overall misses
2463system.l2c.overall_misses::cpu1.data 20 # number of overall misses
2464system.l2c.overall_misses::cpu2.inst 13 # number of overall misses
2465system.l2c.overall_misses::cpu2.data 13 # number of overall misses
2466system.l2c.overall_misses::cpu3.inst 7 # number of overall misses

2468system.l2c.overall_misses::cpu3.data 13 # number of overall misses

2467system.l2c.overall_misses::cpu3.data 13 # number of overall misses

2469system.l2c.overall_misses::total 677 # number of overall misses
2470system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles
2471system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles
2472system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles
2473system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles
2474system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles
2475system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles
2476system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles
2477system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles
2478system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles
2479system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles
2480system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles
2481system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles
2482system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles
2483system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles
2484system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles
2485system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles
2486system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles
2487system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles
2488system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles
2489system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles
2490system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles
2491system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles
2492system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles
2493system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles
2494system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles
2495system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles
2496system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles
2497system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles
2498system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles
2499system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles
2500system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles
2501system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles
2502system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses)
2503system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
2504system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses)

2468system.l2c.overall_misses::total 682 # number of overall misses
2469system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles
2470system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles
2471system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles
2472system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles
2473system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles
2474system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles
2475system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles
2476system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles
2477system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles
2478system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles
2479system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles
2480system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles
2481system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles
2482system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles
2483system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles
2484system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles
2485system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles
2486system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles
2487system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles
2488system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles
2489system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles
2490system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles
2491system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles
2492system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles
2493system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles
2494system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles
2495system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles
2496system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles
2497system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles
2498system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles
2499system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles
2500system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles
2501system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses)
2502system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses)
2503system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses)

2505system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)

2504system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)

2506system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses)

2505system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses)

2507system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)

2506system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)

2508system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses)

2507system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses)

2509system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)

2508system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)

2510system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses)

2509system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses)

2511system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
2512system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)

2510system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
2511system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)

2513system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses)

2512system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)

2514system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)

2513system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)

2515system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
2516system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
2517system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses)

2514system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
2515system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
2516system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)

2518system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)

2517system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)

2519system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
2520system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)

2518system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
2519system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)

2521system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2522system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2520system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
2521system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)

2523system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses
2524system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
2525system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses
2526system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
2527system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses
2528system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
2529system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses

2522system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses
2523system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
2524system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses
2525system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
2526system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses
2527system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
2528system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses

2530system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses

2529system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses

2531system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses
2532system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses
2533system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
2534system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses
2535system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
2536system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses
2537system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
2538system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses

2530system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses
2531system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses
2532system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
2533system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses
2534system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
2535system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses
2536system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
2537system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses

2539system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses

2538system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses

2540system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses
2541system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses
2542system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
2543system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses
2544system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses
2545system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses
2546system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses
2547system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses

2539system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses
2540system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses
2541system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses
2542system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses
2543system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
2544system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses
2545system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
2546system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses

2548system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses

2547system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses

2549system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses
2550system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses

2548system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses
2549system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses

2551system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2552system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2553system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses

2550system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2551system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
2552system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses

2554system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses

2553system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses

2555system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2556system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2557system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2558system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2559system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2554system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
2555system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
2556system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
2557system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
2558system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

2560system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses
2561system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
2562system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses
2563system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses
2564system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses
2565system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses
2566system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses

2559system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses
2560system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
2561system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses
2562system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
2563system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses
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2567system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses

2566system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses

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2572system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
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2574system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses
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2571system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
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2573system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
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2576system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses

2575system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses

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2583system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency
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2610system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2612system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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2614system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2615system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2616system.l2c.fast_writes 0 # number of fast writes performed
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2609system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2611system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2612system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2613system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2614system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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2701system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles
2702system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles
2703system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles
2704system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles
2705system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles
2706system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles
2707system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses
2708system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
2709system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses
2710system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses
2711system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses
2712system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses
2713system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses

2668system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses
2669system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles
2670system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles
2671system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles
2672system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles
2673system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles
2674system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles
2675system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles
2676system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles
2677system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles
2678system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles
2679system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles
2680system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles
2681system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles
2682system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles
2683system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles
2684system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles
2685system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles
2686system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles
2687system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles
2688system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles
2689system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles
2690system.l2c.demand_mshr_miss_latency::cpu1.inst 5227250 # number of demand (read+write) MSHR miss cycles
2691system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles
2692system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles
2693system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles
2694system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles
2695system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles
2696system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles
2697system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles
2698system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles
2699system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles
2700system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles
2701system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles
2702system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles
2703system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles
2704system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles
2705system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles
2706system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses
2707system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses
2708system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses
2709system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
2710system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses
2711system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
2712system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses

2714system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses

2713system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses

2715system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses
2716system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses

2714system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses
2715system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses

2717system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2718system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2719system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses

2716system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2717system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
2718system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses

2720system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses

2719system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses

2721system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2722system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2723system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2724system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2725system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2720system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
2721system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
2722system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
2723system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
2724system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

2726system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses
2727system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
2728system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses
2729system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
2730system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses
2731system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
2732system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses

2725system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses
2726system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
2727system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses
2728system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
2729system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses
2730system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
2731system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses

2733system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses

2732system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses

2734system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses
2735system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses
2736system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
2737system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses
2738system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
2739system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses
2740system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
2741system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses

2733system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses
2734system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses
2735system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
2736system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses
2737system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
2738system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses
2739system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
2740system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses

2742system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses

2741system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses

2743system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses
2744system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency
2745system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency
2746system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency
2747system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency
2748system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency
2749system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency
2750system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency
2751system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency
2752system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency
2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
2755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
2756system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
2757system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
2758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency
2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency
2760system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency
2761system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency
2762system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency
2763system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency
2764system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency
2765system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency
2766system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency
2767system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency
2768system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency
2769system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency
2770system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency
2771system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency
2772system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency
2773system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency
2774system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency
2775system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency
2776system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency
2777system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency
2778system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency
2779system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency
2780system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency

2742system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses
2743system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency
2744system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency
2745system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency
2746system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency
2747system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency
2748system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency
2749system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency
2750system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency
2751system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency
2752system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency
2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency
2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency
2755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency
2756system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency
2757system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency
2758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency
2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency
2760system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency
2761system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency
2762system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
2763system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
2764system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
2765system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
2766system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
2767system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
2768system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
2769system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
2770system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency
2771system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency
2772system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency
2773system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency
2774system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency
2775system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency
2776system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency
2777system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency
2778system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency
2779system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency

2781system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

2780system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

2782system.membus.trans_dist::ReadReq 534 # Transaction distribution
2783system.membus.trans_dist::ReadResp 533 # Transaction distribution
2784system.membus.trans_dist::UpgradeReq 274 # Transaction distribution
2785system.membus.trans_dist::UpgradeResp 78 # Transaction distribution
2786system.membus.trans_dist::ReadExReq 179 # Transaction distribution

2781system.membus.trans_dist::ReadReq 539 # Transaction distribution
2782system.membus.trans_dist::ReadResp 538 # Transaction distribution
2783system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
2784system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
2785system.membus.trans_dist::ReadExReq 171 # Transaction distribution

2787system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2786system.membus.trans_dist::ReadExResp 131 # Transaction distribution

2788system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes)
2789system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes)
2790system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes)
2791system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes)
2792system.membus.snoops 244 # Total snoops (count)
2793system.membus.snoop_fanout::samples 987 # Request fanout histogram

2787system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes)
2788system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes)
2789system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes)
2790system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes)
2791system.membus.snoops 240 # Total snoops (count)
2792system.membus.snoop_fanout::samples 986 # Request fanout histogram

2794system.membus.snoop_fanout::mean 0 # Request fanout histogram
2795system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2796system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2793system.membus.snoop_fanout::mean 0 # Request fanout histogram
2794system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2795system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2797system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram

2796system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram

2798system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2799system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2800system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2801system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2797system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2798system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2799system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2800system.membus.snoop_fanout::max_value 0 # Request fanout histogram

2802system.membus.snoop_fanout::total 987 # Request fanout histogram
2803system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks)

2801system.membus.snoop_fanout::total 986 # Request fanout histogram
2802system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks)

2804system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)

2803system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)

2805system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks)
2806system.membus.respLayer1.utilization 6.0 # Layer utilization (%)
2807system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution
2808system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution

2804system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks)
2805system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
2806system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution
2807system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution

2809system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution

2808system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution

2810system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
2811system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
2812system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution
2813system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution
2814system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes)
2815system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes)
2816system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes)
2817system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
2818system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes)
2819system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
2820system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes)
2821system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
2822system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes)
2823system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes)
2824system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
2825system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
2826system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
2827system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes)
2828system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2829system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes)

2809system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution
2810system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution
2811system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution
2812system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution
2813system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes)
2814system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes)
2815system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
2816system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes)
2817system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes)
2818system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
2819system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes)
2820system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
2821system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes)
2822system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes)
2823system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
2824system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes)
2825system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
2826system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes)
2827system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
2828system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)

2830system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)

2829system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)

2831system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes)
2832system.toL2Bus.snoops 1023 # Total snoops (count)

2830system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes)
2831system.toL2Bus.snoops 1012 # Total snoops (count)

2833system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram
2834system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
2835system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
2836system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2837system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2838system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2839system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2840system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2841system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2842system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
2843system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
2844system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram
2845system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2846system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2847system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
2848system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
2849system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram

2832system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram
2833system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
2834system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
2835system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2836system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2837system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2838system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2839system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2840system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2841system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
2842system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
2843system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram
2844system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2845system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2846system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
2847system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
2848system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram

2850system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks)

2849system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks)

2851system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)

2850system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)

2852system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks)
2853system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
2854system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks)
2855system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
2856system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks)
2857system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%)
2858system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks)
2859system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
2860system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks)
2861system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%)
2862system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks)
2863system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
2864system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks)
2865system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%)
2866system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks)
2867system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%)

2851system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks)
2852system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
2853system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks)
2854system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
2855system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks)
2856system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
2857system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks)
2858system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
2859system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks)
2860system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
2861system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks)
2862system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
2863system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks)
2864system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
2865system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks)
2866system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)