| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000106 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000106 # Number of seconds simulated |
| 4sim_ticks 105696000 # Number of ticks simulated 5final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 105542000 # Number of ticks simulated 5final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 145069 # Simulator instruction rate (inst/s) 8host_op_rate 145069 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15443503 # Simulator tick rate (ticks/s) 10host_mem_usage 252160 # Number of bytes of host memory used 11host_seconds 6.84 # Real time elapsed on the host 12sim_insts 992854 # Number of instructions simulated 13sim_ops 992854 # Number of ops (including micro ops) simulated | 7host_inst_rate 163449 # Simulator instruction rate (inst/s) 8host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17392605 # Simulator tick rate (ticks/s) 10host_mem_usage 309188 # Number of bytes of host memory used 11host_seconds 6.07 # Real time elapsed on the host 12sim_insts 991839 # Number of instructions simulated 13sim_ops 991839 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory | 22system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::total 42752 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory | 24system.physmem.bytes_read::total 42496 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::total 668 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 669 # Number of read requests accepted | 38system.physmem.num_reads::total 664 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 665 # Number of read requests accepted |
| 63system.physmem.writeReqs 0 # Number of write requests accepted | 63system.physmem.writeReqs 0 # Number of write requests accepted |
| 64system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue | 64system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue |
| 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 66system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM | 66system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM |
| 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 69system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side | 69system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side |
| 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts | 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts |
| 76system.physmem.perBankRdBursts::2 30 # Per bank write bursts | 76system.physmem.perBankRdBursts::2 27 # Per bank write bursts |
| 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts 79system.physmem.perBankRdBursts::5 28 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts | 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts 79system.physmem.perBankRdBursts::5 28 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts |
| 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts | 84system.physmem.perBankRdBursts::10 22 # Per bank write bursts |
| 85system.physmem.perBankRdBursts::11 13 # Per bank write bursts 86system.physmem.perBankRdBursts::12 65 # Per bank write bursts 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts 89system.physmem.perBankRdBursts::15 97 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 85system.physmem.perBankRdBursts::11 13 # Per bank write bursts 86system.physmem.perBankRdBursts::12 65 # Per bank write bursts 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts 89system.physmem.perBankRdBursts::15 97 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 108system.physmem.totGap 105668000 # Total gap between requests | 108system.physmem.totGap 105514000 # Total gap between requests |
| 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) | 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 115system.physmem.readPktSize::6 669 # Read request sizes (log2) | 115system.physmem.readPktSize::6 665 # Read request sizes (log2) |
| 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) | 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 123system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see |
| 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 219system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation 233system.physmem.totQLat 6392250 # Total ticks spent queuing 234system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst | 219system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation 233system.physmem.totQLat 6421750 # Total ticks spent queuing 234system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst |
| 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 238system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s |
| 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 241system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s | 241system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s |
| 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 244system.physmem.busUtil 3.16 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads | 244system.physmem.busUtil 3.15 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads |
| 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 247system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing | 247system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing |
| 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 249system.physmem.readRowHits 515 # Number of row buffer hits during reads | 249system.physmem.readRowHits 512 # Number of row buffer hits during reads |
| 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 251system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads | 251system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads |
| 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 253system.physmem.avgGap 157949.18 # Average gap between requests 254system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states 256system.physmem.memoryStateTime::REF 3380000 # Time in different power states 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem.memoryStateTime::ACT 52590250 # Time in different power states 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.physmem.actEnergy::0 695520 # Energy for activate commands per rank (pJ) 261system.physmem.actEnergy::1 355320 # Energy for activate commands per rank (pJ) 262system.physmem.preEnergy::0 379500 # Energy for precharge commands per rank (pJ) 263system.physmem.preEnergy::1 193875 # Energy for precharge commands per rank (pJ) 264system.physmem.readEnergy::0 2776800 # Energy for read commands per rank (pJ) 265system.physmem.readEnergy::1 2051400 # Energy for read commands per rank (pJ) 266system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 267system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 268system.physmem.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) 269system.physmem.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) 270system.physmem.actBackEnergy::0 36176760 # Energy for active background per rank (pJ) 271system.physmem.actBackEnergy::1 31269060 # Energy for active background per rank (pJ) 272system.physmem.preBackEnergy::0 29154750 # Energy for precharge background per rank (pJ) 273system.physmem.preBackEnergy::1 33459750 # Energy for precharge background per rank (pJ) 274system.physmem.totalEnergy::0 75794610 # Total energy per rank (pJ) 275system.physmem.totalEnergy::1 73940685 # Total energy per rank (pJ) 276system.physmem.averagePower::0 746.882897 # Core power per rank (mW) 277system.physmem.averagePower::1 728.614251 # Core power per rank (mW) 278system.membus.trans_dist::ReadReq 538 # Transaction distribution 279system.membus.trans_dist::ReadResp 537 # Transaction distribution 280system.membus.trans_dist::UpgradeReq 276 # Transaction distribution 281system.membus.trans_dist::UpgradeResp 78 # Transaction distribution 282system.membus.trans_dist::ReadExReq 177 # Transaction distribution 283system.membus.trans_dist::ReadExResp 131 # Transaction distribution 284system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes) 285system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes) 286system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) 287system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) 288system.membus.snoops 244 # Total snoops (count) 289system.membus.snoop_fanout::samples 991 # Request fanout histogram 290system.membus.snoop_fanout::mean 0 # Request fanout histogram 291system.membus.snoop_fanout::stdev 0 # Request fanout histogram 292system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 293system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram 294system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 295system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 296system.membus.snoop_fanout::min_value 0 # Request fanout histogram 297system.membus.snoop_fanout::max_value 0 # Request fanout histogram 298system.membus.snoop_fanout::total 991 # Request fanout histogram 299system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks) 300system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 301system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks) 302system.membus.respLayer1.utilization 6.0 # Layer utilization (%) 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.l2c.tags.replacements 0 # number of replacements 305system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use 306system.l2c.tags.total_refs 1667 # Total number of references to valid blocks. 307system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. 308system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks. 309system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.l2c.tags.occ_blocks::writebacks 0.793516 # Average occupied blocks per requestor 311system.l2c.tags.occ_blocks::cpu0.inst 289.763968 # Average occupied blocks per requestor 312system.l2c.tags.occ_blocks::cpu0.data 58.233930 # Average occupied blocks per requestor 313system.l2c.tags.occ_blocks::cpu1.inst 9.364536 # Average occupied blocks per requestor 314system.l2c.tags.occ_blocks::cpu1.data 0.722908 # Average occupied blocks per requestor 315system.l2c.tags.occ_blocks::cpu2.inst 57.054480 # Average occupied blocks per requestor 316system.l2c.tags.occ_blocks::cpu2.data 5.356180 # Average occupied blocks per requestor 317system.l2c.tags.occ_blocks::cpu3.inst 2.266531 # Average occupied blocks per requestor 318system.l2c.tags.occ_blocks::cpu3.data 0.685395 # Average occupied blocks per requestor 319system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 320system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy 321system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy 322system.l2c.tags.occ_percent::cpu1.inst 0.000143 # Average percentage of cache occupancy 323system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 324system.l2c.tags.occ_percent::cpu2.inst 0.000871 # Average percentage of cache occupancy 325system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy 326system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy 327system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy 328system.l2c.tags.occ_percent::total 0.006473 # Average percentage of cache occupancy 329system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id 330system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 331system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 332system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id 333system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id 334system.l2c.tags.tag_accesses 20109 # Number of tag accesses 335system.l2c.tags.data_accesses 20109 # Number of data accesses 336system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits 337system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 338system.l2c.ReadReq_hits::cpu1.inst 480 # number of ReadReq hits 339system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 340system.l2c.ReadReq_hits::cpu2.inst 413 # number of ReadReq hits 341system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 342system.l2c.ReadReq_hits::cpu3.inst 492 # number of ReadReq hits 343system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 344system.l2c.ReadReq_hits::total 1667 # number of ReadReq hits 345system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 346system.l2c.Writeback_hits::total 1 # number of Writeback hits 347system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 348system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 349system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits 350system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 351system.l2c.demand_hits::cpu1.inst 480 # number of demand (read+write) hits 352system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 353system.l2c.demand_hits::cpu2.inst 413 # number of demand (read+write) hits 354system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 355system.l2c.demand_hits::cpu3.inst 492 # number of demand (read+write) hits 356system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 357system.l2c.demand_hits::total 1667 # number of demand (read+write) hits 358system.l2c.overall_hits::cpu0.inst 250 # number of overall hits 359system.l2c.overall_hits::cpu0.data 5 # number of overall hits 360system.l2c.overall_hits::cpu1.inst 480 # number of overall hits 361system.l2c.overall_hits::cpu1.data 11 # number of overall hits 362system.l2c.overall_hits::cpu2.inst 413 # number of overall hits 363system.l2c.overall_hits::cpu2.data 5 # number of overall hits 364system.l2c.overall_hits::cpu3.inst 492 # number of overall hits 365system.l2c.overall_hits::cpu3.data 11 # number of overall hits 366system.l2c.overall_hits::total 1667 # number of overall hits 367system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses 368system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 369system.l2c.ReadReq_misses::cpu1.inst 17 # number of ReadReq misses 370system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 371system.l2c.ReadReq_misses::cpu2.inst 80 # number of ReadReq misses 372system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 373system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses 374system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 375system.l2c.ReadReq_misses::total 550 # number of ReadReq misses 376system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses 377system.l2c.UpgradeReq_misses::cpu1.data 17 # number of UpgradeReq misses 378system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses 379system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 380system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses 381system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 382system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 383system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 384system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 385system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 386system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses 387system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 388system.l2c.demand_misses::cpu1.inst 17 # number of demand (read+write) misses 389system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 390system.l2c.demand_misses::cpu2.inst 80 # number of demand (read+write) misses 391system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 392system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses 393system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 394system.l2c.demand_misses::total 681 # number of demand (read+write) misses 395system.l2c.overall_misses::cpu0.inst 363 # number of overall misses 396system.l2c.overall_misses::cpu0.data 168 # number of overall misses 397system.l2c.overall_misses::cpu1.inst 17 # number of overall misses 398system.l2c.overall_misses::cpu1.data 13 # number of overall misses 399system.l2c.overall_misses::cpu2.inst 80 # number of overall misses 400system.l2c.overall_misses::cpu2.data 20 # number of overall misses 401system.l2c.overall_misses::cpu3.inst 7 # number of overall misses 402system.l2c.overall_misses::cpu3.data 13 # number of overall misses 403system.l2c.overall_misses::total 681 # number of overall misses 404system.l2c.ReadReq_miss_latency::cpu0.inst 25064250 # number of ReadReq miss cycles 405system.l2c.ReadReq_miss_latency::cpu0.data 5642000 # number of ReadReq miss cycles 406system.l2c.ReadReq_miss_latency::cpu1.inst 1337250 # number of ReadReq miss cycles 407system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles 408system.l2c.ReadReq_miss_latency::cpu2.inst 5652250 # number of ReadReq miss cycles 409system.l2c.ReadReq_miss_latency::cpu2.data 765250 # number of ReadReq miss cycles 410system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles 411system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles 412system.l2c.ReadReq_miss_latency::total 39069000 # number of ReadReq miss cycles 413system.l2c.ReadExReq_miss_latency::cpu0.data 6921000 # number of ReadExReq miss cycles 414system.l2c.ReadExReq_miss_latency::cpu1.data 852750 # number of ReadExReq miss cycles 415system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles 416system.l2c.ReadExReq_miss_latency::cpu3.data 837000 # number of ReadExReq miss cycles 417system.l2c.ReadExReq_miss_latency::total 9658000 # number of ReadExReq miss cycles 418system.l2c.demand_miss_latency::cpu0.inst 25064250 # number of demand (read+write) miss cycles 419system.l2c.demand_miss_latency::cpu0.data 12563000 # number of demand (read+write) miss cycles 420system.l2c.demand_miss_latency::cpu1.inst 1337250 # number of demand (read+write) miss cycles 421system.l2c.demand_miss_latency::cpu1.data 927750 # number of demand (read+write) miss cycles 422system.l2c.demand_miss_latency::cpu2.inst 5652250 # number of demand (read+write) miss cycles 423system.l2c.demand_miss_latency::cpu2.data 1812500 # number of demand (read+write) miss cycles 424system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles 425system.l2c.demand_miss_latency::cpu3.data 912000 # number of demand (read+write) miss cycles 426system.l2c.demand_miss_latency::total 48727000 # number of demand (read+write) miss cycles 427system.l2c.overall_miss_latency::cpu0.inst 25064250 # number of overall miss cycles 428system.l2c.overall_miss_latency::cpu0.data 12563000 # number of overall miss cycles 429system.l2c.overall_miss_latency::cpu1.inst 1337250 # number of overall miss cycles 430system.l2c.overall_miss_latency::cpu1.data 927750 # number of overall miss cycles 431system.l2c.overall_miss_latency::cpu2.inst 5652250 # number of overall miss cycles 432system.l2c.overall_miss_latency::cpu2.data 1812500 # number of overall miss cycles 433system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles 434system.l2c.overall_miss_latency::cpu3.data 912000 # number of overall miss cycles 435system.l2c.overall_miss_latency::total 48727000 # number of overall miss cycles 436system.l2c.ReadReq_accesses::cpu0.inst 613 # number of ReadReq accesses(hits+misses) 437system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 438system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) 439system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 440system.l2c.ReadReq_accesses::cpu2.inst 493 # number of ReadReq accesses(hits+misses) 441system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 442system.l2c.ReadReq_accesses::cpu3.inst 499 # number of ReadReq accesses(hits+misses) 443system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 444system.l2c.ReadReq_accesses::total 2217 # number of ReadReq accesses(hits+misses) 445system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 446system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 447system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) 448system.l2c.UpgradeReq_accesses::cpu1.data 17 # number of UpgradeReq accesses(hits+misses) 449system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) 450system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 451system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 452system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 453system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 454system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 455system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 456system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 457system.l2c.demand_accesses::cpu0.inst 613 # number of demand (read+write) accesses 458system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 459system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses 460system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 461system.l2c.demand_accesses::cpu2.inst 493 # number of demand (read+write) accesses 462system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 463system.l2c.demand_accesses::cpu3.inst 499 # number of demand (read+write) accesses 464system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 465system.l2c.demand_accesses::total 2348 # number of demand (read+write) accesses 466system.l2c.overall_accesses::cpu0.inst 613 # number of overall (read+write) accesses 467system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 468system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses 469system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses 470system.l2c.overall_accesses::cpu2.inst 493 # number of overall (read+write) accesses 471system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 472system.l2c.overall_accesses::cpu3.inst 499 # number of overall (read+write) accesses 473system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 474system.l2c.overall_accesses::total 2348 # number of overall (read+write) accesses 475system.l2c.ReadReq_miss_rate::cpu0.inst 0.592170 # miss rate for ReadReq accesses 476system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 477system.l2c.ReadReq_miss_rate::cpu1.inst 0.034205 # miss rate for ReadReq accesses 478system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses 479system.l2c.ReadReq_miss_rate::cpu2.inst 0.162272 # miss rate for ReadReq accesses 480system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses 481system.l2c.ReadReq_miss_rate::cpu3.inst 0.014028 # miss rate for ReadReq accesses 482system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 483system.l2c.ReadReq_miss_rate::total 0.248083 # miss rate for ReadReq accesses 484system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses 485system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 486system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 487system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 488system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses 489system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 490system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 491system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 492system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 493system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 494system.l2c.demand_miss_rate::cpu0.inst 0.592170 # miss rate for demand accesses 495system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 496system.l2c.demand_miss_rate::cpu1.inst 0.034205 # miss rate for demand accesses 497system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses 498system.l2c.demand_miss_rate::cpu2.inst 0.162272 # miss rate for demand accesses 499system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses 500system.l2c.demand_miss_rate::cpu3.inst 0.014028 # miss rate for demand accesses 501system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 502system.l2c.demand_miss_rate::total 0.290034 # miss rate for demand accesses 503system.l2c.overall_miss_rate::cpu0.inst 0.592170 # miss rate for overall accesses 504system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 505system.l2c.overall_miss_rate::cpu1.inst 0.034205 # miss rate for overall accesses 506system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 507system.l2c.overall_miss_rate::cpu2.inst 0.162272 # miss rate for overall accesses 508system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 509system.l2c.overall_miss_rate::cpu3.inst 0.014028 # miss rate for overall accesses 510system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 511system.l2c.overall_miss_rate::total 0.290034 # miss rate for overall accesses 512system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69047.520661 # average ReadReq miss latency 513system.l2c.ReadReq_avg_miss_latency::cpu0.data 76243.243243 # average ReadReq miss latency 514system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78661.764706 # average ReadReq miss latency 515system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency 516system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70653.125000 # average ReadReq miss latency 517system.l2c.ReadReq_avg_miss_latency::cpu2.data 109321.428571 # average ReadReq miss latency 518system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65428.571429 # average ReadReq miss latency 519system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency 520system.l2c.ReadReq_avg_miss_latency::total 71034.545455 # average ReadReq miss latency 521system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73627.659574 # average ReadExReq miss latency 522system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71062.500000 # average ReadExReq miss latency 523system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency 524system.l2c.ReadExReq_avg_miss_latency::cpu3.data 69750 # average ReadExReq miss latency 525system.l2c.ReadExReq_avg_miss_latency::total 73725.190840 # average ReadExReq miss latency 526system.l2c.demand_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency 527system.l2c.demand_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency 528system.l2c.demand_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency 529system.l2c.demand_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency 530system.l2c.demand_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency 531system.l2c.demand_avg_miss_latency::cpu2.data 90625 # average overall miss latency 532system.l2c.demand_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency 533system.l2c.demand_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency 534system.l2c.demand_avg_miss_latency::total 71552.129222 # average overall miss latency 535system.l2c.overall_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency 536system.l2c.overall_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency 537system.l2c.overall_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency 538system.l2c.overall_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency 539system.l2c.overall_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency 540system.l2c.overall_avg_miss_latency::cpu2.data 90625 # average overall miss latency 541system.l2c.overall_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency 542system.l2c.overall_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency 543system.l2c.overall_avg_miss_latency::total 71552.129222 # average overall miss latency 544system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 545system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 546system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 547system.l2c.blocked::no_targets 0 # number of cycles access was blocked 548system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 549system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 550system.l2c.fast_writes 0 # number of fast writes performed 551system.l2c.cache_copies 0 # number of cache copies performed 552system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 553system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 554system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits 555system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits 556system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 557system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 558system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 559system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits 560system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits 561system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 562system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 563system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 564system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits 565system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits 566system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits 567system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses 568system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses 569system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses 570system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses 571system.l2c.ReadReq_mshr_misses::cpu2.inst 75 # number of ReadReq MSHR misses 572system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 573system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses 574system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 575system.l2c.ReadReq_mshr_misses::total 538 # number of ReadReq MSHR misses 576system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses 577system.l2c.UpgradeReq_mshr_misses::cpu1.data 17 # number of UpgradeReq MSHR misses 578system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses 579system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 580system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses 581system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 582system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 583system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 584system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 585system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 586system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses 587system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses 588system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses 589system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 590system.l2c.demand_mshr_misses::cpu2.inst 75 # number of demand (read+write) MSHR misses 591system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 592system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 593system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 594system.l2c.demand_mshr_misses::total 669 # number of demand (read+write) MSHR misses 595system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses 596system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 597system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses 598system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses 599system.l2c.overall_mshr_misses::cpu2.inst 75 # number of overall MSHR misses 600system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 601system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses 602system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 603system.l2c.overall_mshr_misses::total 669 # number of overall MSHR misses 604system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20478250 # number of ReadReq MSHR miss cycles 605system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4729000 # number of ReadReq MSHR miss cycles 606system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 985000 # number of ReadReq MSHR miss cycles 607system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles 608system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4446750 # number of ReadReq MSHR miss cycles 609system.l2c.ReadReq_mshr_miss_latency::cpu2.data 678750 # number of ReadReq MSHR miss cycles 610system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 236250 # number of ReadReq MSHR miss cycles 611system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles 612system.l2c.ReadReq_mshr_miss_latency::total 31679000 # number of ReadReq MSHR miss cycles 613system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles 614system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of UpgradeReq MSHR miss cycles 615system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles 616system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles 617system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles 618system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles 619system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701250 # number of ReadExReq MSHR miss cycles 620system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles 621system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 687000 # number of ReadExReq MSHR miss cycles 622system.l2c.ReadExReq_mshr_miss_latency::total 8038000 # number of ReadExReq MSHR miss cycles 623system.l2c.demand_mshr_miss_latency::cpu0.inst 20478250 # number of demand (read+write) MSHR miss cycles 624system.l2c.demand_mshr_miss_latency::cpu0.data 10490500 # number of demand (read+write) MSHR miss cycles 625system.l2c.demand_mshr_miss_latency::cpu1.inst 985000 # number of demand (read+write) MSHR miss cycles 626system.l2c.demand_mshr_miss_latency::cpu1.data 763750 # number of demand (read+write) MSHR miss cycles 627system.l2c.demand_mshr_miss_latency::cpu2.inst 4446750 # number of demand (read+write) MSHR miss cycles 628system.l2c.demand_mshr_miss_latency::cpu2.data 1567000 # number of demand (read+write) MSHR miss cycles 629system.l2c.demand_mshr_miss_latency::cpu3.inst 236250 # number of demand (read+write) MSHR miss cycles 630system.l2c.demand_mshr_miss_latency::cpu3.data 749500 # number of demand (read+write) MSHR miss cycles 631system.l2c.demand_mshr_miss_latency::total 39717000 # number of demand (read+write) MSHR miss cycles 632system.l2c.overall_mshr_miss_latency::cpu0.inst 20478250 # number of overall MSHR miss cycles 633system.l2c.overall_mshr_miss_latency::cpu0.data 10490500 # number of overall MSHR miss cycles 634system.l2c.overall_mshr_miss_latency::cpu1.inst 985000 # number of overall MSHR miss cycles 635system.l2c.overall_mshr_miss_latency::cpu1.data 763750 # number of overall MSHR miss cycles 636system.l2c.overall_mshr_miss_latency::cpu2.inst 4446750 # number of overall MSHR miss cycles 637system.l2c.overall_mshr_miss_latency::cpu2.data 1567000 # number of overall MSHR miss cycles 638system.l2c.overall_mshr_miss_latency::cpu3.inst 236250 # number of overall MSHR miss cycles 639system.l2c.overall_mshr_miss_latency::cpu3.data 749500 # number of overall MSHR miss cycles 640system.l2c.overall_mshr_miss_latency::total 39717000 # number of overall MSHR miss cycles 641system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for ReadReq accesses 642system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 643system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for ReadReq accesses 644system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 645system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for ReadReq accesses 646system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 647system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for ReadReq accesses 648system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 649system.l2c.ReadReq_mshr_miss_rate::total 0.242670 # mshr miss rate for ReadReq accesses 650system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses 651system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 652system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 653system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 654system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses 655system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 656system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 657system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 658system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 659system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 660system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for demand accesses 661system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 662system.l2c.demand_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for demand accesses 663system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 664system.l2c.demand_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for demand accesses 665system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 666system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for demand accesses 667system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 668system.l2c.demand_mshr_miss_rate::total 0.284923 # mshr miss rate for demand accesses 669system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses 670system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 671system.l2c.overall_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for overall accesses 672system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 673system.l2c.overall_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for overall accesses 674system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 675system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for overall accesses 676system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 677system.l2c.overall_mshr_miss_rate::total 0.284923 # mshr miss rate for overall accesses 678system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average ReadReq mshr miss latency 679system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63905.405405 # average ReadReq mshr miss latency 680system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average ReadReq mshr miss latency 681system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency 682system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59290 # average ReadReq mshr miss latency 683system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 96964.285714 # average ReadReq mshr miss latency 684system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency 685system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency 686system.l2c.ReadReq_avg_mshr_miss_latency::total 58882.899628 # average ReadReq mshr miss latency 687system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 688system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 689system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 690system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 691system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 692system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency 693system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 # average ReadExReq mshr miss latency 694system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency 695system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency 696system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency 697system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency 698system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency 699system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency 700system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency 701system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency 702system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency 703system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency 704system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency 705system.l2c.demand_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency 706system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency 707system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency 708system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency 709system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency 710system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency 711system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency 712system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency 713system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency 714system.l2c.overall_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency 715system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 716system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution 717system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution 718system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 719system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution 720system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution 721system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution 722system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution 723system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) 724system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) 725system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 726system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 727system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) 728system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes) 729system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes) 730system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) 731system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes) 732system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) 733system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 734system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) 735system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 736system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) 737system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 738system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes) 739system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 740system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes) 741system.toL2Bus.snoops 1022 # Total snoops (count) 742system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram 743system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 744system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 745system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 746system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 747system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 748system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 749system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 750system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 751system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 752system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 753system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram 754system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 755system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 756system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 757system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 758system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram 759system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks) 760system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) 761system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks) 762system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 763system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks) 764system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 765system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks) 766system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) 767system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks) 768system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) 769system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks) 770system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) 771system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks) 772system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 773system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks) 774system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) 775system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks) 776system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) 777system.cpu0.branchPred.lookups 81418 # Number of BP lookups 778system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted 779system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect 780system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups 781system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits | 253system.physmem.avgGap 158667.67 # Average gap between requests 254system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) 257system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 260system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) 263system.physmem_0.averagePower 738.913691 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states 265system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) 277system.physmem_1.averagePower 723.948851 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states 279system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 283system.cpu0.branchPred.lookups 81296 # Number of BP lookups 284system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted 285system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect 286system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups 287system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits |
| 782system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 783system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage 784system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. | 289system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage 290system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. |
| 785system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. | 291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. |
| 292system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 786system.cpu0.workload.num_syscalls 89 # Number of system calls | 293system.cpu0.workload.num_syscalls 89 # Number of system calls |
| 787system.cpu0.numCycles 211393 # number of cpu cycles simulated | 294system.cpu0.numCycles 211085 # number of cpu cycles simulated |
| 788system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 789system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 295system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 296system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 790system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss 791system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed 792system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered 793system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken 794system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked 795system.cpu0.fetch.SquashCycles 2675 # Number of cycles fetch has spent squashing | 297system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss 298system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed 299system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered 300system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken 301system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked 302system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing |
| 796system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 303system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 797system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps 798system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched 799system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed 800system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total) 801system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total) 802system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total) | 304system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps 305system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched 306system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed 307system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) 308system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) 309system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) |
| 803system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 310system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 804system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total) 805system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total) 806system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) 807system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total) 808system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total) 809system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total) 810system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) 811system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) 812system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) | 311system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) 312system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) |
| 813system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 814system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 815system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 320system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 322system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 816system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total) 817system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle 818system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle 819system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle 820system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked 821system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running 822system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking 823system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing 824system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode 825system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing 826system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle 827system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking 828system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst 829system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running 830system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking 831system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename | 323system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle 325system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle 326system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle 327system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked 328system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running 329system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking 330system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing 331system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode 332system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing 333system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle 334system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking 335system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst 336system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running 337system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking 338system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename |
| 832system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full | 339system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full |
| 833system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full | 340system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full |
| 834system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full | 341system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full |
| 835system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed 836system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made 837system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups 838system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed 839system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing 840system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed 841system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed 842system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer 843system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit. 844system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit. 845system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads. 846system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores. 847system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec) 848system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ 849system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued | 342system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed 343system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made 344system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups 345system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed 346system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing 347system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed 348system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed 349system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer 350system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. 351system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. 352system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. 353system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. 354system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) 355system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ 356system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued |
| 850system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued | 357system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued |
| 851system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling 852system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph 853system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed 854system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle 855system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle 856system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle | 358system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling 359system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph 360system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed 361system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle 362system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle 363system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle |
| 857system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 364system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 858system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle 859system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle 860system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle 861system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle 862system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle 863system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle 864system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle 865system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle 866system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle | 365system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle 367system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle |
| 867system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 868system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 869system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 374system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 375system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 376system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 870system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle | 377system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle |
| 871system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 378system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 872system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available 873system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available 874system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available 875system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available 876system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available 877system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available 878system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available 879system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available 880system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available 881system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available 882system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available 883system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available 884system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available 885system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available 886system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available 887system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available 888system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available 889system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available 890system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available 891system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available 892system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available 893system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available 894system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available 895system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available 896system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available 897system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available 898system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available 899system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available 900system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available 901system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available 902system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available | 379system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available 380system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available 381system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available 382system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available 383system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available 384system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available 388system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available 389system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available 408system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available 409system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available |
| 903system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 904system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 905system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 410system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 906system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued 907system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued 908system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued 909system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued 910system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued 911system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued 912system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued 913system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued 914system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued 915system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued 916system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued 917system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued 918system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued 919system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued 920system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued 921system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued 922system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued 923system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued 924system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued 925system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued 926system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued 927system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued 928system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued 929system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued 930system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued 931system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued 932system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued 933system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued 934system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued 935system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued 936system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued | 413system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued 414system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued 415system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued 416system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued 417system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued 418system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued 422system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued 423system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued 442system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued 443system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued |
| 937system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 938system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 444system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 445system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 939system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued 940system.cpu0.iq.rate 1.828145 # Inst issue rate 941system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested 942system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst) 943system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads 944system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes 945system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses | 446system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued 447system.cpu0.iq.rate 1.826459 # Inst issue rate 448system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested 449system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) 450system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads 451system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes 452system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses |
| 946system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 947system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 948system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 453system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 454system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 455system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 949system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses | 456system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses |
| 950system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 457system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 951system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores | 458system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores |
| 952system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 459system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 953system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed | 460system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed |
| 954system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 955system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations | 461system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 462system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations |
| 956system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed | 463system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed |
| 957system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 958system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 959system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 960system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked 961system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 464system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 465system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 466system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 467system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked 468system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 962system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing 963system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking 964system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking 965system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ 966system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch 967system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions 968system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions 969system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions 970system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall | 469system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing 470system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking 471system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking 472system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ 473system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch 474system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions 475system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions 476system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions 477system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall |
| 971system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 972system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations | 478system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 479system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations |
| 973system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly 974system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly 975system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute 976system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions 977system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed 978system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute | 480system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly 481system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly 482system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute 483system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions 484system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed 485system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute |
| 979system.cpu0.iew.exec_swp 0 # number of swp insts executed | 486system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 980system.cpu0.iew.exec_nop 72872 # number of nop insts executed 981system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed 982system.cpu0.iew.exec_branches 76458 # Number of branches executed 983system.cpu0.iew.exec_stores 74381 # Number of stores executed 984system.cpu0.iew.exec_rate 1.823357 # Inst execution rate 985system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit 986system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back 987system.cpu0.iew.wb_producers 228096 # num instructions producing a value 988system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value | 487system.cpu0.iew.exec_nop 72677 # number of nop insts executed 488system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed 489system.cpu0.iew.exec_branches 76264 # Number of branches executed 490system.cpu0.iew.exec_stores 74195 # Number of stores executed 491system.cpu0.iew.exec_rate 1.821660 # Inst execution rate 492system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit 493system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back 494system.cpu0.iew.wb_producers 227520 # num instructions producing a value 495system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value |
| 989system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 496system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 990system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle 991system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back | 497system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle 498system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back |
| 992system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 499system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 993system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit | 500system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit |
| 994system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards | 501system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards |
| 995system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted 996system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle 997system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle 998system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle | 502system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted 503system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle 504system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle 505system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle |
| 999system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 506system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1000system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle 1001system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle 1002system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle 1003system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle 1004system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle 1005system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle | 507system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle 509system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle |
| 1006system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle | 513system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle |
| 1007system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle 1008system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle | 514system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle |
| 1009system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1010system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1011system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 516system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 517system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1012system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle 1013system.cpu0.commit.committedInsts 449934 # Number of instructions committed 1014system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed | 519system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle 520system.cpu0.commit.committedInsts 448740 # Number of instructions committed 521system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed |
| 1015system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 522system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1016system.cpu0.commit.refs 219682 # Number of memory references committed 1017system.cpu0.commit.loads 146117 # Number of loads committed | 523system.cpu0.commit.refs 219085 # Number of memory references committed 524system.cpu0.commit.loads 145719 # Number of loads committed |
| 1018system.cpu0.commit.membars 84 # Number of memory barriers committed | 525system.cpu0.commit.membars 84 # Number of memory barriers committed |
| 1019system.cpu0.commit.branches 75452 # Number of branches committed | 526system.cpu0.commit.branches 75253 # Number of branches committed |
| 1020system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. | 527system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1021system.cpu0.commit.int_insts 303386 # Number of committed integer instructions. | 528system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. |
| 1022system.cpu0.commit.function_calls 223 # Number of function calls committed. | 529system.cpu0.commit.function_calls 223 # Number of function calls committed. |
| 1023system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction 1024system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction | 530system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction 531system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction |
| 1025system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction 1026system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction 1027system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction 1028system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction 1029system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction 1030system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction 1031system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction 1032system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction --- 12 unchanged lines hidden (view full) --- 1045system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction 1046system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction 1047system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction 1048system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction 1049system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction 1050system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction 1051system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction 1052system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction | 532system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction 533system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction 534system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction 535system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction 536system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction 537system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction 538system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction 539system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction --- 12 unchanged lines hidden (view full) --- 552system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction 554system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction 555system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction 556system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction 557system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction 558system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction 559system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction |
| 1053system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction 1054system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction | 560system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction 561system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction |
| 1055system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1056system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 562system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 563system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1057system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction 1058system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached | 564system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction 565system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached |
| 1059system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 566system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1060system.cpu0.rob.rob_reads 646710 # The number of ROB reads 1061system.cpu0.rob.rob_writes 929757 # The number of ROB writes | 567system.cpu0.rob.rob_reads 645314 # The number of ROB reads 568system.cpu0.rob.rob_writes 927635 # The number of ROB writes |
| 1062system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself | 569system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 1063system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling 1064system.cpu0.committedInsts 377666 # Number of Instructions Simulated 1065system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated 1066system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction 1067system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads 1068system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle 1069system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads 1070system.cpu0.int_regfile_reads 689346 # number of integer regfile reads 1071system.cpu0.int_regfile_writes 310987 # number of integer regfile writes | 570system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling 571system.cpu0.committedInsts 376671 # Number of Instructions Simulated 572system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated 573system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction 574system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads 575system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle 576system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads 577system.cpu0.int_regfile_reads 687652 # number of integer regfile reads 578system.cpu0.int_regfile_writes 310240 # number of integer regfile writes |
| 1072system.cpu0.fp_regfile_reads 192 # number of floating regfile reads | 579system.cpu0.fp_regfile_reads 192 # number of floating regfile reads |
| 1073system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads | 580system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads |
| 1074system.cpu0.misc_regfile_writes 564 # number of misc regfile writes | 581system.cpu0.misc_regfile_writes 564 # number of misc regfile writes |
| 1075system.cpu0.icache.tags.replacements 322 # number of replacements 1076system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use 1077system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. 1078system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. 1079system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. 1080system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1081system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor 1082system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy 1083system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy 1084system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 1085system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1086system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1087system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 1088system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id 1089system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses 1090system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses 1091system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits 1092system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits 1093system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits 1094system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits 1095system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits 1096system.cpu0.icache.overall_hits::total 6326 # number of overall hits 1097system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses 1098system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses 1099system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses 1100system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses 1101system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses 1102system.cpu0.icache.overall_misses::total 797 # number of overall misses 1103system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles 1104system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles 1105system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles 1106system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles 1107system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles 1108system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles 1109system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) 1110system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) 1111system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses 1112system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses 1113system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses 1114system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses 1115system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses 1116system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses 1117system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses 1118system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses 1119system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses 1120system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses 1121system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency 1122system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency 1123system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency 1124system.cpu0.icache.demand_avg_miss_latency::total 46034.813049 # average overall miss latency 1125system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency 1126system.cpu0.icache.overall_avg_miss_latency::total 46034.813049 # average overall miss latency 1127system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked 1128system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1129system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1130system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1131system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked 1132system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1133system.cpu0.icache.fast_writes 0 # number of fast writes performed 1134system.cpu0.icache.cache_copies 0 # number of cache copies performed 1135system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits 1136system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits 1137system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits 1138system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits 1139system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits 1140system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits 1141system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses 1142system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses 1143system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses 1144system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses 1145system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses 1146system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses 1147system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28185001 # number of ReadReq MSHR miss cycles 1148system.cpu0.icache.ReadReq_mshr_miss_latency::total 28185001 # number of ReadReq MSHR miss cycles 1149system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28185001 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.icache.demand_mshr_miss_latency::total 28185001 # number of demand (read+write) MSHR miss cycles 1151system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28185001 # number of overall MSHR miss cycles 1152system.cpu0.icache.overall_mshr_miss_latency::total 28185001 # number of overall MSHR miss cycles 1153system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses 1154system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses 1155system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses 1156system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses 1157system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses 1158system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses 1159system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average ReadReq mshr miss latency 1160system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45978.794454 # average ReadReq mshr miss latency 1161system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency 1162system.cpu0.icache.demand_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency 1163system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency 1164system.cpu0.icache.overall_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency 1165system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1166system.cpu0.dcache.tags.replacements 2 # number of replacements | 582system.cpu0.dcache.tags.replacements 2 # number of replacements |
| 1167system.cpu0.dcache.tags.tagsinuse 141.516453 # Cycle average of tags in use 1168system.cpu0.dcache.tags.total_refs 148253 # Total number of references to valid blocks. | 583system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use 584system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. |
| 1169system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. | 585system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. |
| 1170system.cpu0.dcache.tags.avg_refs 872.076471 # Average number of references to valid blocks. | 586system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. |
| 1171system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 587system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1172system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.516453 # Average occupied blocks per requestor 1173system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276399 # Average percentage of cache occupancy 1174system.cpu0.dcache.tags.occ_percent::total 0.276399 # Average percentage of cache occupancy | 588system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor 589system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy 590system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy |
| 1175system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1176system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id | 591system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 592system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id |
| 1177system.cpu0.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 1178system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id | 593system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 594system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id |
| 1179system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id | 595system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id |
| 1180system.cpu0.dcache.tags.tag_accesses 597940 # Number of tag accesses 1181system.cpu0.dcache.tags.data_accesses 597940 # Number of data accesses 1182system.cpu0.dcache.ReadReq_hits::cpu0.data 75362 # number of ReadReq hits 1183system.cpu0.dcache.ReadReq_hits::total 75362 # number of ReadReq hits 1184system.cpu0.dcache.WriteReq_hits::cpu0.data 72979 # number of WriteReq hits 1185system.cpu0.dcache.WriteReq_hits::total 72979 # number of WriteReq hits | 596system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses 597system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses 598system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits 599system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits 600system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits 601system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits |
| 1186system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits 1187system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits | 602system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits 603system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits |
| 1188system.cpu0.dcache.demand_hits::cpu0.data 148341 # number of demand (read+write) hits 1189system.cpu0.dcache.demand_hits::total 148341 # number of demand (read+write) hits 1190system.cpu0.dcache.overall_hits::cpu0.data 148341 # number of overall hits 1191system.cpu0.dcache.overall_hits::total 148341 # number of overall hits 1192system.cpu0.dcache.ReadReq_misses::cpu0.data 480 # number of ReadReq misses 1193system.cpu0.dcache.ReadReq_misses::total 480 # number of ReadReq misses | 604system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits 605system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits 606system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits 607system.cpu0.dcache.overall_hits::total 147973 # number of overall hits 608system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses 609system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses |
| 1194system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses 1195system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses 1196system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses 1197system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses | 610system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses 611system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses 612system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses 613system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses |
| 1198system.cpu0.dcache.demand_misses::cpu0.data 1024 # number of demand (read+write) misses 1199system.cpu0.dcache.demand_misses::total 1024 # number of demand (read+write) misses 1200system.cpu0.dcache.overall_misses::cpu0.data 1024 # number of overall misses 1201system.cpu0.dcache.overall_misses::total 1024 # number of overall misses 1202system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15203420 # number of ReadReq miss cycles 1203system.cpu0.dcache.ReadReq_miss_latency::total 15203420 # number of ReadReq miss cycles 1204system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32866263 # number of WriteReq miss cycles 1205system.cpu0.dcache.WriteReq_miss_latency::total 32866263 # number of WriteReq miss cycles 1206system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles 1207system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles 1208system.cpu0.dcache.demand_miss_latency::cpu0.data 48069683 # number of demand (read+write) miss cycles 1209system.cpu0.dcache.demand_miss_latency::total 48069683 # number of demand (read+write) miss cycles 1210system.cpu0.dcache.overall_miss_latency::cpu0.data 48069683 # number of overall miss cycles 1211system.cpu0.dcache.overall_miss_latency::total 48069683 # number of overall miss cycles 1212system.cpu0.dcache.ReadReq_accesses::cpu0.data 75842 # number of ReadReq accesses(hits+misses) 1213system.cpu0.dcache.ReadReq_accesses::total 75842 # number of ReadReq accesses(hits+misses) 1214system.cpu0.dcache.WriteReq_accesses::cpu0.data 73523 # number of WriteReq accesses(hits+misses) 1215system.cpu0.dcache.WriteReq_accesses::total 73523 # number of WriteReq accesses(hits+misses) | 614system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses 615system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses 616system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses 617system.cpu0.dcache.overall_misses::total 1026 # number of overall misses 618system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles 619system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles 620system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles 621system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles 622system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles 623system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles 624system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles 625system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles 626system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles 627system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles 628system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) 629system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) 630system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) 631system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) |
| 1216system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1217system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) | 632system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 633system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) |
| 1218system.cpu0.dcache.demand_accesses::cpu0.data 149365 # number of demand (read+write) accesses 1219system.cpu0.dcache.demand_accesses::total 149365 # number of demand (read+write) accesses 1220system.cpu0.dcache.overall_accesses::cpu0.data 149365 # number of overall (read+write) accesses 1221system.cpu0.dcache.overall_accesses::total 149365 # number of overall (read+write) accesses 1222system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006329 # miss rate for ReadReq accesses 1223system.cpu0.dcache.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses 1224system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007399 # miss rate for WriteReq accesses 1225system.cpu0.dcache.WriteReq_miss_rate::total 0.007399 # miss rate for WriteReq accesses | 634system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses 635system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses 636system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses 637system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses 638system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses 639system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses 640system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses 641system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses |
| 1226system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses 1227system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses | 642system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses 643system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses |
| 1228system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006856 # miss rate for demand accesses 1229system.cpu0.dcache.demand_miss_rate::total 0.006856 # miss rate for demand accesses 1230system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006856 # miss rate for overall accesses 1231system.cpu0.dcache.overall_miss_rate::total 0.006856 # miss rate for overall accesses 1232system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31673.791667 # average ReadReq miss latency 1233system.cpu0.dcache.ReadReq_avg_miss_latency::total 31673.791667 # average ReadReq miss latency 1234system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60415.924632 # average WriteReq miss latency 1235system.cpu0.dcache.WriteReq_avg_miss_latency::total 60415.924632 # average WriteReq miss latency 1236system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency 1237system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency 1238system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency 1239system.cpu0.dcache.demand_avg_miss_latency::total 46943.049805 # average overall miss latency 1240system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency 1241system.cpu0.dcache.overall_avg_miss_latency::total 46943.049805 # average overall miss latency | 644system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses 645system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses 646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses 647system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses 648system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency 649system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency 650system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency 651system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency 652system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency 653system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency 654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency 655system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency 656system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency 657system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency |
| 1242system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked 1243system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1244system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 1245system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1246system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked 1247system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1248system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1249system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1250system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1251system.cpu0.dcache.writebacks::total 1 # number of writebacks | 658system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked 659system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 660system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 661system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 662system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked 663system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 664system.cpu0.dcache.fast_writes 0 # number of fast writes performed 665system.cpu0.dcache.cache_copies 0 # number of cache copies performed 666system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 667system.cpu0.dcache.writebacks::total 1 # number of writebacks |
| 1252system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 298 # number of ReadReq MSHR hits 1253system.cpu0.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits | 668system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits 669system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits |
| 1254system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits 1255system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits | 670system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits 671system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits |
| 1256system.cpu0.dcache.demand_mshr_hits::cpu0.data 663 # number of demand (read+write) MSHR hits 1257system.cpu0.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits 1258system.cpu0.dcache.overall_mshr_hits::cpu0.data 663 # number of overall MSHR hits 1259system.cpu0.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits 1260system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses 1261system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses | 672system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits 673system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits 674system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits 675system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits 676system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses 677system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses |
| 1262system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses 1263system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses 1264system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses 1265system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses | 678system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses 679system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses 680system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses 681system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses |
| 1266system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses 1267system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 1268system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses 1269system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses 1270system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6258507 # number of ReadReq MSHR miss cycles 1271system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6258507 # number of ReadReq MSHR miss cycles 1272system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7387727 # number of WriteReq MSHR miss cycles 1273system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7387727 # number of WriteReq MSHR miss cycles 1274system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles 1275system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles 1276system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13646234 # number of demand (read+write) MSHR miss cycles 1277system.cpu0.dcache.demand_mshr_miss_latency::total 13646234 # number of demand (read+write) MSHR miss cycles 1278system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13646234 # number of overall MSHR miss cycles 1279system.cpu0.dcache.overall_mshr_miss_latency::total 13646234 # number of overall MSHR miss cycles 1280system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for ReadReq accesses 1281system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002400 # mshr miss rate for ReadReq accesses 1282system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002435 # mshr miss rate for WriteReq accesses 1283system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002435 # mshr miss rate for WriteReq accesses | 682system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses 683system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 685system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses 686system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles 687system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles 688system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles 689system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles 690system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles 691system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles 692system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles 693system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles 694system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles 695system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles 696system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses 697system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses 698system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses 699system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses |
| 1284system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses 1285system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses | 700system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses 701system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses |
| 1286system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for demand accesses 1287system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses 1288system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses 1289system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses 1290system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency 1291system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency 1292system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency 1293system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency 1294system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency 1295system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency 1296system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency 1297system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency 1298system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency 1299system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency | 702system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses 703system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses 704system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses 705system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses 706system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency 707system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency 708system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency 709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency 710system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency 711system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency 712system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency 713system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency 714system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency 715system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency |
| 1300system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 716system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1301system.cpu1.branchPred.lookups 52620 # Number of BP lookups 1302system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted 1303system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect 1304system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups 1305system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits | 717system.cpu0.icache.tags.replacements 319 # number of replacements 718system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use 719system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. 720system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. 721system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. 722system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 723system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor 724system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy 725system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy 726system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id 727system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 728system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 729system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 730system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id 731system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses 732system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses 733system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits 734system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits 735system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits 736system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits 737system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits 738system.cpu0.icache.overall_hits::total 6347 # number of overall hits 739system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses 740system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses 741system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses 742system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses 743system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses 744system.cpu0.icache.overall_misses::total 792 # number of overall misses 745system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles 746system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles 747system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles 748system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles 749system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles 750system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles 751system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) 753system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses 754system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses 755system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses 756system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses 757system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses 758system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses 759system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses 760system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses 761system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses 762system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses 763system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency 764system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency 765system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency 766system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency 768system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency 769system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu0.icache.fast_writes 0 # number of fast writes performed 776system.cpu0.icache.cache_copies 0 # number of cache copies performed 777system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits 778system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits 779system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits 780system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits 781system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits 782system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits 783system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses 784system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses 785system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses 786system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses 787system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses 788system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses 789system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles 790system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles 795system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses 796system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses 797system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses 798system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses 799system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses 800system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses 801system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency 802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency 803system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency 804system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency 805system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency 806system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency 807system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu1.branchPred.lookups 48230 # Number of BP lookups 809system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted 810system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect 811system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups 812system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits |
| 1306system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 813system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1307system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage 1308system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. | 814system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage 815system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. |
| 1309system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 816system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 1310system.cpu1.numCycles 161023 # number of cpu cycles simulated | 817system.cpu1.numCycles 160735 # number of cpu cycles simulated |
| 1311system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1312system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 818system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 819system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1313system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss 1314system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed 1315system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered 1316system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken 1317system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked 1318system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing | 820system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss 821system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed 822system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered 823system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken 824system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked 825system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing |
| 1319system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1320system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from | 826system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 827system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from |
| 1321system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps 1322system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched 1323system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed 1324system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total) 1325system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total) 1326system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total) | 828system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps 829system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched 830system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed 831system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) 832system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) 833system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) |
| 1327system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 834system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1328system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total) 1329system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total) 1330system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total) 1331system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total) 1332system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total) 1333system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total) 1334system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total) 1335system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total) 1336system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total) | 835system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) 836system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) 837system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) |
| 1337system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1338system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1339system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 844system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 846system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1340system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total) 1341system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle 1342system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle 1343system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle 1344system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked 1345system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running 1346system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking 1347system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing 1348system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode 1349system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing 1350system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle 1351system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking 1352system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst 1353system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running 1354system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking 1355system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename 1356system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full 1357system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full | 847system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle 849system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle 850system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle 851system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked 852system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running 853system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking 854system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing 855system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode 856system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing 857system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle 858system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking 859system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst 860system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running 861system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking 862system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename 863system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full 864system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full |
| 1358system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers | 865system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers |
| 1359system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed 1360system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made 1361system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups 1362system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed 1363system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing 1364system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed 1365system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed 1366system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer 1367system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit. 1368system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit. 1369system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads. 1370system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores. 1371system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec) 1372system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ 1373system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued 1374system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued 1375system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling 1376system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph 1377system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed 1378system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle 1379system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle 1380system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle | 866system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed 867system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made 868system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups 869system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed 870system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing 871system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed 872system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed 873system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer 874system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. 875system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. 876system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. 877system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. 878system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) 879system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ 880system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued 881system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 882system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling 883system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph 884system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed 885system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle 886system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle 887system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle |
| 1381system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 888system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1382system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle 1383system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle 1384system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle 1385system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle 1386system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle 1387system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle 1388system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle 1389system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle 1390system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle | 889system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle 890system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle 891system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle |
| 1391system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1392system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1393system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 898system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 900system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1394system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle | 901system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle |
| 1395system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 902system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1396system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available 1397system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available 1414system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available 1416system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available 1417system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available 1418system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available 1419system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available 1420system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available 1421system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available 1422system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available 1423system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available 1424system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available 1425system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available 1426system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available | 903system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available 904system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available 905system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available 906system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available 907system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available 908system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available 909system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available 910system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available 912system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available 913system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available 932system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available 933system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available |
| 1427system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1428system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1429system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 934system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 935system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 936system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1430system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued 1431system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued 1432system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued 1433system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued 1434system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued 1435system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued 1436system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued 1437system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued 1438system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued 1439system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued 1440system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued 1446system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued 1447system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued 1448system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued 1449system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued 1450system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued 1451system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued 1452system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued 1453system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued 1454system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued 1455system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued 1456system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued 1457system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued 1458system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued 1459system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued 1460system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued | 937system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued 938system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued 939system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued 940system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued 941system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued 942system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued 943system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued 944system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued 946system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued 947system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued 966system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued 967system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued |
| 1461system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1462system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 968system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 969system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1463system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued 1464system.cpu1.iq.rate 1.413134 # Inst issue rate 1465system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested 1466system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst) 1467system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads 1468system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes 1469system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses | 970system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued 971system.cpu1.iq.rate 1.263247 # Inst issue rate 972system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested 973system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) 974system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads 975system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes 976system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses |
| 1470system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1471system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1472system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 977system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 978system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 979system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1473system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses | 980system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses |
| 1474system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 981system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1475system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores | 982system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores |
| 1476system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 983system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1477system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed | 984system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed |
| 1478system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 985system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 1479system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 1480system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed | 986system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 987system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed |
| 1481system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1482system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1483system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1484system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1485system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 988system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 989system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 990system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 991system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 992system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1486system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing 1487system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking 1488system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking 1489system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ 1490system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch 1491system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions 1492system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions 1493system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions 1494system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall | 993system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing 994system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking 995system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking 996system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ 997system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch 998system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions 999system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions 1000system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions 1001system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall |
| 1495system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1002system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 1496system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations 1497system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly 1498system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly 1499system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute 1500system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions 1501system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed 1502system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute | 1003system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations 1004system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1005system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly 1006system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute 1007system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions 1008system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed 1009system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute |
| 1503system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1010system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1504system.cpu1.iew.exec_nop 37236 # number of nop insts executed 1505system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed 1506system.cpu1.iew.exec_branches 46633 # Number of branches executed 1507system.cpu1.iew.exec_stores 35145 # Number of stores executed 1508system.cpu1.iew.exec_rate 1.406060 # Inst execution rate 1509system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit 1510system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back 1511system.cpu1.iew.wb_producers 127804 # num instructions producing a value 1512system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value | 1011system.cpu1.iew.exec_nop 32947 # number of nop insts executed 1012system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed 1013system.cpu1.iew.exec_branches 42219 # Number of branches executed 1014system.cpu1.iew.exec_stores 29534 # Number of stores executed 1015system.cpu1.iew.exec_rate 1.256422 # Inst execution rate 1016system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit 1017system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back 1018system.cpu1.iew.wb_producers 112178 # num instructions producing a value 1019system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value |
| 1513system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1020system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1514system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle 1515system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back | 1021system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle 1022system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back |
| 1516system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1023system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1517system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit 1518system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards 1519system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted 1520system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle 1521system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle 1522system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle | 1024system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit 1025system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards 1026system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted 1027system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle 1028system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle 1029system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle |
| 1523system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1030system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1524system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle 1525system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle 1526system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle 1527system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle 1528system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle 1529system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle 1530system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle 1531system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle 1532system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle | 1031system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle 1032system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle 1033system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle |
| 1533system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1534system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1535system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1040system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1042system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1536system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle 1537system.cpu1.commit.committedInsts 255365 # Number of instructions committed 1538system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed | 1043system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle 1044system.cpu1.commit.committedInsts 226660 # Number of instructions committed 1045system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed |
| 1539system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1046system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1540system.cpu1.commit.refs 107755 # Number of memory references committed 1541system.cpu1.commit.loads 73429 # Number of loads committed 1542system.cpu1.commit.membars 5300 # Number of memory barriers committed 1543system.cpu1.commit.branches 45589 # Number of branches committed | 1047system.cpu1.commit.refs 92171 # Number of memory references committed 1048system.cpu1.commit.loads 63450 # Number of loads committed 1049system.cpu1.commit.membars 6533 # Number of memory barriers committed 1050system.cpu1.commit.branches 41215 # Number of branches committed |
| 1544system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. | 1051system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. |
| 1545system.cpu1.commit.int_insts 175463 # Number of committed integer instructions. | 1052system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. |
| 1546system.cpu1.commit.function_calls 322 # Number of function calls committed. | 1053system.cpu1.commit.function_calls 322 # Number of function calls committed. |
| 1547system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction 1548system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction 1549system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction 1550system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction 1551system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction 1552system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction 1553system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction 1554system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction 1555system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction 1556system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction 1557system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction 1558system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction 1559system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction 1560system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction 1561system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction 1562system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction 1563system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction 1564system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction 1565system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction 1566system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction 1567system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction 1568system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction 1569system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction 1570system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction 1571system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction 1572system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction 1573system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction 1574system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction 1575system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction 1576system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction 1577system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction 1578system.cpu1.commit.op_class_0::MemWrite 34326 13.44% 100.00% # Class of committed instruction | 1054system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction 1055system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction 1056system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction 1057system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction 1058system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction 1059system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction 1060system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction 1061system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction 1062system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction 1063system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction 1064system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction 1065system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction 1066system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction 1077system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction 1078system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction 1079system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction 1080system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction 1081system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction 1082system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction 1083system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction 1084system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction 1085system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction |
| 1579system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1580system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1086system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1087system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1581system.cpu1.commit.op_class_0::total 255365 # Class of committed instruction 1582system.cpu1.commit.bw_lim_events 1279 # number cycles where commit BW limit reached | 1088system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction 1089system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached |
| 1583system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1090system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1584system.cpu1.rob.rob_reads 424317 # The number of ROB reads 1585system.cpu1.rob.rob_writes 541540 # The number of ROB writes 1586system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself 1587system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling 1588system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1589system.cpu1.committedInsts 213689 # Number of Instructions Simulated 1590system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated 1591system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction 1592system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads 1593system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle 1594system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads 1595system.cpu1.int_regfile_reads 390200 # number of integer regfile reads 1596system.cpu1.int_regfile_writes 182656 # number of integer regfile writes | 1091system.cpu1.rob.rob_reads 395483 # The number of ROB reads 1092system.cpu1.rob.rob_writes 484550 # The number of ROB writes 1093system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 1094system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling 1095system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1096system.cpu1.committedInsts 188125 # Number of Instructions Simulated 1097system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated 1098system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction 1099system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads 1100system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle 1101system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads 1102system.cpu1.int_regfile_reads 343348 # number of integer regfile reads 1103system.cpu1.int_regfile_writes 161358 # number of integer regfile writes |
| 1597system.cpu1.fp_regfile_writes 64 # number of floating regfile writes | 1104system.cpu1.fp_regfile_writes 64 # number of floating regfile writes |
| 1598system.cpu1.misc_regfile_reads 111763 # number of misc regfile reads | 1105system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads |
| 1599system.cpu1.misc_regfile_writes 648 # number of misc regfile writes | 1106system.cpu1.misc_regfile_writes 648 # number of misc regfile writes |
| 1600system.cpu1.icache.tags.replacements 388 # number of replacements 1601system.cpu1.icache.tags.tagsinuse 78.707719 # Cycle average of tags in use 1602system.cpu1.icache.tags.total_refs 21821 # Total number of references to valid blocks. 1603system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. 1604system.cpu1.icache.tags.avg_refs 43.905433 # Average number of references to valid blocks. 1605system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1606system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.707719 # Average occupied blocks per requestor 1607system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153726 # Average percentage of cache occupancy 1608system.cpu1.icache.tags.occ_percent::total 0.153726 # Average percentage of cache occupancy 1609system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id 1610system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1611system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 1612system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id 1613system.cpu1.icache.tags.tag_accesses 22877 # Number of tag accesses 1614system.cpu1.icache.tags.data_accesses 22877 # Number of data accesses 1615system.cpu1.icache.ReadReq_hits::cpu1.inst 21821 # number of ReadReq hits 1616system.cpu1.icache.ReadReq_hits::total 21821 # number of ReadReq hits 1617system.cpu1.icache.demand_hits::cpu1.inst 21821 # number of demand (read+write) hits 1618system.cpu1.icache.demand_hits::total 21821 # number of demand (read+write) hits 1619system.cpu1.icache.overall_hits::cpu1.inst 21821 # number of overall hits 1620system.cpu1.icache.overall_hits::total 21821 # number of overall hits 1621system.cpu1.icache.ReadReq_misses::cpu1.inst 559 # number of ReadReq misses 1622system.cpu1.icache.ReadReq_misses::total 559 # number of ReadReq misses 1623system.cpu1.icache.demand_misses::cpu1.inst 559 # number of demand (read+write) misses 1624system.cpu1.icache.demand_misses::total 559 # number of demand (read+write) misses 1625system.cpu1.icache.overall_misses::cpu1.inst 559 # number of overall misses 1626system.cpu1.icache.overall_misses::total 559 # number of overall misses 1627system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8425746 # number of ReadReq miss cycles 1628system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles 1629system.cpu1.icache.demand_miss_latency::cpu1.inst 8425746 # number of demand (read+write) miss cycles 1630system.cpu1.icache.demand_miss_latency::total 8425746 # number of demand (read+write) miss cycles 1631system.cpu1.icache.overall_miss_latency::cpu1.inst 8425746 # number of overall miss cycles 1632system.cpu1.icache.overall_miss_latency::total 8425746 # number of overall miss cycles 1633system.cpu1.icache.ReadReq_accesses::cpu1.inst 22380 # number of ReadReq accesses(hits+misses) 1634system.cpu1.icache.ReadReq_accesses::total 22380 # number of ReadReq accesses(hits+misses) 1635system.cpu1.icache.demand_accesses::cpu1.inst 22380 # number of demand (read+write) accesses 1636system.cpu1.icache.demand_accesses::total 22380 # number of demand (read+write) accesses 1637system.cpu1.icache.overall_accesses::cpu1.inst 22380 # number of overall (read+write) accesses 1638system.cpu1.icache.overall_accesses::total 22380 # number of overall (read+write) accesses 1639system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024978 # miss rate for ReadReq accesses 1640system.cpu1.icache.ReadReq_miss_rate::total 0.024978 # miss rate for ReadReq accesses 1641system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024978 # miss rate for demand accesses 1642system.cpu1.icache.demand_miss_rate::total 0.024978 # miss rate for demand accesses 1643system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024978 # miss rate for overall accesses 1644system.cpu1.icache.overall_miss_rate::total 0.024978 # miss rate for overall accesses 1645system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15072.890877 # average ReadReq miss latency 1646system.cpu1.icache.ReadReq_avg_miss_latency::total 15072.890877 # average ReadReq miss latency 1647system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency 1648system.cpu1.icache.demand_avg_miss_latency::total 15072.890877 # average overall miss latency 1649system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency 1650system.cpu1.icache.overall_avg_miss_latency::total 15072.890877 # average overall miss latency 1651system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 1652system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1653system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1654system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1655system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 1656system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1657system.cpu1.icache.fast_writes 0 # number of fast writes performed 1658system.cpu1.icache.cache_copies 0 # number of cache copies performed 1659system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits 1660system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 1661system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits 1662system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 1663system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits 1664system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 1665system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses 1666system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses 1667system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses 1668system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses 1669system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses 1670system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses 1671system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6648254 # number of ReadReq MSHR miss cycles 1672system.cpu1.icache.ReadReq_mshr_miss_latency::total 6648254 # number of ReadReq MSHR miss cycles 1673system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6648254 # number of demand (read+write) MSHR miss cycles 1674system.cpu1.icache.demand_mshr_miss_latency::total 6648254 # number of demand (read+write) MSHR miss cycles 1675system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6648254 # number of overall MSHR miss cycles 1676system.cpu1.icache.overall_mshr_miss_latency::total 6648254 # number of overall MSHR miss cycles 1677system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for ReadReq accesses 1678system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022207 # mshr miss rate for ReadReq accesses 1679system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for demand accesses 1680system.cpu1.icache.demand_mshr_miss_rate::total 0.022207 # mshr miss rate for demand accesses 1681system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for overall accesses 1682system.cpu1.icache.overall_mshr_miss_rate::total 0.022207 # mshr miss rate for overall accesses 1683system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average ReadReq mshr miss latency 1684system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13376.768612 # average ReadReq mshr miss latency 1685system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency 1686system.cpu1.icache.demand_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency 1687system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency 1688system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency 1689system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1690system.cpu1.dcache.tags.replacements 0 # number of replacements | 1107system.cpu1.dcache.tags.replacements 0 # number of replacements |
| 1691system.cpu1.dcache.tags.tagsinuse 24.402316 # Cycle average of tags in use 1692system.cpu1.dcache.tags.total_refs 40362 # Total number of references to valid blocks. | 1108system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use 1109system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. |
| 1693system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. | 1110system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. |
| 1694system.cpu1.dcache.tags.avg_refs 1441.500000 # Average number of references to valid blocks. | 1111system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. |
| 1695system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1112system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1696system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.402316 # Average occupied blocks per requestor 1697system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047661 # Average percentage of cache occupancy 1698system.cpu1.dcache.tags.occ_percent::total 0.047661 # Average percentage of cache occupancy | 1113system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor 1114system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy 1115system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy |
| 1699system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1700system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1701system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id | 1116system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1117system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1118system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id |
| 1702system.cpu1.dcache.tags.tag_accesses 315306 # Number of tag accesses 1703system.cpu1.dcache.tags.data_accesses 315306 # Number of data accesses 1704system.cpu1.dcache.ReadReq_hits::cpu1.data 43998 # number of ReadReq hits 1705system.cpu1.dcache.ReadReq_hits::total 43998 # number of ReadReq hits 1706system.cpu1.dcache.WriteReq_hits::cpu1.data 34119 # number of WriteReq hits 1707system.cpu1.dcache.WriteReq_hits::total 34119 # number of WriteReq hits 1708system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 1709system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 1710system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits 1711system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits 1712system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits 1713system.cpu1.dcache.overall_hits::total 78117 # number of overall hits 1714system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses 1715system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses 1716system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses 1717system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses 1718system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses 1719system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses 1720system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses 1721system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses 1722system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses 1723system.cpu1.dcache.overall_misses::total 575 # number of overall misses 1724system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles 1725system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles 1726system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles 1727system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles 1728system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles 1729system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles 1730system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles 1731system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles 1732system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles 1733system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles 1734system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses) 1735system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses) 1736system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses) 1737system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses) | 1119system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses 1120system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses 1121system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits 1122system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits 1123system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits 1124system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits 1125system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1126system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1127system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits 1128system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits 1129system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits 1130system.cpu1.dcache.overall_hits::total 68186 # number of overall hits 1131system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses 1132system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses 1133system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses 1134system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses 1135system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1136system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1137system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses 1138system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses 1139system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses 1140system.cpu1.dcache.overall_misses::total 559 # number of overall misses 1141system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles 1142system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles 1143system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles 1144system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles 1145system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles 1146system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles 1147system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles 1148system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles 1149system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles 1150system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles 1151system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) 1152system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) 1153system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) 1154system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) |
| 1738system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1739system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) | 1155system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1156system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) |
| 1740system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses 1741system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses 1742system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses 1743system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses 1744system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses 1745system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses 1746system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses 1747system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses 1748system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses 1749system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses 1750system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses 1751system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses 1752system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses 1753system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses 1754system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency 1755system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency 1756system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency 1757system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency 1758system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency 1759system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency 1760system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency 1761system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency 1762system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency 1763system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency | 1157system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses 1158system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses 1159system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses 1160system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses 1161system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses 1162system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses 1163system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses 1164system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses 1165system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 1166system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses 1168system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses 1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses 1170system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses 1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency 1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency 1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency 1175system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency 1176system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency 1177system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency 1178system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency 1179system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency 1180system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency |
| 1764system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1765system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1766system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1767system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1768system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1769system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1770system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1771system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1181system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1182system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1183system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1186system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1187system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1188system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1772system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits 1773system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits 1774system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1775system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1776system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits 1777system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits 1778system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits 1779system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits 1780system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses 1781system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses 1782system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses 1783system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses 1784system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses 1785system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses 1786system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses 1787system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 1788system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses 1789system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 1790system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles 1791system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles 1792system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles 1793system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles 1794system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles 1795system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles 1796system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles 1797system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles 1798system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles 1799system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles 1800system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses 1801system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses 1802system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses 1803system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses 1804system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses 1805system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses 1806system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses 1807system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses 1808system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses 1809system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses 1810system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency 1811system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency 1812system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency 1813system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency 1814system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency 1815system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency 1816system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency 1817system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency 1818system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency 1819system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency | 1189system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits 1190system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits 1191system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits 1192system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 1193system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits 1194system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits 1195system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits 1196system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits 1197system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses 1198system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses 1199system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses 1200system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses 1201system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1202system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1203system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses 1204system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 1205system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses 1206system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 1207system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles 1208system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles 1209system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles 1210system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles 1211system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles 1212system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles 1213system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles 1214system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles 1215system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles 1216system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles 1217system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses 1218system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses 1219system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses 1220system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses 1221system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses 1222system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1223system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses 1224system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses 1225system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses 1226system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses 1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency 1228system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency 1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency 1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency 1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency 1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency 1233system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency 1234system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency 1235system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency 1236system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency |
| 1820system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1237system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1821system.cpu2.branchPred.lookups 52660 # Number of BP lookups 1822system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted 1823system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect 1824system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups 1825system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits | 1238system.cpu1.icache.tags.replacements 388 # number of replacements 1239system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use 1240system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. 1241system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. 1242system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. 1243system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1244system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor 1245system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy 1246system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy 1247system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1248system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1249system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 1250system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 1251system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses 1252system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses 1253system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits 1254system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits 1255system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits 1256system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits 1257system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits 1258system.cpu1.icache.overall_hits::total 24292 # number of overall hits 1259system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses 1260system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses 1261system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses 1262system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses 1263system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses 1264system.cpu1.icache.overall_misses::total 562 # number of overall misses 1265system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles 1266system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles 1267system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles 1268system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles 1269system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles 1270system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles 1271system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) 1272system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) 1273system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses 1274system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses 1275system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses 1276system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses 1277system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses 1278system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses 1279system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses 1280system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses 1281system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses 1282system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses 1283system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency 1284system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency 1285system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency 1286system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency 1287system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency 1288system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency 1289system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 1290system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1291system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1292system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1293system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 1294system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1295system.cpu1.icache.fast_writes 0 # number of fast writes performed 1296system.cpu1.icache.cache_copies 0 # number of cache copies performed 1297system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits 1298system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 1299system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits 1300system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits 1301system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits 1302system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits 1303system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses 1304system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 1305system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses 1306system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses 1307system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses 1308system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses 1309system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles 1310system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles 1311system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles 1312system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles 1313system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles 1314system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles 1315system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses 1316system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses 1317system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses 1318system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses 1319system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses 1320system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses 1321system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency 1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency 1323system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency 1324system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency 1325system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency 1326system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency 1327system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1328system.cpu2.branchPred.lookups 55295 # Number of BP lookups 1329system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted 1330system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect 1331system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups 1332system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits |
| 1826system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1333system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1827system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage 1828system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target. | 1334system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage 1335system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. |
| 1829system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 1336system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 1830system.cpu2.numCycles 160663 # number of cpu cycles simulated | 1337system.cpu2.numCycles 160375 # number of cpu cycles simulated |
| 1831system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1832system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed | 1338system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1339system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1833system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss 1834system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed 1835system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered 1836system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken 1837system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked 1838system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing | 1340system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss 1341system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed 1342system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered 1343system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken 1344system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked 1345system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing |
| 1839system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1840system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from | 1346system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1347system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from |
| 1841system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps | 1348system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps |
| 1842system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR | 1349system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR |
| 1843system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched 1844system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed 1845system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total) 1846system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total) 1847system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total) | 1350system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched 1351system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed 1352system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) 1353system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) 1354system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) |
| 1848system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1355system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1849system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total) 1850system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total) 1851system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total) 1852system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total) 1853system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total) 1854system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total) 1855system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total) 1856system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total) 1857system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total) | 1356system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) 1357system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) 1361system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) 1362system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) 1363system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) 1364system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) |
| 1858system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1859system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1860system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1365system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1366system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1367system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1861system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total) 1862system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle 1863system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle 1864system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle 1865system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked 1866system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running 1867system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking 1868system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing 1869system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode 1870system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing 1871system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle 1872system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking 1873system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst 1874system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running 1875system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking 1876system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename 1877system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full 1878system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full | 1368system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) 1369system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle 1370system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle 1371system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle 1372system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked 1373system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running 1374system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking 1375system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing 1376system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode 1377system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing 1378system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle 1379system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking 1380system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst 1381system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running 1382system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking 1383system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename 1384system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full 1385system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full |
| 1879system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers | 1386system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers |
| 1880system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed 1881system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made 1882system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups 1883system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed 1884system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing 1885system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed 1886system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed 1887system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer 1888system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit. 1889system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit. 1890system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads. 1891system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores. 1892system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec) 1893system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ 1894system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued 1895system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued 1896system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling 1897system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph 1898system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed 1899system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle 1900system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle 1901system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle | 1387system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed 1388system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made 1389system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups 1390system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed 1391system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing 1392system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed 1393system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed 1394system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer 1395system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. 1396system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. 1397system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. 1398system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. 1399system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) 1400system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ 1401system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued 1402system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued 1403system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling 1404system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph 1405system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed 1406system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle 1407system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle 1408system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle |
| 1902system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1409system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1903system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle 1904system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle 1905system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle 1906system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle 1907system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle 1908system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle 1909system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle 1910system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle 1911system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle | 1410system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle 1411system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle 1414system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle 1415system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle 1416system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle 1417system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle 1418system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle |
| 1912system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1913system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1914system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1419system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1420system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1421system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1915system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle | 1422system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle |
| 1916system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1423system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1917system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available 1918system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available 1919system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available 1920system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available 1921system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available 1922system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available 1923system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available 1924system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available 1925system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available 1926system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available 1927system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available 1928system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available 1929system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available 1930system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available 1931system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available 1932system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available 1933system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available 1934system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available 1935system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available 1936system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available 1937system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available 1938system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available 1939system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available 1940system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available 1941system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available 1942system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available 1943system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available 1944system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available 1945system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available 1946system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available 1947system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available | 1424system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available 1425system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available 1426system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available 1427system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available 1428system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available 1448system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available 1449system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available 1450system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available 1451system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available 1452system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available 1453system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available 1454system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available |
| 1948system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1949system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1950system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1455system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1456system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1457system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 1951system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued 1952system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued 1953system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued 1954system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued 1955system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued 1956system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued 1957system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued 1958system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued 1959system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued 1960system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued 1961system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued 1962system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued 1963system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued 1964system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued 1965system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued 1966system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued 1967system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued 1968system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued 1969system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued 1970system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued 1971system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued 1972system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued 1973system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued 1974system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued 1975system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued 1976system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued 1977system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued 1978system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued 1979system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued 1980system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued 1981system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued | 1458system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued 1459system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued 1460system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued 1461system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued 1462system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued 1463system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued 1464system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued 1465system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued 1466system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued 1467system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued 1468system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued 1469system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued 1470system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued 1471system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued 1478system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued 1479system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued 1480system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued 1481system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued 1482system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued 1483system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued 1484system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued 1485system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued 1486system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued 1487system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued 1488system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued |
| 1982system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1983system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1489system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1490system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1984system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued 1985system.cpu2.iq.rate 1.424360 # Inst issue rate 1986system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested 1987system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst) 1988system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads 1989system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes 1990system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses | 1491system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued 1492system.cpu2.iq.rate 1.514600 # Inst issue rate 1493system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested 1494system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) 1495system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads 1496system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes 1497system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses |
| 1991system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1992system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1993system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 1498system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1499system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1500system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 1994system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses | 1501system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses |
| 1995system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 1502system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 1996system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores | 1503system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores |
| 1997system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1504system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1998system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed | 1505system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed |
| 1999system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 1506system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 2000system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 2001system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed | 1507system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations 1508system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed |
| 2002system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2003system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2004system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2005system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2006system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1509system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1510system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1511system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1512system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1513system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2007system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing 2008system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking 2009system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking 2010system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ 2011system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch 2012system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions 2013system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions | 1514system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing 1515system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking 1516system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking 1517system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ 1518system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch 1519system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions 1520system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions |
| 2014system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions | 1521system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions |
| 2015system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall | 1522system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall |
| 2016system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 1523system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 2017system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations | 1524system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations |
| 2018system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly | 1525system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly |
| 2019system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly 2020system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute 2021system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions 2022system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed 2023system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute | 1526system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly 1527system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute 1528system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions 1529system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed 1530system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute |
| 2024system.cpu2.iew.exec_swp 0 # number of swp insts executed | 1531system.cpu2.iew.exec_swp 0 # number of swp insts executed |
| 2025system.cpu2.iew.exec_nop 37107 # number of nop insts executed 2026system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed 2027system.cpu2.iew.exec_branches 46563 # Number of branches executed 2028system.cpu2.iew.exec_stores 35711 # Number of stores executed 2029system.cpu2.iew.exec_rate 1.417252 # Inst execution rate 2030system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit 2031system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back 2032system.cpu2.iew.wb_producers 129036 # num instructions producing a value 2033system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value | 1532system.cpu2.iew.exec_nop 39706 # number of nop insts executed 1533system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed 1534system.cpu2.iew.exec_branches 49059 # Number of branches executed 1535system.cpu2.iew.exec_stores 39036 # Number of stores executed 1536system.cpu2.iew.exec_rate 1.507585 # Inst execution rate 1537system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit 1538system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back 1539system.cpu2.iew.wb_producers 138145 # num instructions producing a value 1540system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value |
| 2034system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1541system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2035system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle 2036system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back | 1542system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle 1543system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back |
| 2037system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1544system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2038system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit 2039system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards 2040system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted 2041system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle 2042system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle 2043system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle | 1545system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit 1546system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards 1547system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted 1548system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle 1549system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle 1550system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle |
| 2044system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1551system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2045system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle 2046system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle 2047system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle 2048system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle 2049system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle 2050system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle 2051system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle 2052system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle 2053system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle | 1552system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle 1553system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle 1556system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle 1557system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle 1558system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle 1559system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle 1560system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle |
| 2054system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2055system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2056system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1561system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1562system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1563system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2057system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle 2058system.cpu2.commit.committedInsts 256170 # Number of instructions committed 2059system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed | 1564system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle 1565system.cpu2.commit.committedInsts 272860 # Number of instructions committed 1566system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed |
| 2060system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed | 1567system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed |
| 2061system.cpu2.commit.refs 108804 # Number of memory references committed 2062system.cpu2.commit.loads 73922 # Number of loads committed 2063system.cpu2.commit.membars 4659 # Number of memory barriers committed 2064system.cpu2.commit.branches 45502 # Number of branches committed | 1568system.cpu2.commit.refs 117938 # Number of memory references committed 1569system.cpu2.commit.loads 79744 # Number of loads committed 1570system.cpu2.commit.membars 3865 # Number of memory barriers committed 1571system.cpu2.commit.branches 48024 # Number of branches committed |
| 2065system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. | 1572system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. |
| 2066system.cpu2.commit.int_insts 176434 # Number of committed integer instructions. | 1573system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. |
| 2067system.cpu2.commit.function_calls 322 # Number of function calls committed. | 1574system.cpu2.commit.function_calls 322 # Number of function calls committed. |
| 2068system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction 2069system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction 2070system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction 2071system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction 2072system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction 2073system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction 2074system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction 2075system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction 2076system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction 2077system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction 2078system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction 2079system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction 2080system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction 2081system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction 2082system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction 2083system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction 2084system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction 2085system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction 2086system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction 2087system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction 2088system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction 2089system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction 2090system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction 2091system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction 2092system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction 2093system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction 2094system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction 2095system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction 2096system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction 2097system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction 2098system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction 2099system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction | 1575system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction 1576system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction 1577system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction 1578system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction 1579system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction 1580system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction 1581system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction 1582system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction 1583system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction 1584system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction 1585system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction 1586system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction 1587system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction 1596system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction 1597system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction 1598system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction 1599system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction 1600system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction 1601system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction 1602system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction 1603system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction 1604system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction 1605system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction 1606system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction |
| 2100system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2101system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1607system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1608system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2102system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction 2103system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached | 1609system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction 1610system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached |
| 2104system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits | 1611system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2105system.cpu2.rob.rob_reads 421739 # The number of ROB reads 2106system.cpu2.rob.rob_writes 544215 # The number of ROB writes | 1612system.cpu2.rob.rob_reads 438358 # The number of ROB reads 1613system.cpu2.rob.rob_writes 577962 # The number of ROB writes |
| 2107system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself | 1614system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 2108system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling 2109system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2110system.cpu2.committedInsts 215214 # Number of Instructions Simulated 2111system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated 2112system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction 2113system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads 2114system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle 2115system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads 2116system.cpu2.int_regfile_reads 394013 # number of integer regfile reads 2117system.cpu2.int_regfile_writes 184721 # number of integer regfile writes | 1615system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling 1616system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1617system.cpu2.committedInsts 230180 # Number of Instructions Simulated 1618system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated 1619system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction 1620system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads 1621system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle 1622system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads 1623system.cpu2.int_regfile_reads 421380 # number of integer regfile reads 1624system.cpu2.int_regfile_writes 197053 # number of integer regfile writes |
| 2118system.cpu2.fp_regfile_writes 64 # number of floating regfile writes | 1625system.cpu2.fp_regfile_writes 64 # number of floating regfile writes |
| 2119system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads | 1626system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads |
| 2120system.cpu2.misc_regfile_writes 648 # number of misc regfile writes | 1627system.cpu2.misc_regfile_writes 648 # number of misc regfile writes |
| 2121system.cpu2.icache.tags.replacements 380 # number of replacements 2122system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use 2123system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks. 2124system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. 2125system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks. 2126system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2127system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor 2128system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy 2129system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy 2130system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id 2131system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2132system.cpu2.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 2133system.cpu2.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id 2134system.cpu2.icache.tags.tag_accesses 21662 # Number of tag accesses 2135system.cpu2.icache.tags.data_accesses 21662 # Number of data accesses 2136system.cpu2.icache.ReadReq_hits::cpu2.inst 20592 # number of ReadReq hits 2137system.cpu2.icache.ReadReq_hits::total 20592 # number of ReadReq hits 2138system.cpu2.icache.demand_hits::cpu2.inst 20592 # number of demand (read+write) hits 2139system.cpu2.icache.demand_hits::total 20592 # number of demand (read+write) hits 2140system.cpu2.icache.overall_hits::cpu2.inst 20592 # number of overall hits 2141system.cpu2.icache.overall_hits::total 20592 # number of overall hits 2142system.cpu2.icache.ReadReq_misses::cpu2.inst 577 # number of ReadReq misses 2143system.cpu2.icache.ReadReq_misses::total 577 # number of ReadReq misses 2144system.cpu2.icache.demand_misses::cpu2.inst 577 # number of demand (read+write) misses 2145system.cpu2.icache.demand_misses::total 577 # number of demand (read+write) misses 2146system.cpu2.icache.overall_misses::cpu2.inst 577 # number of overall misses 2147system.cpu2.icache.overall_misses::total 577 # number of overall misses 2148system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13065992 # number of ReadReq miss cycles 2149system.cpu2.icache.ReadReq_miss_latency::total 13065992 # number of ReadReq miss cycles 2150system.cpu2.icache.demand_miss_latency::cpu2.inst 13065992 # number of demand (read+write) miss cycles 2151system.cpu2.icache.demand_miss_latency::total 13065992 # number of demand (read+write) miss cycles 2152system.cpu2.icache.overall_miss_latency::cpu2.inst 13065992 # number of overall miss cycles 2153system.cpu2.icache.overall_miss_latency::total 13065992 # number of overall miss cycles 2154system.cpu2.icache.ReadReq_accesses::cpu2.inst 21169 # number of ReadReq accesses(hits+misses) 2155system.cpu2.icache.ReadReq_accesses::total 21169 # number of ReadReq accesses(hits+misses) 2156system.cpu2.icache.demand_accesses::cpu2.inst 21169 # number of demand (read+write) accesses 2157system.cpu2.icache.demand_accesses::total 21169 # number of demand (read+write) accesses 2158system.cpu2.icache.overall_accesses::cpu2.inst 21169 # number of overall (read+write) accesses 2159system.cpu2.icache.overall_accesses::total 21169 # number of overall (read+write) accesses 2160system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.027257 # miss rate for ReadReq accesses 2161system.cpu2.icache.ReadReq_miss_rate::total 0.027257 # miss rate for ReadReq accesses 2162system.cpu2.icache.demand_miss_rate::cpu2.inst 0.027257 # miss rate for demand accesses 2163system.cpu2.icache.demand_miss_rate::total 0.027257 # miss rate for demand accesses 2164system.cpu2.icache.overall_miss_rate::cpu2.inst 0.027257 # miss rate for overall accesses 2165system.cpu2.icache.overall_miss_rate::total 0.027257 # miss rate for overall accesses 2166system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22644.700173 # average ReadReq miss latency 2167system.cpu2.icache.ReadReq_avg_miss_latency::total 22644.700173 # average ReadReq miss latency 2168system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency 2169system.cpu2.icache.demand_avg_miss_latency::total 22644.700173 # average overall miss latency 2170system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency 2171system.cpu2.icache.overall_avg_miss_latency::total 22644.700173 # average overall miss latency 2172system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked 2173system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2174system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked 2175system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 2176system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked 2177system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2178system.cpu2.icache.fast_writes 0 # number of fast writes performed 2179system.cpu2.icache.cache_copies 0 # number of cache copies performed 2180system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 84 # number of ReadReq MSHR hits 2181system.cpu2.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits 2182system.cpu2.icache.demand_mshr_hits::cpu2.inst 84 # number of demand (read+write) MSHR hits 2183system.cpu2.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits 2184system.cpu2.icache.overall_mshr_hits::cpu2.inst 84 # number of overall MSHR hits 2185system.cpu2.icache.overall_mshr_hits::total 84 # number of overall MSHR hits 2186system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 493 # number of ReadReq MSHR misses 2187system.cpu2.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses 2188system.cpu2.icache.demand_mshr_misses::cpu2.inst 493 # number of demand (read+write) MSHR misses 2189system.cpu2.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses 2190system.cpu2.icache.overall_mshr_misses::cpu2.inst 493 # number of overall MSHR misses 2191system.cpu2.icache.overall_mshr_misses::total 493 # number of overall MSHR misses 2192system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10294257 # number of ReadReq MSHR miss cycles 2193system.cpu2.icache.ReadReq_mshr_miss_latency::total 10294257 # number of ReadReq MSHR miss cycles 2194system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10294257 # number of demand (read+write) MSHR miss cycles 2195system.cpu2.icache.demand_mshr_miss_latency::total 10294257 # number of demand (read+write) MSHR miss cycles 2196system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10294257 # number of overall MSHR miss cycles 2197system.cpu2.icache.overall_mshr_miss_latency::total 10294257 # number of overall MSHR miss cycles 2198system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for ReadReq accesses 2199system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.023289 # mshr miss rate for ReadReq accesses 2200system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for demand accesses 2201system.cpu2.icache.demand_mshr_miss_rate::total 0.023289 # mshr miss rate for demand accesses 2202system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for overall accesses 2203system.cpu2.icache.overall_mshr_miss_rate::total 0.023289 # mshr miss rate for overall accesses 2204system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average ReadReq mshr miss latency 2205system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 20880.845842 # average ReadReq mshr miss latency 2206system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency 2207system.cpu2.icache.demand_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency 2208system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency 2209system.cpu2.icache.overall_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency 2210system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2211system.cpu2.dcache.tags.replacements 0 # number of replacements | 1628system.cpu2.dcache.tags.replacements 0 # number of replacements |
| 2212system.cpu2.dcache.tags.tagsinuse 25.876504 # Cycle average of tags in use 2213system.cpu2.dcache.tags.total_refs 41118 # Total number of references to valid blocks. 2214system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 2215system.cpu2.dcache.tags.avg_refs 1417.862069 # Average number of references to valid blocks. | 1629system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use 1630system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. 1631system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1632system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. |
| 2216system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1633system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2217system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.876504 # Average occupied blocks per requestor 2218system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050540 # Average percentage of cache occupancy 2219system.cpu2.dcache.tags.occ_percent::total 0.050540 # Average percentage of cache occupancy 2220system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2221system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id | 1634system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor 1635system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy 1636system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy 1637system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id |
| 2222system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id | 1638system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id |
| 2223system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 2224system.cpu2.dcache.tags.tag_accesses 317671 # Number of tag accesses 2225system.cpu2.dcache.tags.data_accesses 317671 # Number of data accesses 2226system.cpu2.dcache.ReadReq_hits::cpu2.data 44059 # number of ReadReq hits 2227system.cpu2.dcache.ReadReq_hits::total 44059 # number of ReadReq hits 2228system.cpu2.dcache.WriteReq_hits::cpu2.data 34671 # number of WriteReq hits 2229system.cpu2.dcache.WriteReq_hits::total 34671 # number of WriteReq hits 2230system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits 2231system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2232system.cpu2.dcache.demand_hits::cpu2.data 78730 # number of demand (read+write) hits 2233system.cpu2.dcache.demand_hits::total 78730 # number of demand (read+write) hits 2234system.cpu2.dcache.overall_hits::cpu2.data 78730 # number of overall hits 2235system.cpu2.dcache.overall_hits::total 78730 # number of overall hits 2236system.cpu2.dcache.ReadReq_misses::cpu2.data 415 # number of ReadReq misses 2237system.cpu2.dcache.ReadReq_misses::total 415 # number of ReadReq misses 2238system.cpu2.dcache.WriteReq_misses::cpu2.data 148 # number of WriteReq misses 2239system.cpu2.dcache.WriteReq_misses::total 148 # number of WriteReq misses 2240system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses 2241system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses 2242system.cpu2.dcache.demand_misses::cpu2.data 563 # number of demand (read+write) misses 2243system.cpu2.dcache.demand_misses::total 563 # number of demand (read+write) misses 2244system.cpu2.dcache.overall_misses::cpu2.data 563 # number of overall misses 2245system.cpu2.dcache.overall_misses::total 563 # number of overall misses 2246system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7441548 # number of ReadReq miss cycles 2247system.cpu2.dcache.ReadReq_miss_latency::total 7441548 # number of ReadReq miss cycles 2248system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3663511 # number of WriteReq miss cycles 2249system.cpu2.dcache.WriteReq_miss_latency::total 3663511 # number of WriteReq miss cycles 2250system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 451006 # number of SwapReq miss cycles 2251system.cpu2.dcache.SwapReq_miss_latency::total 451006 # number of SwapReq miss cycles 2252system.cpu2.dcache.demand_miss_latency::cpu2.data 11105059 # number of demand (read+write) miss cycles 2253system.cpu2.dcache.demand_miss_latency::total 11105059 # number of demand (read+write) miss cycles 2254system.cpu2.dcache.overall_miss_latency::cpu2.data 11105059 # number of overall miss cycles 2255system.cpu2.dcache.overall_miss_latency::total 11105059 # number of overall miss cycles 2256system.cpu2.dcache.ReadReq_accesses::cpu2.data 44474 # number of ReadReq accesses(hits+misses) 2257system.cpu2.dcache.ReadReq_accesses::total 44474 # number of ReadReq accesses(hits+misses) 2258system.cpu2.dcache.WriteReq_accesses::cpu2.data 34819 # number of WriteReq accesses(hits+misses) 2259system.cpu2.dcache.WriteReq_accesses::total 34819 # number of WriteReq accesses(hits+misses) 2260system.cpu2.dcache.SwapReq_accesses::cpu2.data 63 # number of SwapReq accesses(hits+misses) 2261system.cpu2.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) 2262system.cpu2.dcache.demand_accesses::cpu2.data 79293 # number of demand (read+write) accesses 2263system.cpu2.dcache.demand_accesses::total 79293 # number of demand (read+write) accesses 2264system.cpu2.dcache.overall_accesses::cpu2.data 79293 # number of overall (read+write) accesses 2265system.cpu2.dcache.overall_accesses::total 79293 # number of overall (read+write) accesses 2266system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009331 # miss rate for ReadReq accesses 2267system.cpu2.dcache.ReadReq_miss_rate::total 0.009331 # miss rate for ReadReq accesses 2268system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004251 # miss rate for WriteReq accesses 2269system.cpu2.dcache.WriteReq_miss_rate::total 0.004251 # miss rate for WriteReq accesses 2270system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.777778 # miss rate for SwapReq accesses 2271system.cpu2.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses 2272system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007100 # miss rate for demand accesses 2273system.cpu2.dcache.demand_miss_rate::total 0.007100 # miss rate for demand accesses 2274system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007100 # miss rate for overall accesses 2275system.cpu2.dcache.overall_miss_rate::total 0.007100 # miss rate for overall accesses 2276system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17931.440964 # average ReadReq miss latency 2277system.cpu2.dcache.ReadReq_avg_miss_latency::total 17931.440964 # average ReadReq miss latency 2278system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24753.452703 # average WriteReq miss latency 2279system.cpu2.dcache.WriteReq_avg_miss_latency::total 24753.452703 # average WriteReq miss latency 2280system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9204.204082 # average SwapReq miss latency 2281system.cpu2.dcache.SwapReq_avg_miss_latency::total 9204.204082 # average SwapReq miss latency 2282system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency 2283system.cpu2.dcache.demand_avg_miss_latency::total 19724.793961 # average overall miss latency 2284system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency 2285system.cpu2.dcache.overall_avg_miss_latency::total 19724.793961 # average overall miss latency | 1639system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 1640system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses 1641system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses 1642system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits 1643system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits 1644system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits 1645system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits 1646system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 1647system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1648system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits 1649system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits 1650system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits 1651system.cpu2.dcache.overall_hits::total 84526 # number of overall hits 1652system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses 1653system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses 1654system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses 1655system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses 1656system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 1657system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 1658system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses 1659system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses 1660system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses 1661system.cpu2.dcache.overall_misses::total 597 # number of overall misses 1662system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles 1663system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles 1664system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles 1665system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles 1666system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles 1667system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles 1668system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles 1669system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles 1670system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles 1671system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles 1672system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses) 1673system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses) 1674system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) 1675system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) 1676system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) 1677system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 1678system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses 1679system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses 1680system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses 1681system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses 1682system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses 1683system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses 1684system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses 1685system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses 1686system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses 1687system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses 1688system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses 1689system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses 1690system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses 1691system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses 1692system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency 1693system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency 1694system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency 1695system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency 1696system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency 1697system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency 1698system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency 1699system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency 1700system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency 1701system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency |
| 2286system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2287system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2288system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2289system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2290system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2291system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2292system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2293system.cpu2.dcache.cache_copies 0 # number of cache copies performed | 1702system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1703system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1704system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1705system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1706system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1707system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1708system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1709system.cpu2.dcache.cache_copies 0 # number of cache copies performed |
| 2294system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 262 # number of ReadReq MSHR hits 2295system.cpu2.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits 2296system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits 2297system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits 2298system.cpu2.dcache.demand_mshr_hits::cpu2.data 302 # number of demand (read+write) MSHR hits 2299system.cpu2.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits 2300system.cpu2.dcache.overall_mshr_hits::cpu2.data 302 # number of overall MSHR hits 2301system.cpu2.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits 2302system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 153 # number of ReadReq MSHR misses 2303system.cpu2.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses | 1710system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits 1711system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits 1712system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits 1713system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits 1714system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits 1715system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits 1716system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits 1717system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits 1718system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses 1719system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses |
| 2304system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 2305system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses | 1720system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses 1721system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses |
| 2306system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses 2307system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses 2308system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses 2309system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses 2310system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses 2311system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses 2312system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles 2313system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles 2314system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles 2315system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles 2316system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles 2317system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles 2318system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles 2319system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles 2320system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles 2321system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles 2322system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses 2323system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses 2324system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses 2325system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses 2326system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses 2327system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses 2328system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses 2329system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses 2330system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses 2331system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses 2332system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency 2333system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency 2334system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency 2335system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency 2336system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency 2337system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency 2338system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency 2339system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency 2340system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency 2341system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency | 1722system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses 1723system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses 1724system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses 1725system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 1726system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses 1727system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 1728system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles 1729system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles 1730system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles 1731system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles 1732system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles 1733system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles 1734system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles 1735system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles 1736system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles 1737system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles 1738system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses 1739system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses 1740system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses 1741system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses 1742system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses 1743system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses 1744system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses 1745system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses 1746system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses 1747system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses 1748system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency 1749system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency 1750system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency 1751system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency 1752system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency 1753system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency 1754system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency 1755system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency 1756system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency 1757system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency |
| 2342system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1758system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2343system.cpu3.branchPred.lookups 48141 # Number of BP lookups 2344system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted 2345system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect 2346system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups 2347system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits | 1759system.cpu2.icache.tags.replacements 378 # number of replacements 1760system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use 1761system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. 1762system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. 1763system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. 1764system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1765system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor 1766system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy 1767system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy 1768system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id 1769system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1770system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 1771system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id 1772system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses 1773system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses 1774system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits 1775system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits 1776system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits 1777system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits 1778system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits 1779system.cpu2.icache.overall_hits::total 18881 # number of overall hits 1780system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses 1781system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses 1782system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses 1783system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses 1784system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses 1785system.cpu2.icache.overall_misses::total 570 # number of overall misses 1786system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles 1787system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles 1788system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles 1789system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles 1790system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles 1791system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles 1792system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) 1793system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) 1794system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses 1795system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses 1796system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses 1797system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses 1798system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses 1799system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses 1800system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses 1801system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses 1802system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses 1803system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses 1804system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency 1805system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency 1806system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency 1807system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency 1808system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency 1809system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency 1810system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked 1811system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1812system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked 1813system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1814system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked 1815system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1816system.cpu2.icache.fast_writes 0 # number of fast writes performed 1817system.cpu2.icache.cache_copies 0 # number of cache copies performed 1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits 1819system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits 1821system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits 1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits 1823system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits 1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses 1825system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses 1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses 1827system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses 1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses 1829system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses 1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles 1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles 1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles 1833system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles 1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles 1835system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles 1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses 1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses 1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses 1839system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses 1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses 1841system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses 1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency 1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency 1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency 1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency 1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency 1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency 1848system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1849system.cpu3.branchPred.lookups 49708 # Number of BP lookups 1850system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted 1851system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect 1852system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups 1853system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits |
| 2348system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1854system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 2349system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage 2350system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target. | 1855system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage 1856system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. |
| 2351system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. | 1857system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. |
| 2352system.cpu3.numCycles 160319 # number of cpu cycles simulated | 1858system.cpu3.numCycles 160031 # number of cpu cycles simulated |
| 2353system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2354system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed | 1859system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1860system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2355system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss 2356system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed 2357system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered 2358system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken 2359system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked 2360system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing | 1861system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss 1862system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed 1863system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered 1864system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken 1865system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked 1866system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing |
| 2361system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2362system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from | 1867system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1868system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from |
| 2363system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps 2364system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched 2365system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed 2366system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total) 2367system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total) 2368system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total) | 1869system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps 1870system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched 1871system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed 1872system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) 1873system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) 1874system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) |
| 2369system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1875system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2370system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total) 2371system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total) 2372system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total) 2373system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total) 2374system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total) 2375system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total) 2376system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total) 2377system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total) 2378system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total) | 1876system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) 1877system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) 1878system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) 1879system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) 1882system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) 1883system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) 1884system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) |
| 2379system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2380system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2381system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1885system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 2382system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total) 2383system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle 2384system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle 2385system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle 2386system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked 2387system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running 2388system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking 2389system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing 2390system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode 2391system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing 2392system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle 2393system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking 2394system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst 2395system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running 2396system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking 2397system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename 2398system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full 2399system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full | 1888system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) 1889system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle 1890system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle 1891system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle 1892system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked 1893system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running 1894system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking 1895system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing 1896system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode 1897system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing 1898system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle 1899system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking 1900system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst 1901system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running 1902system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking 1903system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename 1904system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full 1905system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full |
| 2400system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers | 1906system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers |
| 2401system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed 2402system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made 2403system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups 2404system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed 2405system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing 2406system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed 2407system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed 2408system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer 2409system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit. 2410system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit. 2411system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads. 2412system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores. 2413system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec) 2414system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ 2415system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued 2416system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued 2417system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling 2418system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph 2419system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed 2420system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle 2421system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle 2422system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle | 1907system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed 1908system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made 1909system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups 1910system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed 1911system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing 1912system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed 1913system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed 1914system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer 1915system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. 1916system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. 1917system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. 1918system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. 1919system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) 1920system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ 1921system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued 1922system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued 1923system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling 1924system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph 1925system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed 1926system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle 1927system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle 1928system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle |
| 2423system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1929system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2424system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle 2425system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle 2426system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle 2427system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle 2428system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle 2429system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle 2430system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle 2431system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle 2432system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle | 1930system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle 1931system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle 1932system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle 1933system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle 1934system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle 1935system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle 1936system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle 1937system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle 1938system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle |
| 2433system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2434system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2435system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1939system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1940system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1941system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 2436system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle | 1942system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle |
| 2437system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1943system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2438system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available 2439system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available 2440system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available 2441system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available 2442system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available 2443system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available 2444system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available 2445system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available 2446system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available 2447system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available 2448system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available 2449system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available 2450system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available 2451system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available 2452system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available 2453system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available 2454system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available 2455system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available 2456system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available 2457system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available 2458system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available 2459system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available 2460system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available 2461system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available 2462system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available 2463system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available 2464system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available 2465system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available 2466system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available 2467system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available 2468system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available | 1944system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available 1945system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available 1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available 1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available 1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available 1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available 1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available 1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available 1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available 1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available 1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available 1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available 1973system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available 1974system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available |
| 2469system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2470system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2471system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 1975system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1976system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1977system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 2472system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued 2473system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.13% # Type of FU issued 2474system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued 2475system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued 2476system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued 2477system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued 2478system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued 2479system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued 2480system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued 2481system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued 2482system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued 2483system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued 2484system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued 2485system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued 2486system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued 2487system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued 2488system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued 2489system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued 2490system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued 2491system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued 2492system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued 2493system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued 2494system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued 2495system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued 2496system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued 2497system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued 2498system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued 2499system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued 2500system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued 2501system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued 2502system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued | 1978system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued 1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued 1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued 1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued 1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued 1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued 1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued 1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued 1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued 1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued 1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued 1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued 1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued 1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued 1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued 1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued 1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued 1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued 2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued 2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued 2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued 2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued 2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued 2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued 2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued 2007system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued 2008system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued |
| 2503system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2504system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2009system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2010system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2505system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued 2506system.cpu3.iq.rate 1.256389 # Inst issue rate 2507system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested 2508system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst) 2509system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads 2510system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes 2511system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses | 2011system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued 2012system.cpu3.iq.rate 1.322737 # Inst issue rate 2013system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested 2014system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) 2015system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads 2016system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes 2017system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses |
| 2512system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2513system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2514system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 2018system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2019system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2020system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 2515system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses | 2021system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses |
| 2516system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 2022system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 2517system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores | 2023system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores |
| 2518system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2024system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2519system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed | 2025system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed |
| 2520system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed | 2026system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed |
| 2521system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 2522system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed | 2027system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations 2028system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed |
| 2523system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2524system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2525system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2526system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2527system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2029system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2030system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2031system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2032system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2033system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2528system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing 2529system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking 2530system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking 2531system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ 2532system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch 2533system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions 2534system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions 2535system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions 2536system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall | 2034system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing 2035system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking 2036system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking 2037system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ 2038system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch 2039system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions 2040system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions 2041system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions 2042system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall |
| 2537system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 2043system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 2538system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations 2539system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly 2540system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly 2541system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute 2542system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions 2543system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed 2544system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute | 2044system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations 2045system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly 2046system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly 2047system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute 2048system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions 2049system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed 2050system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute |
| 2545system.cpu3.iew.exec_swp 0 # number of swp insts executed | 2051system.cpu3.iew.exec_swp 0 # number of swp insts executed |
| 2546system.cpu3.iew.exec_nop 32617 # number of nop insts executed 2547system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed 2548system.cpu3.iew.exec_branches 41928 # Number of branches executed 2549system.cpu3.iew.exec_stores 29146 # Number of stores executed 2550system.cpu3.iew.exec_rate 1.249328 # Inst execution rate 2551system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit 2552system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back 2553system.cpu3.iew.wb_producers 111117 # num instructions producing a value 2554system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value | 2052system.cpu3.iew.exec_nop 34395 # number of nop insts executed 2053system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed 2054system.cpu3.iew.exec_branches 43728 # Number of branches executed 2055system.cpu3.iew.exec_stores 31474 # Number of stores executed 2056system.cpu3.iew.exec_rate 1.315601 # Inst execution rate 2057system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit 2058system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back 2059system.cpu3.iew.wb_producers 117676 # num instructions producing a value 2060system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value |
| 2555system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2061system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2556system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle 2557system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back | 2062system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle 2063system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back |
| 2558system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2064system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2559system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit 2560system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards 2561system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted 2562system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle 2563system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle 2564system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle | 2065system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit 2066system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards 2067system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted 2068system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle 2069system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle 2070system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle |
| 2565system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2071system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2566system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle 2567system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle 2568system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle 2569system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle 2570system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle 2571system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle 2572system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle 2573system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle 2574system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle | 2072system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle 2073system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle 2076system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle 2077system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle 2078system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle 2079system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle 2080system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle |
| 2575system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2576system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2577system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2081system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2082system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2083system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2578system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle 2579system.cpu3.commit.committedInsts 224520 # Number of instructions committed 2580system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed | 2084system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle 2085system.cpu3.commit.committedInsts 236439 # Number of instructions committed 2086system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed |
| 2581system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed | 2087system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed |
| 2582system.cpu3.commit.refs 91055 # Number of memory references committed 2583system.cpu3.commit.loads 62716 # Number of loads committed 2584system.cpu3.commit.membars 6575 # Number of memory barriers committed 2585system.cpu3.commit.branches 40877 # Number of branches committed | 2088system.cpu3.commit.refs 97502 # Number of memory references committed 2089system.cpu3.commit.loads 66856 # Number of loads committed 2090system.cpu3.commit.membars 6091 # Number of memory barriers committed 2091system.cpu3.commit.branches 42698 # Number of branches committed |
| 2586system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. | 2092system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. |
| 2587system.cpu3.commit.int_insts 154046 # Number of committed integer instructions. | 2093system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. |
| 2588system.cpu3.commit.function_calls 322 # Number of function calls committed. | 2094system.cpu3.commit.function_calls 322 # Number of function calls committed. |
| 2589system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction 2590system.cpu3.commit.op_class_0::IntAlu 95230 42.41% 56.52% # Class of committed instruction 2591system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.52% # Class of committed instruction 2592system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.52% # Class of committed instruction 2593system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.52% # Class of committed instruction 2594system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.52% # Class of committed instruction 2595system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.52% # Class of committed instruction 2596system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.52% # Class of committed instruction 2597system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.52% # Class of committed instruction 2598system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.52% # Class of committed instruction 2599system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.52% # Class of committed instruction 2600system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.52% # Class of committed instruction 2601system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.52% # Class of committed instruction 2602system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.52% # Class of committed instruction 2603system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.52% # Class of committed instruction 2604system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.52% # Class of committed instruction 2605system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.52% # Class of committed instruction 2606system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.52% # Class of committed instruction 2607system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.52% # Class of committed instruction 2608system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.52% # Class of committed instruction 2609system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.52% # Class of committed instruction 2610system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.52% # Class of committed instruction 2611system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.52% # Class of committed instruction 2612system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.52% # Class of committed instruction 2613system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.52% # Class of committed instruction 2614system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.52% # Class of committed instruction 2615system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.52% # Class of committed instruction 2616system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.52% # Class of committed instruction 2617system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.52% # Class of committed instruction 2618system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.52% # Class of committed instruction 2619system.cpu3.commit.op_class_0::MemRead 69291 30.86% 87.38% # Class of committed instruction 2620system.cpu3.commit.op_class_0::MemWrite 28339 12.62% 100.00% # Class of committed instruction | 2095system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction 2096system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction 2097system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction 2098system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction 2099system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction 2100system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction 2101system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction 2102system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction 2103system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction 2104system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction 2105system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction 2106system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction 2107system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction 2108system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction 2109system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction 2116system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction 2117system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction 2118system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction 2119system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction 2120system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction 2121system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction 2122system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction 2123system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction 2124system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction 2125system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction 2126system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction |
| 2621system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2622system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2127system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2128system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2623system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction 2624system.cpu3.commit.bw_lim_events 1306 # number cycles where commit BW limit reached | 2129system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction 2130system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached |
| 2625system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits | 2131system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2626system.cpu3.rob.rob_reads 393745 # The number of ROB reads 2627system.cpu3.rob.rob_writes 480811 # The number of ROB writes 2628system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself 2629system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling 2630system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2631system.cpu3.committedInsts 186285 # Number of Instructions Simulated 2632system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated 2633system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction 2634system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads 2635system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle 2636system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads 2637system.cpu3.int_regfile_reads 340113 # number of integer regfile reads 2638system.cpu3.int_regfile_writes 159981 # number of integer regfile writes | 2132system.cpu3.rob.rob_reads 405464 # The number of ROB reads 2133system.cpu3.rob.rob_writes 504751 # The number of ROB writes 2134system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself 2135system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling 2136system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2137system.cpu3.committedInsts 196863 # Number of Instructions Simulated 2138system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated 2139system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction 2140system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads 2141system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle 2142system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads 2143system.cpu3.int_regfile_reads 359772 # number of integer regfile reads 2144system.cpu3.int_regfile_writes 168916 # number of integer regfile writes |
| 2639system.cpu3.fp_regfile_writes 64 # number of floating regfile writes | 2145system.cpu3.fp_regfile_writes 64 # number of floating regfile writes |
| 2640system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads | 2146system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads |
| 2641system.cpu3.misc_regfile_writes 648 # number of misc regfile writes | 2147system.cpu3.misc_regfile_writes 648 # number of misc regfile writes |
| 2642system.cpu3.icache.tags.replacements 386 # number of replacements 2643system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use 2644system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks. 2645system.cpu3.icache.tags.sampled_refs 499 # Sample count of references to valid blocks. 2646system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks. 2647system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2648system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.771025 # Average occupied blocks per requestor 2649system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151897 # Average percentage of cache occupancy 2650system.cpu3.icache.tags.occ_percent::total 0.151897 # Average percentage of cache occupancy 2651system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id 2652system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2653system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 2654system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id 2655system.cpu3.icache.tags.tag_accesses 25471 # Number of tag accesses 2656system.cpu3.icache.tags.data_accesses 25471 # Number of data accesses 2657system.cpu3.icache.ReadReq_hits::cpu3.inst 24411 # number of ReadReq hits 2658system.cpu3.icache.ReadReq_hits::total 24411 # number of ReadReq hits 2659system.cpu3.icache.demand_hits::cpu3.inst 24411 # number of demand (read+write) hits 2660system.cpu3.icache.demand_hits::total 24411 # number of demand (read+write) hits 2661system.cpu3.icache.overall_hits::cpu3.inst 24411 # number of overall hits 2662system.cpu3.icache.overall_hits::total 24411 # number of overall hits 2663system.cpu3.icache.ReadReq_misses::cpu3.inst 561 # number of ReadReq misses 2664system.cpu3.icache.ReadReq_misses::total 561 # number of ReadReq misses 2665system.cpu3.icache.demand_misses::cpu3.inst 561 # number of demand (read+write) misses 2666system.cpu3.icache.demand_misses::total 561 # number of demand (read+write) misses 2667system.cpu3.icache.overall_misses::cpu3.inst 561 # number of overall misses 2668system.cpu3.icache.overall_misses::total 561 # number of overall misses 2669system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7400997 # number of ReadReq miss cycles 2670system.cpu3.icache.ReadReq_miss_latency::total 7400997 # number of ReadReq miss cycles 2671system.cpu3.icache.demand_miss_latency::cpu3.inst 7400997 # number of demand (read+write) miss cycles 2672system.cpu3.icache.demand_miss_latency::total 7400997 # number of demand (read+write) miss cycles 2673system.cpu3.icache.overall_miss_latency::cpu3.inst 7400997 # number of overall miss cycles 2674system.cpu3.icache.overall_miss_latency::total 7400997 # number of overall miss cycles 2675system.cpu3.icache.ReadReq_accesses::cpu3.inst 24972 # number of ReadReq accesses(hits+misses) 2676system.cpu3.icache.ReadReq_accesses::total 24972 # number of ReadReq accesses(hits+misses) 2677system.cpu3.icache.demand_accesses::cpu3.inst 24972 # number of demand (read+write) accesses 2678system.cpu3.icache.demand_accesses::total 24972 # number of demand (read+write) accesses 2679system.cpu3.icache.overall_accesses::cpu3.inst 24972 # number of overall (read+write) accesses 2680system.cpu3.icache.overall_accesses::total 24972 # number of overall (read+write) accesses 2681system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022465 # miss rate for ReadReq accesses 2682system.cpu3.icache.ReadReq_miss_rate::total 0.022465 # miss rate for ReadReq accesses 2683system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022465 # miss rate for demand accesses 2684system.cpu3.icache.demand_miss_rate::total 0.022465 # miss rate for demand accesses 2685system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022465 # miss rate for overall accesses 2686system.cpu3.icache.overall_miss_rate::total 0.022465 # miss rate for overall accesses 2687system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13192.508021 # average ReadReq miss latency 2688system.cpu3.icache.ReadReq_avg_miss_latency::total 13192.508021 # average ReadReq miss latency 2689system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency 2690system.cpu3.icache.demand_avg_miss_latency::total 13192.508021 # average overall miss latency 2691system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency 2692system.cpu3.icache.overall_avg_miss_latency::total 13192.508021 # average overall miss latency 2693system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2694system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2695system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2696system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2697system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2698system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2699system.cpu3.icache.fast_writes 0 # number of fast writes performed 2700system.cpu3.icache.cache_copies 0 # number of cache copies performed 2701system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits 2702system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 2703system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits 2704system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 2705system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits 2706system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 2707system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 499 # number of ReadReq MSHR misses 2708system.cpu3.icache.ReadReq_mshr_misses::total 499 # number of ReadReq MSHR misses 2709system.cpu3.icache.demand_mshr_misses::cpu3.inst 499 # number of demand (read+write) MSHR misses 2710system.cpu3.icache.demand_mshr_misses::total 499 # number of demand (read+write) MSHR misses 2711system.cpu3.icache.overall_mshr_misses::cpu3.inst 499 # number of overall MSHR misses 2712system.cpu3.icache.overall_mshr_misses::total 499 # number of overall MSHR misses 2713system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5888752 # number of ReadReq MSHR miss cycles 2714system.cpu3.icache.ReadReq_mshr_miss_latency::total 5888752 # number of ReadReq MSHR miss cycles 2715system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5888752 # number of demand (read+write) MSHR miss cycles 2716system.cpu3.icache.demand_mshr_miss_latency::total 5888752 # number of demand (read+write) MSHR miss cycles 2717system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5888752 # number of overall MSHR miss cycles 2718system.cpu3.icache.overall_mshr_miss_latency::total 5888752 # number of overall MSHR miss cycles 2719system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for ReadReq accesses 2720system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019982 # mshr miss rate for ReadReq accesses 2721system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for demand accesses 2722system.cpu3.icache.demand_mshr_miss_rate::total 0.019982 # mshr miss rate for demand accesses 2723system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for overall accesses 2724system.cpu3.icache.overall_mshr_miss_rate::total 0.019982 # mshr miss rate for overall accesses 2725system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average ReadReq mshr miss latency 2726system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11801.106212 # average ReadReq mshr miss latency 2727system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency 2728system.cpu3.icache.demand_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency 2729system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency 2730system.cpu3.icache.overall_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency 2731system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 2732system.cpu3.dcache.tags.replacements 0 # number of replacements | 2148system.cpu3.dcache.tags.replacements 0 # number of replacements |
| 2733system.cpu3.dcache.tags.tagsinuse 23.453129 # Cycle average of tags in use 2734system.cpu3.dcache.tags.total_refs 34358 # Total number of references to valid blocks. 2735system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2736system.cpu3.dcache.tags.avg_refs 1227.071429 # Average number of references to valid blocks. | 2149system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use 2150system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks. 2151system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 2152system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks. |
| 2737system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2153system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2738system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.453129 # Average occupied blocks per requestor 2739system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045807 # Average percentage of cache occupancy 2740system.cpu3.dcache.tags.occ_percent::total 0.045807 # Average percentage of cache occupancy 2741system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id | 2154system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor 2155system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy 2156system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy 2157system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2158system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id |
| 2742system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id | 2159system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id |
| 2743system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2744system.cpu3.dcache.tags.tag_accesses 272485 # Number of tag accesses 2745system.cpu3.dcache.tags.data_accesses 272485 # Number of data accesses 2746system.cpu3.dcache.ReadReq_hits::cpu3.data 39283 # number of ReadReq hits 2747system.cpu3.dcache.ReadReq_hits::total 39283 # number of ReadReq hits 2748system.cpu3.dcache.WriteReq_hits::cpu3.data 28128 # number of WriteReq hits 2749system.cpu3.dcache.WriteReq_hits::total 28128 # number of WriteReq hits 2750system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits 2751system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits 2752system.cpu3.dcache.demand_hits::cpu3.data 67411 # number of demand (read+write) hits 2753system.cpu3.dcache.demand_hits::total 67411 # number of demand (read+write) hits 2754system.cpu3.dcache.overall_hits::cpu3.data 67411 # number of overall hits 2755system.cpu3.dcache.overall_hits::total 67411 # number of overall hits 2756system.cpu3.dcache.ReadReq_misses::cpu3.data 435 # number of ReadReq misses 2757system.cpu3.dcache.ReadReq_misses::total 435 # number of ReadReq misses 2758system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses 2759system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses 2760system.cpu3.dcache.SwapReq_misses::cpu3.data 62 # number of SwapReq misses 2761system.cpu3.dcache.SwapReq_misses::total 62 # number of SwapReq misses 2762system.cpu3.dcache.demand_misses::cpu3.data 571 # number of demand (read+write) misses 2763system.cpu3.dcache.demand_misses::total 571 # number of demand (read+write) misses 2764system.cpu3.dcache.overall_misses::cpu3.data 571 # number of overall misses 2765system.cpu3.dcache.overall_misses::total 571 # number of overall misses 2766system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5776999 # number of ReadReq miss cycles 2767system.cpu3.dcache.ReadReq_miss_latency::total 5776999 # number of ReadReq miss cycles 2768system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2748012 # number of WriteReq miss cycles 2769system.cpu3.dcache.WriteReq_miss_latency::total 2748012 # number of WriteReq miss cycles 2770system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 544508 # number of SwapReq miss cycles 2771system.cpu3.dcache.SwapReq_miss_latency::total 544508 # number of SwapReq miss cycles 2772system.cpu3.dcache.demand_miss_latency::cpu3.data 8525011 # number of demand (read+write) miss cycles 2773system.cpu3.dcache.demand_miss_latency::total 8525011 # number of demand (read+write) miss cycles 2774system.cpu3.dcache.overall_miss_latency::cpu3.data 8525011 # number of overall miss cycles 2775system.cpu3.dcache.overall_miss_latency::total 8525011 # number of overall miss cycles 2776system.cpu3.dcache.ReadReq_accesses::cpu3.data 39718 # number of ReadReq accesses(hits+misses) 2777system.cpu3.dcache.ReadReq_accesses::total 39718 # number of ReadReq accesses(hits+misses) 2778system.cpu3.dcache.WriteReq_accesses::cpu3.data 28264 # number of WriteReq accesses(hits+misses) 2779system.cpu3.dcache.WriteReq_accesses::total 28264 # number of WriteReq accesses(hits+misses) 2780system.cpu3.dcache.SwapReq_accesses::cpu3.data 75 # number of SwapReq accesses(hits+misses) 2781system.cpu3.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) 2782system.cpu3.dcache.demand_accesses::cpu3.data 67982 # number of demand (read+write) accesses 2783system.cpu3.dcache.demand_accesses::total 67982 # number of demand (read+write) accesses 2784system.cpu3.dcache.overall_accesses::cpu3.data 67982 # number of overall (read+write) accesses 2785system.cpu3.dcache.overall_accesses::total 67982 # number of overall (read+write) accesses 2786system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010952 # miss rate for ReadReq accesses 2787system.cpu3.dcache.ReadReq_miss_rate::total 0.010952 # miss rate for ReadReq accesses 2788system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004812 # miss rate for WriteReq accesses 2789system.cpu3.dcache.WriteReq_miss_rate::total 0.004812 # miss rate for WriteReq accesses 2790system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.826667 # miss rate for SwapReq accesses 2791system.cpu3.dcache.SwapReq_miss_rate::total 0.826667 # miss rate for SwapReq accesses 2792system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008399 # miss rate for demand accesses 2793system.cpu3.dcache.demand_miss_rate::total 0.008399 # miss rate for demand accesses 2794system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008399 # miss rate for overall accesses 2795system.cpu3.dcache.overall_miss_rate::total 0.008399 # miss rate for overall accesses 2796system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.457471 # average ReadReq miss latency 2797system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.457471 # average ReadReq miss latency 2798system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20205.970588 # average WriteReq miss latency 2799system.cpu3.dcache.WriteReq_avg_miss_latency::total 20205.970588 # average WriteReq miss latency 2800system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8782.387097 # average SwapReq miss latency 2801system.cpu3.dcache.SwapReq_avg_miss_latency::total 8782.387097 # average SwapReq miss latency 2802system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency 2803system.cpu3.dcache.demand_avg_miss_latency::total 14929.966725 # average overall miss latency 2804system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency 2805system.cpu3.dcache.overall_avg_miss_latency::total 14929.966725 # average overall miss latency | 2160system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 2161system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses 2162system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses 2163system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits 2164system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits 2165system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits 2166system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits 2167system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 2168system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2169system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits 2170system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits 2171system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits 2172system.cpu3.dcache.overall_hits::total 71643 # number of overall hits 2173system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses 2174system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses 2175system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses 2176system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses 2177system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses 2178system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2179system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses 2180system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses 2181system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses 2182system.cpu3.dcache.overall_misses::total 560 # number of overall misses 2183system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles 2184system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles 2185system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles 2186system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles 2187system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles 2188system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles 2189system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles 2190system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles 2191system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles 2192system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles 2193system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses) 2194system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses) 2195system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses) 2196system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses) 2197system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 2198system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 2199system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses 2200system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses 2201system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses 2202system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses 2203system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses 2204system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses 2205system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses 2206system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses 2207system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses 2208system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 2209system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses 2210system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses 2211system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses 2212system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses 2213system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency 2214system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency 2215system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency 2216system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency 2217system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency 2218system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency 2219system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency 2220system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency 2221system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency 2222system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency |
| 2806system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2807system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2808system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2809system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2810system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2811system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2812system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2813system.cpu3.dcache.cache_copies 0 # number of cache copies performed | 2223system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2224system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2225system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2226system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2227system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2228system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2229system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2230system.cpu3.dcache.cache_copies 0 # number of cache copies performed |
| 2814system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 269 # number of ReadReq MSHR hits 2815system.cpu3.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits 2816system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2817system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2818system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits 2819system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits 2820system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits 2821system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits 2822system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 166 # number of ReadReq MSHR misses 2823system.cpu3.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses 2824system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses 2825system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses 2826system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 62 # number of SwapReq MSHR misses 2827system.cpu3.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses 2828system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses 2829system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses 2830system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses 2831system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses 2832system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1189025 # number of ReadReq MSHR miss cycles 2833system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1189025 # number of ReadReq MSHR miss cycles 2834system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1291488 # number of WriteReq MSHR miss cycles 2835system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1291488 # number of WriteReq MSHR miss cycles 2836system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 420492 # number of SwapReq MSHR miss cycles 2837system.cpu3.dcache.SwapReq_mshr_miss_latency::total 420492 # number of SwapReq MSHR miss cycles 2838system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2480513 # number of demand (read+write) MSHR miss cycles 2839system.cpu3.dcache.demand_mshr_miss_latency::total 2480513 # number of demand (read+write) MSHR miss cycles 2840system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2480513 # number of overall MSHR miss cycles 2841system.cpu3.dcache.overall_mshr_miss_latency::total 2480513 # number of overall MSHR miss cycles 2842system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004179 # mshr miss rate for ReadReq accesses 2843system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004179 # mshr miss rate for ReadReq accesses 2844system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003644 # mshr miss rate for WriteReq accesses 2845system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003644 # mshr miss rate for WriteReq accesses 2846system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.826667 # mshr miss rate for SwapReq accesses 2847system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.826667 # mshr miss rate for SwapReq accesses 2848system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for demand accesses 2849system.cpu3.dcache.demand_mshr_miss_rate::total 0.003957 # mshr miss rate for demand accesses 2850system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for overall accesses 2851system.cpu3.dcache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses 2852system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7162.801205 # average ReadReq mshr miss latency 2853system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7162.801205 # average ReadReq mshr miss latency 2854system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12538.718447 # average WriteReq mshr miss latency 2855system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12538.718447 # average WriteReq mshr miss latency 2856system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6782.129032 # average SwapReq mshr miss latency 2857system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6782.129032 # average SwapReq mshr miss latency 2858system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency 2859system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency 2860system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency 2861system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency | 2231system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits 2232system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits 2233system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits 2234system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 2235system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits 2236system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits 2237system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits 2238system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits 2239system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses 2240system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses 2241system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 2242system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 2243system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses 2244system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 2245system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses 2246system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 2247system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses 2248system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses 2249system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles 2250system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles 2251system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles 2252system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles 2253system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles 2254system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles 2255system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles 2256system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles 2257system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles 2258system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles 2259system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses 2260system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses 2261system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses 2262system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses 2263system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses 2264system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 2265system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses 2266system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses 2267system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses 2268system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses 2269system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency 2270system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency 2271system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency 2272system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency 2273system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency 2274system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency 2275system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency 2276system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency 2277system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency 2278system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency |
| 2862system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2279system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2280system.cpu3.icache.tags.replacements 386 # number of replacements 2281system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use 2282system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks. 2283system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks. 2284system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks. 2285system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2286system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor 2287system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy 2288system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy 2289system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id 2290system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2291system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 2292system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id 2293system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses 2294system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses 2295system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits 2296system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits 2297system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits 2298system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits 2299system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits 2300system.cpu3.icache.overall_hits::total 23274 # number of overall hits 2301system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses 2302system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses 2303system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses 2304system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses 2305system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses 2306system.cpu3.icache.overall_misses::total 556 # number of overall misses 2307system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles 2308system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles 2309system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles 2310system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles 2311system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles 2312system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles 2313system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses) 2314system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses) 2315system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses 2316system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses 2317system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses 2318system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses 2319system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses 2320system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses 2321system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses 2322system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses 2323system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses 2324system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses 2325system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency 2326system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency 2327system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency 2328system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency 2329system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency 2330system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency 2331system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2332system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2333system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2334system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2335system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2336system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2337system.cpu3.icache.fast_writes 0 # number of fast writes performed 2338system.cpu3.icache.cache_copies 0 # number of cache copies performed 2339system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits 2340system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 2341system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits 2342system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits 2343system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits 2344system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits 2345system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses 2346system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses 2347system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses 2348system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses 2349system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses 2350system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses 2351system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles 2352system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles 2353system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles 2354system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles 2355system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles 2356system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles 2357system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses 2358system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses 2359system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses 2360system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses 2361system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses 2362system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses 2363system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency 2364system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency 2365system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency 2366system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency 2367system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency 2368system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency 2369system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2370system.l2c.tags.replacements 0 # number of replacements 2371system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use 2372system.l2c.tags.total_refs 1661 # Total number of references to valid blocks. 2373system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks. 2374system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks. 2375system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2376system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor 2377system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor 2378system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor 2379system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor 2381system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor 2382system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor 2383system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor 2384system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor 2385system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2386system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy 2387system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy 2388system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy 2389system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy 2390system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy 2391system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy 2392system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy 2393system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2394system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy 2395system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id 2396system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 2397system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id 2398system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id 2399system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id 2400system.l2c.tags.tag_accesses 20025 # Number of tag accesses 2401system.l2c.tags.data_accesses 20025 # Number of data accesses 2402system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits 2403system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2404system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits 2405system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 2406system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits 2407system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 2408system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits 2409system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 2410system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits 2411system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2412system.l2c.Writeback_hits::total 1 # number of Writeback hits 2413system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2414system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2415system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 2421system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits 2422system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2423system.l2c.demand_hits::total 1661 # number of demand (read+write) hits 2424system.l2c.overall_hits::cpu0.inst 248 # number of overall hits 2425system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2426system.l2c.overall_hits::cpu1.inst 483 # number of overall hits 2427system.l2c.overall_hits::cpu1.data 11 # number of overall hits 2428system.l2c.overall_hits::cpu2.inst 409 # number of overall hits 2429system.l2c.overall_hits::cpu2.data 5 # number of overall hits 2430system.l2c.overall_hits::cpu3.inst 489 # number of overall hits 2431system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2432system.l2c.overall_hits::total 1661 # number of overall hits 2433system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses 2434system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2435system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses 2436system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 2437system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses 2438system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 2439system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses 2440system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 2441system.l2c.ReadReq_misses::total 546 # number of ReadReq misses 2442system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses 2443system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 2444system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses 2445system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses 2446system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses 2447system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2448system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 2449system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 2450system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2451system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2452system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses 2453system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2454system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses 2455system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2460system.l2c.demand_misses::total 677 # number of demand (read+write) misses 2461system.l2c.overall_misses::cpu0.inst 361 # number of overall misses 2462system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2463system.l2c.overall_misses::cpu1.inst 15 # number of overall misses 2464system.l2c.overall_misses::cpu1.data 13 # number of overall misses 2465system.l2c.overall_misses::cpu2.inst 81 # number of overall misses 2466system.l2c.overall_misses::cpu2.data 20 # number of overall misses 2467system.l2c.overall_misses::cpu3.inst 6 # number of overall misses 2468system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2469system.l2c.overall_misses::total 677 # number of overall misses 2470system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles 2471system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles 2472system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles 2473system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles 2474system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles 2475system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles 2476system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles 2477system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles 2478system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles 2479system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles 2480system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles 2481system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles 2482system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles 2483system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles 2484system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles 2485system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles 2488system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles 2489system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles 2490system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles 2491system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles 2493system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles 2494system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles 2497system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles 2498system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles 2499system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles 2500system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles 2501system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles 2502system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses) 2503system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2504system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses) 2505system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 2506system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses) 2507system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 2508system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses) 2509system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 2510system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses) 2511system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2512system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2513system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) 2514system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 2515system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) 2516system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) 2517system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 2518system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2519system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 2520system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 2521system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2522system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2523system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses 2524system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2525system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses 2526system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 2527system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses 2528system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 2529system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses 2530system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2531system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses 2532system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses 2533system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2534system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses 2535system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses 2536system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses 2537system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 2538system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses 2539system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses 2541system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses 2542system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2543system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses 2544system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses 2545system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses 2546system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses 2547system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses 2548system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 2549system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses 2550system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses 2551system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2552system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2553system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2554system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses 2555system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2556system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2557system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2558system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2559system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2560system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses 2561system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 2562system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses 2563system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses 2565system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses 2566system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses 2567system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2568system.l2c.demand_miss_rate::total 0.289564 # miss rate for demand accesses 2569system.l2c.overall_miss_rate::cpu0.inst 0.592775 # miss rate for overall accesses 2570system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2571system.l2c.overall_miss_rate::cpu1.inst 0.030120 # miss rate for overall accesses 2572system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses 2574system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 2575system.l2c.overall_miss_rate::cpu3.inst 0.012121 # miss rate for overall accesses 2576system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2577system.l2c.overall_miss_rate::total 0.289564 # miss rate for overall accesses 2578system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68970.914127 # average ReadReq miss latency 2579system.l2c.ReadReq_avg_miss_latency::cpu0.data 80027.027027 # average ReadReq miss latency 2580system.l2c.ReadReq_avg_miss_latency::cpu1.inst 68466.666667 # average ReadReq miss latency 2581system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # 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average overall miss latency 2593system.l2c.demand_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency 2594system.l2c.demand_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency 2595system.l2c.demand_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency 2596system.l2c.demand_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency 2597system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency 2598system.l2c.demand_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency 2599system.l2c.demand_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency 2600system.l2c.demand_avg_miss_latency::total 71699.039882 # average overall miss latency 2601system.l2c.overall_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency 2602system.l2c.overall_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency 2603system.l2c.overall_avg_miss_latency::cpu1.inst 68466.666667 # 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average number of cycles each access was blocked 2616system.l2c.fast_writes 0 # number of fast writes performed 2617system.l2c.cache_copies 0 # number of cache copies performed 2618system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 2619system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2620system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits 2621system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits 2622system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 2623system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2624system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2625system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits 2626system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits 2627system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 2628system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2629system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2630system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits 2631system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits 2632system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits 2633system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses 2634system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses 2635system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses 2636system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses 2637system.l2c.ReadReq_mshr_misses::cpu2.inst 76 # number of ReadReq MSHR misses 2638system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 2639system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses 2640system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 2641system.l2c.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses 2642system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses 2643system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses 2644system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses 2645system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses 2646system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses 2647system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2648system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 2649system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 2650system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2651system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2652system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses 2653system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses 2654system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses 2655system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 2656system.l2c.demand_mshr_misses::cpu2.inst 76 # number of demand (read+write) MSHR misses 2657system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 2658system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses 2659system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2660system.l2c.demand_mshr_misses::total 665 # number of demand (read+write) MSHR misses 2661system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses 2662system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 2663system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses 2664system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses 2665system.l2c.overall_mshr_misses::cpu2.inst 76 # number of overall MSHR misses 2666system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 2667system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses 2668system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2669system.l2c.overall_mshr_misses::total 665 # number of overall MSHR misses 2670system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20340000 # number of ReadReq MSHR miss cycles 2671system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5009000 # number of ReadReq MSHR miss cycles 2672system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 701250 # number of ReadReq MSHR miss cycles 2673system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles 2674system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4539000 # number of ReadReq MSHR miss cycles 2675system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles 2676system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 390250 # number of ReadReq MSHR miss cycles 2677system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles 2678system.l2c.ReadReq_mshr_miss_latency::total 31540750 # number of ReadReq MSHR miss cycles 2679system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles 2680system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of UpgradeReq MSHR miss cycles 2681system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 200020 # number of UpgradeReq MSHR miss cycles 2682system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles 2683system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles 2684system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles 2685system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 687000 # number of ReadExReq MSHR miss cycles 2686system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles 2687system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700750 # number of ReadExReq MSHR miss cycles 2688system.l2c.ReadExReq_mshr_miss_latency::total 8037500 # number of ReadExReq MSHR miss cycles 2689system.l2c.demand_mshr_miss_latency::cpu0.inst 20340000 # number of demand (read+write) MSHR miss cycles 2690system.l2c.demand_mshr_miss_latency::cpu0.data 10770500 # number of demand (read+write) MSHR miss cycles 2691system.l2c.demand_mshr_miss_latency::cpu1.inst 701250 # number of demand (read+write) MSHR miss cycles 2692system.l2c.demand_mshr_miss_latency::cpu1.data 749500 # number of demand (read+write) MSHR miss cycles 2693system.l2c.demand_mshr_miss_latency::cpu2.inst 4539000 # number of demand (read+write) MSHR miss cycles 2694system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles 2695system.l2c.demand_mshr_miss_latency::cpu3.inst 390250 # number of demand (read+write) MSHR miss cycles 2696system.l2c.demand_mshr_miss_latency::cpu3.data 763250 # number of demand (read+write) MSHR miss cycles 2697system.l2c.demand_mshr_miss_latency::total 39578250 # number of demand (read+write) MSHR miss cycles 2698system.l2c.overall_mshr_miss_latency::cpu0.inst 20340000 # number of overall MSHR miss cycles 2699system.l2c.overall_mshr_miss_latency::cpu0.data 10770500 # number of overall MSHR miss cycles 2700system.l2c.overall_mshr_miss_latency::cpu1.inst 701250 # number of overall MSHR miss cycles 2701system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles 2702system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles 2703system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles 2704system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles 2705system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles 2706system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles 2707system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses 2708system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2709system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses 2710system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 2711system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses 2712system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 2713system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses 2714system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 2715system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses 2716system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses 2717system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2718system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2719system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2720system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses 2721system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2722system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2723system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2724system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2725system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2726system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses 2727system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2728system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses 2729system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 2730system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses 2731system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 2732system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses 2733system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2734system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses 2735system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses 2736system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2737system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses 2738system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 2739system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses 2740system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 2741system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses 2742system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2743system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses 2744system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency 2745system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency 2746system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency 2747system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency 2748system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency 2749system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency 2750system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency 2751system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency 2752system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency 2753system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 2754system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 2756system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 2757system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 2758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency 2759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency 2760system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency 2761system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency 2762system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency 2763system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency 2764system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency 2765system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency 2766system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency 2767system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency 2768system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency 2769system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency 2770system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency 2771system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency 2772system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency 2773system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency 2774system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency 2775system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency 2776system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency 2777system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency 2778system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency 2779system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency 2780system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency 2781system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2782system.membus.trans_dist::ReadReq 534 # Transaction distribution 2783system.membus.trans_dist::ReadResp 533 # Transaction distribution 2784system.membus.trans_dist::UpgradeReq 274 # Transaction distribution 2785system.membus.trans_dist::UpgradeResp 78 # Transaction distribution 2786system.membus.trans_dist::ReadExReq 179 # Transaction distribution 2787system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2788system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) 2789system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) 2790system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) 2791system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) 2792system.membus.snoops 244 # Total snoops (count) 2793system.membus.snoop_fanout::samples 987 # Request fanout histogram 2794system.membus.snoop_fanout::mean 0 # Request fanout histogram 2795system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2796system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2797system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram 2798system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2799system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2800system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2801system.membus.snoop_fanout::max_value 0 # Request fanout histogram 2802system.membus.snoop_fanout::total 987 # Request fanout histogram 2803system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) 2804system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 2805system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) 2806system.membus.respLayer1.utilization 6.0 # Layer utilization (%) 2807system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution 2808system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution 2809system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 2810system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution 2811system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution 2812system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution 2813system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution 2814system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) 2815system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) 2816system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) 2817system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) 2818system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) 2819system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) 2820system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) 2821system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 2822system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) 2823system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) 2824system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 2825system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) 2826system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2827system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) 2828system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2829system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) 2830system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2831system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) 2832system.toL2Bus.snoops 1023 # Total snoops (count) 2833system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram 2834system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 2835system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 2836system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2837system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2838system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2839system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2840system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2841system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2842system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 2843system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 2844system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram 2845system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2846system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2847system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 2848system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 2849system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram 2850system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) 2851system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) 2852system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) 2853system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 2854system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) 2855system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 2856system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) 2857system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) 2858system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) 2859system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) 2860system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) 2861system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) 2862system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) 2863system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 2864system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) 2865system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) 2866system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) 2867system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) |
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| 2863 2864---------- End Simulation Statistics ---------- | 2868 2869---------- End Simulation Statistics ---------- |